diff options
author | Glenn Elliott <gelliott@cs.unc.edu> | 2012-03-04 19:47:13 -0500 |
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committer | Glenn Elliott <gelliott@cs.unc.edu> | 2012-03-04 19:47:13 -0500 |
commit | c71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch) | |
tree | ecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/x86/pci/ce4100.c | |
parent | ea53c912f8a86a8567697115b6a0d8152beee5c8 (diff) | |
parent | 6a00f206debf8a5c8899055726ad127dbeeed098 (diff) |
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts:
litmus/sched_cedf.c
Diffstat (limited to 'arch/x86/pci/ce4100.c')
-rw-r--r-- | arch/x86/pci/ce4100.c | 316 |
1 files changed, 316 insertions, 0 deletions
diff --git a/arch/x86/pci/ce4100.c b/arch/x86/pci/ce4100.c new file mode 100644 index 000000000000..67858be4b52b --- /dev/null +++ b/arch/x86/pci/ce4100.c | |||
@@ -0,0 +1,316 @@ | |||
1 | /* | ||
2 | * GPL LICENSE SUMMARY | ||
3 | * | ||
4 | * Copyright(c) 2010 Intel Corporation. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of version 2 of the GNU General Public License as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, but | ||
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
13 | * General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
18 | * The full GNU General Public License is included in this distribution | ||
19 | * in the file called LICENSE.GPL. | ||
20 | * | ||
21 | * Contact Information: | ||
22 | * Intel Corporation | ||
23 | * 2200 Mission College Blvd. | ||
24 | * Santa Clara, CA 97052 | ||
25 | * | ||
26 | * This provides access methods for PCI registers that mis-behave on | ||
27 | * the CE4100. Each register can be assigned a private init, read and | ||
28 | * write routine. The exception to this is the bridge device. The | ||
29 | * bridge device is the only device on bus zero (0) that requires any | ||
30 | * fixup so it is a special case ATM | ||
31 | */ | ||
32 | |||
33 | #include <linux/kernel.h> | ||
34 | #include <linux/pci.h> | ||
35 | #include <linux/init.h> | ||
36 | |||
37 | #include <asm/ce4100.h> | ||
38 | #include <asm/pci_x86.h> | ||
39 | |||
40 | struct sim_reg { | ||
41 | u32 value; | ||
42 | u32 mask; | ||
43 | }; | ||
44 | |||
45 | struct sim_dev_reg { | ||
46 | int dev_func; | ||
47 | int reg; | ||
48 | void (*init)(struct sim_dev_reg *reg); | ||
49 | void (*read)(struct sim_dev_reg *reg, u32 *value); | ||
50 | void (*write)(struct sim_dev_reg *reg, u32 value); | ||
51 | struct sim_reg sim_reg; | ||
52 | }; | ||
53 | |||
54 | struct sim_reg_op { | ||
55 | void (*init)(struct sim_dev_reg *reg); | ||
56 | void (*read)(struct sim_dev_reg *reg, u32 value); | ||
57 | void (*write)(struct sim_dev_reg *reg, u32 value); | ||
58 | }; | ||
59 | |||
60 | #define MB (1024 * 1024) | ||
61 | #define KB (1024) | ||
62 | #define SIZE_TO_MASK(size) (~(size - 1)) | ||
63 | |||
64 | #define DEFINE_REG(device, func, offset, size, init_op, read_op, write_op)\ | ||
65 | { PCI_DEVFN(device, func), offset, init_op, read_op, write_op,\ | ||
66 | {0, SIZE_TO_MASK(size)} }, | ||
67 | |||
68 | static void reg_init(struct sim_dev_reg *reg) | ||
69 | { | ||
70 | pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4, | ||
71 | ®->sim_reg.value); | ||
72 | } | ||
73 | |||
74 | static void reg_read(struct sim_dev_reg *reg, u32 *value) | ||
75 | { | ||
76 | unsigned long flags; | ||
77 | |||
78 | raw_spin_lock_irqsave(&pci_config_lock, flags); | ||
79 | *value = reg->sim_reg.value; | ||
80 | raw_spin_unlock_irqrestore(&pci_config_lock, flags); | ||
81 | } | ||
82 | |||
83 | static void reg_write(struct sim_dev_reg *reg, u32 value) | ||
84 | { | ||
85 | unsigned long flags; | ||
86 | |||
87 | raw_spin_lock_irqsave(&pci_config_lock, flags); | ||
88 | reg->sim_reg.value = (value & reg->sim_reg.mask) | | ||
89 | (reg->sim_reg.value & ~reg->sim_reg.mask); | ||
90 | raw_spin_unlock_irqrestore(&pci_config_lock, flags); | ||
91 | } | ||
92 | |||
93 | static void sata_reg_init(struct sim_dev_reg *reg) | ||
94 | { | ||
95 | pci_direct_conf1.read(0, 1, PCI_DEVFN(14, 0), 0x10, 4, | ||
96 | ®->sim_reg.value); | ||
97 | reg->sim_reg.value += 0x400; | ||
98 | } | ||
99 | |||
100 | static void ehci_reg_read(struct sim_dev_reg *reg, u32 *value) | ||
101 | { | ||
102 | reg_read(reg, value); | ||
103 | if (*value != reg->sim_reg.mask) | ||
104 | *value |= 0x100; | ||
105 | } | ||
106 | |||
107 | void sata_revid_init(struct sim_dev_reg *reg) | ||
108 | { | ||
109 | reg->sim_reg.value = 0x01060100; | ||
110 | reg->sim_reg.mask = 0; | ||
111 | } | ||
112 | |||
113 | static void sata_revid_read(struct sim_dev_reg *reg, u32 *value) | ||
114 | { | ||
115 | reg_read(reg, value); | ||
116 | } | ||
117 | |||
118 | static struct sim_dev_reg bus1_fixups[] = { | ||
119 | DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write) | ||
120 | DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write) | ||
121 | DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write) | ||
122 | DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write) | ||
123 | DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) | ||
124 | DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write) | ||
125 | DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write) | ||
126 | DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write) | ||
127 | DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write) | ||
128 | DEFINE_REG(8, 0, 0x10, (1*MB), reg_init, reg_read, reg_write) | ||
129 | DEFINE_REG(8, 1, 0x10, (64*KB), reg_init, reg_read, reg_write) | ||
130 | DEFINE_REG(8, 2, 0x10, (64*KB), reg_init, reg_read, reg_write) | ||
131 | DEFINE_REG(9, 0, 0x10 , (1*MB), reg_init, reg_read, reg_write) | ||
132 | DEFINE_REG(9, 0, 0x14, (64*KB), reg_init, reg_read, reg_write) | ||
133 | DEFINE_REG(10, 0, 0x10, (256), reg_init, reg_read, reg_write) | ||
134 | DEFINE_REG(10, 0, 0x14, (256*MB), reg_init, reg_read, reg_write) | ||
135 | DEFINE_REG(11, 0, 0x10, (256), reg_init, reg_read, reg_write) | ||
136 | DEFINE_REG(11, 0, 0x14, (256), reg_init, reg_read, reg_write) | ||
137 | DEFINE_REG(11, 1, 0x10, (256), reg_init, reg_read, reg_write) | ||
138 | DEFINE_REG(11, 2, 0x10, (256), reg_init, reg_read, reg_write) | ||
139 | DEFINE_REG(11, 2, 0x14, (256), reg_init, reg_read, reg_write) | ||
140 | DEFINE_REG(11, 2, 0x18, (256), reg_init, reg_read, reg_write) | ||
141 | DEFINE_REG(11, 3, 0x10, (256), reg_init, reg_read, reg_write) | ||
142 | DEFINE_REG(11, 3, 0x14, (256), reg_init, reg_read, reg_write) | ||
143 | DEFINE_REG(11, 4, 0x10, (256), reg_init, reg_read, reg_write) | ||
144 | DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write) | ||
145 | DEFINE_REG(11, 6, 0x10, (256), reg_init, reg_read, reg_write) | ||
146 | DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write) | ||
147 | DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) | ||
148 | DEFINE_REG(12, 0, 0x14, (256), reg_init, reg_read, reg_write) | ||
149 | DEFINE_REG(12, 1, 0x10, (1024), reg_init, reg_read, reg_write) | ||
150 | DEFINE_REG(13, 0, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write) | ||
151 | DEFINE_REG(13, 1, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write) | ||
152 | DEFINE_REG(14, 0, 0x8, 0, sata_revid_init, sata_revid_read, 0) | ||
153 | DEFINE_REG(14, 0, 0x10, 0, reg_init, reg_read, reg_write) | ||
154 | DEFINE_REG(14, 0, 0x14, 0, reg_init, reg_read, reg_write) | ||
155 | DEFINE_REG(14, 0, 0x18, 0, reg_init, reg_read, reg_write) | ||
156 | DEFINE_REG(14, 0, 0x1C, 0, reg_init, reg_read, reg_write) | ||
157 | DEFINE_REG(14, 0, 0x20, 0, reg_init, reg_read, reg_write) | ||
158 | DEFINE_REG(14, 0, 0x24, (0x200), sata_reg_init, reg_read, reg_write) | ||
159 | DEFINE_REG(15, 0, 0x10, (64*KB), reg_init, reg_read, reg_write) | ||
160 | DEFINE_REG(15, 0, 0x14, (64*KB), reg_init, reg_read, reg_write) | ||
161 | DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write) | ||
162 | DEFINE_REG(16, 0, 0x14, (64*MB), reg_init, reg_read, reg_write) | ||
163 | DEFINE_REG(16, 0, 0x18, (64*MB), reg_init, reg_read, reg_write) | ||
164 | DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write) | ||
165 | DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write) | ||
166 | }; | ||
167 | |||
168 | static void __init init_sim_regs(void) | ||
169 | { | ||
170 | int i; | ||
171 | |||
172 | for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { | ||
173 | if (bus1_fixups[i].init) | ||
174 | bus1_fixups[i].init(&bus1_fixups[i]); | ||
175 | } | ||
176 | } | ||
177 | |||
178 | static inline void extract_bytes(u32 *value, int reg, int len) | ||
179 | { | ||
180 | uint32_t mask; | ||
181 | |||
182 | *value >>= ((reg & 3) * 8); | ||
183 | mask = 0xFFFFFFFF >> ((4 - len) * 8); | ||
184 | *value &= mask; | ||
185 | } | ||
186 | |||
187 | int bridge_read(unsigned int devfn, int reg, int len, u32 *value) | ||
188 | { | ||
189 | u32 av_bridge_base, av_bridge_limit; | ||
190 | int retval = 0; | ||
191 | |||
192 | switch (reg) { | ||
193 | /* Make BARs appear to not request any memory. */ | ||
194 | case PCI_BASE_ADDRESS_0: | ||
195 | case PCI_BASE_ADDRESS_0 + 1: | ||
196 | case PCI_BASE_ADDRESS_0 + 2: | ||
197 | case PCI_BASE_ADDRESS_0 + 3: | ||
198 | *value = 0; | ||
199 | break; | ||
200 | |||
201 | /* Since subordinate bus number register is hardwired | ||
202 | * to zero and read only, so do the simulation. | ||
203 | */ | ||
204 | case PCI_PRIMARY_BUS: | ||
205 | if (len == 4) | ||
206 | *value = 0x00010100; | ||
207 | break; | ||
208 | |||
209 | case PCI_SUBORDINATE_BUS: | ||
210 | *value = 1; | ||
211 | break; | ||
212 | |||
213 | case PCI_MEMORY_BASE: | ||
214 | case PCI_MEMORY_LIMIT: | ||
215 | /* Get the A/V bridge base address. */ | ||
216 | pci_direct_conf1.read(0, 0, devfn, | ||
217 | PCI_BASE_ADDRESS_0, 4, &av_bridge_base); | ||
218 | |||
219 | av_bridge_limit = av_bridge_base + (512*MB - 1); | ||
220 | av_bridge_limit >>= 16; | ||
221 | av_bridge_limit &= 0xFFF0; | ||
222 | |||
223 | av_bridge_base >>= 16; | ||
224 | av_bridge_base &= 0xFFF0; | ||
225 | |||
226 | if (reg == PCI_MEMORY_LIMIT) | ||
227 | *value = av_bridge_limit; | ||
228 | else if (len == 2) | ||
229 | *value = av_bridge_base; | ||
230 | else | ||
231 | *value = (av_bridge_limit << 16) | av_bridge_base; | ||
232 | break; | ||
233 | /* Make prefetchable memory limit smaller than prefetchable | ||
234 | * memory base, so not claim prefetchable memory space. | ||
235 | */ | ||
236 | case PCI_PREF_MEMORY_BASE: | ||
237 | *value = 0xFFF0; | ||
238 | break; | ||
239 | case PCI_PREF_MEMORY_LIMIT: | ||
240 | *value = 0x0; | ||
241 | break; | ||
242 | /* Make IO limit smaller than IO base, so not claim IO space. */ | ||
243 | case PCI_IO_BASE: | ||
244 | *value = 0xF0; | ||
245 | break; | ||
246 | case PCI_IO_LIMIT: | ||
247 | *value = 0; | ||
248 | break; | ||
249 | default: | ||
250 | retval = 1; | ||
251 | } | ||
252 | return retval; | ||
253 | } | ||
254 | |||
255 | static int ce4100_conf_read(unsigned int seg, unsigned int bus, | ||
256 | unsigned int devfn, int reg, int len, u32 *value) | ||
257 | { | ||
258 | int i; | ||
259 | |||
260 | if (bus == 1) { | ||
261 | for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { | ||
262 | if (bus1_fixups[i].dev_func == devfn && | ||
263 | bus1_fixups[i].reg == (reg & ~3) && | ||
264 | bus1_fixups[i].read) { | ||
265 | bus1_fixups[i].read(&(bus1_fixups[i]), | ||
266 | value); | ||
267 | extract_bytes(value, reg, len); | ||
268 | return 0; | ||
269 | } | ||
270 | } | ||
271 | } | ||
272 | |||
273 | if (bus == 0 && (PCI_DEVFN(1, 0) == devfn) && | ||
274 | !bridge_read(devfn, reg, len, value)) | ||
275 | return 0; | ||
276 | |||
277 | return pci_direct_conf1.read(seg, bus, devfn, reg, len, value); | ||
278 | } | ||
279 | |||
280 | static int ce4100_conf_write(unsigned int seg, unsigned int bus, | ||
281 | unsigned int devfn, int reg, int len, u32 value) | ||
282 | { | ||
283 | int i; | ||
284 | |||
285 | if (bus == 1) { | ||
286 | for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) { | ||
287 | if (bus1_fixups[i].dev_func == devfn && | ||
288 | bus1_fixups[i].reg == (reg & ~3) && | ||
289 | bus1_fixups[i].write) { | ||
290 | bus1_fixups[i].write(&(bus1_fixups[i]), | ||
291 | value); | ||
292 | return 0; | ||
293 | } | ||
294 | } | ||
295 | } | ||
296 | |||
297 | /* Discard writes to A/V bridge BAR. */ | ||
298 | if (bus == 0 && PCI_DEVFN(1, 0) == devfn && | ||
299 | ((reg & ~3) == PCI_BASE_ADDRESS_0)) | ||
300 | return 0; | ||
301 | |||
302 | return pci_direct_conf1.write(seg, bus, devfn, reg, len, value); | ||
303 | } | ||
304 | |||
305 | struct pci_raw_ops ce4100_pci_conf = { | ||
306 | .read = ce4100_conf_read, | ||
307 | .write = ce4100_conf_write, | ||
308 | }; | ||
309 | |||
310 | int __init ce4100_pci_init(void) | ||
311 | { | ||
312 | init_sim_regs(); | ||
313 | raw_pci_ops = &ce4100_pci_conf; | ||
314 | /* Indicate caller that it should invoke pci_legacy_init() */ | ||
315 | return 1; | ||
316 | } | ||