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| author | Robert Richter <robert.richter@amd.com> | 2010-03-23 14:33:21 -0400 |
|---|---|---|
| committer | Robert Richter <robert.richter@amd.com> | 2010-05-04 05:35:26 -0400 |
| commit | d0e4120fda6f87eead438eed4d49032e12060e58 (patch) | |
| tree | 57f3ab727aa12bc63f19437a0a026e2ea5bd6d67 /arch/x86/oprofile/op_model_p4.c | |
| parent | 8f5a2dd83a1f8e89fdc17eb0f2f07c2e713e635a (diff) | |
oprofile/x86: reserve counter msrs pairwise
For AMD's and Intel's P6 generic performance counters have pairwise
counter and control msrs. This patch changes the counter reservation
in a way that both msrs must be registered. It joins some counter
loops and also removes the unnecessary NUM_CONTROLS macro in the AMD
implementation.
Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'arch/x86/oprofile/op_model_p4.c')
0 files changed, 0 insertions, 0 deletions