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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2008-02-06 16:54:09 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2008-02-06 16:54:09 -0500
commit3e6bdf473f489664dac4d7511d26c7ac3dfdc748 (patch)
tree10cb2e928830b9de8bbc3f6dd47c18c24cd2affa /arch/x86/mm/pageattr.c
parent3d4d4582e5b3f67a68f2cf32fd5b70d8d80f119d (diff)
parent58d5d0d8dd52cbca988af24b5692a20b00285543 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86
* git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86: x86: fix deadlock, make pgd_lock irq-safe virtio: fix trivial build bug x86: fix mttr trimming x86: delay CPA self-test and repeat it x86: fix 64-bit sections generic: add __FINITDATA x86: remove suprious ifdefs from pageattr.c x86: mark the .rodata section also NX x86: fix iret exception recovery on 64-bit cpuidle: dubious one-bit signed bitfield in cpuidle.h x86: fix sparse warnings in powernow-k8.c x86: fix sparse error in traps_32.c x86: trivial sparse/checkpatch in quirks.c x86 ptrace: disallow null cs/ss MAINTAINERS: RDC R-321x SoC maintainer brk randomization: introduce CONFIG_COMPAT_BRK brk: check the lower bound properly x86: remove X2 workaround x86: make spurious fault handler aware of large mappings x86: make traps on entry code be debuggable in user space, 64-bit
Diffstat (limited to 'arch/x86/mm/pageattr.c')
-rw-r--r--arch/x86/mm/pageattr.c14
1 files changed, 0 insertions, 14 deletions
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 16ce841f08d6..8493c855582b 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -167,8 +167,6 @@ static inline pgprot_t static_protections(pgprot_t prot, unsigned long address)
167 if (within(address, virt_to_highmap(_text), virt_to_highmap(_etext))) 167 if (within(address, virt_to_highmap(_text), virt_to_highmap(_etext)))
168 pgprot_val(forbidden) |= _PAGE_NX; 168 pgprot_val(forbidden) |= _PAGE_NX;
169 169
170
171#ifdef CONFIG_DEBUG_RODATA
172 /* The .rodata section needs to be read-only */ 170 /* The .rodata section needs to be read-only */
173 if (within(address, (unsigned long)__start_rodata, 171 if (within(address, (unsigned long)__start_rodata,
174 (unsigned long)__end_rodata)) 172 (unsigned long)__end_rodata))
@@ -179,7 +177,6 @@ static inline pgprot_t static_protections(pgprot_t prot, unsigned long address)
179 if (within(address, virt_to_highmap(__start_rodata), 177 if (within(address, virt_to_highmap(__start_rodata),
180 virt_to_highmap(__end_rodata))) 178 virt_to_highmap(__end_rodata)))
181 pgprot_val(forbidden) |= _PAGE_RW; 179 pgprot_val(forbidden) |= _PAGE_RW;
182#endif
183 180
184 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); 181 prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
185 182
@@ -260,17 +257,6 @@ try_preserve_large_page(pte_t *kpte, unsigned long address,
260 pgprot_t old_prot, new_prot; 257 pgprot_t old_prot, new_prot;
261 int level, do_split = 1; 258 int level, do_split = 1;
262 259
263 /*
264 * An Athlon 64 X2 showed hard hangs if we tried to preserve
265 * largepages and changed the PSE entry from RW to RO.
266 *
267 * As AMD CPUs have a long series of erratas in this area,
268 * (and none of the known ones seem to explain this hang),
269 * disable this code until the hang can be debugged:
270 */
271 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
272 return 1;
273
274 spin_lock_irqsave(&pgd_lock, flags); 260 spin_lock_irqsave(&pgd_lock, flags);
275 /* 261 /*
276 * Check for races, another CPU might have split this page 262 * Check for races, another CPU might have split this page