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authorAvi Kivity <avi.kivity@gmail.com>2013-02-09 04:31:46 -0500
committerGleb Natapov <gleb@redhat.com>2013-05-21 08:43:17 -0400
commitab2c5ce66661e07c315a53bef9b507cf766d7905 (patch)
tree2d847fc55edc97bead2329a088e4bdf90fc1c41b /arch/x86/kvm/emulate.c
parent820207c8fc508be8f104d4d6b19c8f695fe0d5f3 (diff)
KVM: x86 emulator: switch MUL/DIV to DstXacc
Signed-off-by: Avi Kivity <avi.kivity@gmail.com> Signed-off-by: Gleb Natapov <gleb@redhat.com>
Diffstat (limited to 'arch/x86/kvm/emulate.c')
-rw-r--r--arch/x86/kvm/emulate.c15
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 36cb786122fe..b9fb89b4ee26 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -142,6 +142,7 @@
142/* Source 2 operand type */ 142/* Source 2 operand type */
143#define Src2Shift (31) 143#define Src2Shift (31)
144#define Src2None (OpNone << Src2Shift) 144#define Src2None (OpNone << Src2Shift)
145#define Src2Mem (OpMem << Src2Shift)
145#define Src2CL (OpCL << Src2Shift) 146#define Src2CL (OpCL << Src2Shift)
146#define Src2ImmByte (OpImmByte << Src2Shift) 147#define Src2ImmByte (OpImmByte << Src2Shift)
147#define Src2One (OpOne << Src2Shift) 148#define Src2One (OpOne << Src2Shift)
@@ -548,8 +549,8 @@ FOP_END;
548#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \ 549#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \
549 do { \ 550 do { \
550 unsigned long _tmp; \ 551 unsigned long _tmp; \
551 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \ 552 ulong *rax = &ctxt->dst.val; \
552 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \ 553 ulong *rdx = &ctxt->src.val; \
553 \ 554 \
554 __asm__ __volatile__ ( \ 555 __asm__ __volatile__ ( \
555 _PRE_EFLAGS("0", "5", "1") \ 556 _PRE_EFLAGS("0", "5", "1") \
@@ -564,7 +565,7 @@ FOP_END;
564 _ASM_EXTABLE(1b, 3b) \ 565 _ASM_EXTABLE(1b, 3b) \
565 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \ 566 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \
566 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \ 567 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \
567 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \ 568 : "i" (EFLAGS_MASK), "m" ((ctxt)->src2.val)); \
568 } while (0) 569 } while (0)
569 570
570/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ 571/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
@@ -3735,10 +3736,10 @@ static const struct opcode group3[] = {
3735 F(DstMem | SrcImm | NoWrite, em_test), 3736 F(DstMem | SrcImm | NoWrite, em_test),
3736 F(DstMem | SrcNone | Lock, em_not), 3737 F(DstMem | SrcNone | Lock, em_not),
3737 F(DstMem | SrcNone | Lock, em_neg), 3738 F(DstMem | SrcNone | Lock, em_neg),
3738 I(SrcMem, em_mul_ex), 3739 I(DstXacc | Src2Mem, em_mul_ex),
3739 I(SrcMem, em_imul_ex), 3740 I(DstXacc | Src2Mem, em_imul_ex),
3740 I(SrcMem, em_div_ex), 3741 I(DstXacc | Src2Mem, em_div_ex),
3741 I(SrcMem, em_idiv_ex), 3742 I(DstXacc | Src2Mem, em_idiv_ex),
3742}; 3743};
3743 3744
3744static const struct opcode group4[] = { 3745static const struct opcode group4[] = {