x86, mce: fix reporting of Thermal Monitoring mechanism enabled

Early Pentium M models use different method for enabling TM2
(per paragraph 13.5.2.3 of the "Intel 64 and IA-32 Architectures
Software Developer's Manual Volume 3A: System Programming Guide,
Part 1").

Tested on the affected Pentium M variant (model == 13).

Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Cc: Andi Kleen <andi@firstfloor.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>

1 files changed, 10 insertions, 3 deletions

diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index bff8dd191dd5..15f2bc07bb60 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -253,9 +253,6 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
                 return;
         }
 
-        if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))
-                tm2 = 1;
-
         /* Check whether a vector already exists */
         if (h & APIC_VECTOR_MASK) {
                 printk(KERN_DEBUG
@@ -264,6 +261,16 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
                 return;
         }
 
+        /* early Pentium M models use different method for enabling TM2 */
+        if (cpu_has(c, X86_FEATURE_TM2)) {
+                if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
+                        rdmsr(MSR_THERM2_CTL, l, h);
+                        if (l & MSR_THERM2_CTL_TM_SELECT)
+                                tm2 = 1;
+                } else if (l & MSR_IA32_MISC_ENABLE_TM2)
+                        tm2 = 1;
+        }
+
         /* We'll mask the thermal vector in the lapic till we're ready: */
         h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
         apic_write(APIC_LVTTHMR, h);