diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2009-05-23 15:57:31 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-05-23 15:57:31 -0400 |
commit | a2ab67fae1ab9226679495a8d260f4e6555efc5f (patch) | |
tree | f7de683c9c8ff0869a7e11f1d40802145d05f5b4 /arch/x86/kernel | |
parent | 6d0485a99366d4e0e7e725f14995c74cb7ca4499 (diff) | |
parent | 135cad366b4e7d6a79f6369f6cb5b721985aa62f (diff) |
Merge branch 'for-rmk-devel' of git://git.pengutronix.de/git/imx/linux-2.6 into devel
Conflicts:
arch/arm/Kconfig
arch/arm/Makefile
Diffstat (limited to 'arch/x86/kernel')
-rw-r--r-- | arch/x86/kernel/apic/io_apic.c | 2 | ||||
-rw-r--r-- | arch/x86/kernel/apic/nmi.c | 5 | ||||
-rw-r--r-- | arch/x86/kernel/apic/x2apic_uv_x.c | 15 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/mcheck/mce_64.c | 33 | ||||
-rw-r--r-- | arch/x86/kernel/entry_64.S | 3 | ||||
-rw-r--r-- | arch/x86/kernel/hpet.c | 18 | ||||
-rw-r--r-- | arch/x86/kernel/quirks.c | 2 | ||||
-rw-r--r-- | arch/x86/kernel/uv_time.c | 10 | ||||
-rw-r--r-- | arch/x86/kernel/xsave.c | 4 |
9 files changed, 65 insertions, 27 deletions
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index a2789e42e162..30da617d18e4 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c | |||
@@ -3670,12 +3670,14 @@ int arch_setup_hpet_msi(unsigned int irq) | |||
3670 | { | 3670 | { |
3671 | int ret; | 3671 | int ret; |
3672 | struct msi_msg msg; | 3672 | struct msi_msg msg; |
3673 | struct irq_desc *desc = irq_to_desc(irq); | ||
3673 | 3674 | ||
3674 | ret = msi_compose_msg(NULL, irq, &msg); | 3675 | ret = msi_compose_msg(NULL, irq, &msg); |
3675 | if (ret < 0) | 3676 | if (ret < 0) |
3676 | return ret; | 3677 | return ret; |
3677 | 3678 | ||
3678 | hpet_msi_write(irq, &msg); | 3679 | hpet_msi_write(irq, &msg); |
3680 | desc->status |= IRQ_MOVE_PCNTXT; | ||
3679 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, | 3681 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, |
3680 | "edge"); | 3682 | "edge"); |
3681 | 3683 | ||
diff --git a/arch/x86/kernel/apic/nmi.c b/arch/x86/kernel/apic/nmi.c index d6bd62407152..ce4fbfa315a1 100644 --- a/arch/x86/kernel/apic/nmi.c +++ b/arch/x86/kernel/apic/nmi.c | |||
@@ -138,7 +138,7 @@ int __init check_nmi_watchdog(void) | |||
138 | if (!prev_nmi_count) | 138 | if (!prev_nmi_count) |
139 | goto error; | 139 | goto error; |
140 | 140 | ||
141 | alloc_cpumask_var(&backtrace_mask, GFP_KERNEL); | 141 | alloc_cpumask_var(&backtrace_mask, GFP_KERNEL|__GFP_ZERO); |
142 | printk(KERN_INFO "Testing NMI watchdog ... "); | 142 | printk(KERN_INFO "Testing NMI watchdog ... "); |
143 | 143 | ||
144 | #ifdef CONFIG_SMP | 144 | #ifdef CONFIG_SMP |
@@ -414,7 +414,8 @@ nmi_watchdog_tick(struct pt_regs *regs, unsigned reason) | |||
414 | touched = 1; | 414 | touched = 1; |
415 | } | 415 | } |
416 | 416 | ||
417 | if (cpumask_test_cpu(cpu, backtrace_mask)) { | 417 | /* We can be called before check_nmi_watchdog, hence NULL check. */ |
418 | if (backtrace_mask != NULL && cpumask_test_cpu(cpu, backtrace_mask)) { | ||
418 | static DEFINE_SPINLOCK(lock); /* Serialise the printks */ | 419 | static DEFINE_SPINLOCK(lock); /* Serialise the printks */ |
419 | 420 | ||
420 | spin_lock(&lock); | 421 | spin_lock(&lock); |
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index de1a50af807b..2bda69352976 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <linux/timer.h> | 19 | #include <linux/timer.h> |
20 | #include <linux/cpu.h> | 20 | #include <linux/cpu.h> |
21 | #include <linux/init.h> | 21 | #include <linux/init.h> |
22 | #include <linux/io.h> | ||
22 | 23 | ||
23 | #include <asm/uv/uv_mmrs.h> | 24 | #include <asm/uv/uv_mmrs.h> |
24 | #include <asm/uv/uv_hub.h> | 25 | #include <asm/uv/uv_hub.h> |
@@ -34,6 +35,17 @@ DEFINE_PER_CPU(int, x2apic_extra_bits); | |||
34 | 35 | ||
35 | static enum uv_system_type uv_system_type; | 36 | static enum uv_system_type uv_system_type; |
36 | 37 | ||
38 | static int early_get_nodeid(void) | ||
39 | { | ||
40 | union uvh_node_id_u node_id; | ||
41 | unsigned long *mmr; | ||
42 | |||
43 | mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr)); | ||
44 | node_id.v = *mmr; | ||
45 | early_iounmap(mmr, sizeof(*mmr)); | ||
46 | return node_id.s.node_id; | ||
47 | } | ||
48 | |||
37 | static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) | 49 | static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
38 | { | 50 | { |
39 | if (!strcmp(oem_id, "SGI")) { | 51 | if (!strcmp(oem_id, "SGI")) { |
@@ -42,6 +54,8 @@ static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) | |||
42 | else if (!strcmp(oem_table_id, "UVX")) | 54 | else if (!strcmp(oem_table_id, "UVX")) |
43 | uv_system_type = UV_X2APIC; | 55 | uv_system_type = UV_X2APIC; |
44 | else if (!strcmp(oem_table_id, "UVH")) { | 56 | else if (!strcmp(oem_table_id, "UVH")) { |
57 | __get_cpu_var(x2apic_extra_bits) = | ||
58 | early_get_nodeid() << (UV_APIC_PNODE_SHIFT - 1); | ||
45 | uv_system_type = UV_NON_UNIQUE_APIC; | 59 | uv_system_type = UV_NON_UNIQUE_APIC; |
46 | return 1; | 60 | return 1; |
47 | } | 61 | } |
@@ -638,6 +652,7 @@ void __init uv_system_init(void) | |||
638 | if (uv_node_to_blade[nid] >= 0) | 652 | if (uv_node_to_blade[nid] >= 0) |
639 | continue; | 653 | continue; |
640 | paddr = node_start_pfn(nid) << PAGE_SHIFT; | 654 | paddr = node_start_pfn(nid) << PAGE_SHIFT; |
655 | paddr = uv_soc_phys_ram_to_gpa(paddr); | ||
641 | pnode = (paddr >> m_val) & pnode_mask; | 656 | pnode = (paddr >> m_val) & pnode_mask; |
642 | blade = boot_pnode_to_blade(pnode); | 657 | blade = boot_pnode_to_blade(pnode); |
643 | uv_node_to_blade[nid] = blade; | 658 | uv_node_to_blade[nid] = blade; |
diff --git a/arch/x86/kernel/cpu/mcheck/mce_64.c b/arch/x86/kernel/cpu/mcheck/mce_64.c index 863f89568b1a..6fb0b359d2a5 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_64.c +++ b/arch/x86/kernel/cpu/mcheck/mce_64.c | |||
@@ -239,9 +239,10 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) | |||
239 | * Don't get the IP here because it's unlikely to | 239 | * Don't get the IP here because it's unlikely to |
240 | * have anything to do with the actual error location. | 240 | * have anything to do with the actual error location. |
241 | */ | 241 | */ |
242 | 242 | if (!(flags & MCP_DONTLOG)) { | |
243 | mce_log(&m); | 243 | mce_log(&m); |
244 | add_taint(TAINT_MACHINE_CHECK); | 244 | add_taint(TAINT_MACHINE_CHECK); |
245 | } | ||
245 | 246 | ||
246 | /* | 247 | /* |
247 | * Clear state for this bank. | 248 | * Clear state for this bank. |
@@ -452,13 +453,14 @@ void mce_log_therm_throt_event(__u64 status) | |||
452 | */ | 453 | */ |
453 | 454 | ||
454 | static int check_interval = 5 * 60; /* 5 minutes */ | 455 | static int check_interval = 5 * 60; /* 5 minutes */ |
455 | static int next_interval; /* in jiffies */ | 456 | static DEFINE_PER_CPU(int, next_interval); /* in jiffies */ |
456 | static void mcheck_timer(unsigned long); | 457 | static void mcheck_timer(unsigned long); |
457 | static DEFINE_PER_CPU(struct timer_list, mce_timer); | 458 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
458 | 459 | ||
459 | static void mcheck_timer(unsigned long data) | 460 | static void mcheck_timer(unsigned long data) |
460 | { | 461 | { |
461 | struct timer_list *t = &per_cpu(mce_timer, data); | 462 | struct timer_list *t = &per_cpu(mce_timer, data); |
463 | int *n; | ||
462 | 464 | ||
463 | WARN_ON(smp_processor_id() != data); | 465 | WARN_ON(smp_processor_id() != data); |
464 | 466 | ||
@@ -470,14 +472,14 @@ static void mcheck_timer(unsigned long data) | |||
470 | * Alert userspace if needed. If we logged an MCE, reduce the | 472 | * Alert userspace if needed. If we logged an MCE, reduce the |
471 | * polling interval, otherwise increase the polling interval. | 473 | * polling interval, otherwise increase the polling interval. |
472 | */ | 474 | */ |
475 | n = &__get_cpu_var(next_interval); | ||
473 | if (mce_notify_user()) { | 476 | if (mce_notify_user()) { |
474 | next_interval = max(next_interval/2, HZ/100); | 477 | *n = max(*n/2, HZ/100); |
475 | } else { | 478 | } else { |
476 | next_interval = min(next_interval * 2, | 479 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
477 | (int)round_jiffies_relative(check_interval*HZ)); | ||
478 | } | 480 | } |
479 | 481 | ||
480 | t->expires = jiffies + next_interval; | 482 | t->expires = jiffies + *n; |
481 | add_timer(t); | 483 | add_timer(t); |
482 | } | 484 | } |
483 | 485 | ||
@@ -584,7 +586,7 @@ static void mce_init(void *dummy) | |||
584 | * Log the machine checks left over from the previous reset. | 586 | * Log the machine checks left over from the previous reset. |
585 | */ | 587 | */ |
586 | bitmap_fill(all_banks, MAX_NR_BANKS); | 588 | bitmap_fill(all_banks, MAX_NR_BANKS); |
587 | machine_check_poll(MCP_UC, &all_banks); | 589 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
588 | 590 | ||
589 | set_in_cr4(X86_CR4_MCE); | 591 | set_in_cr4(X86_CR4_MCE); |
590 | 592 | ||
@@ -632,14 +634,13 @@ static void mce_cpu_features(struct cpuinfo_x86 *c) | |||
632 | static void mce_init_timer(void) | 634 | static void mce_init_timer(void) |
633 | { | 635 | { |
634 | struct timer_list *t = &__get_cpu_var(mce_timer); | 636 | struct timer_list *t = &__get_cpu_var(mce_timer); |
637 | int *n = &__get_cpu_var(next_interval); | ||
635 | 638 | ||
636 | /* data race harmless because everyone sets to the same value */ | 639 | *n = check_interval * HZ; |
637 | if (!next_interval) | 640 | if (!*n) |
638 | next_interval = check_interval * HZ; | ||
639 | if (!next_interval) | ||
640 | return; | 641 | return; |
641 | setup_timer(t, mcheck_timer, smp_processor_id()); | 642 | setup_timer(t, mcheck_timer, smp_processor_id()); |
642 | t->expires = round_jiffies(jiffies + next_interval); | 643 | t->expires = round_jiffies(jiffies + *n); |
643 | add_timer(t); | 644 | add_timer(t); |
644 | } | 645 | } |
645 | 646 | ||
@@ -907,7 +908,6 @@ static void mce_cpu_restart(void *data) | |||
907 | /* Reinit MCEs after user configuration changes */ | 908 | /* Reinit MCEs after user configuration changes */ |
908 | static void mce_restart(void) | 909 | static void mce_restart(void) |
909 | { | 910 | { |
910 | next_interval = check_interval * HZ; | ||
911 | on_each_cpu(mce_cpu_restart, NULL, 1); | 911 | on_each_cpu(mce_cpu_restart, NULL, 1); |
912 | } | 912 | } |
913 | 913 | ||
@@ -1110,7 +1110,8 @@ static int __cpuinit mce_cpu_callback(struct notifier_block *nfb, | |||
1110 | break; | 1110 | break; |
1111 | case CPU_DOWN_FAILED: | 1111 | case CPU_DOWN_FAILED: |
1112 | case CPU_DOWN_FAILED_FROZEN: | 1112 | case CPU_DOWN_FAILED_FROZEN: |
1113 | t->expires = round_jiffies(jiffies + next_interval); | 1113 | t->expires = round_jiffies(jiffies + |
1114 | __get_cpu_var(next_interval)); | ||
1114 | add_timer_on(t, cpu); | 1115 | add_timer_on(t, cpu); |
1115 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); | 1116 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1116 | break; | 1117 | break; |
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S index a331ec38af9e..38946c6e8433 100644 --- a/arch/x86/kernel/entry_64.S +++ b/arch/x86/kernel/entry_64.S | |||
@@ -1410,7 +1410,10 @@ ENTRY(paranoid_exit) | |||
1410 | paranoid_swapgs: | 1410 | paranoid_swapgs: |
1411 | TRACE_IRQS_IRETQ 0 | 1411 | TRACE_IRQS_IRETQ 0 |
1412 | SWAPGS_UNSAFE_STACK | 1412 | SWAPGS_UNSAFE_STACK |
1413 | RESTORE_ALL 8 | ||
1414 | jmp irq_return | ||
1413 | paranoid_restore: | 1415 | paranoid_restore: |
1416 | TRACE_IRQS_IRETQ 0 | ||
1414 | RESTORE_ALL 8 | 1417 | RESTORE_ALL 8 |
1415 | jmp irq_return | 1418 | jmp irq_return |
1416 | paranoid_userspace: | 1419 | paranoid_userspace: |
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 3f0019e0a229..81408b93f887 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c | |||
@@ -236,6 +236,10 @@ static void hpet_stop_counter(void) | |||
236 | unsigned long cfg = hpet_readl(HPET_CFG); | 236 | unsigned long cfg = hpet_readl(HPET_CFG); |
237 | cfg &= ~HPET_CFG_ENABLE; | 237 | cfg &= ~HPET_CFG_ENABLE; |
238 | hpet_writel(cfg, HPET_CFG); | 238 | hpet_writel(cfg, HPET_CFG); |
239 | } | ||
240 | |||
241 | static void hpet_reset_counter(void) | ||
242 | { | ||
239 | hpet_writel(0, HPET_COUNTER); | 243 | hpet_writel(0, HPET_COUNTER); |
240 | hpet_writel(0, HPET_COUNTER + 4); | 244 | hpet_writel(0, HPET_COUNTER + 4); |
241 | } | 245 | } |
@@ -250,6 +254,7 @@ static void hpet_start_counter(void) | |||
250 | static void hpet_restart_counter(void) | 254 | static void hpet_restart_counter(void) |
251 | { | 255 | { |
252 | hpet_stop_counter(); | 256 | hpet_stop_counter(); |
257 | hpet_reset_counter(); | ||
253 | hpet_start_counter(); | 258 | hpet_start_counter(); |
254 | } | 259 | } |
255 | 260 | ||
@@ -309,7 +314,7 @@ static int hpet_setup_msi_irq(unsigned int irq); | |||
309 | static void hpet_set_mode(enum clock_event_mode mode, | 314 | static void hpet_set_mode(enum clock_event_mode mode, |
310 | struct clock_event_device *evt, int timer) | 315 | struct clock_event_device *evt, int timer) |
311 | { | 316 | { |
312 | unsigned long cfg; | 317 | unsigned long cfg, cmp, now; |
313 | uint64_t delta; | 318 | uint64_t delta; |
314 | 319 | ||
315 | switch (mode) { | 320 | switch (mode) { |
@@ -317,12 +322,23 @@ static void hpet_set_mode(enum clock_event_mode mode, | |||
317 | hpet_stop_counter(); | 322 | hpet_stop_counter(); |
318 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; | 323 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; |
319 | delta >>= evt->shift; | 324 | delta >>= evt->shift; |
325 | now = hpet_readl(HPET_COUNTER); | ||
326 | cmp = now + (unsigned long) delta; | ||
320 | cfg = hpet_readl(HPET_Tn_CFG(timer)); | 327 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
321 | /* Make sure we use edge triggered interrupts */ | 328 | /* Make sure we use edge triggered interrupts */ |
322 | cfg &= ~HPET_TN_LEVEL; | 329 | cfg &= ~HPET_TN_LEVEL; |
323 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | | 330 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | |
324 | HPET_TN_SETVAL | HPET_TN_32BIT; | 331 | HPET_TN_SETVAL | HPET_TN_32BIT; |
325 | hpet_writel(cfg, HPET_Tn_CFG(timer)); | 332 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
333 | hpet_writel(cmp, HPET_Tn_CMP(timer)); | ||
334 | udelay(1); | ||
335 | /* | ||
336 | * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL | ||
337 | * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL | ||
338 | * bit is automatically cleared after the first write. | ||
339 | * (See AMD-8111 HyperTransport I/O Hub Data Sheet, | ||
340 | * Publication # 24674) | ||
341 | */ | ||
326 | hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer)); | 342 | hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer)); |
327 | hpet_start_counter(); | 343 | hpet_start_counter(); |
328 | hpet_print_config(); | 344 | hpet_print_config(); |
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c index e95022e4f5d5..7563b31b4f03 100644 --- a/arch/x86/kernel/quirks.c +++ b/arch/x86/kernel/quirks.c | |||
@@ -261,8 +261,6 @@ static void old_ich_force_enable_hpet_user(struct pci_dev *dev) | |||
261 | { | 261 | { |
262 | if (hpet_force_user) | 262 | if (hpet_force_user) |
263 | old_ich_force_enable_hpet(dev); | 263 | old_ich_force_enable_hpet(dev); |
264 | else | ||
265 | hpet_print_force_info(); | ||
266 | } | 264 | } |
267 | 265 | ||
268 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, | 266 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, |
diff --git a/arch/x86/kernel/uv_time.c b/arch/x86/kernel/uv_time.c index 2ffb6c53326e..583f11d5c480 100644 --- a/arch/x86/kernel/uv_time.c +++ b/arch/x86/kernel/uv_time.c | |||
@@ -29,7 +29,7 @@ | |||
29 | 29 | ||
30 | #define RTC_NAME "sgi_rtc" | 30 | #define RTC_NAME "sgi_rtc" |
31 | 31 | ||
32 | static cycle_t uv_read_rtc(void); | 32 | static cycle_t uv_read_rtc(struct clocksource *cs); |
33 | static int uv_rtc_next_event(unsigned long, struct clock_event_device *); | 33 | static int uv_rtc_next_event(unsigned long, struct clock_event_device *); |
34 | static void uv_rtc_timer_setup(enum clock_event_mode, | 34 | static void uv_rtc_timer_setup(enum clock_event_mode, |
35 | struct clock_event_device *); | 35 | struct clock_event_device *); |
@@ -123,7 +123,7 @@ static int uv_setup_intr(int cpu, u64 expires) | |||
123 | /* Initialize comparator value */ | 123 | /* Initialize comparator value */ |
124 | uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires); | 124 | uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires); |
125 | 125 | ||
126 | return (expires < uv_read_rtc() && !uv_intr_pending(pnode)); | 126 | return (expires < uv_read_rtc(NULL) && !uv_intr_pending(pnode)); |
127 | } | 127 | } |
128 | 128 | ||
129 | /* | 129 | /* |
@@ -256,7 +256,7 @@ static int uv_rtc_unset_timer(int cpu) | |||
256 | 256 | ||
257 | spin_lock_irqsave(&head->lock, flags); | 257 | spin_lock_irqsave(&head->lock, flags); |
258 | 258 | ||
259 | if (head->next_cpu == bcpu && uv_read_rtc() >= *t) | 259 | if (head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) |
260 | rc = 1; | 260 | rc = 1; |
261 | 261 | ||
262 | *t = ULLONG_MAX; | 262 | *t = ULLONG_MAX; |
@@ -278,7 +278,7 @@ static int uv_rtc_unset_timer(int cpu) | |||
278 | /* | 278 | /* |
279 | * Read the RTC. | 279 | * Read the RTC. |
280 | */ | 280 | */ |
281 | static cycle_t uv_read_rtc(void) | 281 | static cycle_t uv_read_rtc(struct clocksource *cs) |
282 | { | 282 | { |
283 | return (cycle_t)uv_read_local_mmr(UVH_RTC); | 283 | return (cycle_t)uv_read_local_mmr(UVH_RTC); |
284 | } | 284 | } |
@@ -291,7 +291,7 @@ static int uv_rtc_next_event(unsigned long delta, | |||
291 | { | 291 | { |
292 | int ced_cpu = cpumask_first(ced->cpumask); | 292 | int ced_cpu = cpumask_first(ced->cpumask); |
293 | 293 | ||
294 | return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc()); | 294 | return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL)); |
295 | } | 295 | } |
296 | 296 | ||
297 | /* | 297 | /* |
diff --git a/arch/x86/kernel/xsave.c b/arch/x86/kernel/xsave.c index 0a5b04aa98f1..c5ee17e8c6d9 100644 --- a/arch/x86/kernel/xsave.c +++ b/arch/x86/kernel/xsave.c | |||
@@ -89,7 +89,7 @@ int save_i387_xstate(void __user *buf) | |||
89 | 89 | ||
90 | if (!used_math()) | 90 | if (!used_math()) |
91 | return 0; | 91 | return 0; |
92 | clear_used_math(); /* trigger finit */ | 92 | |
93 | if (task_thread_info(tsk)->status & TS_USEDFPU) { | 93 | if (task_thread_info(tsk)->status & TS_USEDFPU) { |
94 | /* | 94 | /* |
95 | * Start with clearing the user buffer. This will present a | 95 | * Start with clearing the user buffer. This will present a |
@@ -114,6 +114,8 @@ int save_i387_xstate(void __user *buf) | |||
114 | return -1; | 114 | return -1; |
115 | } | 115 | } |
116 | 116 | ||
117 | clear_used_math(); /* trigger finit */ | ||
118 | |||
117 | if (task_thread_info(tsk)->status & TS_XSAVE) { | 119 | if (task_thread_info(tsk)->status & TS_XSAVE) { |
118 | struct _fpstate __user *fx = buf; | 120 | struct _fpstate __user *fx = buf; |
119 | struct _xstate __user *x = buf; | 121 | struct _xstate __user *x = buf; |