diff options
author | Vince Weaver <vincent.weaver@maine.edu> | 2012-10-19 17:33:38 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@kernel.org> | 2012-10-24 04:32:00 -0400 |
commit | 58e9eaf06f5476cb2192ec1d012674ce5e79dd21 (patch) | |
tree | 9e5d64ad3aa856c29b39c941bae67490e89b87dd /arch/x86/kernel | |
parent | e09df47885d767e418902067ce1885aafa3b27db (diff) |
perf/x86: Remove P6 cpuc->enabled check
Between 2.6.33 and 2.6.34 the PMU code was made modular.
The x86_pmu_enable() call was extended to disable cpuc->enabled
and iterate the counters, enabling one at a time, before calling
enable_all() at the end, followed by re-enabling cpuc->enabled.
Since cpuc->enabled was set to 0, that change effectively caused
the "val |= ARCH_PERFMON_EVENTSEL_ENABLE;" code in p6_pmu_enable_event()
and p6_pmu_disable_event() to be dead code that was never called.
This change removes this code (which was confusing) and adds some
extra commentary to make it more clear what is going on.
Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1210191732000.14552@vincent-weaver-1.um.maine.edu
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel')
-rw-r--r-- | arch/x86/kernel/cpu/perf_event_p6.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c index 9582fcbcd8ec..7d0270bd793e 100644 --- a/arch/x86/kernel/cpu/perf_event_p6.c +++ b/arch/x86/kernel/cpu/perf_event_p6.c | |||
@@ -157,25 +157,25 @@ static void p6_pmu_enable_all(int added) | |||
157 | static inline void | 157 | static inline void |
158 | p6_pmu_disable_event(struct perf_event *event) | 158 | p6_pmu_disable_event(struct perf_event *event) |
159 | { | 159 | { |
160 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | ||
161 | struct hw_perf_event *hwc = &event->hw; | 160 | struct hw_perf_event *hwc = &event->hw; |
162 | u64 val = P6_NOP_EVENT; | 161 | u64 val = P6_NOP_EVENT; |
163 | 162 | ||
164 | if (cpuc->enabled) | ||
165 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; | ||
166 | |||
167 | (void)wrmsrl_safe(hwc->config_base, val); | 163 | (void)wrmsrl_safe(hwc->config_base, val); |
168 | } | 164 | } |
169 | 165 | ||
170 | static void p6_pmu_enable_event(struct perf_event *event) | 166 | static void p6_pmu_enable_event(struct perf_event *event) |
171 | { | 167 | { |
172 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | ||
173 | struct hw_perf_event *hwc = &event->hw; | 168 | struct hw_perf_event *hwc = &event->hw; |
174 | u64 val; | 169 | u64 val; |
175 | 170 | ||
176 | val = hwc->config; | 171 | val = hwc->config; |
177 | if (cpuc->enabled) | 172 | |
178 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; | 173 | /* |
174 | * p6 only has a global event enable, set on PerfEvtSel0 | ||
175 | * We "disable" events by programming P6_NOP_EVENT | ||
176 | * and we rely on p6_pmu_enable_all() being called | ||
177 | * to actually enable the events. | ||
178 | */ | ||
179 | 179 | ||
180 | (void)wrmsrl_safe(hwc->config_base, val); | 180 | (void)wrmsrl_safe(hwc->config_base, val); |
181 | } | 181 | } |