x86: make /proc/stat account for all interrupts

LAPIC interrupts, which don't go through the generic interrupt handling
code, aren't accounted for in /proc/stat. Hence this patch adds a
mechanism architectures can use to accordingly adjust the statistics.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

1 files changed, 28 insertions, 0 deletions

diff --git a/arch/x86/kernel/irq_64.c b/arch/x86/kernel/irq_64.c
index 3aac15466a91..1f78b238d8d2 100644
--- a/arch/x86/kernel/irq_64.c
+++ b/arch/x86/kernel/irq_64.c
@@ -135,6 +135,7 @@ skip:
                         seq_printf(p, "%10u ", cpu_pda(j)->irq_tlb_count);
                 seq_printf(p, "  TLB shootdowns\n");
 #endif
+#ifdef CONFIG_X86_MCE
                 seq_printf(p, "TRM: ");
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ", cpu_pda(j)->irq_thermal_count);
@@ -143,6 +144,7 @@ skip:
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ", cpu_pda(j)->irq_threshold_count);
                 seq_printf(p, "  Threshold APIC interrupts\n");
+#endif
                 seq_printf(p, "SPU: ");
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ", cpu_pda(j)->irq_spurious_count);
@@ -153,6 +155,32 @@ skip:
 }
 
 /*
+ * /proc/stat helpers
+ */
+u64 arch_irq_stat_cpu(unsigned int cpu)
+{
+        u64 sum = cpu_pda(cpu)->__nmi_count;
+
+        sum += cpu_pda(cpu)->apic_timer_irqs;
+#ifdef CONFIG_SMP
+        sum += cpu_pda(cpu)->irq_resched_count;
+        sum += cpu_pda(cpu)->irq_call_count;
+        sum += cpu_pda(cpu)->irq_tlb_count;
+#endif
+#ifdef CONFIG_X86_MCE
+        sum += cpu_pda(cpu)->irq_thermal_count;
+        sum += cpu_pda(cpu)->irq_threshold_count;
+#endif
+        sum += cpu_pda(cpu)->irq_spurious_count;
+        return sum;
+}
+
+u64 arch_irq_stat(void)
+{
+        return atomic_read(&irq_err_count);
+}
+
+/*
  * do_IRQ handles all normal device IRQ's (the special
  * SMP cross-CPU interrupts have their own specific
  * handlers).