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authorMaria Dimakopoulou <maria.n.dimakopoulou@gmail.com>2014-11-17 14:07:00 -0500
committerIngo Molnar <mingo@kernel.org>2015-04-02 11:33:13 -0400
commitb63b4b459a78a9a45ea47a4803b8d1868e9d17d5 (patch)
treef7b343da87412c3c226702a5cf31d148f18c1dcd /arch/x86/kernel/cpu
parent93fcf72cc0fa286aa8c3e11a1a8fd4659f0e27c0 (diff)
perf/x86/intel: Enforce HT bug workaround with PEBS for SNB/IVB/HSW
This patch modifies the PEBS constraint tables for SNB/IVB/HSW such that corrupting events supporting PEBS activate the HT workaround. Signed-off-by: Maria Dimakopoulou <maria.n.dimakopoulou@gmail.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Stephane Eranian <eranian@google.com> Cc: bp@alien8.de Cc: jolsa@redhat.com Cc: kan.liang@intel.com Link: http://lkml.kernel.org/r/1416251225-17721-9-git-send-email-eranian@google.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel/cpu')
-rw-r--r--arch/x86/kernel/cpu/perf_event.h20
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_ds.c28
2 files changed, 37 insertions, 11 deletions
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index 236afee35587..2ba71ecc244f 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -326,22 +326,40 @@ struct cpu_hw_events {
326 326
327/* Check flags and event code, and set the HSW load flag */ 327/* Check flags and event code, and set the HSW load flag */
328#define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \ 328#define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
329 __EVENT_CONSTRAINT(code, n, \ 329 __EVENT_CONSTRAINT(code, n, \
330 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \ 330 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
331 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 331 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
332 332
333#define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
334 __EVENT_CONSTRAINT(code, n, \
335 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
336 HWEIGHT(n), 0, \
337 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
338
333/* Check flags and event code/umask, and set the HSW store flag */ 339/* Check flags and event code/umask, and set the HSW store flag */
334#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \ 340#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
335 __EVENT_CONSTRAINT(code, n, \ 341 __EVENT_CONSTRAINT(code, n, \
336 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 342 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
337 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW) 343 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
338 344
345#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
346 __EVENT_CONSTRAINT(code, n, \
347 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
348 HWEIGHT(n), 0, \
349 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
350
339/* Check flags and event code/umask, and set the HSW load flag */ 351/* Check flags and event code/umask, and set the HSW load flag */
340#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \ 352#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
341 __EVENT_CONSTRAINT(code, n, \ 353 __EVENT_CONSTRAINT(code, n, \
342 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \ 354 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
343 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW) 355 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
344 356
357#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
358 __EVENT_CONSTRAINT(code, n, \
359 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
360 HWEIGHT(n), 0, \
361 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
362
345/* Check flags and event code/umask, and set the HSW N/A flag */ 363/* Check flags and event code/umask, and set the HSW N/A flag */
346#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \ 364#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
347 __EVENT_CONSTRAINT(code, n, \ 365 __EVENT_CONSTRAINT(code, n, \
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index a5149c7abe73..ca69ea56c712 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -612,6 +612,10 @@ struct event_constraint intel_snb_pebs_event_constraints[] = {
612 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ 612 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
613 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 613 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
614 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 614 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
615 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
616 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
617 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
618 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
615 /* Allow all events as PEBS with no flags */ 619 /* Allow all events as PEBS with no flags */
616 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 620 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
617 EVENT_CONSTRAINT_END 621 EVENT_CONSTRAINT_END
@@ -623,6 +627,10 @@ struct event_constraint intel_ivb_pebs_event_constraints[] = {
623 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ 627 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
624 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 628 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
625 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 629 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
630 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
631 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
632 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
633 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
626 /* Allow all events as PEBS with no flags */ 634 /* Allow all events as PEBS with no flags */
627 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 635 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
628 EVENT_CONSTRAINT_END 636 EVENT_CONSTRAINT_END
@@ -634,16 +642,16 @@ struct event_constraint intel_hsw_pebs_event_constraints[] = {
634 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ 642 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
635 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), 643 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
636 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ 644 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
637 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ 645 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
638 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ 646 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
639 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ 647 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
640 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ 648 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
641 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ 649 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
642 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ 650 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
643 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ 651 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
644 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 652 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
645 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ 653 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
646 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ 654 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
647 /* Allow all events as PEBS with no flags */ 655 /* Allow all events as PEBS with no flags */
648 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), 656 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
649 EVENT_CONSTRAINT_END 657 EVENT_CONSTRAINT_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-14 11:24:38 -0400