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authorStephane Eranian <eranian@google.com>2012-02-09 17:20:56 -0500
committerIngo Molnar <mingo@elte.hu>2012-03-05 08:55:41 -0500
commit88c9a65e13f393fd60d8b9e9c659a34f9e39967d (patch)
treea609acb6ae06c162015d6d32b9c8a1d5313ec3e2 /arch/x86/kernel/cpu
parentc5cc2cd906ea9fe73e3c93f9ad824996faa278cc (diff)
perf/x86: Disable LBR support for older Intel Atom processors
The patch adds a restriction for Intel Atom LBR support. Only steppings 10 (PineView) and more recent are supported. Older models do not have a functional LBR. Their LBR does not freeze on PMU interrupt which makes LBR unusable in the context of perf_events. Signed-off-by: Stephane Eranian <eranian@google.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1328826068-11713-7-git-send-email-eranian@google.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu')
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_lbr.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index e54a063b2863..07f0ff88e443 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -315,6 +315,16 @@ void intel_pmu_lbr_init_snb(void)
315/* atom */ 315/* atom */
316void intel_pmu_lbr_init_atom(void) 316void intel_pmu_lbr_init_atom(void)
317{ 317{
318 /*
319 * only models starting at stepping 10 seems
320 * to have an operational LBR which can freeze
321 * on PMU interrupt
322 */
323 if (boot_cpu_data.x86_mask < 10) {
324 pr_cont("LBR disabled due to erratum");
325 return;
326 }
327
318 x86_pmu.lbr_nr = 8; 328 x86_pmu.lbr_nr = 8;
319 x86_pmu.lbr_tos = MSR_LBR_TOS; 329 x86_pmu.lbr_tos = MSR_LBR_TOS;
320 x86_pmu.lbr_from = MSR_LBR_CORE_FROM; 330 x86_pmu.lbr_from = MSR_LBR_CORE_FROM;