Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  x86, cpu: Fix detection of Celeron Covington stepping A1 and B0
  Documentation, ABI: Update L3 cache index disable text
  x86, AMD, cacheinfo: Fix L3 cache index disable checks
  x86, AMD, cacheinfo: Fix fallout caused by max3 conversion
  x86, cpu: Change NOP selection for certain Intel CPUs
  x86, cpu: Clean up and unify the NOP selection infrastructure
  x86, percpu: Use ASM_NOP4 instead of hardcoding P6_NOP4
  x86, cpu: Move AMD Elan Kconfig under "Processor family"

Fix up trivial conflicts in alternative handling (commit dc326fca2b64
"x86, cpu: Clean up and unify the NOP selection infrastructure" removed
some hacky 5-byte instruction stuff, while commit d430d3d7e646 "jump
label: Introduce static_branch() interface" renamed HAVE_JUMP_LABEL to
CONFIG_JUMP_LABEL in the code that went away)

2 files changed, 8 insertions, 22 deletions

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index fc73a34ba8c9..1edf5ba4fb2b 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -411,12 +411,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
                 switch (c->x86_model) {
                 case 5:
-                        if (c->x86_mask == 0) {
-                                if (l2 == 0)
-                                        p = "Celeron (Covington)";
-                                else if (l2 == 256)
-                                        p = "Mobile Pentium II (Dixon)";
-                        }
+                        if (l2 == 0)
+                                p = "Celeron (Covington)";
+                        else if (l2 == 256)
+                                p = "Mobile Pentium II (Dixon)";
                         break;
 
                 case 6:
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 1ce1af2899df..c105c533ed94 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -327,7 +327,6 @@ static void __cpuinit amd_calc_l3_indices(struct amd_l3_cache *l3)
         l3->subcaches[2] = sc2 = !(val & BIT(8))  + !(val & BIT(9));
         l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13));
 
-        l3->indices = (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;
         l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1;
 }
 
@@ -454,27 +453,16 @@ int amd_set_l3_disable_slot(struct amd_l3_cache *l3, int cpu, unsigned slot,
 {
         int ret = 0;
 
-#define SUBCACHE_MASK   (3UL << 20)
-#define SUBCACHE_INDEX  0xfff
-
-        /*
-         * check whether this slot is already used or
-         * the index is already disabled
-         */
+        /*  check if @slot is already used or the index is already disabled */
         ret = amd_get_l3_disable_slot(l3, slot);
         if (ret >= 0)
                 return -EINVAL;
 
-        /*
-         * check whether the other slot has disabled the
-         * same index already
-         */
-        if (index == amd_get_l3_disable_slot(l3, !slot))
+        if (index > l3->indices)
                 return -EINVAL;
 
-        /* do not allow writes outside of allowed bits */
-        if ((index & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
-            ((index & SUBCACHE_INDEX) > l3->indices))
+        /* check whether the other slot has disabled the same index already */
+        if (index == amd_get_l3_disable_slot(l3, !slot))
                 return -EINVAL;
 
         amd_l3_disable_index(l3, cpu, slot, index);