diff options
author | Don Zickus <dzickus@redhat.com> | 2011-04-27 06:32:33 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2011-04-27 11:59:11 -0400 |
commit | 2bce5daca28346f19c190dbdb5542c9fe3e8c6e6 (patch) | |
tree | 01543a887959d5e5d821c3ce77c171d96eac78fe /arch/x86/kernel/cpu/perf_event_p4.c | |
parent | 6c8a7213278324f381cbcbf51510711ed745d8e6 (diff) |
perf, x86, nmi: Move LVT un-masking into irq handlers
It was noticed that P4 machines were generating double NMIs for
each perf event. These extra NMIs lead to 'Dazed and confused'
messages on the screen.
I tracked this down to a P4 quirk that said the overflow bit had
to be cleared before re-enabling the apic LVT mask. My first
attempt was to move the un-masking inside the perf nmi handler
from before the chipset NMI handler to after.
This broke Nehalem boxes that seem to like the unmasking before
the counters themselves are re-enabled.
In order to keep this change simple for 2.6.39, I decided to
just simply move the apic LVT un-masking to the beginning of all
the chipset NMI handlers, with the exception of Pentium4's to
fix the double NMI issue.
Later on we can move the un-masking to later in the handlers to
save a number of 'extra' NMIs on those particular chipsets.
I tested this change on a P4 machine, an AMD machine, a Nehalem
box, and a core2quad box. 'perf top' worked correctly along
with various other small 'perf record' runs. Anything high
stress breaks all the machines but that is a different problem.
Thanks to various people for testing different versions of this
patch.
Reported-and-tested-by: Shaun Ruffell <sruffell@digium.com>
Signed-off-by: Don Zickus <dzickus@redhat.com>
Cc: Cyrill Gorcunov <gorcunov@gmail.com>
Link: http://lkml.kernel.org/r/1303900353-10242-1-git-send-email-dzickus@redhat.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
CC: Cyrill Gorcunov <gorcunov@gmail.com>
Diffstat (limited to 'arch/x86/kernel/cpu/perf_event_p4.c')
-rw-r--r-- | arch/x86/kernel/cpu/perf_event_p4.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c index d1f77e2934a1..e93fcd55fae1 100644 --- a/arch/x86/kernel/cpu/perf_event_p4.c +++ b/arch/x86/kernel/cpu/perf_event_p4.c | |||
@@ -950,11 +950,20 @@ static int p4_pmu_handle_irq(struct pt_regs *regs) | |||
950 | x86_pmu_stop(event, 0); | 950 | x86_pmu_stop(event, 0); |
951 | } | 951 | } |
952 | 952 | ||
953 | if (handled) { | 953 | if (handled) |
954 | /* p4 quirk: unmask it again */ | ||
955 | apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED); | ||
956 | inc_irq_stat(apic_perf_irqs); | 954 | inc_irq_stat(apic_perf_irqs); |
957 | } | 955 | |
956 | /* | ||
957 | * When dealing with the unmasking of the LVTPC on P4 perf hw, it has | ||
958 | * been observed that the OVF bit flag has to be cleared first _before_ | ||
959 | * the LVTPC can be unmasked. | ||
960 | * | ||
961 | * The reason is the NMI line will continue to be asserted while the OVF | ||
962 | * bit is set. This causes a second NMI to generate if the LVTPC is | ||
963 | * unmasked before the OVF bit is cleared, leading to unknown NMI | ||
964 | * messages. | ||
965 | */ | ||
966 | apic_write(APIC_LVTPC, APIC_DM_NMI); | ||
958 | 967 | ||
959 | return handled; | 968 | return handled; |
960 | } | 969 | } |