perf/x86: Add Intel LBR MSR definitions

This patch adds the LBR definitions for NHM/WSM/SNB and Core.
It also adds the definitions for the architected LBR MSR:
LBR_SELECT, LBRT_TOS.

Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1328826068-11713-3-git-send-email-eranian@google.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>

1 files changed, 9 insertions, 9 deletions

diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 309d0cc69163..6710a5116ebd 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -203,23 +203,23 @@ void intel_pmu_lbr_read(void)
 void intel_pmu_lbr_init_core(void)
 {
         x86_pmu.lbr_nr     = 4;
-        x86_pmu.lbr_tos    = 0x01c9;
-        x86_pmu.lbr_from   = 0x40;
-        x86_pmu.lbr_to     = 0x60;
+        x86_pmu.lbr_tos    = MSR_LBR_TOS;
+        x86_pmu.lbr_from   = MSR_LBR_CORE_FROM;
+        x86_pmu.lbr_to     = MSR_LBR_CORE_TO;
 }
 
 void intel_pmu_lbr_init_nhm(void)
 {
         x86_pmu.lbr_nr     = 16;
-        x86_pmu.lbr_tos    = 0x01c9;
-        x86_pmu.lbr_from   = 0x680;
-        x86_pmu.lbr_to     = 0x6c0;
+        x86_pmu.lbr_tos    = MSR_LBR_TOS;
+        x86_pmu.lbr_from   = MSR_LBR_NHM_FROM;
+        x86_pmu.lbr_to     = MSR_LBR_NHM_TO;
 }
 
 void intel_pmu_lbr_init_atom(void)
 {
         x86_pmu.lbr_nr     = 8;
-        x86_pmu.lbr_tos    = 0x01c9;
-        x86_pmu.lbr_from   = 0x40;
-        x86_pmu.lbr_to     = 0x60;
+        x86_pmu.lbr_tos    = MSR_LBR_TOS;
+        x86_pmu.lbr_from   = MSR_LBR_CORE_FROM;
+        x86_pmu.lbr_to     = MSR_LBR_CORE_TO;
 }