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authorAndi Kleen <andi@firstfloor.org>2009-02-12 07:43:22 -0500
committerH. Peter Anvin <hpa@linux.intel.com>2009-02-19 17:51:39 -0500
commitb5f2fa4ea00a179ac1c2ff342ceeee261dd75e53 (patch)
tree08fcd00fe45ba442d4bf51cc9fdc34e8b16238b3 /arch/x86/kernel/cpu/mcheck
parent0d7482e3d76522157c9d741d79fce22c401fa0c5 (diff)
x86, mce: factor out duplicated struct mce setup into one function
Impact: cleanup This merely factors out duplicated code to set up the initial struct mce state into a single function. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/kernel/cpu/mcheck')
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_64.c23
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_amd_64.c4
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_intel_64.c2
3 files changed, 16 insertions, 13 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce_64.c b/arch/x86/kernel/cpu/mcheck/mce_64.c
index 2297730bb514..fed875742b1a 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_64.c
@@ -65,6 +65,14 @@ static char *trigger_argv[2] = { trigger, NULL };
65 65
66static DECLARE_WAIT_QUEUE_HEAD(mce_wait); 66static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
67 67
68/* Do initial initialization of a struct mce */
69void mce_setup(struct mce *m)
70{
71 memset(m, 0, sizeof(struct mce));
72 m->cpu = smp_processor_id();
73 rdtscll(m->tsc);
74}
75
68/* 76/*
69 * Lockless MCE logging infrastructure. 77 * Lockless MCE logging infrastructure.
70 * This avoids deadlocks on printk locks without having to break locks. Also 78 * This avoids deadlocks on printk locks without having to break locks. Also
@@ -208,8 +216,8 @@ void do_machine_check(struct pt_regs * regs, long error_code)
208 || !banks) 216 || !banks)
209 goto out2; 217 goto out2;
210 218
211 memset(&m, 0, sizeof(struct mce)); 219 mce_setup(&m);
212 m.cpu = smp_processor_id(); 220
213 rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); 221 rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
214 /* if the restart IP is not valid, we're done for */ 222 /* if the restart IP is not valid, we're done for */
215 if (!(m.mcgstatus & MCG_STATUS_RIPV)) 223 if (!(m.mcgstatus & MCG_STATUS_RIPV))
@@ -225,7 +233,6 @@ void do_machine_check(struct pt_regs * regs, long error_code)
225 m.misc = 0; 233 m.misc = 0;
226 m.addr = 0; 234 m.addr = 0;
227 m.bank = i; 235 m.bank = i;
228 m.tsc = 0;
229 236
230 rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); 237 rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status);
231 if ((m.status & MCI_STATUS_VAL) == 0) 238 if ((m.status & MCI_STATUS_VAL) == 0)
@@ -252,8 +259,8 @@ void do_machine_check(struct pt_regs * regs, long error_code)
252 rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); 259 rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr);
253 260
254 mce_get_rip(&m, regs); 261 mce_get_rip(&m, regs);
255 if (error_code >= 0) 262 if (error_code < 0)
256 rdtscll(m.tsc); 263 m.tsc = 0;
257 if (error_code != -2) 264 if (error_code != -2)
258 mce_log(&m); 265 mce_log(&m);
259 266
@@ -341,15 +348,13 @@ void do_machine_check(struct pt_regs * regs, long error_code)
341 * and historically has been the register value of the 348 * and historically has been the register value of the
342 * MSR_IA32_THERMAL_STATUS (Intel) msr. 349 * MSR_IA32_THERMAL_STATUS (Intel) msr.
343 */ 350 */
344void mce_log_therm_throt_event(unsigned int cpu, __u64 status) 351void mce_log_therm_throt_event(__u64 status)
345{ 352{
346 struct mce m; 353 struct mce m;
347 354
348 memset(&m, 0, sizeof(m)); 355 mce_setup(&m);
349 m.cpu = cpu;
350 m.bank = MCE_THERMAL_BANK; 356 m.bank = MCE_THERMAL_BANK;
351 m.status = status; 357 m.status = status;
352 rdtscll(m.tsc);
353 mce_log(&m); 358 mce_log(&m);
354} 359}
355#endif /* CONFIG_X86_MCE_INTEL */ 360#endif /* CONFIG_X86_MCE_INTEL */
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
index 8ae8c4ff094d..75d9dd25e3dc 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
@@ -197,9 +197,7 @@ asmlinkage void mce_threshold_interrupt(void)
197 exit_idle(); 197 exit_idle();
198 irq_enter(); 198 irq_enter();
199 199
200 memset(&m, 0, sizeof(m)); 200 mce_setup(&m);
201 rdtscll(m.tsc);
202 m.cpu = smp_processor_id();
203 201
204 /* assume first bank caused it */ 202 /* assume first bank caused it */
205 for (bank = 0; bank < NR_BANKS; ++bank) { 203 for (bank = 0; bank < NR_BANKS; ++bank) {
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
index 4b48f251fd39..7f7f1015ef19 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
@@ -24,7 +24,7 @@ asmlinkage void smp_thermal_interrupt(void)
24 24
25 rdmsrl(MSR_IA32_THERM_STATUS, msr_val); 25 rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
26 if (therm_throt_process(msr_val & 1)) 26 if (therm_throt_process(msr_val & 1))
27 mce_log_therm_throt_event(smp_processor_id(), msr_val); 27 mce_log_therm_throt_event(msr_val);
28 28
29 inc_irq_stat(irq_thermal_count); 29 inc_irq_stat(irq_thermal_count);
30 irq_exit(); 30 irq_exit();