x86/MCE/intel: Cleanup CMCI storm logic

Initially, this started with the yet another report about a race
condition in the CMCI storm adaptive period length thing. Yes, we have
to admit, it is fragile and error prone. So let's simplify it.

The simpler logic is: now, after we enter storm mode, we go straight to
polling with CMCI_STORM_INTERVAL, i.e. once a second. We remain in storm
mode as long as we see errors being logged while polling.

Theoretically, if we see an uninterrupted error stream, we will remain
in storm mode indefinitely and keep polling the MSRs.

However, when the storm is actually a burst of errors, once we have
logged them all, we back out of it after ~5 mins of polling and no more
errors logged.

If we encounter an error during those 5 minutes, we reset the polling
interval to 5 mins.

Making machine_check_poll() return a bool and denoting whether it has
seen an error or not lets us simplify a bunch of code and move the storm
handling private to mce_intel.c.

Some minor cleanups while at it.

Reported-by: Calvin Owens <calvinowens@fb.com>
Tested-by: Tony Luck <tony.luck@intel.com>
Link: http://lkml.kernel.org/r/1417746575-23299-1-git-send-email-calvinowens@fb.com
Signed-off-by: Borislav Petkov <bp@suse.de>

1 files changed, 45 insertions, 41 deletions

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index d2c611699cd9..d60cbb8d78f7 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -58,7 +58,7 @@ static DEFINE_MUTEX(mce_chrdev_read_mutex);
 #define CREATE_TRACE_POINTS
 #include <trace/events/mce.h>
 
-#define SPINUNIT 100    /* 100ns */
+#define SPINUNIT                100     /* 100ns */
 
 DEFINE_PER_CPU(unsigned, mce_exception_count);
 
@@ -87,9 +87,6 @@ static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
 static DEFINE_PER_CPU(struct mce, mces_seen);
 static int                      cpu_missing;
 
-/* CMCI storm detection filter */
-static DEFINE_PER_CPU(unsigned long, mce_polled_error);
-
 /*
  * MCA banks polled by the period polling timer for corrected events.
  * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
@@ -623,8 +620,9 @@ DEFINE_PER_CPU(unsigned, mce_poll_count);
  * is already totally * confused. In this case it's likely it will
  * not fully execute the machine check handler either.
  */
-void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
+bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
 {
+        bool error_logged = false;
         struct mce m;
         int severity;
         int i;
@@ -647,7 +645,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
                 if (!(m.status & MCI_STATUS_VAL))
                         continue;
 
-                this_cpu_write(mce_polled_error, 1);
+
                 /*
                  * Uncorrected or signalled events are handled by the exception
                  * handler when it is enabled, so don't process those here.
@@ -680,8 +678,10 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
                  * Don't get the IP here because it's unlikely to
                  * have anything to do with the actual error location.
                  */
-                if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce)
+                if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) {
+                        error_logged = true;
                         mce_log(&m);
+                }
 
                 /*
                  * Clear state for this bank.
@@ -695,6 +695,8 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
          */
 
         sync_core();
+
+        return error_logged;
 }
 EXPORT_SYMBOL_GPL(machine_check_poll);
 
@@ -1311,7 +1313,7 @@ void mce_log_therm_throt_event(__u64 status)
  * poller finds an MCE, poll 2x faster.  When the poller finds no more
  * errors, poll 2x slower (up to check_interval seconds).
  */
-static unsigned long check_interval = 5 * 60; /* 5 minutes */
+static unsigned long check_interval = INITIAL_CHECK_INTERVAL;
 
 static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */
 static DEFINE_PER_CPU(struct timer_list, mce_timer);
@@ -1321,49 +1323,57 @@ static unsigned long mce_adjust_timer_default(unsigned long interval)
         return interval;
 }
 
-static unsigned long (*mce_adjust_timer)(unsigned long interval) =
-        mce_adjust_timer_default;
+static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default;
 
-static int cmc_error_seen(void)
+static void __restart_timer(struct timer_list *t, unsigned long interval)
 {
-        unsigned long *v = this_cpu_ptr(&mce_polled_error);
+        unsigned long when = jiffies + interval;
+        unsigned long flags;
 
-        return test_and_clear_bit(0, v);
+        local_irq_save(flags);
+
+        if (timer_pending(t)) {
+                if (time_before(when, t->expires))
+                        mod_timer_pinned(t, when);
+        } else {
+                t->expires = round_jiffies(when);
+                add_timer_on(t, smp_processor_id());
+        }
+
+        local_irq_restore(flags);
 }
 
 static void mce_timer_fn(unsigned long data)
 {
         struct timer_list *t = this_cpu_ptr(&mce_timer);
+        int cpu = smp_processor_id();
         unsigned long iv;
-        int notify;
 
-        WARN_ON(smp_processor_id() != data);
+        WARN_ON(cpu != data);
+
+        iv = __this_cpu_read(mce_next_interval);
 
         if (mce_available(this_cpu_ptr(&cpu_info))) {
-                machine_check_poll(MCP_TIMESTAMP,
-                                this_cpu_ptr(&mce_poll_banks));
-                mce_intel_cmci_poll();
+                machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_poll_banks));
+
+                if (mce_intel_cmci_poll()) {
+                        iv = mce_adjust_timer(iv);
+                        goto done;
+                }
         }
 
         /*
-         * Alert userspace if needed.  If we logged an MCE, reduce the
-         * polling interval, otherwise increase the polling interval.
+         * Alert userspace if needed. If we logged an MCE, reduce the polling
+         * interval, otherwise increase the polling interval.
          */
-        iv = __this_cpu_read(mce_next_interval);
-        notify = mce_notify_irq();
-        notify |= cmc_error_seen();
-        if (notify) {
+        if (mce_notify_irq())
                 iv = max(iv / 2, (unsigned long) HZ/100);
-        } else {
+        else
                 iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
-                iv = mce_adjust_timer(iv);
-        }
+
+done:
         __this_cpu_write(mce_next_interval, iv);
-        /* Might have become 0 after CMCI storm subsided */
-        if (iv) {
-                t->expires = jiffies + iv;
-                add_timer_on(t, smp_processor_id());
-        }
+        __restart_timer(t, iv);
 }
 
 /*
@@ -1372,16 +1382,10 @@ static void mce_timer_fn(unsigned long data)
 void mce_timer_kick(unsigned long interval)
 {
         struct timer_list *t = this_cpu_ptr(&mce_timer);
-        unsigned long when = jiffies + interval;
         unsigned long iv = __this_cpu_read(mce_next_interval);
 
-        if (timer_pending(t)) {
-                if (time_before(when, t->expires))
-                        mod_timer_pinned(t, when);
-        } else {
-                t->expires = round_jiffies(when);
-                add_timer_on(t, smp_processor_id());
-        }
+        __restart_timer(t, interval);
+
         if (interval < iv)
                 __this_cpu_write(mce_next_interval, interval);
 }
@@ -1682,7 +1686,7 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
         switch (c->x86_vendor) {
         case X86_VENDOR_INTEL:
                 mce_intel_feature_init(c);
-                mce_adjust_timer = mce_intel_adjust_timer;
+                mce_adjust_timer = cmci_intel_adjust_timer;
                 break;
         case X86_VENDOR_AMD:
                 mce_amd_feature_init(c);