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authorVenki Pallipadi <venkatesh.pallipadi@intel.com>2008-11-17 19:11:37 -0500
committerIngo Molnar <mingo@elte.hu>2008-12-16 15:02:50 -0500
commit40fb17152c50a69dc304dd632131c2f41281ce44 (patch)
treeae4ab9fc72183968d4e3ff5c5d07cf7573954455 /arch/x86/kernel/cpu/intel.c
parent7e91a122b11bb250d08ab125afd2c232c87502e1 (diff)
x86: support always running TSC on Intel CPUs
Impact: reward non-stop TSCs with good TSC-based clocksources, etc. Add support for CPUID_0x80000007_Bit8 on Intel CPUs as well. This bit means that the TSC is invariant with C/P/T states and always runs at constant frequency. With Intel CPUs, we have 3 classes * CPUs where TSC runs at constant rate and does not stop n C-states * CPUs where TSC runs at constant rate, but will stop in deep C-states * CPUs where TSC rate will vary based on P/T-states and TSC will stop in deep C-states. To cover these 3, one feature bit (CONSTANT_TSC) is not enough. So, add a second bit (NONSTOP_TSC). CONSTANT_TSC indicates that the TSC runs at constant frequency irrespective of P/T-states, and NONSTOP_TSC indicates that TSC does not stop in deep C-states. CPUID_0x8000000_Bit8 indicates both these feature bit can be set. We still have CONSTANT_TSC _set_ and NONSTOP_TSC _not_set_ on some older Intel CPUs, based on model checks. We can use TSC on such CPUs for time, as long as those CPUs do not support/enter deep C-states. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
-rw-r--r--arch/x86/kernel/cpu/intel.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index cce0b6118d55..caec59437a22 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -41,6 +41,16 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
41 if (c->x86 == 15 && c->x86_cache_alignment == 64) 41 if (c->x86 == 15 && c->x86_cache_alignment == 64)
42 c->x86_cache_alignment = 128; 42 c->x86_cache_alignment = 128;
43#endif 43#endif
44
45 /*
46 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
47 * with P/T states and does not stop in deep C-states
48 */
49 if (c->x86_power & (1 << 8)) {
50 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
51 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
52 }
53
44} 54}
45 55
46#ifdef CONFIG_X86_32 56#ifdef CONFIG_X86_32