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authorIngo Molnar <mingo@elte.hu>2008-07-22 05:58:14 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-22 06:24:00 -0400
commit026e2c05ef58ef413e2d52696f125d5ea1aa8bce (patch)
treea9efc0fd19fe72e00d9bbd0b805c7c8dc7715653 /arch/x86/kernel/cpu/cyrix.c
parent93ded9b8fd42abe2c3607097963d8de6ad9117eb (diff)
x86, cyrix: debug
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/kernel/cpu/cyrix.c')
-rw-r--r--arch/x86/kernel/cpu/cyrix.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
index 3fd7a67bb06a..db5868cd2443 100644
--- a/arch/x86/kernel/cpu/cyrix.c
+++ b/arch/x86/kernel/cpu/cyrix.c
@@ -116,7 +116,7 @@ static void __cpuinit set_cx86_reorder(void)
116 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 116 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
117 117
118 /* Load/Store Serialize to mem access disable (=reorder it) */ 118 /* Load/Store Serialize to mem access disable (=reorder it) */
119 setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80); 119 setCx86_old(CX86_PCR0, getCx86_old(CX86_PCR0) & ~0x80);
120 /* set load/store serialize from 1GB to 4GB */ 120 /* set load/store serialize from 1GB to 4GB */
121 ccr3 |= 0xe0; 121 ccr3 |= 0xe0;
122 setCx86(CX86_CCR3, ccr3); 122 setCx86(CX86_CCR3, ccr3);
@@ -127,11 +127,11 @@ static void __cpuinit set_cx86_memwb(void)
127 printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n"); 127 printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n");
128 128
129 /* CCR2 bit 2: unlock NW bit */ 129 /* CCR2 bit 2: unlock NW bit */
130 setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04); 130 setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) & ~0x04);
131 /* set 'Not Write-through' */ 131 /* set 'Not Write-through' */
132 write_cr0(read_cr0() | X86_CR0_NW); 132 write_cr0(read_cr0() | X86_CR0_NW);
133 /* CCR2 bit 2: lock NW bit and set WT1 */ 133 /* CCR2 bit 2: lock NW bit and set WT1 */
134 setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14); 134 setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x14);
135} 135}
136 136
137static void __cpuinit set_cx86_inc(void) 137static void __cpuinit set_cx86_inc(void)
@@ -144,10 +144,10 @@ static void __cpuinit set_cx86_inc(void)
144 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 144 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
145 /* PCR1 -- Performance Control */ 145 /* PCR1 -- Performance Control */
146 /* Incrementor on, whatever that is */ 146 /* Incrementor on, whatever that is */
147 setCx86(CX86_PCR1, getCx86(CX86_PCR1) | 0x02); 147 setCx86_old(CX86_PCR1, getCx86_old(CX86_PCR1) | 0x02);
148 /* PCR0 -- Performance Control */ 148 /* PCR0 -- Performance Control */
149 /* Incrementor Margin 10 */ 149 /* Incrementor Margin 10 */
150 setCx86(CX86_PCR0, getCx86(CX86_PCR0) | 0x04); 150 setCx86_old(CX86_PCR0, getCx86_old(CX86_PCR0) | 0x04);
151 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ 151 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
152} 152}
153 153
@@ -162,14 +162,14 @@ static void __cpuinit geode_configure(void)
162 local_irq_save(flags); 162 local_irq_save(flags);
163 163
164 /* Suspend on halt power saving and enable #SUSP pin */ 164 /* Suspend on halt power saving and enable #SUSP pin */
165 setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88); 165 setCx86_old(CX86_CCR2, getCx86_old(CX86_CCR2) | 0x88);
166 166
167 ccr3 = getCx86(CX86_CCR3); 167 ccr3 = getCx86(CX86_CCR3);
168 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 168 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
169 169
170 170
171 /* FPU fast, DTE cache, Mem bypass */ 171 /* FPU fast, DTE cache, Mem bypass */
172 setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38); 172 setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x38);
173 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ 173 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
174 174
175 set_cx86_memwb(); 175 set_cx86_memwb();
@@ -286,7 +286,7 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
286 /* GXm supports extended cpuid levels 'ala' AMD */ 286 /* GXm supports extended cpuid levels 'ala' AMD */
287 if (c->cpuid_level == 2) { 287 if (c->cpuid_level == 2) {
288 /* Enable cxMMX extensions (GX1 Datasheet 54) */ 288 /* Enable cxMMX extensions (GX1 Datasheet 54) */
289 setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1); 289 setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7) | 1);
290 290
291 /* 291 /*
292 * GXm : 0x30 ... 0x5f GXm datasheet 51 292 * GXm : 0x30 ... 0x5f GXm datasheet 51
@@ -309,7 +309,7 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
309 if (dir1 > 7) { 309 if (dir1 > 7) {
310 dir0_msn++; /* M II */ 310 dir0_msn++; /* M II */
311 /* Enable MMX extensions (App note 108) */ 311 /* Enable MMX extensions (App note 108) */
312 setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1); 312 setCx86_old(CX86_CCR7, getCx86_old(CX86_CCR7)|1);
313 } else { 313 } else {
314 c->coma_bug = 1; /* 6x86MX, it has the bug. */ 314 c->coma_bug = 1; /* 6x86MX, it has the bug. */
315 } 315 }
@@ -424,7 +424,7 @@ static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c)
424 local_irq_save(flags); 424 local_irq_save(flags);
425 ccr3 = getCx86(CX86_CCR3); 425 ccr3 = getCx86(CX86_CCR3);
426 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ 426 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
427 setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x80); /* enable cpuid */ 427 setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x80); /* enable cpuid */
428 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ 428 setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
429 local_irq_restore(flags); 429 local_irq_restore(flags);
430 } 430 }