perf/x86/intel/pt: Add Intel PT PMU driver

Add support for Intel Processor Trace (PT) to kernel's perf events.
PT is an extension of Intel Architecture that collects information about
software execuction such as control flow, execution modes and timings and
formats it into highly compressed binary packets. Even being compressed,
these packets are generated at hundreds of megabytes per second per core,
which makes it impractical to decode them on the fly in the kernel.

This driver exports trace data by through AUX space in the perf ring
buffer, which is zero-copy mapped into userspace for faster data retrieval.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Kaixu Xia <kaixu.xia@linaro.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Robert Richter <rric@kernel.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: acme@infradead.org
Cc: adrian.hunter@intel.com
Cc: kan.liang@intel.com
Cc: markus.t.metzger@intel.com
Cc: mathieu.poirier@linaro.org
Link: http://lkml.kernel.org/r/1422614392-114498-1-git-send-email-alexander.shishkin@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

1 files changed, 18 insertions, 0 deletions

diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 3ce079136c11..1a4eae695ca8 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -74,6 +74,24 @@
 #define MSR_IA32_PERF_CAPABILITIES      0x00000345
 #define MSR_PEBS_LD_LAT_THRESHOLD       0x000003f6
 
+#define MSR_IA32_RTIT_CTL               0x00000570
+#define RTIT_CTL_TRACEEN                BIT(0)
+#define RTIT_CTL_OS                     BIT(2)
+#define RTIT_CTL_USR                    BIT(3)
+#define RTIT_CTL_CR3EN                  BIT(7)
+#define RTIT_CTL_TOPA                   BIT(8)
+#define RTIT_CTL_TSC_EN                 BIT(10)
+#define RTIT_CTL_DISRETC                BIT(11)
+#define RTIT_CTL_BRANCH_EN              BIT(13)
+#define MSR_IA32_RTIT_STATUS            0x00000571
+#define RTIT_STATUS_CONTEXTEN           BIT(1)
+#define RTIT_STATUS_TRIGGEREN           BIT(2)
+#define RTIT_STATUS_ERROR               BIT(4)
+#define RTIT_STATUS_STOPPED             BIT(5)
+#define MSR_IA32_RTIT_CR3_MATCH         0x00000572
+#define MSR_IA32_RTIT_OUTPUT_BASE       0x00000560
+#define MSR_IA32_RTIT_OUTPUT_MASK       0x00000561
+
 #define MSR_MTRRfix64K_00000            0x00000250
 #define MSR_MTRRfix16K_80000            0x00000258
 #define MSR_MTRRfix16K_A0000            0x00000259