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authorLen Brown <len.brown@intel.com>2015-03-26 00:50:30 -0400
committerLen Brown <len.brown@intel.com>2015-04-18 14:20:51 -0400
commit0b2bb6925eb602eae993a4b5c282a8c18ad1c949 (patch)
tree24367037aecceac63d546eff7dc249871de4ee3a /arch/x86/include
parentf82263c6989c31ae9b94cecddffb29dcbec38710 (diff)
tools/power turbostat: Initial Skylake support
Skylake adds some additional residency counters. Skylake supports a different mix of RAPL registers from any previous product. In most other ways, Skylake is like Broadwell. Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch/x86/include')
-rw-r--r--arch/x86/include/uapi/asm/msr-index.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index c4c75272314a..fe01b0a784e7 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -150,6 +150,11 @@
150#define MSR_PP1_ENERGY_STATUS 0x00000641 150#define MSR_PP1_ENERGY_STATUS 0x00000641
151#define MSR_PP1_POLICY 0x00000642 151#define MSR_PP1_POLICY 0x00000642
152 152
153#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
154#define MSR_PKG_ANY_CORE_C0_RES 0x00000659
155#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
156#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
157
153#define MSR_CORE_C1_RES 0x00000660 158#define MSR_CORE_C1_RES 0x00000660
154 159
155#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 160#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668