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authorcpw@sgi.com <cpw@sgi.com>2011-06-21 08:21:33 -0400
committerIngo Molnar <mingo@elte.hu>2011-06-21 08:50:34 -0400
commitae90c232be376bd8a283f3b6fb37cb5bd2635d67 (patch)
tree44257f318d85f6a2a4bba58261c5327bed2371cc /arch/x86/include/asm/uv/uv_bau.h
parentbbd270e6f45a5ca30e1d3b6133c516a9dc9dd6c0 (diff)
x86, UV: Correct UV2 BAU destination timeout
Correct the UV2 broacast assist unit's destination timeout period. And the activation status register in UV2 should be tested for a destination timeout with a 4, not a 2. The values for Active versus Timeout were reversed. This patch is critical for TLB shootdown on an Altix UV2 system (i.e. the follow-on to the current Altix UV). Destination timeout period: The period is set in 4 bits of memory-mapped register MISC_CONTROL. The left bit toggles base period between 10us and 80us. The other 3 bits are the multiplier. Decimal 15, hex f, gives the maximum: 7 * 80us Signed-off-by: Cliff Wickman <cpw@sgi.com> Link: http://lkml.kernel.org/r/20110621122243.117324443@sgi.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/include/asm/uv/uv_bau.h')
-rw-r--r--arch/x86/include/asm/uv/uv_bau.h18
1 files changed, 13 insertions, 5 deletions
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index 16ce58c6d252..37d369859c8e 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -67,7 +67,7 @@
67 * we're using 655us, similar to UV1: 65 units of 10us 67 * we're using 655us, similar to UV1: 65 units of 10us
68 */ 68 */
69#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL) 69#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
70#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (65*10UL) 70#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
71 71
72#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \ 72#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
73 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \ 73 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
@@ -106,12 +106,20 @@
106#define DS_SOURCE_TIMEOUT 3 106#define DS_SOURCE_TIMEOUT 3
107/* 107/*
108 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2 108 * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
109 * values 1 and 5 will not occur 109 * values 1 and 3 will not occur
110 * Decoded meaning ERROR BUSY AUX ERR
111 * ------------------------------- ---- ----- -------
112 * IDLE 0 0 0
113 * BUSY (active) 0 1 0
114 * SW Ack Timeout (destination) 1 0 0
115 * SW Ack INTD rejected (strong NACK) 1 0 1
116 * Source Side Time Out Detected 1 1 0
117 * Destination Side PUT Failed 1 1 1
110 */ 118 */
111#define UV2H_DESC_IDLE 0 119#define UV2H_DESC_IDLE 0
112#define UV2H_DESC_DEST_TIMEOUT 2 120#define UV2H_DESC_BUSY 2
113#define UV2H_DESC_DEST_STRONG_NACK 3 121#define UV2H_DESC_DEST_TIMEOUT 4
114#define UV2H_DESC_BUSY 4 122#define UV2H_DESC_DEST_STRONG_NACK 5
115#define UV2H_DESC_SOURCE_TIMEOUT 6 123#define UV2H_DESC_SOURCE_TIMEOUT 6
116#define UV2H_DESC_DEST_PUT_ERR 7 124#define UV2H_DESC_DEST_PUT_ERR 7
117 125