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authorH. Peter Anvin <hpa@zytor.com>2008-10-23 01:26:29 -0400
committerH. Peter Anvin <hpa@zytor.com>2008-10-23 01:55:23 -0400
commit1965aae3c98397aad957412413c07e97b1bd4e64 (patch)
tree1386fcb54753f8dda8f99ca6e5ecab0add1f029f /arch/x86/include/asm/pgtable-3level.h
parent87e299e5c7508a9443f04703f1d0c7f518f79ea9 (diff)
x86: Fix ASM_X86__ header guards
Change header guards named "ASM_X86__*" to "_ASM_X86_*" since: a. the double underscore is ugly and pointless. b. no leading underscore violates namespace constraints. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/include/asm/pgtable-3level.h')
-rw-r--r--arch/x86/include/asm/pgtable-3level.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h
index 75f4276b5ddb..fb16cec702e4 100644
--- a/arch/x86/include/asm/pgtable-3level.h
+++ b/arch/x86/include/asm/pgtable-3level.h
@@ -1,5 +1,5 @@
1#ifndef ASM_X86__PGTABLE_3LEVEL_H 1#ifndef _ASM_X86_PGTABLE_3LEVEL_H
2#define ASM_X86__PGTABLE_3LEVEL_H 2#define _ASM_X86_PGTABLE_3LEVEL_H
3 3
4/* 4/*
5 * Intel Physical Address Extension (PAE) Mode - three-level page 5 * Intel Physical Address Extension (PAE) Mode - three-level page
@@ -172,4 +172,4 @@ static inline int pte_none(pte_t pte)
172#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high }) 172#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
173#define __swp_entry_to_pte(x) ((pte_t){ { .pte_high = (x).val } }) 173#define __swp_entry_to_pte(x) ((pte_t){ { .pte_high = (x).val } })
174 174
175#endif /* ASM_X86__PGTABLE_3LEVEL_H */ 175#endif /* _ASM_X86_PGTABLE_3LEVEL_H */