diff options
author | R, Durgadoss <durgadoss.r@intel.com> | 2011-01-03 06:52:04 -0500 |
---|---|---|
committer | H. Peter Anvin <hpa@linux.intel.com> | 2011-01-03 11:30:30 -0500 |
commit | 9e76a97efd31a08cb19d0ba12013b8fb4ad3e474 (patch) | |
tree | ad7ce5dd1aa746635ffb80fb0b4e8a8d606fa42b /arch/x86/include/asm/msr-index.h | |
parent | 387c31c7e5c9805b0aef8833d1731a5fe7bdea14 (diff) |
x86, hwmon: Add core threshold notification to therm_throt.c
This patch adds code to therm_throt.c to notify core thermal threshold
events. These thresholds are supported by the IA32_THERM_INTERRUPT register.
The status/log for the same is monitored using the IA32_THERM_STATUS register.
The necessary #defines are in msr-index.h. A call back is added to mce.h, to
further notify the thermal stack, about the threshold events.
Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
LKML-Reference: <D6D887BA8C9DFF48B5233887EF04654105C1251710@bgsmsx502.gar.corp.intel.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
-rw-r--r-- | arch/x86/include/asm/msr-index.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 6b89f5e86021..622c80b7dbee 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h | |||
@@ -253,6 +253,18 @@ | |||
253 | #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) | 253 | #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) |
254 | #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) | 254 | #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) |
255 | 255 | ||
256 | /* Thermal Thresholds Support */ | ||
257 | #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) | ||
258 | #define THERM_SHIFT_THRESHOLD0 8 | ||
259 | #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) | ||
260 | #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) | ||
261 | #define THERM_SHIFT_THRESHOLD1 16 | ||
262 | #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) | ||
263 | #define THERM_STATUS_THRESHOLD0 (1 << 6) | ||
264 | #define THERM_LOG_THRESHOLD0 (1 << 7) | ||
265 | #define THERM_STATUS_THRESHOLD1 (1 << 8) | ||
266 | #define THERM_LOG_THRESHOLD1 (1 << 9) | ||
267 | |||
256 | /* MISC_ENABLE bits: architectural */ | 268 | /* MISC_ENABLE bits: architectural */ |
257 | #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) | 269 | #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) |
258 | #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) | 270 | #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) |