diff options
author | Alexander Graf <agraf@suse.de> | 2008-11-25 14:17:02 -0500 |
---|---|---|
committer | Avi Kivity <avi@redhat.com> | 2009-03-24 05:02:46 -0400 |
commit | 9962d032bbff0268f22068787831405f8468c8b4 (patch) | |
tree | 3a9cd94334d419097923c5c4140770c17aa06cc8 /arch/x86/include/asm/msr-index.h | |
parent | f0b85051d0f0891378a83db22c0786f1d756fbff (diff) |
KVM: SVM: Move EFER and MSR constants to generic x86 code
MSR_EFER_SVME_MASK, MSR_VM_CR and MSR_VM_HSAVE_PA are set in KVM
specific headers. Linux does have nice header files to collect
EFER bits and MSR IDs, so IMHO we should put them there.
While at it, I also changed the naming scheme to match that
of the other defines.
(introduced in v6)
Acked-by: Joerg Roedel <joro@8bytes.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
-rw-r--r-- | arch/x86/include/asm/msr-index.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 358acc59ae04..46e9646e7a66 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h | |||
@@ -18,11 +18,13 @@ | |||
18 | #define _EFER_LME 8 /* Long mode enable */ | 18 | #define _EFER_LME 8 /* Long mode enable */ |
19 | #define _EFER_LMA 10 /* Long mode active (read-only) */ | 19 | #define _EFER_LMA 10 /* Long mode active (read-only) */ |
20 | #define _EFER_NX 11 /* No execute enable */ | 20 | #define _EFER_NX 11 /* No execute enable */ |
21 | #define _EFER_SVME 12 /* Enable virtualization */ | ||
21 | 22 | ||
22 | #define EFER_SCE (1<<_EFER_SCE) | 23 | #define EFER_SCE (1<<_EFER_SCE) |
23 | #define EFER_LME (1<<_EFER_LME) | 24 | #define EFER_LME (1<<_EFER_LME) |
24 | #define EFER_LMA (1<<_EFER_LMA) | 25 | #define EFER_LMA (1<<_EFER_LMA) |
25 | #define EFER_NX (1<<_EFER_NX) | 26 | #define EFER_NX (1<<_EFER_NX) |
27 | #define EFER_SVME (1<<_EFER_SVME) | ||
26 | 28 | ||
27 | /* Intel MSRs. Some also available on other CPUs */ | 29 | /* Intel MSRs. Some also available on other CPUs */ |
28 | #define MSR_IA32_PERFCTR0 0x000000c1 | 30 | #define MSR_IA32_PERFCTR0 0x000000c1 |
@@ -360,4 +362,9 @@ | |||
360 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b | 362 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b |
361 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c | 363 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c |
362 | 364 | ||
365 | /* AMD-V MSRs */ | ||
366 | |||
367 | #define MSR_VM_CR 0xc0010114 | ||
368 | #define MSR_VM_HSAVE_PA 0xc0010117 | ||
369 | |||
363 | #endif /* _ASM_X86_MSR_INDEX_H */ | 370 | #endif /* _ASM_X86_MSR_INDEX_H */ |