crypto: crc32c - Use Intel CRC32 instruction

From NHM processor onward, Intel processors can support hardware accelerated
CRC32c algorithm with the new CRC32 instruction in SSE 4.2 instruction set.
The patch detects the availability of the feature, and chooses the most proper
way to calculate CRC32c checksum.
Byte code instructions are used for compiler compatibility.
No MMX / XMM registers is involved in the implementation.

Signed-off-by: Austin Zhang <austin.zhang@intel.com>
Signed-off-by: Kent Liu <kent.liu@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

2 files changed, 199 insertions, 0 deletions

diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile
index 3874c2de5403..903de4aa5094 100644
--- a/arch/x86/crypto/Makefile
+++ b/arch/x86/crypto/Makefile
@@ -10,6 +10,8 @@ obj-$(CONFIG_CRYPTO_AES_X86_64) += aes-x86_64.o
 obj-$(CONFIG_CRYPTO_TWOFISH_X86_64) += twofish-x86_64.o
 obj-$(CONFIG_CRYPTO_SALSA20_X86_64) += salsa20-x86_64.o
 
+obj-$(CONFIG_CRYPTO_CRC32C_INTEL) += crc32c-intel.o
+
 aes-i586-y := aes-i586-asm_32.o aes_glue.o
 twofish-i586-y := twofish-i586-asm_32.o twofish_glue.o
 salsa20-i586-y := salsa20-i586-asm_32.o salsa20_glue.o
diff --git a/arch/x86/crypto/crc32c-intel.c b/arch/x86/crypto/crc32c-intel.c
new file mode 100644
index 000000000000..070afc5b6c94
--- /dev/null
+++ b/arch/x86/crypto/crc32c-intel.c
@@ -0,0 +1,197 @@
+/*
+ * Using hardware provided CRC32 instruction to accelerate the CRC32 disposal.
+ * CRC32C polynomial:0x1EDC6F41(BE)/0x82F63B78(LE)
+ * CRC32 is a new instruction in Intel SSE4.2, the reference can be found at:
+ * http://www.intel.com/products/processor/manuals/
+ * Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+ * Volume 2A: Instruction Set Reference, A-M
+ *
+ * Copyright (c) 2008 Austin Zhang <austin_zhang@linux.intel.com>
+ * Copyright (c) 2008 Kent Liu <kent.liu@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <crypto/internal/hash.h>
+
+#include <asm/cpufeature.h>
+
+#define CHKSUM_BLOCK_SIZE       1
+#define CHKSUM_DIGEST_SIZE      4
+
+#define SCALE_F sizeof(unsigned long)
+
+#ifdef CONFIG_X86_64
+#define REX_PRE "0x48, "
+#else
+#define REX_PRE
+#endif
+
+static u32 crc32c_intel_le_hw_byte(u32 crc, unsigned char const *data, size_t length)
+{
+        while (length--) {
+                __asm__ __volatile__(
+                        ".byte 0xf2, 0xf, 0x38, 0xf0, 0xf1"
+                        :"=S"(crc)
+                        :"0"(crc), "c"(*data)
+                );
+                data++;
+        }
+
+        return crc;
+}
+
+static u32 __pure crc32c_intel_le_hw(u32 crc, unsigned char const *p, size_t len)
+{
+        unsigned int iquotient = len / SCALE_F;
+        unsigned int iremainder = len % SCALE_F;
+        unsigned long *ptmp = (unsigned long *)p;
+
+        while (iquotient--) {
+                __asm__ __volatile__(
+                        ".byte 0xf2, " REX_PRE "0xf, 0x38, 0xf1, 0xf1;"
+                        :"=S"(crc)
+                        :"0"(crc), "c"(*ptmp)
+                );
+                ptmp++;
+        }
+
+        if (iremainder)
+                crc = crc32c_intel_le_hw_byte(crc, (unsigned char *)ptmp,
+                                 iremainder);
+
+        return crc;
+}
+
+/*
+ * Setting the seed allows arbitrary accumulators and flexible XOR policy
+ * If your algorithm starts with ~0, then XOR with ~0 before you set
+ * the seed.
+ */
+static int crc32c_intel_setkey(struct crypto_ahash *hash, const u8 *key,
+                        unsigned int keylen)
+{
+        u32 *mctx = crypto_ahash_ctx(hash);
+
+        if (keylen != sizeof(u32)) {
+                crypto_ahash_set_flags(hash, CRYPTO_TFM_RES_BAD_KEY_LEN);
+                return -EINVAL;
+        }
+        *mctx = le32_to_cpup((__le32 *)key);
+        return 0;
+}
+
+static int crc32c_intel_init(struct ahash_request *req)
+{
+        u32 *mctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
+        u32 *crcp = ahash_request_ctx(req);
+
+        *crcp = *mctx;
+
+        return 0;
+}
+
+static int crc32c_intel_update(struct ahash_request *req)
+{
+        struct crypto_hash_walk walk;
+        u32 *crcp = ahash_request_ctx(req);
+        u32 crc = *crcp;
+        int nbytes;
+
+        for (nbytes = crypto_hash_walk_first(req, &walk); nbytes;
+           nbytes = crypto_hash_walk_done(&walk, 0))
+        crc = crc32c_intel_le_hw(crc, walk.data, nbytes);
+
+        *crcp = crc;
+        return 0;
+}
+
+static int crc32c_intel_final(struct ahash_request *req)
+{
+        u32 *crcp = ahash_request_ctx(req);
+
+        *(__le32 *)req->result = ~cpu_to_le32p(crcp);
+        return 0;
+}
+
+static int crc32c_intel_digest(struct ahash_request *req)
+{
+        struct crypto_hash_walk walk;
+        u32 *mctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
+        u32 crc = *mctx;
+        int nbytes;
+
+        for (nbytes = crypto_hash_walk_first(req, &walk); nbytes;
+           nbytes = crypto_hash_walk_done(&walk, 0))
+                crc = crc32c_intel_le_hw(crc, walk.data, nbytes);
+
+        *(__le32 *)req->result = ~cpu_to_le32(crc);
+        return 0;
+}
+
+static int crc32c_intel_cra_init(struct crypto_tfm *tfm)
+{
+        u32 *key = crypto_tfm_ctx(tfm);
+
+        *key = ~0;
+
+        tfm->crt_ahash.reqsize = sizeof(u32);
+
+        return 0;
+}
+
+static struct crypto_alg alg = {
+        .cra_name               =       "crc32c",
+        .cra_driver_name        =       "crc32c-intel",
+        .cra_priority           =       200,
+        .cra_flags              =       CRYPTO_ALG_TYPE_AHASH,
+        .cra_blocksize          =       CHKSUM_BLOCK_SIZE,
+        .cra_alignmask          =       3,
+        .cra_ctxsize            =       sizeof(u32),
+        .cra_module             =       THIS_MODULE,
+        .cra_list               =       LIST_HEAD_INIT(alg.cra_list),
+        .cra_init               =       crc32c_intel_cra_init,
+        .cra_type               =       &crypto_ahash_type,
+        .cra_u                  =       {
+                .ahash = {
+                        .digestsize    =       CHKSUM_DIGEST_SIZE,
+                        .setkey        =       crc32c_intel_setkey,
+                        .init          =       crc32c_intel_init,
+                        .update        =       crc32c_intel_update,
+                        .final         =       crc32c_intel_final,
+                        .digest        =       crc32c_intel_digest,
+                }
+        }
+};
+
+
+static int __init crc32c_intel_mod_init(void)
+{
+        if (cpu_has_xmm4_2)
+                return crypto_register_alg(&alg);
+        else
+                return -ENODEV;
+}
+
+static void __exit crc32c_intel_mod_fini(void)
+{
+        crypto_unregister_alg(&alg);
+}
+
+module_init(crc32c_intel_mod_init);
+module_exit(crc32c_intel_mod_fini);
+
+MODULE_AUTHOR("Austin Zhang <austin.zhang@intel.com>, Kent Liu <kent.liu@intel.com>");
+MODULE_DESCRIPTION("CRC32c (Castagnoli) optimization using Intel Hardware.");
+MODULE_LICENSE("GPL");
+
+MODULE_ALIAS("crc32c");
+MODULE_ALIAS("crc32c-intel");
+