aboutsummaryrefslogtreecommitdiffstats
path: root/arch/x86/crypto/ghash-clmulni-intel_glue.c
diff options
context:
space:
mode:
authorAndi Kleen <ak@linux.intel.com>2012-01-25 18:09:06 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2012-01-26 19:48:10 -0500
commit3bd391f056df61e928de1680ff4a3e7e07e5b399 (patch)
treef50b5c80010b901a6542b7f4e4913b76d77f3b72 /arch/x86/crypto/ghash-clmulni-intel_glue.c
parent644e9cbbe3fc032cc92d0936057e166a994dc246 (diff)
crypto: Add support for x86 cpuid auto loading for x86 crypto drivers
Add support for auto-loading of crypto drivers based on cpuid features. This enables auto-loading of the VIA and Intel specific drivers for AES, hashing and CRCs. Requires the earlier infrastructure patch to add x86 modinfo. I kept it all in a single patch for now. I dropped the printks when the driver cpuid doesn't match (imho drivers never should print anything in such a case) One drawback is that udev doesn't know if the drivers are used or not, so they will be unconditionally loaded at boot up. That's better than not loading them at all, like it often happens. Cc: Dave Jones <davej@redhat.com> Cc: Kay Sievers <kay.sievers@vrfy.org> Cc: Jen Axboe <axboe@kernel.dk> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: Huang Ying <ying.huang@intel.com> Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Thomas Renninger <trenn@suse.de> Acked-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'arch/x86/crypto/ghash-clmulni-intel_glue.c')
-rw-r--r--arch/x86/crypto/ghash-clmulni-intel_glue.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/x86/crypto/ghash-clmulni-intel_glue.c b/arch/x86/crypto/ghash-clmulni-intel_glue.c
index 976aa64d9a20..b4bf0a63b520 100644
--- a/arch/x86/crypto/ghash-clmulni-intel_glue.c
+++ b/arch/x86/crypto/ghash-clmulni-intel_glue.c
@@ -20,6 +20,7 @@
20#include <crypto/gf128mul.h> 20#include <crypto/gf128mul.h>
21#include <crypto/internal/hash.h> 21#include <crypto/internal/hash.h>
22#include <asm/i387.h> 22#include <asm/i387.h>
23#include <asm/cpu_device_id.h>
23 24
24#define GHASH_BLOCK_SIZE 16 25#define GHASH_BLOCK_SIZE 16
25#define GHASH_DIGEST_SIZE 16 26#define GHASH_DIGEST_SIZE 16
@@ -294,15 +295,18 @@ static struct ahash_alg ghash_async_alg = {
294 }, 295 },
295}; 296};
296 297
298static const struct x86_cpu_id pcmul_cpu_id[] = {
299 X86_FEATURE_MATCH(X86_FEATURE_PCLMULQDQ), /* Pickle-Mickle-Duck */
300 {}
301};
302MODULE_DEVICE_TABLE(x86cpu, pcmul_cpu_id);
303
297static int __init ghash_pclmulqdqni_mod_init(void) 304static int __init ghash_pclmulqdqni_mod_init(void)
298{ 305{
299 int err; 306 int err;
300 307
301 if (!cpu_has_pclmulqdq) { 308 if (!x86_match_cpu(pcmul_cpu_id))
302 printk(KERN_INFO "Intel PCLMULQDQ-NI instructions are not"
303 " detected.\n");
304 return -ENODEV; 309 return -ENODEV;
305 }
306 310
307 err = crypto_register_shash(&ghash_alg); 311 err = crypto_register_shash(&ghash_alg);
308 if (err) 312 if (err)