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authorGuanXuetao <gxt@mprc.pku.edu.cn>2011-02-26 08:21:18 -0500
committerGuanXuetao <gxt@mprc.pku.edu.cn>2011-03-16 21:19:19 -0400
commite5abf78b57199a417eb01ff922a5ea6ff9e10b61 (patch)
tree6f72a13d44c0dc8c4d575d84885f5694c16ed1da /arch/unicore32/kernel/process.c
parent4517366d870b89d6fb8c0c90deb6c73d975908af (diff)
unicore32 io: redefine __REG(x) and re-use readl/writel funcs
-- by advice of Arnd Bergmann Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/unicore32/kernel/process.c')
-rw-r--r--arch/unicore32/kernel/process.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/unicore32/kernel/process.c b/arch/unicore32/kernel/process.c
index 8d4a273ae086..ba401df971ed 100644
--- a/arch/unicore32/kernel/process.c
+++ b/arch/unicore32/kernel/process.c
@@ -125,9 +125,9 @@ void machine_restart(char *cmd)
125 /* Jump into ROM at address 0xffff0000 */ 125 /* Jump into ROM at address 0xffff0000 */
126 cpu_reset(VECTORS_BASE); 126 cpu_reset(VECTORS_BASE);
127 } else { 127 } else {
128 PM_PLLSYSCFG = 0x00002001; /* cpu clk = 250M */ 128 writel(0x00002001, PM_PLLSYSCFG); /* cpu clk = 250M */
129 PM_PLLDDRCFG = 0x00100800; /* ddr clk = 44M */ 129 writel(0x00100800, PM_PLLDDRCFG); /* ddr clk = 44M */
130 PM_PLLVGACFG = 0x00002001; /* vga clk = 250M */ 130 writel(0x00002001, PM_PLLVGACFG); /* vga clk = 250M */
131 131
132 /* Use on-chip reset capability */ 132 /* Use on-chip reset capability */
133 /* following instructions must be in one icache line */ 133 /* following instructions must be in one icache line */
@@ -141,10 +141,10 @@ void machine_restart(char *cmd)
141 " nop; nop; nop\n\t" 141 " nop; nop; nop\n\t"
142 /* prefetch 3 instructions at most */ 142 /* prefetch 3 instructions at most */
143 : 143 :
144 : "r" ((unsigned long)&PM_PMCR), 144 : "r" (PM_PMCR),
145 "r" (PM_PMCR_CFBSYS | PM_PMCR_CFBDDR 145 "r" (PM_PMCR_CFBSYS | PM_PMCR_CFBDDR
146 | PM_PMCR_CFBVGA), 146 | PM_PMCR_CFBVGA),
147 "r" ((unsigned long)&RESETC_SWRR), 147 "r" (RESETC_SWRR),
148 "r" (RESETC_SWRR_SRB) 148 "r" (RESETC_SWRR_SRB)
149 : "r0", "memory"); 149 : "r0", "memory");
150 } 150 }