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authorGuanXuetao <gxt@mprc.pku.edu.cn>2011-03-04 05:07:48 -0500
committerGuanXuetao <gxt@mprc.pku.edu.cn>2011-03-16 21:19:21 -0400
commit1cf46c42d7688a2e09de87fc9201b0e9a0961866 (patch)
treef6bba402319785ed745be62e5b655715626d2761 /arch/unicore32/include
parent4fde87cb13a29c06e0b4c2cba86445492098fbc2 (diff)
unicore32: modify io_p2v and io_v2p macros, and adjust PKUNITY_mmio_BASEs
1. remove __REG macro 2. add (void __iomem *) to io_p2v macro 3. add (phys_addr_t) to io_v2p macro 4. add PKUNITY_AHB_BASE and PKUNITY_APB_BASE definitions 5. modify all PKUNITY_mmio_BASEs from physical addr to virtual addr 6. adjust prefix macro for all usage of PKUNITY_mmio_BASEs -- by advice with Arnd Bergmann Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/unicore32/include')
-rw-r--r--arch/unicore32/include/asm/io.h2
-rw-r--r--arch/unicore32/include/mach/PKUnity.h88
-rw-r--r--arch/unicore32/include/mach/hardware.h11
-rw-r--r--arch/unicore32/include/mach/memory.h4
-rw-r--r--arch/unicore32/include/mach/regs-ac97.h20
-rw-r--r--arch/unicore32/include/mach/regs-dmac.h20
-rw-r--r--arch/unicore32/include/mach/regs-gpio.h16
-rw-r--r--arch/unicore32/include/mach/regs-i2c.h16
-rw-r--r--arch/unicore32/include/mach/regs-intc.h12
-rw-r--r--arch/unicore32/include/mach/regs-nand.h32
-rw-r--r--arch/unicore32/include/mach/regs-ost.h22
-rw-r--r--arch/unicore32/include/mach/regs-pci.h122
-rw-r--r--arch/unicore32/include/mach/regs-pm.h36
-rw-r--r--arch/unicore32/include/mach/regs-ps2.h8
-rw-r--r--arch/unicore32/include/mach/regs-resetc.h4
-rw-r--r--arch/unicore32/include/mach/regs-rtc.h8
-rw-r--r--arch/unicore32/include/mach/regs-sdc.h32
-rw-r--r--arch/unicore32/include/mach/regs-spi.h12
-rw-r--r--arch/unicore32/include/mach/regs-umal.h76
-rw-r--r--arch/unicore32/include/mach/regs-unigfx.h128
20 files changed, 336 insertions, 333 deletions
diff --git a/arch/unicore32/include/asm/io.h b/arch/unicore32/include/asm/io.h
index 2483fcbadbe4..4bd87f3d13d4 100644
--- a/arch/unicore32/include/asm/io.h
+++ b/arch/unicore32/include/asm/io.h
@@ -18,7 +18,7 @@
18#include <asm/memory.h> 18#include <asm/memory.h>
19#include <asm/system.h> 19#include <asm/system.h>
20 20
21#define PCI_IOBASE io_p2v(PKUNITY_PCILIO_BASE) 21#define PCI_IOBASE PKUNITY_PCILIO_BASE
22#include <asm-generic/io.h> 22#include <asm-generic/io.h>
23 23
24/* 24/*
diff --git a/arch/unicore32/include/mach/PKUnity.h b/arch/unicore32/include/mach/PKUnity.h
index 940e9ed0941c..a18bdc3810e6 100644
--- a/arch/unicore32/include/mach/PKUnity.h
+++ b/arch/unicore32/include/mach/PKUnity.h
@@ -22,83 +22,87 @@
22 */ 22 */
23#define PKUNITY_SDRAM_BASE 0x00000000 /* 0x00000000 - 0x7FFFFFFF 2GB */ 23#define PKUNITY_SDRAM_BASE 0x00000000 /* 0x00000000 - 0x7FFFFFFF 2GB */
24#define PKUNITY_MMIO_BASE 0x80000000 /* 0x80000000 - 0xFFFFFFFF 2GB */ 24#define PKUNITY_MMIO_BASE 0x80000000 /* 0x80000000 - 0xFFFFFFFF 2GB */
25#define PKUNITY_PCI_BASE 0x80000000 /* 0x80000000 - 0xBFFFFFFF 1GB */
26#include "regs-pci.h"
27#define PKUNITY_BOOT_ROM2_BASE 0xF4000000 /* 0xF4000000 - 0xF7FFFFFF 64MB */
28#define PKUNITY_BOOT_SRAM2_BASE 0xF8000000 /* 0xF8000000 - 0xFBFFFFFF 64MB */
29#define PKUNITY_BOOT_FLASH_BASE 0xFC000000 /* 0xFC000000 - 0xFFFFFFFF 64MB */
30 25
31/* 26/*
32 * PKUNITY Memory Map Addresses: 0x0D000000 - 0x0EFFFFFF (32MB) 27 * PKUNITY Memory Map Addresses: 0x0D000000 - 0x0EFFFFFF (32MB)
28 * 0x0D000000 - 0x0DFFFFFF 16MB: for UVC
29 * 0x0E000000 - 0x0EFFFFFF 16MB: for UNIGFX
33 */ 30 */
34#define PKUNITY_UVC_MMAP_BASE 0x0D000000 /* 0x0D000000 - 0x0DFFFFFF 16MB */ 31#define PKUNITY_UVC_MMAP_BASE 0x0D000000
35#define PKUNITY_UVC_MMAP_SIZE 0x01000000 /* 16MB */ 32#define PKUNITY_UVC_MMAP_SIZE 0x01000000 /* 16MB */
36#define PKUNITY_UNIGFX_MMAP_BASE 0x0E000000 /* 0x0E000000 - 0x0EFFFFFF 16MB */ 33#define PKUNITY_UNIGFX_MMAP_BASE 0x0E000000
37#define PKUNITY_UNIGFX_MMAP_SIZE 0x01000000 /* 16MB */ 34#define PKUNITY_UNIGFX_MMAP_SIZE 0x01000000 /* 16MB */
38 35
39/* 36/*
40 * PKUNITY System Bus Addresses (PCI): 0x80000000 - 0xBFFFFFFF (1GB) 37 * PKUNITY System Bus Addresses (PCI): 0x80000000 - 0xBFFFFFFF (1GB)
38 * 0x80000000 - 0x8000000B 12B PCI Configuration regs
39 * 0x80010000 - 0x80010250 592B PCI Bridge Base
40 * 0x80030000 - 0x8003FFFF 64KB PCI Legacy IO
41 * 0x90000000 - 0x97FFFFFF 128MB PCI AHB-PCI MEM-mapping
42 * 0x98000000 - 0x9FFFFFFF 128MB PCI PCI-AHB MEM-mapping
41 */ 43 */
42/* PCI Configuration regs */ 44#define PKUNITY_PCI_BASE io_p2v(0x80000000) /* 0x80000000 - 0xBFFFFFFF 1GB */
43#define PKUNITY_PCICFG_BASE 0x80000000 /* 0x80000000 - 0x8000000B 12B */ 45#include "regs-pci.h"
44/* PCI Bridge Base */ 46
45#define PKUNITY_PCIBRI_BASE 0x80010000 /* 0x80010000 - 0x80010250 592B */ 47#define PKUNITY_PCICFG_BASE (PKUNITY_PCI_BASE + 0x0)
46/* PCI Legacy IO */ 48#define PKUNITY_PCIBRI_BASE (PKUNITY_PCI_BASE + 0x00010000)
47#define PKUNITY_PCILIO_BASE 0x80030000 /* 0x80030000 - 0x8003FFFF 64KB */ 49#define PKUNITY_PCILIO_BASE (PKUNITY_PCI_BASE + 0x00030000)
48/* PCI AHB-PCI MEM-mapping */ 50#define PKUNITY_PCIMEM_BASE (PKUNITY_PCI_BASE + 0x10000000)
49#define PKUNITY_PCIMEM_BASE 0x90000000 /* 0x90000000 - 0x97FFFFFF 128MB */ 51#define PKUNITY_PCIAHB_BASE (PKUNITY_PCI_BASE + 0x18000000)
50/* PCI PCI-AHB MEM-mapping */
51#define PKUNITY_PCIAHB_BASE 0x98000000 /* 0x98000000 - 0x9FFFFFFF 128MB */
52 52
53/* 53/*
54 * PKUNITY System Bus Addresses (AHB): 0xC0000000 - 0xEDFFFFFF (640MB) 54 * PKUNITY System Bus Addresses (AHB): 0xC0000000 - 0xEDFFFFFF (640MB)
55 */ 55 */
56#define PKUNITY_AHB_BASE io_p2v(0xC0000000)
57
56/* AHB-0 is DDR2 SDRAM */ 58/* AHB-0 is DDR2 SDRAM */
57/* AHB-1 is PCI Space */ 59/* AHB-1 is PCI Space */
58#define PKUNITY_ARBITER_BASE 0xC0000000 /* AHB-2 */ 60#define PKUNITY_ARBITER_BASE (PKUNITY_AHB_BASE + 0x000000) /* AHB-2 */
59#define PKUNITY_DDR2CTRL_BASE 0xC0100000 /* AHB-3 */ 61#define PKUNITY_DDR2CTRL_BASE (PKUNITY_AHB_BASE + 0x100000) /* AHB-3 */
60#define PKUNITY_DMAC_BASE 0xC0200000 /* AHB-4 */ 62#define PKUNITY_DMAC_BASE (PKUNITY_AHB_BASE + 0x200000) /* AHB-4 */
61#include "regs-dmac.h" 63#include "regs-dmac.h"
62#define PKUNITY_UMAL_BASE 0xC0300000 /* AHB-5 */ 64#define PKUNITY_UMAL_BASE (PKUNITY_AHB_BASE + 0x300000) /* AHB-5 */
63#include "regs-umal.h" 65#include "regs-umal.h"
64#define PKUNITY_USB_BASE 0xC0400000 /* AHB-6 */ 66#define PKUNITY_USB_BASE (PKUNITY_AHB_BASE + 0x400000) /* AHB-6 */
65#define PKUNITY_SATA_BASE 0xC0500000 /* AHB-7 */ 67#define PKUNITY_SATA_BASE (PKUNITY_AHB_BASE + 0x500000) /* AHB-7 */
66#define PKUNITY_SMC_BASE 0xC0600000 /* AHB-8 */ 68#define PKUNITY_SMC_BASE (PKUNITY_AHB_BASE + 0x600000) /* AHB-8 */
67/* AHB-9 is for APB bridge */ 69/* AHB-9 is for APB bridge */
68#define PKUNITY_MME_BASE 0xC0700000 /* AHB-10 */ 70#define PKUNITY_MME_BASE (PKUNITY_AHB_BASE + 0x700000) /* AHB-10 */
69#define PKUNITY_UNIGFX_BASE 0xC0800000 /* AHB-11 */ 71#define PKUNITY_UNIGFX_BASE (PKUNITY_AHB_BASE + 0x800000) /* AHB-11 */
70#include "regs-unigfx.h" 72#include "regs-unigfx.h"
71#define PKUNITY_NAND_BASE 0xC0900000 /* AHB-12 */ 73#define PKUNITY_NAND_BASE (PKUNITY_AHB_BASE + 0x900000) /* AHB-12 */
72#include "regs-nand.h" 74#include "regs-nand.h"
73#define PKUNITY_H264D_BASE 0xC0A00000 /* AHB-13 */ 75#define PKUNITY_H264D_BASE (PKUNITY_AHB_BASE + 0xA00000) /* AHB-13 */
74#define PKUNITY_H264E_BASE 0xC0B00000 /* AHB-14 */ 76#define PKUNITY_H264E_BASE (PKUNITY_AHB_BASE + 0xB00000) /* AHB-14 */
75 77
76/* 78/*
77 * PKUNITY Peripheral Bus Addresses (APB): 0xEE000000 - 0xEFFFFFFF (128MB) 79 * PKUNITY Peripheral Bus Addresses (APB): 0xEE000000 - 0xEFFFFFFF (128MB)
78 */ 80 */
79#define PKUNITY_UART0_BASE 0xEE000000 /* APB-0 */ 81#define PKUNITY_APB_BASE io_p2v(0xEE000000)
80#define PKUNITY_UART1_BASE 0xEE100000 /* APB-1 */ 82
83#define PKUNITY_UART0_BASE (PKUNITY_APB_BASE + 0x000000) /* APB-0 */
84#define PKUNITY_UART1_BASE (PKUNITY_APB_BASE + 0x100000) /* APB-1 */
81#include "regs-uart.h" 85#include "regs-uart.h"
82#define PKUNITY_I2C_BASE 0xEE200000 /* APB-2 */ 86#define PKUNITY_I2C_BASE (PKUNITY_APB_BASE + 0x200000) /* APB-2 */
83#include "regs-i2c.h" 87#include "regs-i2c.h"
84#define PKUNITY_SPI_BASE 0xEE300000 /* APB-3 */ 88#define PKUNITY_SPI_BASE (PKUNITY_APB_BASE + 0x300000) /* APB-3 */
85#include "regs-spi.h" 89#include "regs-spi.h"
86#define PKUNITY_AC97_BASE 0xEE400000 /* APB-4 */ 90#define PKUNITY_AC97_BASE (PKUNITY_APB_BASE + 0x400000) /* APB-4 */
87#include "regs-ac97.h" 91#include "regs-ac97.h"
88#define PKUNITY_GPIO_BASE 0xEE500000 /* APB-5 */ 92#define PKUNITY_GPIO_BASE (PKUNITY_APB_BASE + 0x500000) /* APB-5 */
89#include "regs-gpio.h" 93#include "regs-gpio.h"
90#define PKUNITY_INTC_BASE 0xEE600000 /* APB-6 */ 94#define PKUNITY_INTC_BASE (PKUNITY_APB_BASE + 0x600000) /* APB-6 */
91#include "regs-intc.h" 95#include "regs-intc.h"
92#define PKUNITY_RTC_BASE 0xEE700000 /* APB-7 */ 96#define PKUNITY_RTC_BASE (PKUNITY_APB_BASE + 0x700000) /* APB-7 */
93#include "regs-rtc.h" 97#include "regs-rtc.h"
94#define PKUNITY_OST_BASE 0xEE800000 /* APB-8 */ 98#define PKUNITY_OST_BASE (PKUNITY_APB_BASE + 0x800000) /* APB-8 */
95#include "regs-ost.h" 99#include "regs-ost.h"
96#define PKUNITY_RESETC_BASE 0xEE900000 /* APB-9 */ 100#define PKUNITY_RESETC_BASE (PKUNITY_APB_BASE + 0x900000) /* APB-9 */
97#include "regs-resetc.h" 101#include "regs-resetc.h"
98#define PKUNITY_PM_BASE 0xEEA00000 /* APB-10 */ 102#define PKUNITY_PM_BASE (PKUNITY_APB_BASE + 0xA00000) /* APB-10 */
99#include "regs-pm.h" 103#include "regs-pm.h"
100#define PKUNITY_PS2_BASE 0xEEB00000 /* APB-11 */ 104#define PKUNITY_PS2_BASE (PKUNITY_APB_BASE + 0xB00000) /* APB-11 */
101#include "regs-ps2.h" 105#include "regs-ps2.h"
102#define PKUNITY_SDC_BASE 0xEEC00000 /* APB-12 */ 106#define PKUNITY_SDC_BASE (PKUNITY_APB_BASE + 0xC00000) /* APB-12 */
103#include "regs-sdc.h" 107#include "regs-sdc.h"
104 108
diff --git a/arch/unicore32/include/mach/hardware.h b/arch/unicore32/include/mach/hardware.h
index b71405ab6de6..930bea6e129a 100644
--- a/arch/unicore32/include/mach/hardware.h
+++ b/arch/unicore32/include/mach/hardware.h
@@ -17,17 +17,16 @@
17 17
18#include "PKUnity.h" 18#include "PKUnity.h"
19 19
20#ifndef __ASSEMBLY__
21#define io_p2v(x) (void __iomem *)((x) - PKUNITY_MMIO_BASE)
22#define io_v2p(x) (phys_addr_t)((x) + PKUNITY_MMIO_BASE)
23#else
20#define io_p2v(x) ((x) - PKUNITY_MMIO_BASE) 24#define io_p2v(x) ((x) - PKUNITY_MMIO_BASE)
21#define io_v2p(x) ((x) + PKUNITY_MMIO_BASE) 25#define io_v2p(x) ((x) + PKUNITY_MMIO_BASE)
22
23#ifndef __ASSEMBLY__
24
25# define __REG(x) (void __iomem *)io_p2v(x)
26
27#endif 26#endif
28 27
29#define PCIBIOS_MIN_IO 0x4000 /* should lower than 64KB */ 28#define PCIBIOS_MIN_IO 0x4000 /* should lower than 64KB */
30#define PCIBIOS_MIN_MEM PKUNITY_PCIMEM_BASE 29#define PCIBIOS_MIN_MEM io_v2p(PKUNITY_PCIMEM_BASE)
31 30
32/* 31/*
33 * We override the standard dma-mask routines for bouncing. 32 * We override the standard dma-mask routines for bouncing.
diff --git a/arch/unicore32/include/mach/memory.h b/arch/unicore32/include/mach/memory.h
index b774eff3ea65..0bf21c944710 100644
--- a/arch/unicore32/include/mach/memory.h
+++ b/arch/unicore32/include/mach/memory.h
@@ -45,8 +45,8 @@ void puv3_pci_adjust_zones(unsigned long *size, unsigned long *holes);
45#define is_pcibus_device(dev) (dev && \ 45#define is_pcibus_device(dev) (dev && \
46 (strncmp(dev->bus->name, "pci", 3) == 0)) 46 (strncmp(dev->bus->name, "pci", 3) == 0))
47 47
48#define __virt_to_pcibus(x) (__virt_to_phys(x) + PKUNITY_PCIAHB_BASE) 48#define __virt_to_pcibus(x) (__virt_to_phys((x) + PKUNITY_PCIAHB_BASE))
49#define __pcibus_to_virt(x) __phys_to_virt((x) - PKUNITY_PCIAHB_BASE) 49#define __pcibus_to_virt(x) (__phys_to_virt(x) - PKUNITY_PCIAHB_BASE)
50 50
51/* kuser area */ 51/* kuser area */
52#define KUSER_VECPAGE_BASE (KUSER_BASE + UL(0x3fff0000)) 52#define KUSER_VECPAGE_BASE (KUSER_BASE + UL(0x3fff0000))
diff --git a/arch/unicore32/include/mach/regs-ac97.h b/arch/unicore32/include/mach/regs-ac97.h
index ce299bf4adae..b7563e9d6503 100644
--- a/arch/unicore32/include/mach/regs-ac97.h
+++ b/arch/unicore32/include/mach/regs-ac97.h
@@ -2,16 +2,16 @@
2 * PKUnity AC97 Registers 2 * PKUnity AC97 Registers
3 */ 3 */
4 4
5#define PKUNITY_AC97_CONR __REG(PKUNITY_AC97_BASE + 0x0000) 5#define PKUNITY_AC97_CONR (PKUNITY_AC97_BASE + 0x0000)
6#define PKUNITY_AC97_OCR __REG(PKUNITY_AC97_BASE + 0x0004) 6#define PKUNITY_AC97_OCR (PKUNITY_AC97_BASE + 0x0004)
7#define PKUNITY_AC97_ICR __REG(PKUNITY_AC97_BASE + 0x0008) 7#define PKUNITY_AC97_ICR (PKUNITY_AC97_BASE + 0x0008)
8#define PKUNITY_AC97_CRAC __REG(PKUNITY_AC97_BASE + 0x000C) 8#define PKUNITY_AC97_CRAC (PKUNITY_AC97_BASE + 0x000C)
9#define PKUNITY_AC97_INTR __REG(PKUNITY_AC97_BASE + 0x0010) 9#define PKUNITY_AC97_INTR (PKUNITY_AC97_BASE + 0x0010)
10#define PKUNITY_AC97_INTRSTAT __REG(PKUNITY_AC97_BASE + 0x0014) 10#define PKUNITY_AC97_INTRSTAT (PKUNITY_AC97_BASE + 0x0014)
11#define PKUNITY_AC97_INTRCLEAR __REG(PKUNITY_AC97_BASE + 0x0018) 11#define PKUNITY_AC97_INTRCLEAR (PKUNITY_AC97_BASE + 0x0018)
12#define PKUNITY_AC97_ENABLE __REG(PKUNITY_AC97_BASE + 0x001C) 12#define PKUNITY_AC97_ENABLE (PKUNITY_AC97_BASE + 0x001C)
13#define PKUNITY_AC97_OUT_FIFO __REG(PKUNITY_AC97_BASE + 0x0020) 13#define PKUNITY_AC97_OUT_FIFO (PKUNITY_AC97_BASE + 0x0020)
14#define PKUNITY_AC97_IN_FIFO __REG(PKUNITY_AC97_BASE + 0x0030) 14#define PKUNITY_AC97_IN_FIFO (PKUNITY_AC97_BASE + 0x0030)
15 15
16#define AC97_CODEC_REG(v) FIELD((v), 7, 16) 16#define AC97_CODEC_REG(v) FIELD((v), 7, 16)
17#define AC97_CODEC_VAL(v) FIELD((v), 16, 0) 17#define AC97_CODEC_VAL(v) FIELD((v), 16, 0)
diff --git a/arch/unicore32/include/mach/regs-dmac.h b/arch/unicore32/include/mach/regs-dmac.h
index 09fce9d0d640..66de9e7d1c8f 100644
--- a/arch/unicore32/include/mach/regs-dmac.h
+++ b/arch/unicore32/include/mach/regs-dmac.h
@@ -5,27 +5,27 @@
5/* 5/*
6 * Interrupt Status Reg DMAC_ISR. 6 * Interrupt Status Reg DMAC_ISR.
7 */ 7 */
8#define DMAC_ISR __REG(PKUNITY_DMAC_BASE + 0x0020) 8#define DMAC_ISR (PKUNITY_DMAC_BASE + 0x0020)
9/* 9/*
10 * Interrupt Transfer Complete Status Reg DMAC_ITCSR. 10 * Interrupt Transfer Complete Status Reg DMAC_ITCSR.
11 */ 11 */
12#define DMAC_ITCSR __REG(PKUNITY_DMAC_BASE + 0x0050) 12#define DMAC_ITCSR (PKUNITY_DMAC_BASE + 0x0050)
13/* 13/*
14 * Interrupt Transfer Complete Clear Reg DMAC_ITCCR. 14 * Interrupt Transfer Complete Clear Reg DMAC_ITCCR.
15 */ 15 */
16#define DMAC_ITCCR __REG(PKUNITY_DMAC_BASE + 0x0060) 16#define DMAC_ITCCR (PKUNITY_DMAC_BASE + 0x0060)
17/* 17/*
18 * Interrupt Error Status Reg DMAC_IESR. 18 * Interrupt Error Status Reg DMAC_IESR.
19 */ 19 */
20#define DMAC_IESR __REG(PKUNITY_DMAC_BASE + 0x0080) 20#define DMAC_IESR (PKUNITY_DMAC_BASE + 0x0080)
21/* 21/*
22 * Interrupt Error Clear Reg DMAC_IECR. 22 * Interrupt Error Clear Reg DMAC_IECR.
23 */ 23 */
24#define DMAC_IECR __REG(PKUNITY_DMAC_BASE + 0x0090) 24#define DMAC_IECR (PKUNITY_DMAC_BASE + 0x0090)
25/* 25/*
26 * Enable Channels Reg DMAC_ENCH. 26 * Enable Channels Reg DMAC_ENCH.
27 */ 27 */
28#define DMAC_ENCH __REG(PKUNITY_DMAC_BASE + 0x00B0) 28#define DMAC_ENCH (PKUNITY_DMAC_BASE + 0x00B0)
29 29
30/* 30/*
31 * DMA control reg. Space [byte] 31 * DMA control reg. Space [byte]
@@ -35,19 +35,19 @@
35/* 35/*
36 * Source Addr DMAC_SRCADDR(ch). 36 * Source Addr DMAC_SRCADDR(ch).
37 */ 37 */
38#define DMAC_SRCADDR(ch) __REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00) 38#define DMAC_SRCADDR(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00)
39/* 39/*
40 * Destination Addr DMAC_DESTADDR(ch). 40 * Destination Addr DMAC_DESTADDR(ch).
41 */ 41 */
42#define DMAC_DESTADDR(ch) __REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04) 42#define DMAC_DESTADDR(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04)
43/* 43/*
44 * Control Reg DMAC_CONTROL(ch). 44 * Control Reg DMAC_CONTROL(ch).
45 */ 45 */
46#define DMAC_CONTROL(ch) __REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C) 46#define DMAC_CONTROL(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C)
47/* 47/*
48 * Configuration Reg DMAC_CONFIG(ch). 48 * Configuration Reg DMAC_CONFIG(ch).
49 */ 49 */
50#define DMAC_CONFIG(ch) __REG(PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10) 50#define DMAC_CONFIG(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10)
51 51
52#define DMAC_IR_MASK FMASK(6, 0) 52#define DMAC_IR_MASK FMASK(6, 0)
53/* 53/*
diff --git a/arch/unicore32/include/mach/regs-gpio.h b/arch/unicore32/include/mach/regs-gpio.h
index 5dd99d4c209e..0273b861ef96 100644
--- a/arch/unicore32/include/mach/regs-gpio.h
+++ b/arch/unicore32/include/mach/regs-gpio.h
@@ -5,35 +5,35 @@
5/* 5/*
6 * Voltage Status Reg GPIO_GPLR. 6 * Voltage Status Reg GPIO_GPLR.
7 */ 7 */
8#define GPIO_GPLR __REG(PKUNITY_GPIO_BASE + 0x0000) 8#define GPIO_GPLR (PKUNITY_GPIO_BASE + 0x0000)
9/* 9/*
10 * Pin Direction Reg GPIO_GPDR. 10 * Pin Direction Reg GPIO_GPDR.
11 */ 11 */
12#define GPIO_GPDR __REG(PKUNITY_GPIO_BASE + 0x0004) 12#define GPIO_GPDR (PKUNITY_GPIO_BASE + 0x0004)
13/* 13/*
14 * Output Pin Set Reg GPIO_GPSR. 14 * Output Pin Set Reg GPIO_GPSR.
15 */ 15 */
16#define GPIO_GPSR __REG(PKUNITY_GPIO_BASE + 0x0008) 16#define GPIO_GPSR (PKUNITY_GPIO_BASE + 0x0008)
17/* 17/*
18 * Output Pin Clear Reg GPIO_GPCR. 18 * Output Pin Clear Reg GPIO_GPCR.
19 */ 19 */
20#define GPIO_GPCR __REG(PKUNITY_GPIO_BASE + 0x000C) 20#define GPIO_GPCR (PKUNITY_GPIO_BASE + 0x000C)
21/* 21/*
22 * Raise Edge Detect Reg GPIO_GRER. 22 * Raise Edge Detect Reg GPIO_GRER.
23 */ 23 */
24#define GPIO_GRER __REG(PKUNITY_GPIO_BASE + 0x0010) 24#define GPIO_GRER (PKUNITY_GPIO_BASE + 0x0010)
25/* 25/*
26 * Fall Edge Detect Reg GPIO_GFER. 26 * Fall Edge Detect Reg GPIO_GFER.
27 */ 27 */
28#define GPIO_GFER __REG(PKUNITY_GPIO_BASE + 0x0014) 28#define GPIO_GFER (PKUNITY_GPIO_BASE + 0x0014)
29/* 29/*
30 * Edge Status Reg GPIO_GEDR. 30 * Edge Status Reg GPIO_GEDR.
31 */ 31 */
32#define GPIO_GEDR __REG(PKUNITY_GPIO_BASE + 0x0018) 32#define GPIO_GEDR (PKUNITY_GPIO_BASE + 0x0018)
33/* 33/*
34 * Sepcial Voltage Detect Reg GPIO_GPIR. 34 * Sepcial Voltage Detect Reg GPIO_GPIR.
35 */ 35 */
36#define GPIO_GPIR __REG(PKUNITY_GPIO_BASE + 0x0020) 36#define GPIO_GPIR (PKUNITY_GPIO_BASE + 0x0020)
37 37
38#define GPIO_MIN (0) 38#define GPIO_MIN (0)
39#define GPIO_MAX (27) 39#define GPIO_MAX (27)
diff --git a/arch/unicore32/include/mach/regs-i2c.h b/arch/unicore32/include/mach/regs-i2c.h
index 70b704f8dda8..463d108f8bfb 100644
--- a/arch/unicore32/include/mach/regs-i2c.h
+++ b/arch/unicore32/include/mach/regs-i2c.h
@@ -5,35 +5,35 @@
5/* 5/*
6 * Control Reg I2C_CON. 6 * Control Reg I2C_CON.
7 */ 7 */
8#define I2C_CON __REG(PKUNITY_I2C_BASE + 0x0000) 8#define I2C_CON (PKUNITY_I2C_BASE + 0x0000)
9/* 9/*
10 * Target Address Reg I2C_TAR. 10 * Target Address Reg I2C_TAR.
11 */ 11 */
12#define I2C_TAR __REG(PKUNITY_I2C_BASE + 0x0004) 12#define I2C_TAR (PKUNITY_I2C_BASE + 0x0004)
13/* 13/*
14 * Data buffer and command Reg I2C_DATACMD. 14 * Data buffer and command Reg I2C_DATACMD.
15 */ 15 */
16#define I2C_DATACMD __REG(PKUNITY_I2C_BASE + 0x0010) 16#define I2C_DATACMD (PKUNITY_I2C_BASE + 0x0010)
17/* 17/*
18 * Enable Reg I2C_ENABLE. 18 * Enable Reg I2C_ENABLE.
19 */ 19 */
20#define I2C_ENABLE __REG(PKUNITY_I2C_BASE + 0x006C) 20#define I2C_ENABLE (PKUNITY_I2C_BASE + 0x006C)
21/* 21/*
22 * Status Reg I2C_STATUS. 22 * Status Reg I2C_STATUS.
23 */ 23 */
24#define I2C_STATUS __REG(PKUNITY_I2C_BASE + 0x0070) 24#define I2C_STATUS (PKUNITY_I2C_BASE + 0x0070)
25/* 25/*
26 * Tx FIFO Length Reg I2C_TXFLR. 26 * Tx FIFO Length Reg I2C_TXFLR.
27 */ 27 */
28#define I2C_TXFLR __REG(PKUNITY_I2C_BASE + 0x0074) 28#define I2C_TXFLR (PKUNITY_I2C_BASE + 0x0074)
29/* 29/*
30 * Rx FIFO Length Reg I2C_RXFLR. 30 * Rx FIFO Length Reg I2C_RXFLR.
31 */ 31 */
32#define I2C_RXFLR __REG(PKUNITY_I2C_BASE + 0x0078) 32#define I2C_RXFLR (PKUNITY_I2C_BASE + 0x0078)
33/* 33/*
34 * Enable Status Reg I2C_ENSTATUS. 34 * Enable Status Reg I2C_ENSTATUS.
35 */ 35 */
36#define I2C_ENSTATUS __REG(PKUNITY_I2C_BASE + 0x009C) 36#define I2C_ENSTATUS (PKUNITY_I2C_BASE + 0x009C)
37 37
38#define I2C_CON_MASTER FIELD(1, 1, 0) 38#define I2C_CON_MASTER FIELD(1, 1, 0)
39#define I2C_CON_SPEED_STD FIELD(1, 2, 1) 39#define I2C_CON_SPEED_STD FIELD(1, 2, 1)
diff --git a/arch/unicore32/include/mach/regs-intc.h b/arch/unicore32/include/mach/regs-intc.h
index 409ae4776145..25648f89cbd3 100644
--- a/arch/unicore32/include/mach/regs-intc.h
+++ b/arch/unicore32/include/mach/regs-intc.h
@@ -4,25 +4,25 @@
4/* 4/*
5 * INTC Level Reg INTC_ICLR. 5 * INTC Level Reg INTC_ICLR.
6 */ 6 */
7#define INTC_ICLR __REG(PKUNITY_INTC_BASE + 0x0000) 7#define INTC_ICLR (PKUNITY_INTC_BASE + 0x0000)
8/* 8/*
9 * INTC Mask Reg INTC_ICMR. 9 * INTC Mask Reg INTC_ICMR.
10 */ 10 */
11#define INTC_ICMR __REG(PKUNITY_INTC_BASE + 0x0004) 11#define INTC_ICMR (PKUNITY_INTC_BASE + 0x0004)
12/* 12/*
13 * INTC Pending Reg INTC_ICPR. 13 * INTC Pending Reg INTC_ICPR.
14 */ 14 */
15#define INTC_ICPR __REG(PKUNITY_INTC_BASE + 0x0008) 15#define INTC_ICPR (PKUNITY_INTC_BASE + 0x0008)
16/* 16/*
17 * INTC IRQ Pending Reg INTC_ICIP. 17 * INTC IRQ Pending Reg INTC_ICIP.
18 */ 18 */
19#define INTC_ICIP __REG(PKUNITY_INTC_BASE + 0x000C) 19#define INTC_ICIP (PKUNITY_INTC_BASE + 0x000C)
20/* 20/*
21 * INTC REAL Pending Reg INTC_ICFP. 21 * INTC REAL Pending Reg INTC_ICFP.
22 */ 22 */
23#define INTC_ICFP __REG(PKUNITY_INTC_BASE + 0x0010) 23#define INTC_ICFP (PKUNITY_INTC_BASE + 0x0010)
24/* 24/*
25 * INTC Control Reg INTC_ICCR. 25 * INTC Control Reg INTC_ICCR.
26 */ 26 */
27#define INTC_ICCR __REG(PKUNITY_INTC_BASE + 0x0014) 27#define INTC_ICCR (PKUNITY_INTC_BASE + 0x0014)
28 28
diff --git a/arch/unicore32/include/mach/regs-nand.h b/arch/unicore32/include/mach/regs-nand.h
index 0c33fe8c3090..a7c5563bb550 100644
--- a/arch/unicore32/include/mach/regs-nand.h
+++ b/arch/unicore32/include/mach/regs-nand.h
@@ -4,67 +4,67 @@
4/* 4/*
5 * ID Reg. 0 NAND_IDR0 5 * ID Reg. 0 NAND_IDR0
6 */ 6 */
7#define NAND_IDR0 __REG(PKUNITY_NAND_BASE + 0x0000) 7#define NAND_IDR0 (PKUNITY_NAND_BASE + 0x0000)
8/* 8/*
9 * ID Reg. 1 NAND_IDR1 9 * ID Reg. 1 NAND_IDR1
10 */ 10 */
11#define NAND_IDR1 __REG(PKUNITY_NAND_BASE + 0x0004) 11#define NAND_IDR1 (PKUNITY_NAND_BASE + 0x0004)
12/* 12/*
13 * ID Reg. 2 NAND_IDR2 13 * ID Reg. 2 NAND_IDR2
14 */ 14 */
15#define NAND_IDR2 __REG(PKUNITY_NAND_BASE + 0x0008) 15#define NAND_IDR2 (PKUNITY_NAND_BASE + 0x0008)
16/* 16/*
17 * ID Reg. 3 NAND_IDR3 17 * ID Reg. 3 NAND_IDR3
18 */ 18 */
19#define NAND_IDR3 __REG(PKUNITY_NAND_BASE + 0x000C) 19#define NAND_IDR3 (PKUNITY_NAND_BASE + 0x000C)
20/* 20/*
21 * Page Address Reg 0 NAND_PAR0 21 * Page Address Reg 0 NAND_PAR0
22 */ 22 */
23#define NAND_PAR0 __REG(PKUNITY_NAND_BASE + 0x0010) 23#define NAND_PAR0 (PKUNITY_NAND_BASE + 0x0010)
24/* 24/*
25 * Page Address Reg 1 NAND_PAR1 25 * Page Address Reg 1 NAND_PAR1
26 */ 26 */
27#define NAND_PAR1 __REG(PKUNITY_NAND_BASE + 0x0014) 27#define NAND_PAR1 (PKUNITY_NAND_BASE + 0x0014)
28/* 28/*
29 * Page Address Reg 2 NAND_PAR2 29 * Page Address Reg 2 NAND_PAR2
30 */ 30 */
31#define NAND_PAR2 __REG(PKUNITY_NAND_BASE + 0x0018) 31#define NAND_PAR2 (PKUNITY_NAND_BASE + 0x0018)
32/* 32/*
33 * ECC Enable Reg NAND_ECCEN 33 * ECC Enable Reg NAND_ECCEN
34 */ 34 */
35#define NAND_ECCEN __REG(PKUNITY_NAND_BASE + 0x001C) 35#define NAND_ECCEN (PKUNITY_NAND_BASE + 0x001C)
36/* 36/*
37 * Buffer Reg NAND_BUF 37 * Buffer Reg NAND_BUF
38 */ 38 */
39#define NAND_BUF __REG(PKUNITY_NAND_BASE + 0x0020) 39#define NAND_BUF (PKUNITY_NAND_BASE + 0x0020)
40/* 40/*
41 * ECC Status Reg NAND_ECCSR 41 * ECC Status Reg NAND_ECCSR
42 */ 42 */
43#define NAND_ECCSR __REG(PKUNITY_NAND_BASE + 0x0024) 43#define NAND_ECCSR (PKUNITY_NAND_BASE + 0x0024)
44/* 44/*
45 * Command Reg NAND_CMD 45 * Command Reg NAND_CMD
46 */ 46 */
47#define NAND_CMD __REG(PKUNITY_NAND_BASE + 0x0028) 47#define NAND_CMD (PKUNITY_NAND_BASE + 0x0028)
48/* 48/*
49 * DMA Configure Reg NAND_DMACR 49 * DMA Configure Reg NAND_DMACR
50 */ 50 */
51#define NAND_DMACR __REG(PKUNITY_NAND_BASE + 0x002C) 51#define NAND_DMACR (PKUNITY_NAND_BASE + 0x002C)
52/* 52/*
53 * Interrupt Reg NAND_IR 53 * Interrupt Reg NAND_IR
54 */ 54 */
55#define NAND_IR __REG(PKUNITY_NAND_BASE + 0x0030) 55#define NAND_IR (PKUNITY_NAND_BASE + 0x0030)
56/* 56/*
57 * Interrupt Mask Reg NAND_IMR 57 * Interrupt Mask Reg NAND_IMR
58 */ 58 */
59#define NAND_IMR __REG(PKUNITY_NAND_BASE + 0x0034) 59#define NAND_IMR (PKUNITY_NAND_BASE + 0x0034)
60/* 60/*
61 * Chip Enable Reg NAND_CHIPEN 61 * Chip Enable Reg NAND_CHIPEN
62 */ 62 */
63#define NAND_CHIPEN __REG(PKUNITY_NAND_BASE + 0x0038) 63#define NAND_CHIPEN (PKUNITY_NAND_BASE + 0x0038)
64/* 64/*
65 * Address Reg NAND_ADDR 65 * Address Reg NAND_ADDR
66 */ 66 */
67#define NAND_ADDR __REG(PKUNITY_NAND_BASE + 0x003C) 67#define NAND_ADDR (PKUNITY_NAND_BASE + 0x003C)
68 68
69/* 69/*
70 * Command bits NAND_CMD_CMD_MASK 70 * Command bits NAND_CMD_CMD_MASK
diff --git a/arch/unicore32/include/mach/regs-ost.h b/arch/unicore32/include/mach/regs-ost.h
index 33049a827518..7b91fe698eed 100644
--- a/arch/unicore32/include/mach/regs-ost.h
+++ b/arch/unicore32/include/mach/regs-ost.h
@@ -4,47 +4,47 @@
4/* 4/*
5 * Match Reg 0 OST_OSMR0 5 * Match Reg 0 OST_OSMR0
6 */ 6 */
7#define OST_OSMR0 __REG(PKUNITY_OST_BASE + 0x0000) 7#define OST_OSMR0 (PKUNITY_OST_BASE + 0x0000)
8/* 8/*
9 * Match Reg 1 OST_OSMR1 9 * Match Reg 1 OST_OSMR1
10 */ 10 */
11#define OST_OSMR1 __REG(PKUNITY_OST_BASE + 0x0004) 11#define OST_OSMR1 (PKUNITY_OST_BASE + 0x0004)
12/* 12/*
13 * Match Reg 2 OST_OSMR2 13 * Match Reg 2 OST_OSMR2
14 */ 14 */
15#define OST_OSMR2 __REG(PKUNITY_OST_BASE + 0x0008) 15#define OST_OSMR2 (PKUNITY_OST_BASE + 0x0008)
16/* 16/*
17 * Match Reg 3 OST_OSMR3 17 * Match Reg 3 OST_OSMR3
18 */ 18 */
19#define OST_OSMR3 __REG(PKUNITY_OST_BASE + 0x000C) 19#define OST_OSMR3 (PKUNITY_OST_BASE + 0x000C)
20/* 20/*
21 * Counter Reg OST_OSCR 21 * Counter Reg OST_OSCR
22 */ 22 */
23#define OST_OSCR __REG(PKUNITY_OST_BASE + 0x0010) 23#define OST_OSCR (PKUNITY_OST_BASE + 0x0010)
24/* 24/*
25 * Status Reg OST_OSSR 25 * Status Reg OST_OSSR
26 */ 26 */
27#define OST_OSSR __REG(PKUNITY_OST_BASE + 0x0014) 27#define OST_OSSR (PKUNITY_OST_BASE + 0x0014)
28/* 28/*
29 * Watchdog Enable Reg OST_OWER 29 * Watchdog Enable Reg OST_OWER
30 */ 30 */
31#define OST_OWER __REG(PKUNITY_OST_BASE + 0x0018) 31#define OST_OWER (PKUNITY_OST_BASE + 0x0018)
32/* 32/*
33 * Interrupt Enable Reg OST_OIER 33 * Interrupt Enable Reg OST_OIER
34 */ 34 */
35#define OST_OIER __REG(PKUNITY_OST_BASE + 0x001C) 35#define OST_OIER (PKUNITY_OST_BASE + 0x001C)
36/* 36/*
37 * PWM Pulse Width Control Reg OST_PWMPWCR 37 * PWM Pulse Width Control Reg OST_PWMPWCR
38 */ 38 */
39#define OST_PWMPWCR __REG(PKUNITY_OST_BASE + 0x0080) 39#define OST_PWMPWCR (PKUNITY_OST_BASE + 0x0080)
40/* 40/*
41 * PWM Duty Cycle Control Reg OST_PWMDCCR 41 * PWM Duty Cycle Control Reg OST_PWMDCCR
42 */ 42 */
43#define OST_PWMDCCR __REG(PKUNITY_OST_BASE + 0x0084) 43#define OST_PWMDCCR (PKUNITY_OST_BASE + 0x0084)
44/* 44/*
45 * PWM Period Control Reg OST_PWMPCR 45 * PWM Period Control Reg OST_PWMPCR
46 */ 46 */
47#define OST_PWMPCR __REG(PKUNITY_OST_BASE + 0x0088) 47#define OST_PWMPCR (PKUNITY_OST_BASE + 0x0088)
48 48
49/* 49/*
50 * Match detected 0 OST_OSSR_M0 50 * Match detected 0 OST_OSSR_M0
diff --git a/arch/unicore32/include/mach/regs-pci.h b/arch/unicore32/include/mach/regs-pci.h
index e8e1f1a52fd0..6a9341686bf8 100644
--- a/arch/unicore32/include/mach/regs-pci.h
+++ b/arch/unicore32/include/mach/regs-pci.h
@@ -8,79 +8,79 @@
8/* 8/*
9 * PCICFG Bridge Base Reg. 9 * PCICFG Bridge Base Reg.
10 */ 10 */
11#define PCICFG_BRIBASE __REG(PKUNITY_PCICFG_BASE + 0x0000) 11#define PCICFG_BRIBASE (PKUNITY_PCICFG_BASE + 0x0000)
12/* 12/*
13 * PCICFG Address Reg. 13 * PCICFG Address Reg.
14 */ 14 */
15#define PCICFG_ADDR __REG(PKUNITY_PCICFG_BASE + 0x0004) 15#define PCICFG_ADDR (PKUNITY_PCICFG_BASE + 0x0004)
16/* 16/*
17 * PCICFG Address Reg. 17 * PCICFG Address Reg.
18 */ 18 */
19#define PCICFG_DATA __REG(PKUNITY_PCICFG_BASE + 0x0008) 19#define PCICFG_DATA (PKUNITY_PCICFG_BASE + 0x0008)
20 20
21/* 21/*
22 * PCI Bridge configuration space 22 * PCI Bridge configuration space
23 */ 23 */
24#define PCIBRI_ID __REG(PKUNITY_PCIBRI_BASE + 0x0000) 24#define PCIBRI_ID (PKUNITY_PCIBRI_BASE + 0x0000)
25#define PCIBRI_CMD __REG(PKUNITY_PCIBRI_BASE + 0x0004) 25#define PCIBRI_CMD (PKUNITY_PCIBRI_BASE + 0x0004)
26#define PCIBRI_CLASS __REG(PKUNITY_PCIBRI_BASE + 0x0008) 26#define PCIBRI_CLASS (PKUNITY_PCIBRI_BASE + 0x0008)
27#define PCIBRI_LTR __REG(PKUNITY_PCIBRI_BASE + 0x000C) 27#define PCIBRI_LTR (PKUNITY_PCIBRI_BASE + 0x000C)
28#define PCIBRI_BAR0 __REG(PKUNITY_PCIBRI_BASE + 0x0010) 28#define PCIBRI_BAR0 (PKUNITY_PCIBRI_BASE + 0x0010)
29#define PCIBRI_BAR1 __REG(PKUNITY_PCIBRI_BASE + 0x0014) 29#define PCIBRI_BAR1 (PKUNITY_PCIBRI_BASE + 0x0014)
30#define PCIBRI_BAR2 __REG(PKUNITY_PCIBRI_BASE + 0x0018) 30#define PCIBRI_BAR2 (PKUNITY_PCIBRI_BASE + 0x0018)
31#define PCIBRI_BAR3 __REG(PKUNITY_PCIBRI_BASE + 0x001C) 31#define PCIBRI_BAR3 (PKUNITY_PCIBRI_BASE + 0x001C)
32#define PCIBRI_BAR4 __REG(PKUNITY_PCIBRI_BASE + 0x0020) 32#define PCIBRI_BAR4 (PKUNITY_PCIBRI_BASE + 0x0020)
33#define PCIBRI_BAR5 __REG(PKUNITY_PCIBRI_BASE + 0x0024) 33#define PCIBRI_BAR5 (PKUNITY_PCIBRI_BASE + 0x0024)
34 34
35#define PCIBRI_PCICTL0 __REG(PKUNITY_PCIBRI_BASE + 0x0100) 35#define PCIBRI_PCICTL0 (PKUNITY_PCIBRI_BASE + 0x0100)
36#define PCIBRI_PCIBAR0 __REG(PKUNITY_PCIBRI_BASE + 0x0104) 36#define PCIBRI_PCIBAR0 (PKUNITY_PCIBRI_BASE + 0x0104)
37#define PCIBRI_PCIAMR0 __REG(PKUNITY_PCIBRI_BASE + 0x0108) 37#define PCIBRI_PCIAMR0 (PKUNITY_PCIBRI_BASE + 0x0108)
38#define PCIBRI_PCITAR0 __REG(PKUNITY_PCIBRI_BASE + 0x010C) 38#define PCIBRI_PCITAR0 (PKUNITY_PCIBRI_BASE + 0x010C)
39#define PCIBRI_PCICTL1 __REG(PKUNITY_PCIBRI_BASE + 0x0110) 39#define PCIBRI_PCICTL1 (PKUNITY_PCIBRI_BASE + 0x0110)
40#define PCIBRI_PCIBAR1 __REG(PKUNITY_PCIBRI_BASE + 0x0114) 40#define PCIBRI_PCIBAR1 (PKUNITY_PCIBRI_BASE + 0x0114)
41#define PCIBRI_PCIAMR1 __REG(PKUNITY_PCIBRI_BASE + 0x0118) 41#define PCIBRI_PCIAMR1 (PKUNITY_PCIBRI_BASE + 0x0118)
42#define PCIBRI_PCITAR1 __REG(PKUNITY_PCIBRI_BASE + 0x011C) 42#define PCIBRI_PCITAR1 (PKUNITY_PCIBRI_BASE + 0x011C)
43#define PCIBRI_PCICTL2 __REG(PKUNITY_PCIBRI_BASE + 0x0120) 43#define PCIBRI_PCICTL2 (PKUNITY_PCIBRI_BASE + 0x0120)
44#define PCIBRI_PCIBAR2 __REG(PKUNITY_PCIBRI_BASE + 0x0124) 44#define PCIBRI_PCIBAR2 (PKUNITY_PCIBRI_BASE + 0x0124)
45#define PCIBRI_PCIAMR2 __REG(PKUNITY_PCIBRI_BASE + 0x0128) 45#define PCIBRI_PCIAMR2 (PKUNITY_PCIBRI_BASE + 0x0128)
46#define PCIBRI_PCITAR2 __REG(PKUNITY_PCIBRI_BASE + 0x012C) 46#define PCIBRI_PCITAR2 (PKUNITY_PCIBRI_BASE + 0x012C)
47#define PCIBRI_PCICTL3 __REG(PKUNITY_PCIBRI_BASE + 0x0130) 47#define PCIBRI_PCICTL3 (PKUNITY_PCIBRI_BASE + 0x0130)
48#define PCIBRI_PCIBAR3 __REG(PKUNITY_PCIBRI_BASE + 0x0134) 48#define PCIBRI_PCIBAR3 (PKUNITY_PCIBRI_BASE + 0x0134)
49#define PCIBRI_PCIAMR3 __REG(PKUNITY_PCIBRI_BASE + 0x0138) 49#define PCIBRI_PCIAMR3 (PKUNITY_PCIBRI_BASE + 0x0138)
50#define PCIBRI_PCITAR3 __REG(PKUNITY_PCIBRI_BASE + 0x013C) 50#define PCIBRI_PCITAR3 (PKUNITY_PCIBRI_BASE + 0x013C)
51#define PCIBRI_PCICTL4 __REG(PKUNITY_PCIBRI_BASE + 0x0140) 51#define PCIBRI_PCICTL4 (PKUNITY_PCIBRI_BASE + 0x0140)
52#define PCIBRI_PCIBAR4 __REG(PKUNITY_PCIBRI_BASE + 0x0144) 52#define PCIBRI_PCIBAR4 (PKUNITY_PCIBRI_BASE + 0x0144)
53#define PCIBRI_PCIAMR4 __REG(PKUNITY_PCIBRI_BASE + 0x0148) 53#define PCIBRI_PCIAMR4 (PKUNITY_PCIBRI_BASE + 0x0148)
54#define PCIBRI_PCITAR4 __REG(PKUNITY_PCIBRI_BASE + 0x014C) 54#define PCIBRI_PCITAR4 (PKUNITY_PCIBRI_BASE + 0x014C)
55#define PCIBRI_PCICTL5 __REG(PKUNITY_PCIBRI_BASE + 0x0150) 55#define PCIBRI_PCICTL5 (PKUNITY_PCIBRI_BASE + 0x0150)
56#define PCIBRI_PCIBAR5 __REG(PKUNITY_PCIBRI_BASE + 0x0154) 56#define PCIBRI_PCIBAR5 (PKUNITY_PCIBRI_BASE + 0x0154)
57#define PCIBRI_PCIAMR5 __REG(PKUNITY_PCIBRI_BASE + 0x0158) 57#define PCIBRI_PCIAMR5 (PKUNITY_PCIBRI_BASE + 0x0158)
58#define PCIBRI_PCITAR5 __REG(PKUNITY_PCIBRI_BASE + 0x015C) 58#define PCIBRI_PCITAR5 (PKUNITY_PCIBRI_BASE + 0x015C)
59 59
60#define PCIBRI_AHBCTL0 __REG(PKUNITY_PCIBRI_BASE + 0x0180) 60#define PCIBRI_AHBCTL0 (PKUNITY_PCIBRI_BASE + 0x0180)
61#define PCIBRI_AHBBAR0 __REG(PKUNITY_PCIBRI_BASE + 0x0184) 61#define PCIBRI_AHBBAR0 (PKUNITY_PCIBRI_BASE + 0x0184)
62#define PCIBRI_AHBAMR0 __REG(PKUNITY_PCIBRI_BASE + 0x0188) 62#define PCIBRI_AHBAMR0 (PKUNITY_PCIBRI_BASE + 0x0188)
63#define PCIBRI_AHBTAR0 __REG(PKUNITY_PCIBRI_BASE + 0x018C) 63#define PCIBRI_AHBTAR0 (PKUNITY_PCIBRI_BASE + 0x018C)
64#define PCIBRI_AHBCTL1 __REG(PKUNITY_PCIBRI_BASE + 0x0190) 64#define PCIBRI_AHBCTL1 (PKUNITY_PCIBRI_BASE + 0x0190)
65#define PCIBRI_AHBBAR1 __REG(PKUNITY_PCIBRI_BASE + 0x0194) 65#define PCIBRI_AHBBAR1 (PKUNITY_PCIBRI_BASE + 0x0194)
66#define PCIBRI_AHBAMR1 __REG(PKUNITY_PCIBRI_BASE + 0x0198) 66#define PCIBRI_AHBAMR1 (PKUNITY_PCIBRI_BASE + 0x0198)
67#define PCIBRI_AHBTAR1 __REG(PKUNITY_PCIBRI_BASE + 0x019C) 67#define PCIBRI_AHBTAR1 (PKUNITY_PCIBRI_BASE + 0x019C)
68#define PCIBRI_AHBCTL2 __REG(PKUNITY_PCIBRI_BASE + 0x01A0) 68#define PCIBRI_AHBCTL2 (PKUNITY_PCIBRI_BASE + 0x01A0)
69#define PCIBRI_AHBBAR2 __REG(PKUNITY_PCIBRI_BASE + 0x01A4) 69#define PCIBRI_AHBBAR2 (PKUNITY_PCIBRI_BASE + 0x01A4)
70#define PCIBRI_AHBAMR2 __REG(PKUNITY_PCIBRI_BASE + 0x01A8) 70#define PCIBRI_AHBAMR2 (PKUNITY_PCIBRI_BASE + 0x01A8)
71#define PCIBRI_AHBTAR2 __REG(PKUNITY_PCIBRI_BASE + 0x01AC) 71#define PCIBRI_AHBTAR2 (PKUNITY_PCIBRI_BASE + 0x01AC)
72#define PCIBRI_AHBCTL3 __REG(PKUNITY_PCIBRI_BASE + 0x01B0) 72#define PCIBRI_AHBCTL3 (PKUNITY_PCIBRI_BASE + 0x01B0)
73#define PCIBRI_AHBBAR3 __REG(PKUNITY_PCIBRI_BASE + 0x01B4) 73#define PCIBRI_AHBBAR3 (PKUNITY_PCIBRI_BASE + 0x01B4)
74#define PCIBRI_AHBAMR3 __REG(PKUNITY_PCIBRI_BASE + 0x01B8) 74#define PCIBRI_AHBAMR3 (PKUNITY_PCIBRI_BASE + 0x01B8)
75#define PCIBRI_AHBTAR3 __REG(PKUNITY_PCIBRI_BASE + 0x01BC) 75#define PCIBRI_AHBTAR3 (PKUNITY_PCIBRI_BASE + 0x01BC)
76#define PCIBRI_AHBCTL4 __REG(PKUNITY_PCIBRI_BASE + 0x01C0) 76#define PCIBRI_AHBCTL4 (PKUNITY_PCIBRI_BASE + 0x01C0)
77#define PCIBRI_AHBBAR4 __REG(PKUNITY_PCIBRI_BASE + 0x01C4) 77#define PCIBRI_AHBBAR4 (PKUNITY_PCIBRI_BASE + 0x01C4)
78#define PCIBRI_AHBAMR4 __REG(PKUNITY_PCIBRI_BASE + 0x01C8) 78#define PCIBRI_AHBAMR4 (PKUNITY_PCIBRI_BASE + 0x01C8)
79#define PCIBRI_AHBTAR4 __REG(PKUNITY_PCIBRI_BASE + 0x01CC) 79#define PCIBRI_AHBTAR4 (PKUNITY_PCIBRI_BASE + 0x01CC)
80#define PCIBRI_AHBCTL5 __REG(PKUNITY_PCIBRI_BASE + 0x01D0) 80#define PCIBRI_AHBCTL5 (PKUNITY_PCIBRI_BASE + 0x01D0)
81#define PCIBRI_AHBBAR5 __REG(PKUNITY_PCIBRI_BASE + 0x01D4) 81#define PCIBRI_AHBBAR5 (PKUNITY_PCIBRI_BASE + 0x01D4)
82#define PCIBRI_AHBAMR5 __REG(PKUNITY_PCIBRI_BASE + 0x01D8) 82#define PCIBRI_AHBAMR5 (PKUNITY_PCIBRI_BASE + 0x01D8)
83#define PCIBRI_AHBTAR5 __REG(PKUNITY_PCIBRI_BASE + 0x01DC) 83#define PCIBRI_AHBTAR5 (PKUNITY_PCIBRI_BASE + 0x01DC)
84 84
85#define PCIBRI_CTLx_AT FIELD(1, 1, 2) 85#define PCIBRI_CTLx_AT FIELD(1, 1, 2)
86#define PCIBRI_CTLx_PREF FIELD(1, 1, 1) 86#define PCIBRI_CTLx_PREF FIELD(1, 1, 1)
diff --git a/arch/unicore32/include/mach/regs-pm.h b/arch/unicore32/include/mach/regs-pm.h
index ed2d2fc6ad0c..854844aa8f4b 100644
--- a/arch/unicore32/include/mach/regs-pm.h
+++ b/arch/unicore32/include/mach/regs-pm.h
@@ -4,75 +4,75 @@
4/* 4/*
5 * PM Control Reg PM_PMCR 5 * PM Control Reg PM_PMCR
6 */ 6 */
7#define PM_PMCR __REG(PKUNITY_PM_BASE + 0x0000) 7#define PM_PMCR (PKUNITY_PM_BASE + 0x0000)
8/* 8/*
9 * PM General Conf. Reg PM_PGCR 9 * PM General Conf. Reg PM_PGCR
10 */ 10 */
11#define PM_PGCR __REG(PKUNITY_PM_BASE + 0x0004) 11#define PM_PGCR (PKUNITY_PM_BASE + 0x0004)
12/* 12/*
13 * PM PLL Conf. Reg PM_PPCR 13 * PM PLL Conf. Reg PM_PPCR
14 */ 14 */
15#define PM_PPCR __REG(PKUNITY_PM_BASE + 0x0008) 15#define PM_PPCR (PKUNITY_PM_BASE + 0x0008)
16/* 16/*
17 * PM Wakeup Enable Reg PM_PWER 17 * PM Wakeup Enable Reg PM_PWER
18 */ 18 */
19#define PM_PWER __REG(PKUNITY_PM_BASE + 0x000C) 19#define PM_PWER (PKUNITY_PM_BASE + 0x000C)
20/* 20/*
21 * PM GPIO Sleep Status Reg PM_PGSR 21 * PM GPIO Sleep Status Reg PM_PGSR
22 */ 22 */
23#define PM_PGSR __REG(PKUNITY_PM_BASE + 0x0010) 23#define PM_PGSR (PKUNITY_PM_BASE + 0x0010)
24/* 24/*
25 * PM Clock Gate Reg PM_PCGR 25 * PM Clock Gate Reg PM_PCGR
26 */ 26 */
27#define PM_PCGR __REG(PKUNITY_PM_BASE + 0x0014) 27#define PM_PCGR (PKUNITY_PM_BASE + 0x0014)
28/* 28/*
29 * PM SYS PLL Conf. Reg PM_PLLSYSCFG 29 * PM SYS PLL Conf. Reg PM_PLLSYSCFG
30 */ 30 */
31#define PM_PLLSYSCFG __REG(PKUNITY_PM_BASE + 0x0018) 31#define PM_PLLSYSCFG (PKUNITY_PM_BASE + 0x0018)
32/* 32/*
33 * PM DDR PLL Conf. Reg PM_PLLDDRCFG 33 * PM DDR PLL Conf. Reg PM_PLLDDRCFG
34 */ 34 */
35#define PM_PLLDDRCFG __REG(PKUNITY_PM_BASE + 0x001C) 35#define PM_PLLDDRCFG (PKUNITY_PM_BASE + 0x001C)
36/* 36/*
37 * PM VGA PLL Conf. Reg PM_PLLVGACFG 37 * PM VGA PLL Conf. Reg PM_PLLVGACFG
38 */ 38 */
39#define PM_PLLVGACFG __REG(PKUNITY_PM_BASE + 0x0020) 39#define PM_PLLVGACFG (PKUNITY_PM_BASE + 0x0020)
40/* 40/*
41 * PM Div Conf. Reg PM_DIVCFG 41 * PM Div Conf. Reg PM_DIVCFG
42 */ 42 */
43#define PM_DIVCFG __REG(PKUNITY_PM_BASE + 0x0024) 43#define PM_DIVCFG (PKUNITY_PM_BASE + 0x0024)
44/* 44/*
45 * PM SYS PLL Status Reg PM_PLLSYSSTATUS 45 * PM SYS PLL Status Reg PM_PLLSYSSTATUS
46 */ 46 */
47#define PM_PLLSYSSTATUS __REG(PKUNITY_PM_BASE + 0x0028) 47#define PM_PLLSYSSTATUS (PKUNITY_PM_BASE + 0x0028)
48/* 48/*
49 * PM DDR PLL Status Reg PM_PLLDDRSTATUS 49 * PM DDR PLL Status Reg PM_PLLDDRSTATUS
50 */ 50 */
51#define PM_PLLDDRSTATUS __REG(PKUNITY_PM_BASE + 0x002C) 51#define PM_PLLDDRSTATUS (PKUNITY_PM_BASE + 0x002C)
52/* 52/*
53 * PM VGA PLL Status Reg PM_PLLVGASTATUS 53 * PM VGA PLL Status Reg PM_PLLVGASTATUS
54 */ 54 */
55#define PM_PLLVGASTATUS __REG(PKUNITY_PM_BASE + 0x0030) 55#define PM_PLLVGASTATUS (PKUNITY_PM_BASE + 0x0030)
56/* 56/*
57 * PM Div Status Reg PM_DIVSTATUS 57 * PM Div Status Reg PM_DIVSTATUS
58 */ 58 */
59#define PM_DIVSTATUS __REG(PKUNITY_PM_BASE + 0x0034) 59#define PM_DIVSTATUS (PKUNITY_PM_BASE + 0x0034)
60/* 60/*
61 * PM Software Reset Reg PM_SWRESET 61 * PM Software Reset Reg PM_SWRESET
62 */ 62 */
63#define PM_SWRESET __REG(PKUNITY_PM_BASE + 0x0038) 63#define PM_SWRESET (PKUNITY_PM_BASE + 0x0038)
64/* 64/*
65 * PM DDR2 PAD Start Reg PM_DDR2START 65 * PM DDR2 PAD Start Reg PM_DDR2START
66 */ 66 */
67#define PM_DDR2START __REG(PKUNITY_PM_BASE + 0x003C) 67#define PM_DDR2START (PKUNITY_PM_BASE + 0x003C)
68/* 68/*
69 * PM DDR2 PAD Status Reg PM_DDR2CAL0 69 * PM DDR2 PAD Status Reg PM_DDR2CAL0
70 */ 70 */
71#define PM_DDR2CAL0 __REG(PKUNITY_PM_BASE + 0x0040) 71#define PM_DDR2CAL0 (PKUNITY_PM_BASE + 0x0040)
72/* 72/*
73 * PM PLL DFC Done Reg PM_PLLDFCDONE 73 * PM PLL DFC Done Reg PM_PLLDFCDONE
74 */ 74 */
75#define PM_PLLDFCDONE __REG(PKUNITY_PM_BASE + 0x0044) 75#define PM_PLLDFCDONE (PKUNITY_PM_BASE + 0x0044)
76 76
77#define PM_PMCR_SFB FIELD(1, 1, 0) 77#define PM_PMCR_SFB FIELD(1, 1, 0)
78#define PM_PMCR_IFB FIELD(1, 1, 1) 78#define PM_PMCR_IFB FIELD(1, 1, 1)
diff --git a/arch/unicore32/include/mach/regs-ps2.h b/arch/unicore32/include/mach/regs-ps2.h
index 7da2071838ab..17d4e6dc0069 100644
--- a/arch/unicore32/include/mach/regs-ps2.h
+++ b/arch/unicore32/include/mach/regs-ps2.h
@@ -4,17 +4,17 @@
4/* 4/*
5 * the same as I8042_DATA_REG PS2_DATA 5 * the same as I8042_DATA_REG PS2_DATA
6 */ 6 */
7#define PS2_DATA __REG(PKUNITY_PS2_BASE + 0x0060) 7#define PS2_DATA (PKUNITY_PS2_BASE + 0x0060)
8/* 8/*
9 * the same as I8042_COMMAND_REG PS2_COMMAND 9 * the same as I8042_COMMAND_REG PS2_COMMAND
10 */ 10 */
11#define PS2_COMMAND __REG(PKUNITY_PS2_BASE + 0x0064) 11#define PS2_COMMAND (PKUNITY_PS2_BASE + 0x0064)
12/* 12/*
13 * the same as I8042_STATUS_REG PS2_STATUS 13 * the same as I8042_STATUS_REG PS2_STATUS
14 */ 14 */
15#define PS2_STATUS __REG(PKUNITY_PS2_BASE + 0x0064) 15#define PS2_STATUS (PKUNITY_PS2_BASE + 0x0064)
16/* 16/*
17 * counter reg PS2_CNT 17 * counter reg PS2_CNT
18 */ 18 */
19#define PS2_CNT __REG(PKUNITY_PS2_BASE + 0x0068) 19#define PS2_CNT (PKUNITY_PS2_BASE + 0x0068)
20 20
diff --git a/arch/unicore32/include/mach/regs-resetc.h b/arch/unicore32/include/mach/regs-resetc.h
index 17639898fd84..39900cf4c936 100644
--- a/arch/unicore32/include/mach/regs-resetc.h
+++ b/arch/unicore32/include/mach/regs-resetc.h
@@ -4,11 +4,11 @@
4/* 4/*
5 * Software Reset Register 5 * Software Reset Register
6 */ 6 */
7#define RESETC_SWRR __REG(PKUNITY_RESETC_BASE + 0x0000) 7#define RESETC_SWRR (PKUNITY_RESETC_BASE + 0x0000)
8/* 8/*
9 * Reset Status Register 9 * Reset Status Register
10 */ 10 */
11#define RESETC_RSSR __REG(PKUNITY_RESETC_BASE + 0x0004) 11#define RESETC_RSSR (PKUNITY_RESETC_BASE + 0x0004)
12 12
13/* 13/*
14 * Software Reset Bit 14 * Software Reset Bit
diff --git a/arch/unicore32/include/mach/regs-rtc.h b/arch/unicore32/include/mach/regs-rtc.h
index 155e38757186..e94ca193271d 100644
--- a/arch/unicore32/include/mach/regs-rtc.h
+++ b/arch/unicore32/include/mach/regs-rtc.h
@@ -4,19 +4,19 @@
4/* 4/*
5 * RTC Alarm Reg RTC_RTAR 5 * RTC Alarm Reg RTC_RTAR
6 */ 6 */
7#define RTC_RTAR __REG(PKUNITY_RTC_BASE + 0x0000) 7#define RTC_RTAR (PKUNITY_RTC_BASE + 0x0000)
8/* 8/*
9 * RTC Count Reg RTC_RCNR 9 * RTC Count Reg RTC_RCNR
10 */ 10 */
11#define RTC_RCNR __REG(PKUNITY_RTC_BASE + 0x0004) 11#define RTC_RCNR (PKUNITY_RTC_BASE + 0x0004)
12/* 12/*
13 * RTC Trim Reg RTC_RTTR 13 * RTC Trim Reg RTC_RTTR
14 */ 14 */
15#define RTC_RTTR __REG(PKUNITY_RTC_BASE + 0x0008) 15#define RTC_RTTR (PKUNITY_RTC_BASE + 0x0008)
16/* 16/*
17 * RTC Status Reg RTC_RTSR 17 * RTC Status Reg RTC_RTSR
18 */ 18 */
19#define RTC_RTSR __REG(PKUNITY_RTC_BASE + 0x0010) 19#define RTC_RTSR (PKUNITY_RTC_BASE + 0x0010)
20 20
21/* 21/*
22 * ALarm detected RTC_RTSR_AL 22 * ALarm detected RTC_RTSR_AL
diff --git a/arch/unicore32/include/mach/regs-sdc.h b/arch/unicore32/include/mach/regs-sdc.h
index 3457b88c453c..1303ecf660ba 100644
--- a/arch/unicore32/include/mach/regs-sdc.h
+++ b/arch/unicore32/include/mach/regs-sdc.h
@@ -4,67 +4,67 @@
4/* 4/*
5 * Clock Control Reg SDC_CCR 5 * Clock Control Reg SDC_CCR
6 */ 6 */
7#define SDC_CCR __REG(PKUNITY_SDC_BASE + 0x0000) 7#define SDC_CCR (PKUNITY_SDC_BASE + 0x0000)
8/* 8/*
9 * Software Reset Reg SDC_SRR 9 * Software Reset Reg SDC_SRR
10 */ 10 */
11#define SDC_SRR __REG(PKUNITY_SDC_BASE + 0x0004) 11#define SDC_SRR (PKUNITY_SDC_BASE + 0x0004)
12/* 12/*
13 * Argument Reg SDC_ARGUMENT 13 * Argument Reg SDC_ARGUMENT
14 */ 14 */
15#define SDC_ARGUMENT __REG(PKUNITY_SDC_BASE + 0x0008) 15#define SDC_ARGUMENT (PKUNITY_SDC_BASE + 0x0008)
16/* 16/*
17 * Command Reg SDC_COMMAND 17 * Command Reg SDC_COMMAND
18 */ 18 */
19#define SDC_COMMAND __REG(PKUNITY_SDC_BASE + 0x000C) 19#define SDC_COMMAND (PKUNITY_SDC_BASE + 0x000C)
20/* 20/*
21 * Block Size Reg SDC_BLOCKSIZE 21 * Block Size Reg SDC_BLOCKSIZE
22 */ 22 */
23#define SDC_BLOCKSIZE __REG(PKUNITY_SDC_BASE + 0x0010) 23#define SDC_BLOCKSIZE (PKUNITY_SDC_BASE + 0x0010)
24/* 24/*
25 * Block Cound Reg SDC_BLOCKCOUNT 25 * Block Cound Reg SDC_BLOCKCOUNT
26 */ 26 */
27#define SDC_BLOCKCOUNT __REG(PKUNITY_SDC_BASE + 0x0014) 27#define SDC_BLOCKCOUNT (PKUNITY_SDC_BASE + 0x0014)
28/* 28/*
29 * Transfer Mode Reg SDC_TMR 29 * Transfer Mode Reg SDC_TMR
30 */ 30 */
31#define SDC_TMR __REG(PKUNITY_SDC_BASE + 0x0018) 31#define SDC_TMR (PKUNITY_SDC_BASE + 0x0018)
32/* 32/*
33 * Response Reg. 0 SDC_RES0 33 * Response Reg. 0 SDC_RES0
34 */ 34 */
35#define SDC_RES0 __REG(PKUNITY_SDC_BASE + 0x001C) 35#define SDC_RES0 (PKUNITY_SDC_BASE + 0x001C)
36/* 36/*
37 * Response Reg. 1 SDC_RES1 37 * Response Reg. 1 SDC_RES1
38 */ 38 */
39#define SDC_RES1 __REG(PKUNITY_SDC_BASE + 0x0020) 39#define SDC_RES1 (PKUNITY_SDC_BASE + 0x0020)
40/* 40/*
41 * Response Reg. 2 SDC_RES2 41 * Response Reg. 2 SDC_RES2
42 */ 42 */
43#define SDC_RES2 __REG(PKUNITY_SDC_BASE + 0x0024) 43#define SDC_RES2 (PKUNITY_SDC_BASE + 0x0024)
44/* 44/*
45 * Response Reg. 3 SDC_RES3 45 * Response Reg. 3 SDC_RES3
46 */ 46 */
47#define SDC_RES3 __REG(PKUNITY_SDC_BASE + 0x0028) 47#define SDC_RES3 (PKUNITY_SDC_BASE + 0x0028)
48/* 48/*
49 * Read Timeout Control Reg SDC_RTCR 49 * Read Timeout Control Reg SDC_RTCR
50 */ 50 */
51#define SDC_RTCR __REG(PKUNITY_SDC_BASE + 0x002C) 51#define SDC_RTCR (PKUNITY_SDC_BASE + 0x002C)
52/* 52/*
53 * Interrupt Status Reg SDC_ISR 53 * Interrupt Status Reg SDC_ISR
54 */ 54 */
55#define SDC_ISR __REG(PKUNITY_SDC_BASE + 0x0030) 55#define SDC_ISR (PKUNITY_SDC_BASE + 0x0030)
56/* 56/*
57 * Interrupt Status Mask Reg SDC_ISMR 57 * Interrupt Status Mask Reg SDC_ISMR
58 */ 58 */
59#define SDC_ISMR __REG(PKUNITY_SDC_BASE + 0x0034) 59#define SDC_ISMR (PKUNITY_SDC_BASE + 0x0034)
60/* 60/*
61 * RX FIFO SDC_RXFIFO 61 * RX FIFO SDC_RXFIFO
62 */ 62 */
63#define SDC_RXFIFO __REG(PKUNITY_SDC_BASE + 0x0038) 63#define SDC_RXFIFO (PKUNITY_SDC_BASE + 0x0038)
64/* 64/*
65 * TX FIFO SDC_TXFIFO 65 * TX FIFO SDC_TXFIFO
66 */ 66 */
67#define SDC_TXFIFO __REG(PKUNITY_SDC_BASE + 0x003C) 67#define SDC_TXFIFO (PKUNITY_SDC_BASE + 0x003C)
68 68
69/* 69/*
70 * SD Clock Enable SDC_CCR_CLKEN 70 * SD Clock Enable SDC_CCR_CLKEN
diff --git a/arch/unicore32/include/mach/regs-spi.h b/arch/unicore32/include/mach/regs-spi.h
index cadc713c55b9..de16895e2dc0 100644
--- a/arch/unicore32/include/mach/regs-spi.h
+++ b/arch/unicore32/include/mach/regs-spi.h
@@ -4,27 +4,27 @@
4/* 4/*
5 * Control reg. 0 SPI_CR0 5 * Control reg. 0 SPI_CR0
6 */ 6 */
7#define SPI_CR0 __REG(PKUNITY_SPI_BASE + 0x0000) 7#define SPI_CR0 (PKUNITY_SPI_BASE + 0x0000)
8/* 8/*
9 * Control reg. 1 SPI_CR1 9 * Control reg. 1 SPI_CR1
10 */ 10 */
11#define SPI_CR1 __REG(PKUNITY_SPI_BASE + 0x0004) 11#define SPI_CR1 (PKUNITY_SPI_BASE + 0x0004)
12/* 12/*
13 * Enable reg SPI_SSIENR 13 * Enable reg SPI_SSIENR
14 */ 14 */
15#define SPI_SSIENR __REG(PKUNITY_SPI_BASE + 0x0008) 15#define SPI_SSIENR (PKUNITY_SPI_BASE + 0x0008)
16/* 16/*
17 * Status reg SPI_SR 17 * Status reg SPI_SR
18 */ 18 */
19#define SPI_SR __REG(PKUNITY_SPI_BASE + 0x0028) 19#define SPI_SR (PKUNITY_SPI_BASE + 0x0028)
20/* 20/*
21 * Interrupt Mask reg SPI_IMR 21 * Interrupt Mask reg SPI_IMR
22 */ 22 */
23#define SPI_IMR __REG(PKUNITY_SPI_BASE + 0x002C) 23#define SPI_IMR (PKUNITY_SPI_BASE + 0x002C)
24/* 24/*
25 * Interrupt Status reg SPI_ISR 25 * Interrupt Status reg SPI_ISR
26 */ 26 */
27#define SPI_ISR __REG(PKUNITY_SPI_BASE + 0x0030) 27#define SPI_ISR (PKUNITY_SPI_BASE + 0x0030)
28 28
29/* 29/*
30 * Enable SPI Controller SPI_SSIENR_EN 30 * Enable SPI Controller SPI_SSIENR_EN
diff --git a/arch/unicore32/include/mach/regs-umal.h b/arch/unicore32/include/mach/regs-umal.h
index 2e718d1e86cc..885bb62fee71 100644
--- a/arch/unicore32/include/mach/regs-umal.h
+++ b/arch/unicore32/include/mach/regs-umal.h
@@ -10,86 +10,86 @@
10/* 10/*
11 * TX/RX reset and control UMAL_CFG1 11 * TX/RX reset and control UMAL_CFG1
12 */ 12 */
13#define UMAL_CFG1 __REG(PKUNITY_UMAL_BASE + 0x0000) 13#define UMAL_CFG1 (PKUNITY_UMAL_BASE + 0x0000)
14/* 14/*
15 * MAC interface mode control UMAL_CFG2 15 * MAC interface mode control UMAL_CFG2
16 */ 16 */
17#define UMAL_CFG2 __REG(PKUNITY_UMAL_BASE + 0x0004) 17#define UMAL_CFG2 (PKUNITY_UMAL_BASE + 0x0004)
18/* 18/*
19 * Inter Packet/Frame Gap UMAL_IPGIFG 19 * Inter Packet/Frame Gap UMAL_IPGIFG
20 */ 20 */
21#define UMAL_IPGIFG __REG(PKUNITY_UMAL_BASE + 0x0008) 21#define UMAL_IPGIFG (PKUNITY_UMAL_BASE + 0x0008)
22/* 22/*
23 * Collision retry or backoff UMAL_HALFDUPLEX 23 * Collision retry or backoff UMAL_HALFDUPLEX
24 */ 24 */
25#define UMAL_HALFDUPLEX __REG(PKUNITY_UMAL_BASE + 0x000c) 25#define UMAL_HALFDUPLEX (PKUNITY_UMAL_BASE + 0x000c)
26/* 26/*
27 * Maximum Frame Length UMAL_MAXFRAME 27 * Maximum Frame Length UMAL_MAXFRAME
28 */ 28 */
29#define UMAL_MAXFRAME __REG(PKUNITY_UMAL_BASE + 0x0010) 29#define UMAL_MAXFRAME (PKUNITY_UMAL_BASE + 0x0010)
30/* 30/*
31 * Test Regsiter UMAL_TESTREG 31 * Test Regsiter UMAL_TESTREG
32 */ 32 */
33#define UMAL_TESTREG __REG(PKUNITY_UMAL_BASE + 0x001c) 33#define UMAL_TESTREG (PKUNITY_UMAL_BASE + 0x001c)
34/* 34/*
35 * MII Management Configure UMAL_MIICFG 35 * MII Management Configure UMAL_MIICFG
36 */ 36 */
37#define UMAL_MIICFG __REG(PKUNITY_UMAL_BASE + 0x0020) 37#define UMAL_MIICFG (PKUNITY_UMAL_BASE + 0x0020)
38/* 38/*
39 * MII Management Command UMAL_MIICMD 39 * MII Management Command UMAL_MIICMD
40 */ 40 */
41#define UMAL_MIICMD __REG(PKUNITY_UMAL_BASE + 0x0024) 41#define UMAL_MIICMD (PKUNITY_UMAL_BASE + 0x0024)
42/* 42/*
43 * MII Management Address UMAL_MIIADDR 43 * MII Management Address UMAL_MIIADDR
44 */ 44 */
45#define UMAL_MIIADDR __REG(PKUNITY_UMAL_BASE + 0x0028) 45#define UMAL_MIIADDR (PKUNITY_UMAL_BASE + 0x0028)
46/* 46/*
47 * MII Management Control UMAL_MIICTRL 47 * MII Management Control UMAL_MIICTRL
48 */ 48 */
49#define UMAL_MIICTRL __REG(PKUNITY_UMAL_BASE + 0x002c) 49#define UMAL_MIICTRL (PKUNITY_UMAL_BASE + 0x002c)
50/* 50/*
51 * MII Management Status UMAL_MIISTATUS 51 * MII Management Status UMAL_MIISTATUS
52 */ 52 */
53#define UMAL_MIISTATUS __REG(PKUNITY_UMAL_BASE + 0x0030) 53#define UMAL_MIISTATUS (PKUNITY_UMAL_BASE + 0x0030)
54/* 54/*
55 * MII Managment Indicator UMAL_MIIIDCT 55 * MII Managment Indicator UMAL_MIIIDCT
56 */ 56 */
57#define UMAL_MIIIDCT __REG(PKUNITY_UMAL_BASE + 0x0034) 57#define UMAL_MIIIDCT (PKUNITY_UMAL_BASE + 0x0034)
58/* 58/*
59 * Interface Control UMAL_IFCTRL 59 * Interface Control UMAL_IFCTRL
60 */ 60 */
61#define UMAL_IFCTRL __REG(PKUNITY_UMAL_BASE + 0x0038) 61#define UMAL_IFCTRL (PKUNITY_UMAL_BASE + 0x0038)
62/* 62/*
63 * Interface Status UMAL_IFSTATUS 63 * Interface Status UMAL_IFSTATUS
64 */ 64 */
65#define UMAL_IFSTATUS __REG(PKUNITY_UMAL_BASE + 0x003c) 65#define UMAL_IFSTATUS (PKUNITY_UMAL_BASE + 0x003c)
66/* 66/*
67 * MAC address (high 4 bytes) UMAL_STADDR1 67 * MAC address (high 4 bytes) UMAL_STADDR1
68 */ 68 */
69#define UMAL_STADDR1 __REG(PKUNITY_UMAL_BASE + 0x0040) 69#define UMAL_STADDR1 (PKUNITY_UMAL_BASE + 0x0040)
70/* 70/*
71 * MAC address (low 2 bytes) UMAL_STADDR2 71 * MAC address (low 2 bytes) UMAL_STADDR2
72 */ 72 */
73#define UMAL_STADDR2 __REG(PKUNITY_UMAL_BASE + 0x0044) 73#define UMAL_STADDR2 (PKUNITY_UMAL_BASE + 0x0044)
74 74
75/* FIFO MODULE OF UMAL */ 75/* FIFO MODULE OF UMAL */
76/* UMAL's FIFO module provides data queuing for increased system level 76/* UMAL's FIFO module provides data queuing for increased system level
77 * throughput 77 * throughput
78 */ 78 */
79#define UMAL_FIFOCFG0 __REG(PKUNITY_UMAL_BASE + 0x0048) 79#define UMAL_FIFOCFG0 (PKUNITY_UMAL_BASE + 0x0048)
80#define UMAL_FIFOCFG1 __REG(PKUNITY_UMAL_BASE + 0x004c) 80#define UMAL_FIFOCFG1 (PKUNITY_UMAL_BASE + 0x004c)
81#define UMAL_FIFOCFG2 __REG(PKUNITY_UMAL_BASE + 0x0050) 81#define UMAL_FIFOCFG2 (PKUNITY_UMAL_BASE + 0x0050)
82#define UMAL_FIFOCFG3 __REG(PKUNITY_UMAL_BASE + 0x0054) 82#define UMAL_FIFOCFG3 (PKUNITY_UMAL_BASE + 0x0054)
83#define UMAL_FIFOCFG4 __REG(PKUNITY_UMAL_BASE + 0x0058) 83#define UMAL_FIFOCFG4 (PKUNITY_UMAL_BASE + 0x0058)
84#define UMAL_FIFOCFG5 __REG(PKUNITY_UMAL_BASE + 0x005c) 84#define UMAL_FIFOCFG5 (PKUNITY_UMAL_BASE + 0x005c)
85#define UMAL_FIFORAM0 __REG(PKUNITY_UMAL_BASE + 0x0060) 85#define UMAL_FIFORAM0 (PKUNITY_UMAL_BASE + 0x0060)
86#define UMAL_FIFORAM1 __REG(PKUNITY_UMAL_BASE + 0x0064) 86#define UMAL_FIFORAM1 (PKUNITY_UMAL_BASE + 0x0064)
87#define UMAL_FIFORAM2 __REG(PKUNITY_UMAL_BASE + 0x0068) 87#define UMAL_FIFORAM2 (PKUNITY_UMAL_BASE + 0x0068)
88#define UMAL_FIFORAM3 __REG(PKUNITY_UMAL_BASE + 0x006c) 88#define UMAL_FIFORAM3 (PKUNITY_UMAL_BASE + 0x006c)
89#define UMAL_FIFORAM4 __REG(PKUNITY_UMAL_BASE + 0x0070) 89#define UMAL_FIFORAM4 (PKUNITY_UMAL_BASE + 0x0070)
90#define UMAL_FIFORAM5 __REG(PKUNITY_UMAL_BASE + 0x0074) 90#define UMAL_FIFORAM5 (PKUNITY_UMAL_BASE + 0x0074)
91#define UMAL_FIFORAM6 __REG(PKUNITY_UMAL_BASE + 0x0078) 91#define UMAL_FIFORAM6 (PKUNITY_UMAL_BASE + 0x0078)
92#define UMAL_FIFORAM7 __REG(PKUNITY_UMAL_BASE + 0x007c) 92#define UMAL_FIFORAM7 (PKUNITY_UMAL_BASE + 0x007c)
93 93
94/* MAHBE MODUEL OF UMAL */ 94/* MAHBE MODUEL OF UMAL */
95/* UMAL's MAHBE module interfaces to the host system through 32-bit AHB Master 95/* UMAL's MAHBE module interfaces to the host system through 32-bit AHB Master
@@ -99,35 +99,35 @@
99/* 99/*
100 * Transmit Control UMAL_DMATxCtrl 100 * Transmit Control UMAL_DMATxCtrl
101 */ 101 */
102#define UMAL_DMATxCtrl __REG(PKUNITY_UMAL_BASE + 0x0180) 102#define UMAL_DMATxCtrl (PKUNITY_UMAL_BASE + 0x0180)
103/* 103/*
104 * Pointer to TX Descripter UMAL_DMATxDescriptor 104 * Pointer to TX Descripter UMAL_DMATxDescriptor
105 */ 105 */
106#define UMAL_DMATxDescriptor __REG(PKUNITY_UMAL_BASE + 0x0184) 106#define UMAL_DMATxDescriptor (PKUNITY_UMAL_BASE + 0x0184)
107/* 107/*
108 * Status of Tx Packet Transfers UMAL_DMATxStatus 108 * Status of Tx Packet Transfers UMAL_DMATxStatus
109 */ 109 */
110#define UMAL_DMATxStatus __REG(PKUNITY_UMAL_BASE + 0x0188) 110#define UMAL_DMATxStatus (PKUNITY_UMAL_BASE + 0x0188)
111/* 111/*
112 * Receive Control UMAL_DMARxCtrl 112 * Receive Control UMAL_DMARxCtrl
113 */ 113 */
114#define UMAL_DMARxCtrl __REG(PKUNITY_UMAL_BASE + 0x018c) 114#define UMAL_DMARxCtrl (PKUNITY_UMAL_BASE + 0x018c)
115/* 115/*
116 * Pointer to Rx Descriptor UMAL_DMARxDescriptor 116 * Pointer to Rx Descriptor UMAL_DMARxDescriptor
117 */ 117 */
118#define UMAL_DMARxDescriptor __REG(PKUNITY_UMAL_BASE + 0x0190) 118#define UMAL_DMARxDescriptor (PKUNITY_UMAL_BASE + 0x0190)
119/* 119/*
120 * Status of Rx Packet Transfers UMAL_DMARxStatus 120 * Status of Rx Packet Transfers UMAL_DMARxStatus
121 */ 121 */
122#define UMAL_DMARxStatus __REG(PKUNITY_UMAL_BASE + 0x0194) 122#define UMAL_DMARxStatus (PKUNITY_UMAL_BASE + 0x0194)
123/* 123/*
124 * Interrupt Mask UMAL_DMAIntrMask 124 * Interrupt Mask UMAL_DMAIntrMask
125 */ 125 */
126#define UMAL_DMAIntrMask __REG(PKUNITY_UMAL_BASE + 0x0198) 126#define UMAL_DMAIntrMask (PKUNITY_UMAL_BASE + 0x0198)
127/* 127/*
128 * Interrupts, read only UMAL_DMAInterrupt 128 * Interrupts, read only UMAL_DMAInterrupt
129 */ 129 */
130#define UMAL_DMAInterrupt __REG(PKUNITY_UMAL_BASE + 0x019c) 130#define UMAL_DMAInterrupt (PKUNITY_UMAL_BASE + 0x019c)
131 131
132/* 132/*
133 * Commands for UMAL_CFG1 register 133 * Commands for UMAL_CFG1 register
diff --git a/arch/unicore32/include/mach/regs-unigfx.h b/arch/unicore32/include/mach/regs-unigfx.h
index 58bbd540a393..faf8b287fccf 100644
--- a/arch/unicore32/include/mach/regs-unigfx.h
+++ b/arch/unicore32/include/mach/regs-unigfx.h
@@ -11,67 +11,67 @@
11/* 11/*
12 * control reg UDE_CFG 12 * control reg UDE_CFG
13 */ 13 */
14#define UDE_CFG __REG(UDE_BASE + 0x0000) 14#define UDE_CFG (UDE_BASE + 0x0000)
15/* 15/*
16 * framebuffer start address reg UDE_FSA 16 * framebuffer start address reg UDE_FSA
17 */ 17 */
18#define UDE_FSA __REG(UDE_BASE + 0x0004) 18#define UDE_FSA (UDE_BASE + 0x0004)
19/* 19/*
20 * line size reg UDE_LS 20 * line size reg UDE_LS
21 */ 21 */
22#define UDE_LS __REG(UDE_BASE + 0x0008) 22#define UDE_LS (UDE_BASE + 0x0008)
23/* 23/*
24 * pitch size reg UDE_PS 24 * pitch size reg UDE_PS
25 */ 25 */
26#define UDE_PS __REG(UDE_BASE + 0x000C) 26#define UDE_PS (UDE_BASE + 0x000C)
27/* 27/*
28 * horizontal active time reg UDE_HAT 28 * horizontal active time reg UDE_HAT
29 */ 29 */
30#define UDE_HAT __REG(UDE_BASE + 0x0010) 30#define UDE_HAT (UDE_BASE + 0x0010)
31/* 31/*
32 * horizontal blank time reg UDE_HBT 32 * horizontal blank time reg UDE_HBT
33 */ 33 */
34#define UDE_HBT __REG(UDE_BASE + 0x0014) 34#define UDE_HBT (UDE_BASE + 0x0014)
35/* 35/*
36 * horizontal sync time reg UDE_HST 36 * horizontal sync time reg UDE_HST
37 */ 37 */
38#define UDE_HST __REG(UDE_BASE + 0x0018) 38#define UDE_HST (UDE_BASE + 0x0018)
39/* 39/*
40 * vertival active time reg UDE_VAT 40 * vertival active time reg UDE_VAT
41 */ 41 */
42#define UDE_VAT __REG(UDE_BASE + 0x001C) 42#define UDE_VAT (UDE_BASE + 0x001C)
43/* 43/*
44 * vertival blank time reg UDE_VBT 44 * vertival blank time reg UDE_VBT
45 */ 45 */
46#define UDE_VBT __REG(UDE_BASE + 0x0020) 46#define UDE_VBT (UDE_BASE + 0x0020)
47/* 47/*
48 * vertival sync time reg UDE_VST 48 * vertival sync time reg UDE_VST
49 */ 49 */
50#define UDE_VST __REG(UDE_BASE + 0x0024) 50#define UDE_VST (UDE_BASE + 0x0024)
51/* 51/*
52 * cursor position UDE_CXY 52 * cursor position UDE_CXY
53 */ 53 */
54#define UDE_CXY __REG(UDE_BASE + 0x0028) 54#define UDE_CXY (UDE_BASE + 0x0028)
55/* 55/*
56 * cursor front color UDE_CC0 56 * cursor front color UDE_CC0
57 */ 57 */
58#define UDE_CC0 __REG(UDE_BASE + 0x002C) 58#define UDE_CC0 (UDE_BASE + 0x002C)
59/* 59/*
60 * cursor background color UDE_CC1 60 * cursor background color UDE_CC1
61 */ 61 */
62#define UDE_CC1 __REG(UDE_BASE + 0x0030) 62#define UDE_CC1 (UDE_BASE + 0x0030)
63/* 63/*
64 * video position UDE_VXY 64 * video position UDE_VXY
65 */ 65 */
66#define UDE_VXY __REG(UDE_BASE + 0x0034) 66#define UDE_VXY (UDE_BASE + 0x0034)
67/* 67/*
68 * video start address reg UDE_VSA 68 * video start address reg UDE_VSA
69 */ 69 */
70#define UDE_VSA __REG(UDE_BASE + 0x0040) 70#define UDE_VSA (UDE_BASE + 0x0040)
71/* 71/*
72 * video size reg UDE_VS 72 * video size reg UDE_VS
73 */ 73 */
74#define UDE_VS __REG(UDE_BASE + 0x004C) 74#define UDE_VS (UDE_BASE + 0x004C)
75 75
76/* 76/*
77 * command reg for UNIGFX GE 77 * command reg for UNIGFX GE
@@ -79,102 +79,102 @@
79/* 79/*
80 * src xy reg UGE_SRCXY 80 * src xy reg UGE_SRCXY
81 */ 81 */
82#define UGE_SRCXY __REG(UGE_BASE + 0x0000) 82#define UGE_SRCXY (UGE_BASE + 0x0000)
83/* 83/*
84 * dst xy reg UGE_DSTXY 84 * dst xy reg UGE_DSTXY
85 */ 85 */
86#define UGE_DSTXY __REG(UGE_BASE + 0x0004) 86#define UGE_DSTXY (UGE_BASE + 0x0004)
87/* 87/*
88 * pitch reg UGE_PITCH 88 * pitch reg UGE_PITCH
89 */ 89 */
90#define UGE_PITCH __REG(UGE_BASE + 0x0008) 90#define UGE_PITCH (UGE_BASE + 0x0008)
91/* 91/*
92 * src start reg UGE_SRCSTART 92 * src start reg UGE_SRCSTART
93 */ 93 */
94#define UGE_SRCSTART __REG(UGE_BASE + 0x000C) 94#define UGE_SRCSTART (UGE_BASE + 0x000C)
95/* 95/*
96 * dst start reg UGE_DSTSTART 96 * dst start reg UGE_DSTSTART
97 */ 97 */
98#define UGE_DSTSTART __REG(UGE_BASE + 0x0010) 98#define UGE_DSTSTART (UGE_BASE + 0x0010)
99/* 99/*
100 * width height reg UGE_WIDHEIGHT 100 * width height reg UGE_WIDHEIGHT
101 */ 101 */
102#define UGE_WIDHEIGHT __REG(UGE_BASE + 0x0014) 102#define UGE_WIDHEIGHT (UGE_BASE + 0x0014)
103/* 103/*
104 * rop alpah reg UGE_ROPALPHA 104 * rop alpah reg UGE_ROPALPHA
105 */ 105 */
106#define UGE_ROPALPHA __REG(UGE_BASE + 0x0018) 106#define UGE_ROPALPHA (UGE_BASE + 0x0018)
107/* 107/*
108 * front color UGE_FCOLOR 108 * front color UGE_FCOLOR
109 */ 109 */
110#define UGE_FCOLOR __REG(UGE_BASE + 0x001C) 110#define UGE_FCOLOR (UGE_BASE + 0x001C)
111/* 111/*
112 * background color UGE_BCOLOR 112 * background color UGE_BCOLOR
113 */ 113 */
114#define UGE_BCOLOR __REG(UGE_BASE + 0x0020) 114#define UGE_BCOLOR (UGE_BASE + 0x0020)
115/* 115/*
116 * src color key for high value UGE_SCH 116 * src color key for high value UGE_SCH
117 */ 117 */
118#define UGE_SCH __REG(UGE_BASE + 0x0024) 118#define UGE_SCH (UGE_BASE + 0x0024)
119/* 119/*
120 * dst color key for high value UGE_DCH 120 * dst color key for high value UGE_DCH
121 */ 121 */
122#define UGE_DCH __REG(UGE_BASE + 0x0028) 122#define UGE_DCH (UGE_BASE + 0x0028)
123/* 123/*
124 * src color key for low value UGE_SCL 124 * src color key for low value UGE_SCL
125 */ 125 */
126#define UGE_SCL __REG(UGE_BASE + 0x002C) 126#define UGE_SCL (UGE_BASE + 0x002C)
127/* 127/*
128 * dst color key for low value UGE_DCL 128 * dst color key for low value UGE_DCL
129 */ 129 */
130#define UGE_DCL __REG(UGE_BASE + 0x0030) 130#define UGE_DCL (UGE_BASE + 0x0030)
131/* 131/*
132 * clip 0 reg UGE_CLIP0 132 * clip 0 reg UGE_CLIP0
133 */ 133 */
134#define UGE_CLIP0 __REG(UGE_BASE + 0x0034) 134#define UGE_CLIP0 (UGE_BASE + 0x0034)
135/* 135/*
136 * clip 1 reg UGE_CLIP1 136 * clip 1 reg UGE_CLIP1
137 */ 137 */
138#define UGE_CLIP1 __REG(UGE_BASE + 0x0038) 138#define UGE_CLIP1 (UGE_BASE + 0x0038)
139/* 139/*
140 * command reg UGE_COMMAND 140 * command reg UGE_COMMAND
141 */ 141 */
142#define UGE_COMMAND __REG(UGE_BASE + 0x003C) 142#define UGE_COMMAND (UGE_BASE + 0x003C)
143/* 143/*
144 * pattern 0 UGE_P0 144 * pattern 0 UGE_P0
145 */ 145 */
146#define UGE_P0 __REG(UGE_BASE + 0x0040) 146#define UGE_P0 (UGE_BASE + 0x0040)
147#define UGE_P1 __REG(UGE_BASE + 0x0044) 147#define UGE_P1 (UGE_BASE + 0x0044)
148#define UGE_P2 __REG(UGE_BASE + 0x0048) 148#define UGE_P2 (UGE_BASE + 0x0048)
149#define UGE_P3 __REG(UGE_BASE + 0x004C) 149#define UGE_P3 (UGE_BASE + 0x004C)
150#define UGE_P4 __REG(UGE_BASE + 0x0050) 150#define UGE_P4 (UGE_BASE + 0x0050)
151#define UGE_P5 __REG(UGE_BASE + 0x0054) 151#define UGE_P5 (UGE_BASE + 0x0054)
152#define UGE_P6 __REG(UGE_BASE + 0x0058) 152#define UGE_P6 (UGE_BASE + 0x0058)
153#define UGE_P7 __REG(UGE_BASE + 0x005C) 153#define UGE_P7 (UGE_BASE + 0x005C)
154#define UGE_P8 __REG(UGE_BASE + 0x0060) 154#define UGE_P8 (UGE_BASE + 0x0060)
155#define UGE_P9 __REG(UGE_BASE + 0x0064) 155#define UGE_P9 (UGE_BASE + 0x0064)
156#define UGE_P10 __REG(UGE_BASE + 0x0068) 156#define UGE_P10 (UGE_BASE + 0x0068)
157#define UGE_P11 __REG(UGE_BASE + 0x006C) 157#define UGE_P11 (UGE_BASE + 0x006C)
158#define UGE_P12 __REG(UGE_BASE + 0x0070) 158#define UGE_P12 (UGE_BASE + 0x0070)
159#define UGE_P13 __REG(UGE_BASE + 0x0074) 159#define UGE_P13 (UGE_BASE + 0x0074)
160#define UGE_P14 __REG(UGE_BASE + 0x0078) 160#define UGE_P14 (UGE_BASE + 0x0078)
161#define UGE_P15 __REG(UGE_BASE + 0x007C) 161#define UGE_P15 (UGE_BASE + 0x007C)
162#define UGE_P16 __REG(UGE_BASE + 0x0080) 162#define UGE_P16 (UGE_BASE + 0x0080)
163#define UGE_P17 __REG(UGE_BASE + 0x0084) 163#define UGE_P17 (UGE_BASE + 0x0084)
164#define UGE_P18 __REG(UGE_BASE + 0x0088) 164#define UGE_P18 (UGE_BASE + 0x0088)
165#define UGE_P19 __REG(UGE_BASE + 0x008C) 165#define UGE_P19 (UGE_BASE + 0x008C)
166#define UGE_P20 __REG(UGE_BASE + 0x0090) 166#define UGE_P20 (UGE_BASE + 0x0090)
167#define UGE_P21 __REG(UGE_BASE + 0x0094) 167#define UGE_P21 (UGE_BASE + 0x0094)
168#define UGE_P22 __REG(UGE_BASE + 0x0098) 168#define UGE_P22 (UGE_BASE + 0x0098)
169#define UGE_P23 __REG(UGE_BASE + 0x009C) 169#define UGE_P23 (UGE_BASE + 0x009C)
170#define UGE_P24 __REG(UGE_BASE + 0x00A0) 170#define UGE_P24 (UGE_BASE + 0x00A0)
171#define UGE_P25 __REG(UGE_BASE + 0x00A4) 171#define UGE_P25 (UGE_BASE + 0x00A4)
172#define UGE_P26 __REG(UGE_BASE + 0x00A8) 172#define UGE_P26 (UGE_BASE + 0x00A8)
173#define UGE_P27 __REG(UGE_BASE + 0x00AC) 173#define UGE_P27 (UGE_BASE + 0x00AC)
174#define UGE_P28 __REG(UGE_BASE + 0x00B0) 174#define UGE_P28 (UGE_BASE + 0x00B0)
175#define UGE_P29 __REG(UGE_BASE + 0x00B4) 175#define UGE_P29 (UGE_BASE + 0x00B4)
176#define UGE_P30 __REG(UGE_BASE + 0x00B8) 176#define UGE_P30 (UGE_BASE + 0x00B8)
177#define UGE_P31 __REG(UGE_BASE + 0x00BC) 177#define UGE_P31 (UGE_BASE + 0x00BC)
178 178
179#define UDE_CFG_DST_MASK FMASK(2, 8) 179#define UDE_CFG_DST_MASK FMASK(2, 8)
180#define UDE_CFG_DST8 FIELD(0x0, 2, 8) 180#define UDE_CFG_DST8 FIELD(0x0, 2, 8)
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-16 21:31:57 -0500