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authorLinus Torvalds <torvalds@linux-foundation.org>2014-12-10 12:01:01 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-12-10 12:01:01 -0500
commit9e66645d72d3c395da92b0f8855c787f4b5f0e89 (patch)
tree61b94adb6c32340c45b6d984837556b6b845e983 /arch/tile
parentecb50f0afd35a51ef487e8a54b976052eb03d729 (diff)
parent74faaf7aa64c76b60db0f5c994fd43a46be772ce (diff)
Merge branch 'irq-irqdomain-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq domain updates from Thomas Gleixner: "The real interesting irq updates: - Support for hierarchical irq domains: For complex interrupt routing scenarios where more than one interrupt related chip is involved we had no proper representation in the generic interrupt infrastructure so far. That made people implement rather ugly constructs in their nested irq chip implementations. The main offenders are x86 and arm/gic. To distangle that mess we have now hierarchical irqdomains which seperate the various interrupt chips and connect them via the hierarchical domains. That keeps the domain specific details internal to the particular hierarchy level and removes the criss/cross referencing of chip internals. The resulting hierarchy for a complex x86 system will look like this: vector mapped: 74 msi-0 mapped: 2 dmar-ir-1 mapped: 69 ioapic-1 mapped: 4 ioapic-0 mapped: 20 pci-msi-2 mapped: 45 dmar-ir-0 mapped: 3 ioapic-2 mapped: 1 pci-msi-1 mapped: 2 htirq mapped: 0 Neither ioapic nor pci-msi know about the dmar interrupt remapping between themself and the vector domain. If interrupt remapping is disabled ioapic and pci-msi become direct childs of the vector domain. In hindsight we should have done that years ago, but in hindsight we always know better :) - Support for generic MSI interrupt domain handling We have more and more non PCI related MSI interrupts, so providing a generic infrastructure for this is better than having all affected architectures implementing their own private hacks. - Support for PCI-MSI interrupt domain handling, based on the generic MSI support. This part carries the pci/msi branch from Bjorn Helgaas pci tree to avoid a massive conflict. The PCI/MSI parts are acked by Bjorn. I have two more branches on top of this. The full conversion of x86 to hierarchical domains and a partial conversion of arm/gic" * 'irq-irqdomain-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (41 commits) genirq: Move irq_chip_write_msi_msg() helper to core PCI/MSI: Allow an msi_controller to be associated to an irq domain PCI/MSI: Provide mechanism to alloc/free MSI/MSIX interrupt from irqdomain PCI/MSI: Enhance core to support hierarchy irqdomain PCI/MSI: Move cached entry functions to irq core genirq: Provide default callbacks for msi_domain_ops genirq: Introduce msi_domain_alloc/free_irqs() asm-generic: Add msi.h genirq: Add generic msi irq domain support genirq: Introduce callback irq_chip.irq_write_msi_msg genirq: Work around __irq_set_handler vs stacked domains ordering issues irqdomain: Introduce helper function irq_domain_add_hierarchy() irqdomain: Implement a method to automatically call parent domains alloc/free genirq: Introduce helper irq_domain_set_info() to reduce duplicated code genirq: Split out flow handler typedefs into seperate header file genirq: Add IRQ_SET_MASK_OK_DONE to support stacked irqchip genirq: Introduce irq_chip.irq_compose_msi_msg() to support stacked irqchip genirq: Add more helper functions to support stacked irq_chip genirq: Introduce helper functions to support stacked irq_chip irqdomain: Do irq_find_mapping and set_type for hierarchy irqdomain in case OF ...
Diffstat (limited to 'arch/tile')
-rw-r--r--arch/tile/kernel/pci_gx.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c
index e39f9c542807..e717af20dada 100644
--- a/arch/tile/kernel/pci_gx.c
+++ b/arch/tile/kernel/pci_gx.c
@@ -1453,7 +1453,7 @@ static struct pci_ops tile_cfg_ops = {
1453static unsigned int tilegx_msi_startup(struct irq_data *d) 1453static unsigned int tilegx_msi_startup(struct irq_data *d)
1454{ 1454{
1455 if (d->msi_desc) 1455 if (d->msi_desc)
1456 unmask_msi_irq(d); 1456 pci_msi_unmask_irq(d);
1457 1457
1458 return 0; 1458 return 0;
1459} 1459}
@@ -1465,14 +1465,14 @@ static void tilegx_msi_ack(struct irq_data *d)
1465 1465
1466static void tilegx_msi_mask(struct irq_data *d) 1466static void tilegx_msi_mask(struct irq_data *d)
1467{ 1467{
1468 mask_msi_irq(d); 1468 pci_msi_mask_irq(d);
1469 __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq); 1469 __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
1470} 1470}
1471 1471
1472static void tilegx_msi_unmask(struct irq_data *d) 1472static void tilegx_msi_unmask(struct irq_data *d)
1473{ 1473{
1474 __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq); 1474 __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
1475 unmask_msi_irq(d); 1475 pci_msi_unmask_irq(d);
1476} 1476}
1477 1477
1478static struct irq_chip tilegx_msi_chip = { 1478static struct irq_chip tilegx_msi_chip = {
@@ -1590,7 +1590,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1590 msg.address_hi = msi_addr >> 32; 1590 msg.address_hi = msi_addr >> 32;
1591 msg.address_lo = msi_addr & 0xffffffff; 1591 msg.address_lo = msi_addr & 0xffffffff;
1592 1592
1593 write_msi_msg(irq, &msg); 1593 pci_write_msi_msg(irq, &msg);
1594 irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq); 1594 irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq);
1595 irq_set_handler_data(irq, controller); 1595 irq_set_handler_data(irq, controller);
1596 1596