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authorChris Metcalf <cmetcalf@tilera.com>2013-08-12 14:09:28 -0400
committerChris Metcalf <cmetcalf@tilera.com>2013-09-03 14:50:36 -0400
commit6ec006ede5e0526c20cd7ed5e20df637ea592b1f (patch)
treea05b7f36199a31d11e54ae1e87a8c2fa6dafdfa0 /arch/tile
parentacbde1db294932623aad15dd8cc6e37b28340f26 (diff)
tilegx: provide kernel support for the tilegx UART shim
The TILE-Gx chip includes an on-chip UART. This change adds support for using the UART from within the kernel. The UART shim has more functionality than is exposed here, but to keep the kernel code and binary simpler, this is a subset of the full API designed to enable a standard Linux tty serial driver only. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile')
-rw-r--r--arch/tile/gxio/Kconfig5
-rw-r--r--arch/tile/gxio/Makefile1
-rw-r--r--arch/tile/gxio/iorpc_uart.c77
-rw-r--r--arch/tile/gxio/uart.c87
-rw-r--r--arch/tile/include/arch/uart.h300
-rw-r--r--arch/tile/include/arch/uart_def.h120
-rw-r--r--arch/tile/include/gxio/iorpc_uart.h40
-rw-r--r--arch/tile/include/gxio/uart.h105
-rw-r--r--arch/tile/include/hv/drv_uart_intf.h33
9 files changed, 768 insertions, 0 deletions
diff --git a/arch/tile/gxio/Kconfig b/arch/tile/gxio/Kconfig
index d221f8d6de8b..d4e10d58071b 100644
--- a/arch/tile/gxio/Kconfig
+++ b/arch/tile/gxio/Kconfig
@@ -26,3 +26,8 @@ config TILE_GXIO_TRIO
26config TILE_GXIO_USB_HOST 26config TILE_GXIO_USB_HOST
27 bool 27 bool
28 select TILE_GXIO 28 select TILE_GXIO
29
30# Support direct access to the TILE-Gx UART hardware from kernel space.
31config TILE_GXIO_UART
32 bool
33 select TILE_GXIO
diff --git a/arch/tile/gxio/Makefile b/arch/tile/gxio/Makefile
index 8684bcaa74ea..26ae2c727467 100644
--- a/arch/tile/gxio/Makefile
+++ b/arch/tile/gxio/Makefile
@@ -6,4 +6,5 @@ obj-$(CONFIG_TILE_GXIO) += iorpc_globals.o kiorpc.o
6obj-$(CONFIG_TILE_GXIO_DMA) += dma_queue.o 6obj-$(CONFIG_TILE_GXIO_DMA) += dma_queue.o
7obj-$(CONFIG_TILE_GXIO_MPIPE) += mpipe.o iorpc_mpipe.o iorpc_mpipe_info.o 7obj-$(CONFIG_TILE_GXIO_MPIPE) += mpipe.o iorpc_mpipe.o iorpc_mpipe_info.o
8obj-$(CONFIG_TILE_GXIO_TRIO) += trio.o iorpc_trio.o 8obj-$(CONFIG_TILE_GXIO_TRIO) += trio.o iorpc_trio.o
9obj-$(CONFIG_TILE_GXIO_UART) += uart.o iorpc_uart.o
9obj-$(CONFIG_TILE_GXIO_USB_HOST) += usb_host.o iorpc_usb_host.o 10obj-$(CONFIG_TILE_GXIO_USB_HOST) += usb_host.o iorpc_usb_host.o
diff --git a/arch/tile/gxio/iorpc_uart.c b/arch/tile/gxio/iorpc_uart.c
new file mode 100644
index 000000000000..b9a6d6193d73
--- /dev/null
+++ b/arch/tile/gxio/iorpc_uart.c
@@ -0,0 +1,77 @@
1/*
2 * Copyright 2013 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* This file is machine-generated; DO NOT EDIT! */
16#include "gxio/iorpc_uart.h"
17
18struct cfg_interrupt_param {
19 union iorpc_interrupt interrupt;
20};
21
22int gxio_uart_cfg_interrupt(gxio_uart_context_t *context, int inter_x,
23 int inter_y, int inter_ipi, int inter_event)
24{
25 struct cfg_interrupt_param temp;
26 struct cfg_interrupt_param *params = &temp;
27
28 params->interrupt.kernel.x = inter_x;
29 params->interrupt.kernel.y = inter_y;
30 params->interrupt.kernel.ipi = inter_ipi;
31 params->interrupt.kernel.event = inter_event;
32
33 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
34 sizeof(*params), GXIO_UART_OP_CFG_INTERRUPT);
35}
36
37EXPORT_SYMBOL(gxio_uart_cfg_interrupt);
38
39struct get_mmio_base_param {
40 HV_PTE base;
41};
42
43int gxio_uart_get_mmio_base(gxio_uart_context_t *context, HV_PTE *base)
44{
45 int __result;
46 struct get_mmio_base_param temp;
47 struct get_mmio_base_param *params = &temp;
48
49 __result =
50 hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
51 GXIO_UART_OP_GET_MMIO_BASE);
52 *base = params->base;
53
54 return __result;
55}
56
57EXPORT_SYMBOL(gxio_uart_get_mmio_base);
58
59struct check_mmio_offset_param {
60 unsigned long offset;
61 unsigned long size;
62};
63
64int gxio_uart_check_mmio_offset(gxio_uart_context_t *context,
65 unsigned long offset, unsigned long size)
66{
67 struct check_mmio_offset_param temp;
68 struct check_mmio_offset_param *params = &temp;
69
70 params->offset = offset;
71 params->size = size;
72
73 return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
74 sizeof(*params), GXIO_UART_OP_CHECK_MMIO_OFFSET);
75}
76
77EXPORT_SYMBOL(gxio_uart_check_mmio_offset);
diff --git a/arch/tile/gxio/uart.c b/arch/tile/gxio/uart.c
new file mode 100644
index 000000000000..ba585175ef88
--- /dev/null
+++ b/arch/tile/gxio/uart.c
@@ -0,0 +1,87 @@
1/*
2 * Copyright 2013 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/*
16 * Implementation of UART gxio calls.
17 */
18
19#include <linux/io.h>
20#include <linux/errno.h>
21#include <linux/module.h>
22
23#include <gxio/uart.h>
24#include <gxio/iorpc_globals.h>
25#include <gxio/iorpc_uart.h>
26#include <gxio/kiorpc.h>
27
28int gxio_uart_init(gxio_uart_context_t *context, int uart_index)
29{
30 char file[32];
31 int fd;
32
33 snprintf(file, sizeof(file), "uart/%d/iorpc", uart_index);
34 fd = hv_dev_open((HV_VirtAddr) file, 0);
35 if (fd < 0) {
36 if (fd >= GXIO_ERR_MIN && fd <= GXIO_ERR_MAX)
37 return fd;
38 else
39 return -ENODEV;
40 }
41
42 context->fd = fd;
43
44 /* Map in the MMIO space. */
45 context->mmio_base = (void __force *)
46 iorpc_ioremap(fd, HV_UART_MMIO_OFFSET, HV_UART_MMIO_SIZE);
47
48 if (context->mmio_base == NULL) {
49 hv_dev_close(context->fd);
50 context->fd = -1;
51 return -ENODEV;
52 }
53
54 return 0;
55}
56
57EXPORT_SYMBOL_GPL(gxio_uart_init);
58
59int gxio_uart_destroy(gxio_uart_context_t *context)
60{
61 iounmap((void __force __iomem *)(context->mmio_base));
62 hv_dev_close(context->fd);
63
64 context->mmio_base = NULL;
65 context->fd = -1;
66
67 return 0;
68}
69
70EXPORT_SYMBOL_GPL(gxio_uart_destroy);
71
72/* UART register write wrapper. */
73void gxio_uart_write(gxio_uart_context_t *context, uint64_t offset,
74 uint64_t word)
75{
76 __gxio_mmio_write(context->mmio_base + offset, word);
77}
78
79EXPORT_SYMBOL_GPL(gxio_uart_write);
80
81/* UART register read wrapper. */
82uint64_t gxio_uart_read(gxio_uart_context_t *context, uint64_t offset)
83{
84 return __gxio_mmio_read(context->mmio_base + offset);
85}
86
87EXPORT_SYMBOL_GPL(gxio_uart_read);
diff --git a/arch/tile/include/arch/uart.h b/arch/tile/include/arch/uart.h
new file mode 100644
index 000000000000..07966970adad
--- /dev/null
+++ b/arch/tile/include/arch/uart.h
@@ -0,0 +1,300 @@
1/*
2 * Copyright 2013 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* Machine-generated file; do not edit. */
16
17#ifndef __ARCH_UART_H__
18#define __ARCH_UART_H__
19
20#include <arch/abi.h>
21#include <arch/uart_def.h>
22
23#ifndef __ASSEMBLER__
24
25/* Divisor. */
26
27__extension__
28typedef union
29{
30 struct
31 {
32#ifndef __BIG_ENDIAN__
33 /*
34 * Baud Rate Divisor. Desired_baud_rate = REF_CLK frequency / (baud *
35 * 16).
36 * Note: REF_CLK is always 125 MHz, the default
37 * divisor = 68, baud rate = 125M/(68*16) = 115200 baud.
38 */
39 uint_reg_t divisor : 12;
40 /* Reserved. */
41 uint_reg_t __reserved : 52;
42#else /* __BIG_ENDIAN__ */
43 uint_reg_t __reserved : 52;
44 uint_reg_t divisor : 12;
45#endif
46 };
47
48 uint_reg_t word;
49} UART_DIVISOR_t;
50
51/* FIFO Count. */
52
53__extension__
54typedef union
55{
56 struct
57 {
58#ifndef __BIG_ENDIAN__
59 /*
60 * n: n active entries in the receive FIFO (max is 2**8). Each entry has
61 * 8 bits.
62 * 0: no active entry in the receive FIFO (that is empty).
63 */
64 uint_reg_t rfifo_count : 9;
65 /* Reserved. */
66 uint_reg_t __reserved_0 : 7;
67 /*
68 * n: n active entries in the transmit FIFO (max is 2**8). Each entry has
69 * 8 bits.
70 * 0: no active entry in the transmit FIFO (that is empty).
71 */
72 uint_reg_t tfifo_count : 9;
73 /* Reserved. */
74 uint_reg_t __reserved_1 : 7;
75 /*
76 * n: n active entries in the write FIFO (max is 2**2). Each entry has 8
77 * bits.
78 * 0: no active entry in the write FIFO (that is empty).
79 */
80 uint_reg_t wfifo_count : 3;
81 /* Reserved. */
82 uint_reg_t __reserved_2 : 29;
83#else /* __BIG_ENDIAN__ */
84 uint_reg_t __reserved_2 : 29;
85 uint_reg_t wfifo_count : 3;
86 uint_reg_t __reserved_1 : 7;
87 uint_reg_t tfifo_count : 9;
88 uint_reg_t __reserved_0 : 7;
89 uint_reg_t rfifo_count : 9;
90#endif
91 };
92
93 uint_reg_t word;
94} UART_FIFO_COUNT_t;
95
96/* FLAG. */
97
98__extension__
99typedef union
100{
101 struct
102 {
103#ifndef __BIG_ENDIAN__
104 /* Reserved. */
105 uint_reg_t __reserved_0 : 1;
106 /* 1: receive FIFO is empty */
107 uint_reg_t rfifo_empty : 1;
108 /* 1: write FIFO is empty. */
109 uint_reg_t wfifo_empty : 1;
110 /* 1: transmit FIFO is empty. */
111 uint_reg_t tfifo_empty : 1;
112 /* 1: receive FIFO is full. */
113 uint_reg_t rfifo_full : 1;
114 /* 1: write FIFO is full. */
115 uint_reg_t wfifo_full : 1;
116 /* 1: transmit FIFO is full. */
117 uint_reg_t tfifo_full : 1;
118 /* Reserved. */
119 uint_reg_t __reserved_1 : 57;
120#else /* __BIG_ENDIAN__ */
121 uint_reg_t __reserved_1 : 57;
122 uint_reg_t tfifo_full : 1;
123 uint_reg_t wfifo_full : 1;
124 uint_reg_t rfifo_full : 1;
125 uint_reg_t tfifo_empty : 1;
126 uint_reg_t wfifo_empty : 1;
127 uint_reg_t rfifo_empty : 1;
128 uint_reg_t __reserved_0 : 1;
129#endif
130 };
131
132 uint_reg_t word;
133} UART_FLAG_t;
134
135/*
136 * Interrupt Vector Mask.
137 * Each bit in this register corresponds to a specific interrupt. When set,
138 * the associated interrupt will not be dispatched.
139 */
140
141__extension__
142typedef union
143{
144 struct
145 {
146#ifndef __BIG_ENDIAN__
147 /* Read data FIFO read and no data available */
148 uint_reg_t rdat_err : 1;
149 /* Write FIFO was written but it was full */
150 uint_reg_t wdat_err : 1;
151 /* Stop bit not found when current data was received */
152 uint_reg_t frame_err : 1;
153 /* Parity error was detected when current data was received */
154 uint_reg_t parity_err : 1;
155 /* Data was received but the receive FIFO was full */
156 uint_reg_t rfifo_overflow : 1;
157 /*
158 * An almost full event is reached when data is to be written to the
159 * receive FIFO, and the receive FIFO has more than or equal to
160 * BUFFER_THRESHOLD.RFIFO_AFULL bytes.
161 */
162 uint_reg_t rfifo_afull : 1;
163 /* Reserved. */
164 uint_reg_t __reserved_0 : 1;
165 /* An entry in the transmit FIFO was popped */
166 uint_reg_t tfifo_re : 1;
167 /* An entry has been pushed into the receive FIFO */
168 uint_reg_t rfifo_we : 1;
169 /* An entry of the write FIFO has been popped */
170 uint_reg_t wfifo_re : 1;
171 /* Rshim read receive FIFO in protocol mode */
172 uint_reg_t rfifo_err : 1;
173 /*
174 * An almost empty event is reached when data is to be read from the
175 * transmit FIFO, and the transmit FIFO has less than or equal to
176 * BUFFER_THRESHOLD.TFIFO_AEMPTY bytes.
177 */
178 uint_reg_t tfifo_aempty : 1;
179 /* Reserved. */
180 uint_reg_t __reserved_1 : 52;
181#else /* __BIG_ENDIAN__ */
182 uint_reg_t __reserved_1 : 52;
183 uint_reg_t tfifo_aempty : 1;
184 uint_reg_t rfifo_err : 1;
185 uint_reg_t wfifo_re : 1;
186 uint_reg_t rfifo_we : 1;
187 uint_reg_t tfifo_re : 1;
188 uint_reg_t __reserved_0 : 1;
189 uint_reg_t rfifo_afull : 1;
190 uint_reg_t rfifo_overflow : 1;
191 uint_reg_t parity_err : 1;
192 uint_reg_t frame_err : 1;
193 uint_reg_t wdat_err : 1;
194 uint_reg_t rdat_err : 1;
195#endif
196 };
197
198 uint_reg_t word;
199} UART_INTERRUPT_MASK_t;
200
201/*
202 * Interrupt vector, write-one-to-clear.
203 * Each bit in this register corresponds to a specific interrupt. Hardware
204 * sets the bit when the associated condition has occurred. Writing a 1
205 * clears the status bit.
206 */
207
208__extension__
209typedef union
210{
211 struct
212 {
213#ifndef __BIG_ENDIAN__
214 /* Read data FIFO read and no data available */
215 uint_reg_t rdat_err : 1;
216 /* Write FIFO was written but it was full */
217 uint_reg_t wdat_err : 1;
218 /* Stop bit not found when current data was received */
219 uint_reg_t frame_err : 1;
220 /* Parity error was detected when current data was received */
221 uint_reg_t parity_err : 1;
222 /* Data was received but the receive FIFO was full */
223 uint_reg_t rfifo_overflow : 1;
224 /*
225 * Data was received and the receive FIFO is now almost full (more than
226 * BUFFER_THRESHOLD.RFIFO_AFULL bytes in it)
227 */
228 uint_reg_t rfifo_afull : 1;
229 /* Reserved. */
230 uint_reg_t __reserved_0 : 1;
231 /* An entry in the transmit FIFO was popped */
232 uint_reg_t tfifo_re : 1;
233 /* An entry has been pushed into the receive FIFO */
234 uint_reg_t rfifo_we : 1;
235 /* An entry of the write FIFO has been popped */
236 uint_reg_t wfifo_re : 1;
237 /* Rshim read receive FIFO in protocol mode */
238 uint_reg_t rfifo_err : 1;
239 /*
240 * Data was read from the transmit FIFO and now it is almost empty (less
241 * than or equal to BUFFER_THRESHOLD.TFIFO_AEMPTY bytes in it).
242 */
243 uint_reg_t tfifo_aempty : 1;
244 /* Reserved. */
245 uint_reg_t __reserved_1 : 52;
246#else /* __BIG_ENDIAN__ */
247 uint_reg_t __reserved_1 : 52;
248 uint_reg_t tfifo_aempty : 1;
249 uint_reg_t rfifo_err : 1;
250 uint_reg_t wfifo_re : 1;
251 uint_reg_t rfifo_we : 1;
252 uint_reg_t tfifo_re : 1;
253 uint_reg_t __reserved_0 : 1;
254 uint_reg_t rfifo_afull : 1;
255 uint_reg_t rfifo_overflow : 1;
256 uint_reg_t parity_err : 1;
257 uint_reg_t frame_err : 1;
258 uint_reg_t wdat_err : 1;
259 uint_reg_t rdat_err : 1;
260#endif
261 };
262
263 uint_reg_t word;
264} UART_INTERRUPT_STATUS_t;
265
266/* Type. */
267
268__extension__
269typedef union
270{
271 struct
272 {
273#ifndef __BIG_ENDIAN__
274 /* Number of stop bits, rx and tx */
275 uint_reg_t sbits : 1;
276 /* Reserved. */
277 uint_reg_t __reserved_0 : 1;
278 /* Data word size, rx and tx */
279 uint_reg_t dbits : 1;
280 /* Reserved. */
281 uint_reg_t __reserved_1 : 1;
282 /* Parity selection, rx and tx */
283 uint_reg_t ptype : 3;
284 /* Reserved. */
285 uint_reg_t __reserved_2 : 57;
286#else /* __BIG_ENDIAN__ */
287 uint_reg_t __reserved_2 : 57;
288 uint_reg_t ptype : 3;
289 uint_reg_t __reserved_1 : 1;
290 uint_reg_t dbits : 1;
291 uint_reg_t __reserved_0 : 1;
292 uint_reg_t sbits : 1;
293#endif
294 };
295
296 uint_reg_t word;
297} UART_TYPE_t;
298#endif /* !defined(__ASSEMBLER__) */
299
300#endif /* !defined(__ARCH_UART_H__) */
diff --git a/arch/tile/include/arch/uart_def.h b/arch/tile/include/arch/uart_def.h
new file mode 100644
index 000000000000..42bcaf535379
--- /dev/null
+++ b/arch/tile/include/arch/uart_def.h
@@ -0,0 +1,120 @@
1/*
2 * Copyright 2013 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* Machine-generated file; do not edit. */
16
17#ifndef __ARCH_UART_DEF_H__
18#define __ARCH_UART_DEF_H__
19#define UART_DIVISOR 0x0158
20#define UART_FIFO_COUNT 0x0110
21#define UART_FLAG 0x0108
22#define UART_INTERRUPT_MASK 0x0208
23#define UART_INTERRUPT_MASK__RDAT_ERR_SHIFT 0
24#define UART_INTERRUPT_MASK__RDAT_ERR_WIDTH 1
25#define UART_INTERRUPT_MASK__RDAT_ERR_RESET_VAL 1
26#define UART_INTERRUPT_MASK__RDAT_ERR_RMASK 0x1
27#define UART_INTERRUPT_MASK__RDAT_ERR_MASK 0x1
28#define UART_INTERRUPT_MASK__RDAT_ERR_FIELD 0,0
29#define UART_INTERRUPT_MASK__WDAT_ERR_SHIFT 1
30#define UART_INTERRUPT_MASK__WDAT_ERR_WIDTH 1
31#define UART_INTERRUPT_MASK__WDAT_ERR_RESET_VAL 1
32#define UART_INTERRUPT_MASK__WDAT_ERR_RMASK 0x1
33#define UART_INTERRUPT_MASK__WDAT_ERR_MASK 0x2
34#define UART_INTERRUPT_MASK__WDAT_ERR_FIELD 1,1
35#define UART_INTERRUPT_MASK__FRAME_ERR_SHIFT 2
36#define UART_INTERRUPT_MASK__FRAME_ERR_WIDTH 1
37#define UART_INTERRUPT_MASK__FRAME_ERR_RESET_VAL 1
38#define UART_INTERRUPT_MASK__FRAME_ERR_RMASK 0x1
39#define UART_INTERRUPT_MASK__FRAME_ERR_MASK 0x4
40#define UART_INTERRUPT_MASK__FRAME_ERR_FIELD 2,2
41#define UART_INTERRUPT_MASK__PARITY_ERR_SHIFT 3
42#define UART_INTERRUPT_MASK__PARITY_ERR_WIDTH 1
43#define UART_INTERRUPT_MASK__PARITY_ERR_RESET_VAL 1
44#define UART_INTERRUPT_MASK__PARITY_ERR_RMASK 0x1
45#define UART_INTERRUPT_MASK__PARITY_ERR_MASK 0x8
46#define UART_INTERRUPT_MASK__PARITY_ERR_FIELD 3,3
47#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_SHIFT 4
48#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_WIDTH 1
49#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_RESET_VAL 1
50#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_RMASK 0x1
51#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_MASK 0x10
52#define UART_INTERRUPT_MASK__RFIFO_OVERFLOW_FIELD 4,4
53#define UART_INTERRUPT_MASK__RFIFO_AFULL_SHIFT 5
54#define UART_INTERRUPT_MASK__RFIFO_AFULL_WIDTH 1
55#define UART_INTERRUPT_MASK__RFIFO_AFULL_RESET_VAL 1
56#define UART_INTERRUPT_MASK__RFIFO_AFULL_RMASK 0x1
57#define UART_INTERRUPT_MASK__RFIFO_AFULL_MASK 0x20
58#define UART_INTERRUPT_MASK__RFIFO_AFULL_FIELD 5,5
59#define UART_INTERRUPT_MASK__TFIFO_RE_SHIFT 7
60#define UART_INTERRUPT_MASK__TFIFO_RE_WIDTH 1
61#define UART_INTERRUPT_MASK__TFIFO_RE_RESET_VAL 1
62#define UART_INTERRUPT_MASK__TFIFO_RE_RMASK 0x1
63#define UART_INTERRUPT_MASK__TFIFO_RE_MASK 0x80
64#define UART_INTERRUPT_MASK__TFIFO_RE_FIELD 7,7
65#define UART_INTERRUPT_MASK__RFIFO_WE_SHIFT 8
66#define UART_INTERRUPT_MASK__RFIFO_WE_WIDTH 1
67#define UART_INTERRUPT_MASK__RFIFO_WE_RESET_VAL 1
68#define UART_INTERRUPT_MASK__RFIFO_WE_RMASK 0x1
69#define UART_INTERRUPT_MASK__RFIFO_WE_MASK 0x100
70#define UART_INTERRUPT_MASK__RFIFO_WE_FIELD 8,8
71#define UART_INTERRUPT_MASK__WFIFO_RE_SHIFT 9
72#define UART_INTERRUPT_MASK__WFIFO_RE_WIDTH 1
73#define UART_INTERRUPT_MASK__WFIFO_RE_RESET_VAL 1
74#define UART_INTERRUPT_MASK__WFIFO_RE_RMASK 0x1
75#define UART_INTERRUPT_MASK__WFIFO_RE_MASK 0x200
76#define UART_INTERRUPT_MASK__WFIFO_RE_FIELD 9,9
77#define UART_INTERRUPT_MASK__RFIFO_ERR_SHIFT 10
78#define UART_INTERRUPT_MASK__RFIFO_ERR_WIDTH 1
79#define UART_INTERRUPT_MASK__RFIFO_ERR_RESET_VAL 1
80#define UART_INTERRUPT_MASK__RFIFO_ERR_RMASK 0x1
81#define UART_INTERRUPT_MASK__RFIFO_ERR_MASK 0x400
82#define UART_INTERRUPT_MASK__RFIFO_ERR_FIELD 10,10
83#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_SHIFT 11
84#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_WIDTH 1
85#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_RESET_VAL 1
86#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_RMASK 0x1
87#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_MASK 0x800
88#define UART_INTERRUPT_MASK__TFIFO_AEMPTY_FIELD 11,11
89#define UART_INTERRUPT_STATUS 0x0200
90#define UART_RECEIVE_DATA 0x0148
91#define UART_TRANSMIT_DATA 0x0140
92#define UART_TYPE 0x0160
93#define UART_TYPE__SBITS_SHIFT 0
94#define UART_TYPE__SBITS_WIDTH 1
95#define UART_TYPE__SBITS_RESET_VAL 1
96#define UART_TYPE__SBITS_RMASK 0x1
97#define UART_TYPE__SBITS_MASK 0x1
98#define UART_TYPE__SBITS_FIELD 0,0
99#define UART_TYPE__SBITS_VAL_ONE_SBITS 0x0
100#define UART_TYPE__SBITS_VAL_TWO_SBITS 0x1
101#define UART_TYPE__DBITS_SHIFT 2
102#define UART_TYPE__DBITS_WIDTH 1
103#define UART_TYPE__DBITS_RESET_VAL 0
104#define UART_TYPE__DBITS_RMASK 0x1
105#define UART_TYPE__DBITS_MASK 0x4
106#define UART_TYPE__DBITS_FIELD 2,2
107#define UART_TYPE__DBITS_VAL_EIGHT_DBITS 0x0
108#define UART_TYPE__DBITS_VAL_SEVEN_DBITS 0x1
109#define UART_TYPE__PTYPE_SHIFT 4
110#define UART_TYPE__PTYPE_WIDTH 3
111#define UART_TYPE__PTYPE_RESET_VAL 3
112#define UART_TYPE__PTYPE_RMASK 0x7
113#define UART_TYPE__PTYPE_MASK 0x70
114#define UART_TYPE__PTYPE_FIELD 4,6
115#define UART_TYPE__PTYPE_VAL_NONE 0x0
116#define UART_TYPE__PTYPE_VAL_MARK 0x1
117#define UART_TYPE__PTYPE_VAL_SPACE 0x2
118#define UART_TYPE__PTYPE_VAL_EVEN 0x3
119#define UART_TYPE__PTYPE_VAL_ODD 0x4
120#endif /* !defined(__ARCH_UART_DEF_H__) */
diff --git a/arch/tile/include/gxio/iorpc_uart.h b/arch/tile/include/gxio/iorpc_uart.h
new file mode 100644
index 000000000000..55429d48ea56
--- /dev/null
+++ b/arch/tile/include/gxio/iorpc_uart.h
@@ -0,0 +1,40 @@
1/*
2 * Copyright 2013 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/* This file is machine-generated; DO NOT EDIT! */
16#ifndef __GXIO_UART_LINUX_RPC_H__
17#define __GXIO_UART_LINUX_RPC_H__
18
19#include <hv/iorpc.h>
20
21#include <hv/drv_uart_intf.h>
22#include <gxio/uart.h>
23#include <gxio/kiorpc.h>
24#include <linux/string.h>
25#include <linux/module.h>
26#include <asm/pgtable.h>
27
28#define GXIO_UART_OP_CFG_INTERRUPT IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1900)
29#define GXIO_UART_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
30#define GXIO_UART_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
31
32int gxio_uart_cfg_interrupt(gxio_uart_context_t *context, int inter_x,
33 int inter_y, int inter_ipi, int inter_event);
34
35int gxio_uart_get_mmio_base(gxio_uart_context_t *context, HV_PTE *base);
36
37int gxio_uart_check_mmio_offset(gxio_uart_context_t *context,
38 unsigned long offset, unsigned long size);
39
40#endif /* !__GXIO_UART_LINUX_RPC_H__ */
diff --git a/arch/tile/include/gxio/uart.h b/arch/tile/include/gxio/uart.h
new file mode 100644
index 000000000000..438ee7e46c7b
--- /dev/null
+++ b/arch/tile/include/gxio/uart.h
@@ -0,0 +1,105 @@
1/*
2 * Copyright 2013 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _GXIO_UART_H_
16#define _GXIO_UART_H_
17
18#include "common.h"
19
20#include <hv/drv_uart_intf.h>
21#include <hv/iorpc.h>
22
23/*
24 *
25 * An API for manipulating UART interface.
26 */
27
28/*
29 *
30 * The Rshim allows access to the processor's UART interface.
31 */
32
33/* A context object used to manage UART resources. */
34typedef struct {
35
36 /* File descriptor for calling up to the hypervisor. */
37 int fd;
38
39 /* The VA at which our MMIO registers are mapped. */
40 char *mmio_base;
41
42} gxio_uart_context_t;
43
44/* Request UART interrupts.
45 *
46 * Request that interrupts be delivered to a tile when the UART's
47 * Receive FIFO is written, or the Write FIFO is read.
48 *
49 * @param context Pointer to a properly initialized gxio_uart_context_t.
50 * @param bind_cpu_x X coordinate of CPU to which interrupt will be delivered.
51 * @param bind_cpu_y Y coordinate of CPU to which interrupt will be delivered.
52 * @param bind_interrupt IPI interrupt number.
53 * @param bind_event Sub-interrupt event bit number; a negative value can
54 * disable the interrupt.
55 * @return Zero if all of the requested UART events were successfully
56 * configured to interrupt.
57 */
58extern int gxio_uart_cfg_interrupt(gxio_uart_context_t *context,
59 int bind_cpu_x,
60 int bind_cpu_y,
61 int bind_interrupt, int bind_event);
62
63/* Initialize a UART context.
64 *
65 * A properly initialized context must be obtained before any of the other
66 * gxio_uart routines may be used.
67 *
68 * @param context Pointer to a gxio_uart_context_t, which will be initialized
69 * by this routine, if it succeeds.
70 * @param uart_index Index of the UART to use.
71 * @return Zero if the context was successfully initialized, else a
72 * GXIO_ERR_xxx error code.
73 */
74extern int gxio_uart_init(gxio_uart_context_t *context, int uart_index);
75
76/* Destroy a UART context.
77 *
78 * Once destroyed, a context may not be used with any gxio_uart routines
79 * other than gxio_uart_init(). After this routine returns, no further
80 * interrupts requested on this context will be delivered. The state and
81 * configuration of the pins which had been attached to this context are
82 * unchanged by this operation.
83 *
84 * @param context Pointer to a gxio_uart_context_t.
85 * @return Zero if the context was successfully destroyed, else a
86 * GXIO_ERR_xxx error code.
87 */
88extern int gxio_uart_destroy(gxio_uart_context_t *context);
89
90/* Write UART register.
91 * @param context Pointer to a gxio_uart_context_t.
92 * @param offset UART register offset.
93 * @param word Data will be wrote to UART reigister.
94 */
95extern void gxio_uart_write(gxio_uart_context_t *context, uint64_t offset,
96 uint64_t word);
97
98/* Read UART register.
99 * @param context Pointer to a gxio_uart_context_t.
100 * @param offset UART register offset.
101 * @return Data read from UART register.
102 */
103extern uint64_t gxio_uart_read(gxio_uart_context_t *context, uint64_t offset);
104
105#endif /* _GXIO_UART_H_ */
diff --git a/arch/tile/include/hv/drv_uart_intf.h b/arch/tile/include/hv/drv_uart_intf.h
new file mode 100644
index 000000000000..f5379e2404fd
--- /dev/null
+++ b/arch/tile/include/hv/drv_uart_intf.h
@@ -0,0 +1,33 @@
1/*
2 * Copyright 2013 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/**
16 * Interface definitions for the UART driver.
17 */
18
19#ifndef _SYS_HV_DRV_UART_INTF_H
20#define _SYS_HV_DRV_UART_INTF_H
21
22#include <arch/uart.h>
23
24/** Number of UART ports supported. */
25#define TILEGX_UART_NR 2
26
27/** The mmap file offset (PA) of the UART MMIO region. */
28#define HV_UART_MMIO_OFFSET 0
29
30/** The maximum size of the UARTs MMIO region (64K Bytes). */
31#define HV_UART_MMIO_SIZE (1UL << 16)
32
33#endif /* _SYS_HV_DRV_UART_INTF_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-29 23:37:01 -0400