diff options
author | David Howells <dhowells@redhat.com> | 2012-10-09 04:47:45 -0400 |
---|---|---|
committer | David Howells <dhowells@redhat.com> | 2012-10-09 04:47:45 -0400 |
commit | 43e858598a1a3d0a9352515f847c04e80942ca4a (patch) | |
tree | 60a43644ce34032f65ff254d224cf37ce9c591c7 /arch/tile/include/uapi | |
parent | 9e2d8656f5e8aa214e66b462680cf86b210b74a8 (diff) |
UAPI: (Scripted) Disintegrate arch/tile/include/arch
Signed-off-by: David Howells <dhowells@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Michael Kerrisk <mtk.manpages@gmail.com>
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: Dave Jones <davej@redhat.com>
Diffstat (limited to 'arch/tile/include/uapi')
-rw-r--r-- | arch/tile/include/uapi/arch/Kbuild | 17 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/abi.h | 141 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/chip.h | 23 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/chip_tile64.h | 258 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/chip_tilegx.h | 258 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/chip_tilepro.h | 258 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/icache.h | 93 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/interrupts.h | 19 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/interrupts_32.h | 307 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/interrupts_64.h | 276 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/opcode.h | 21 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/opcode_tilegx.h | 1405 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/opcode_tilepro.h | 1471 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/sim.h | 643 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/sim_def.h | 505 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/spr_def.h | 26 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/spr_def_32.h | 257 | ||||
-rw-r--r-- | arch/tile/include/uapi/arch/spr_def_64.h | 216 |
18 files changed, 6194 insertions, 0 deletions
diff --git a/arch/tile/include/uapi/arch/Kbuild b/arch/tile/include/uapi/arch/Kbuild index aafaa5aa54d4..4ebc34f4768d 100644 --- a/arch/tile/include/uapi/arch/Kbuild +++ b/arch/tile/include/uapi/arch/Kbuild | |||
@@ -1 +1,18 @@ | |||
1 | # UAPI Header export list | 1 | # UAPI Header export list |
2 | header-y += abi.h | ||
3 | header-y += chip.h | ||
4 | header-y += chip_tile64.h | ||
5 | header-y += chip_tilegx.h | ||
6 | header-y += chip_tilepro.h | ||
7 | header-y += icache.h | ||
8 | header-y += interrupts.h | ||
9 | header-y += interrupts_32.h | ||
10 | header-y += interrupts_64.h | ||
11 | header-y += opcode.h | ||
12 | header-y += opcode_tilegx.h | ||
13 | header-y += opcode_tilepro.h | ||
14 | header-y += sim.h | ||
15 | header-y += sim_def.h | ||
16 | header-y += spr_def.h | ||
17 | header-y += spr_def_32.h | ||
18 | header-y += spr_def_64.h | ||
diff --git a/arch/tile/include/uapi/arch/abi.h b/arch/tile/include/uapi/arch/abi.h new file mode 100644 index 000000000000..c55a3d432644 --- /dev/null +++ b/arch/tile/include/uapi/arch/abi.h | |||
@@ -0,0 +1,141 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | /** | ||
16 | * @file | ||
17 | * | ||
18 | * ABI-related register definitions. | ||
19 | */ | ||
20 | |||
21 | #ifndef __ARCH_ABI_H__ | ||
22 | |||
23 | #if !defined __need_int_reg_t && !defined __DOXYGEN__ | ||
24 | # define __ARCH_ABI_H__ | ||
25 | # include <arch/chip.h> | ||
26 | #endif | ||
27 | |||
28 | /* Provide the basic machine types. */ | ||
29 | #ifndef __INT_REG_BITS | ||
30 | |||
31 | /** Number of bits in a register. */ | ||
32 | #if defined __tilegx__ | ||
33 | # define __INT_REG_BITS 64 | ||
34 | #elif defined __tilepro__ | ||
35 | # define __INT_REG_BITS 32 | ||
36 | #elif !defined __need_int_reg_t | ||
37 | # include <arch/chip.h> | ||
38 | # define __INT_REG_BITS CHIP_WORD_SIZE() | ||
39 | #else | ||
40 | # error Unrecognized architecture with __need_int_reg_t | ||
41 | #endif | ||
42 | |||
43 | #if __INT_REG_BITS == 64 | ||
44 | |||
45 | #ifndef __ASSEMBLER__ | ||
46 | /** Unsigned type that can hold a register. */ | ||
47 | typedef unsigned long long __uint_reg_t; | ||
48 | |||
49 | /** Signed type that can hold a register. */ | ||
50 | typedef long long __int_reg_t; | ||
51 | #endif | ||
52 | |||
53 | /** String prefix to use for printf(). */ | ||
54 | #define __INT_REG_FMT "ll" | ||
55 | |||
56 | #else | ||
57 | |||
58 | #ifndef __ASSEMBLER__ | ||
59 | /** Unsigned type that can hold a register. */ | ||
60 | typedef unsigned long __uint_reg_t; | ||
61 | |||
62 | /** Signed type that can hold a register. */ | ||
63 | typedef long __int_reg_t; | ||
64 | #endif | ||
65 | |||
66 | /** String prefix to use for printf(). */ | ||
67 | #define __INT_REG_FMT "l" | ||
68 | |||
69 | #endif | ||
70 | #endif /* __INT_REG_BITS */ | ||
71 | |||
72 | |||
73 | #ifndef __need_int_reg_t | ||
74 | |||
75 | |||
76 | #ifndef __ASSEMBLER__ | ||
77 | /** Unsigned type that can hold a register. */ | ||
78 | typedef __uint_reg_t uint_reg_t; | ||
79 | |||
80 | /** Signed type that can hold a register. */ | ||
81 | typedef __int_reg_t int_reg_t; | ||
82 | #endif | ||
83 | |||
84 | /** String prefix to use for printf(). */ | ||
85 | #define INT_REG_FMT __INT_REG_FMT | ||
86 | |||
87 | /** Number of bits in a register. */ | ||
88 | #define INT_REG_BITS __INT_REG_BITS | ||
89 | |||
90 | |||
91 | /* Registers 0 - 55 are "normal", but some perform special roles. */ | ||
92 | |||
93 | #define TREG_FP 52 /**< Frame pointer. */ | ||
94 | #define TREG_TP 53 /**< Thread pointer. */ | ||
95 | #define TREG_SP 54 /**< Stack pointer. */ | ||
96 | #define TREG_LR 55 /**< Link to calling function PC. */ | ||
97 | |||
98 | /** Index of last normal general-purpose register. */ | ||
99 | #define TREG_LAST_GPR 55 | ||
100 | |||
101 | /* Registers 56 - 62 are "special" network registers. */ | ||
102 | |||
103 | #define TREG_SN 56 /**< Static network access. */ | ||
104 | #define TREG_IDN0 57 /**< IDN demux 0 access. */ | ||
105 | #define TREG_IDN1 58 /**< IDN demux 1 access. */ | ||
106 | #define TREG_UDN0 59 /**< UDN demux 0 access. */ | ||
107 | #define TREG_UDN1 60 /**< UDN demux 1 access. */ | ||
108 | #define TREG_UDN2 61 /**< UDN demux 2 access. */ | ||
109 | #define TREG_UDN3 62 /**< UDN demux 3 access. */ | ||
110 | |||
111 | /* Register 63 is the "special" zero register. */ | ||
112 | |||
113 | #define TREG_ZERO 63 /**< "Zero" register; always reads as "0". */ | ||
114 | |||
115 | |||
116 | /** By convention, this register is used to hold the syscall number. */ | ||
117 | #define TREG_SYSCALL_NR 10 | ||
118 | |||
119 | /** Name of register that holds the syscall number, for use in assembly. */ | ||
120 | #define TREG_SYSCALL_NR_NAME r10 | ||
121 | |||
122 | |||
123 | /** | ||
124 | * The ABI requires callers to allocate a caller state save area of | ||
125 | * this many bytes at the bottom of each stack frame. | ||
126 | */ | ||
127 | #define C_ABI_SAVE_AREA_SIZE (2 * (INT_REG_BITS / 8)) | ||
128 | |||
129 | /** | ||
130 | * The operand to an 'info' opcode directing the backtracer to not | ||
131 | * try to find the calling frame. | ||
132 | */ | ||
133 | #define INFO_OP_CANNOT_BACKTRACE 2 | ||
134 | |||
135 | |||
136 | #endif /* !__need_int_reg_t */ | ||
137 | |||
138 | /* Make sure we later can get all the definitions and declarations. */ | ||
139 | #undef __need_int_reg_t | ||
140 | |||
141 | #endif /* !__ARCH_ABI_H__ */ | ||
diff --git a/arch/tile/include/uapi/arch/chip.h b/arch/tile/include/uapi/arch/chip.h new file mode 100644 index 000000000000..926d3db0e91e --- /dev/null +++ b/arch/tile/include/uapi/arch/chip.h | |||
@@ -0,0 +1,23 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | #if __tile_chip__ == 0 | ||
16 | #include <arch/chip_tile64.h> | ||
17 | #elif __tile_chip__ == 1 | ||
18 | #include <arch/chip_tilepro.h> | ||
19 | #elif defined(__tilegx__) | ||
20 | #include <arch/chip_tilegx.h> | ||
21 | #else | ||
22 | #error Unexpected Tilera chip type | ||
23 | #endif | ||
diff --git a/arch/tile/include/uapi/arch/chip_tile64.h b/arch/tile/include/uapi/arch/chip_tile64.h new file mode 100644 index 000000000000..261aaba092d4 --- /dev/null +++ b/arch/tile/include/uapi/arch/chip_tile64.h | |||
@@ -0,0 +1,258 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | /* | ||
16 | * @file | ||
17 | * Global header file. | ||
18 | * This header file specifies defines for TILE64. | ||
19 | */ | ||
20 | |||
21 | #ifndef __ARCH_CHIP_H__ | ||
22 | #define __ARCH_CHIP_H__ | ||
23 | |||
24 | /** Specify chip version. | ||
25 | * When possible, prefer the CHIP_xxx symbols below for future-proofing. | ||
26 | * This is intended for cross-compiling; native compilation should | ||
27 | * use the predefined __tile_chip__ symbol. | ||
28 | */ | ||
29 | #define TILE_CHIP 0 | ||
30 | |||
31 | /** Specify chip revision. | ||
32 | * This provides for the case of a respin of a particular chip type; | ||
33 | * the normal value for this symbol is "0". | ||
34 | * This is intended for cross-compiling; native compilation should | ||
35 | * use the predefined __tile_chip_rev__ symbol. | ||
36 | */ | ||
37 | #define TILE_CHIP_REV 0 | ||
38 | |||
39 | /** The name of this architecture. */ | ||
40 | #define CHIP_ARCH_NAME "tile64" | ||
41 | |||
42 | /** The ELF e_machine type for binaries for this chip. */ | ||
43 | #define CHIP_ELF_TYPE() EM_TILE64 | ||
44 | |||
45 | /** The alternate ELF e_machine type for binaries for this chip. */ | ||
46 | #define CHIP_COMPAT_ELF_TYPE() 0x2506 | ||
47 | |||
48 | /** What is the native word size of the machine? */ | ||
49 | #define CHIP_WORD_SIZE() 32 | ||
50 | |||
51 | /** How many bits of a virtual address are used. Extra bits must be | ||
52 | * the sign extension of the low bits. | ||
53 | */ | ||
54 | #define CHIP_VA_WIDTH() 32 | ||
55 | |||
56 | /** How many bits are in a physical address? */ | ||
57 | #define CHIP_PA_WIDTH() 36 | ||
58 | |||
59 | /** Size of the L2 cache, in bytes. */ | ||
60 | #define CHIP_L2_CACHE_SIZE() 65536 | ||
61 | |||
62 | /** Log size of an L2 cache line in bytes. */ | ||
63 | #define CHIP_L2_LOG_LINE_SIZE() 6 | ||
64 | |||
65 | /** Size of an L2 cache line, in bytes. */ | ||
66 | #define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE()) | ||
67 | |||
68 | /** Associativity of the L2 cache. */ | ||
69 | #define CHIP_L2_ASSOC() 2 | ||
70 | |||
71 | /** Size of the L1 data cache, in bytes. */ | ||
72 | #define CHIP_L1D_CACHE_SIZE() 8192 | ||
73 | |||
74 | /** Log size of an L1 data cache line in bytes. */ | ||
75 | #define CHIP_L1D_LOG_LINE_SIZE() 4 | ||
76 | |||
77 | /** Size of an L1 data cache line, in bytes. */ | ||
78 | #define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE()) | ||
79 | |||
80 | /** Associativity of the L1 data cache. */ | ||
81 | #define CHIP_L1D_ASSOC() 2 | ||
82 | |||
83 | /** Size of the L1 instruction cache, in bytes. */ | ||
84 | #define CHIP_L1I_CACHE_SIZE() 8192 | ||
85 | |||
86 | /** Log size of an L1 instruction cache line in bytes. */ | ||
87 | #define CHIP_L1I_LOG_LINE_SIZE() 6 | ||
88 | |||
89 | /** Size of an L1 instruction cache line, in bytes. */ | ||
90 | #define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE()) | ||
91 | |||
92 | /** Associativity of the L1 instruction cache. */ | ||
93 | #define CHIP_L1I_ASSOC() 1 | ||
94 | |||
95 | /** Stride with which flush instructions must be issued. */ | ||
96 | #define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE() | ||
97 | |||
98 | /** Stride with which inv instructions must be issued. */ | ||
99 | #define CHIP_INV_STRIDE() CHIP_L1D_LINE_SIZE() | ||
100 | |||
101 | /** Stride with which finv instructions must be issued. */ | ||
102 | #define CHIP_FINV_STRIDE() CHIP_L1D_LINE_SIZE() | ||
103 | |||
104 | /** Can the local cache coherently cache data that is homed elsewhere? */ | ||
105 | #define CHIP_HAS_COHERENT_LOCAL_CACHE() 0 | ||
106 | |||
107 | /** How many simultaneous outstanding victims can the L2 cache have? */ | ||
108 | #define CHIP_MAX_OUTSTANDING_VICTIMS() 2 | ||
109 | |||
110 | /** Does the TLB support the NC and NOALLOC bits? */ | ||
111 | #define CHIP_HAS_NC_AND_NOALLOC_BITS() 0 | ||
112 | |||
113 | /** Does the chip support hash-for-home caching? */ | ||
114 | #define CHIP_HAS_CBOX_HOME_MAP() 0 | ||
115 | |||
116 | /** Number of entries in the chip's home map tables. */ | ||
117 | /* #define CHIP_CBOX_HOME_MAP_SIZE() -- does not apply to chip 0 */ | ||
118 | |||
119 | /** Do uncacheable requests miss in the cache regardless of whether | ||
120 | * there is matching data? */ | ||
121 | #define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 0 | ||
122 | |||
123 | /** Does the mf instruction wait for victims? */ | ||
124 | #define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 1 | ||
125 | |||
126 | /** Does the chip have an "inv" instruction that doesn't also flush? */ | ||
127 | #define CHIP_HAS_INV() 0 | ||
128 | |||
129 | /** Does the chip have a "wh64" instruction? */ | ||
130 | #define CHIP_HAS_WH64() 0 | ||
131 | |||
132 | /** Does this chip have a 'dword_align' instruction? */ | ||
133 | #define CHIP_HAS_DWORD_ALIGN() 0 | ||
134 | |||
135 | /** Number of performance counters. */ | ||
136 | #define CHIP_PERFORMANCE_COUNTERS() 2 | ||
137 | |||
138 | /** Does this chip have auxiliary performance counters? */ | ||
139 | #define CHIP_HAS_AUX_PERF_COUNTERS() 0 | ||
140 | |||
141 | /** Is the CBOX_MSR1 SPR supported? */ | ||
142 | #define CHIP_HAS_CBOX_MSR1() 0 | ||
143 | |||
144 | /** Is the TILE_RTF_HWM SPR supported? */ | ||
145 | #define CHIP_HAS_TILE_RTF_HWM() 0 | ||
146 | |||
147 | /** Is the TILE_WRITE_PENDING SPR supported? */ | ||
148 | #define CHIP_HAS_TILE_WRITE_PENDING() 0 | ||
149 | |||
150 | /** Is the PROC_STATUS SPR supported? */ | ||
151 | #define CHIP_HAS_PROC_STATUS_SPR() 0 | ||
152 | |||
153 | /** Is the DSTREAM_PF SPR supported? */ | ||
154 | #define CHIP_HAS_DSTREAM_PF() 0 | ||
155 | |||
156 | /** Log of the number of mshims we have. */ | ||
157 | #define CHIP_LOG_NUM_MSHIMS() 2 | ||
158 | |||
159 | /** Are the bases of the interrupt vector areas fixed? */ | ||
160 | #define CHIP_HAS_FIXED_INTVEC_BASE() 1 | ||
161 | |||
162 | /** Are the interrupt masks split up into 2 SPRs? */ | ||
163 | #define CHIP_HAS_SPLIT_INTR_MASK() 1 | ||
164 | |||
165 | /** Is the cycle count split up into 2 SPRs? */ | ||
166 | #define CHIP_HAS_SPLIT_CYCLE() 1 | ||
167 | |||
168 | /** Does the chip have a static network? */ | ||
169 | #define CHIP_HAS_SN() 1 | ||
170 | |||
171 | /** Does the chip have a static network processor? */ | ||
172 | #define CHIP_HAS_SN_PROC() 1 | ||
173 | |||
174 | /** Size of the L1 static network processor instruction cache, in bytes. */ | ||
175 | #define CHIP_L1SNI_CACHE_SIZE() 2048 | ||
176 | |||
177 | /** Does the chip have DMA support in each tile? */ | ||
178 | #define CHIP_HAS_TILE_DMA() 1 | ||
179 | |||
180 | /** Does the chip have the second revision of the directly accessible | ||
181 | * dynamic networks? This encapsulates a number of characteristics, | ||
182 | * including the absence of the catch-all, the absence of inline message | ||
183 | * tags, the absence of support for network context-switching, and so on. | ||
184 | */ | ||
185 | #define CHIP_HAS_REV1_XDN() 0 | ||
186 | |||
187 | /** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */ | ||
188 | #define CHIP_HAS_CMPEXCH() 0 | ||
189 | |||
190 | /** Does the chip have memory-mapped I/O support? */ | ||
191 | #define CHIP_HAS_MMIO() 0 | ||
192 | |||
193 | /** Does the chip have post-completion interrupts? */ | ||
194 | #define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 0 | ||
195 | |||
196 | /** Does the chip have native single step support? */ | ||
197 | #define CHIP_HAS_SINGLE_STEP() 0 | ||
198 | |||
199 | #ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */ | ||
200 | |||
201 | /** How many entries are present in the instruction TLB? */ | ||
202 | #define CHIP_ITLB_ENTRIES() 8 | ||
203 | |||
204 | /** How many entries are present in the data TLB? */ | ||
205 | #define CHIP_DTLB_ENTRIES() 16 | ||
206 | |||
207 | /** How many MAF entries does the XAUI shim have? */ | ||
208 | #define CHIP_XAUI_MAF_ENTRIES() 16 | ||
209 | |||
210 | /** Does the memory shim have a source-id table? */ | ||
211 | #define CHIP_HAS_MSHIM_SRCID_TABLE() 1 | ||
212 | |||
213 | /** Does the L1 instruction cache clear on reset? */ | ||
214 | #define CHIP_HAS_L1I_CLEAR_ON_RESET() 0 | ||
215 | |||
216 | /** Does the chip come out of reset with valid coordinates on all tiles? | ||
217 | * Note that if defined, this also implies that the upper left is 1,1. | ||
218 | */ | ||
219 | #define CHIP_HAS_VALID_TILE_COORD_RESET() 0 | ||
220 | |||
221 | /** Does the chip have unified packet formats? */ | ||
222 | #define CHIP_HAS_UNIFIED_PACKET_FORMATS() 0 | ||
223 | |||
224 | /** Does the chip support write reordering? */ | ||
225 | #define CHIP_HAS_WRITE_REORDERING() 0 | ||
226 | |||
227 | /** Does the chip support Y-X routing as well as X-Y? */ | ||
228 | #define CHIP_HAS_Y_X_ROUTING() 0 | ||
229 | |||
230 | /** Is INTCTRL_3 managed with the correct MPL? */ | ||
231 | #define CHIP_HAS_INTCTRL_3_STATUS_FIX() 0 | ||
232 | |||
233 | /** Is it possible to configure the chip to be big-endian? */ | ||
234 | #define CHIP_HAS_BIG_ENDIAN_CONFIG() 0 | ||
235 | |||
236 | /** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */ | ||
237 | #define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0 | ||
238 | |||
239 | /** Is the DIAG_TRACE_WAY SPR supported? */ | ||
240 | #define CHIP_HAS_DIAG_TRACE_WAY() 0 | ||
241 | |||
242 | /** Is the MEM_STRIPE_CONFIG SPR supported? */ | ||
243 | #define CHIP_HAS_MEM_STRIPE_CONFIG() 0 | ||
244 | |||
245 | /** Are the TLB_PERF SPRs supported? */ | ||
246 | #define CHIP_HAS_TLB_PERF() 0 | ||
247 | |||
248 | /** Is the VDN_SNOOP_SHIM_CTL SPR supported? */ | ||
249 | #define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0 | ||
250 | |||
251 | /** Does the chip support rev1 DMA packets? */ | ||
252 | #define CHIP_HAS_REV1_DMA_PACKETS() 0 | ||
253 | |||
254 | /** Does the chip have an IPI shim? */ | ||
255 | #define CHIP_HAS_IPI() 0 | ||
256 | |||
257 | #endif /* !__OPEN_SOURCE__ */ | ||
258 | #endif /* __ARCH_CHIP_H__ */ | ||
diff --git a/arch/tile/include/uapi/arch/chip_tilegx.h b/arch/tile/include/uapi/arch/chip_tilegx.h new file mode 100644 index 000000000000..ea8e4f2c9483 --- /dev/null +++ b/arch/tile/include/uapi/arch/chip_tilegx.h | |||
@@ -0,0 +1,258 @@ | |||
1 | /* | ||
2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | /* | ||
16 | * @file | ||
17 | * Global header file. | ||
18 | * This header file specifies defines for TILE-Gx. | ||
19 | */ | ||
20 | |||
21 | #ifndef __ARCH_CHIP_H__ | ||
22 | #define __ARCH_CHIP_H__ | ||
23 | |||
24 | /** Specify chip version. | ||
25 | * When possible, prefer the CHIP_xxx symbols below for future-proofing. | ||
26 | * This is intended for cross-compiling; native compilation should | ||
27 | * use the predefined __tile_chip__ symbol. | ||
28 | */ | ||
29 | #define TILE_CHIP 10 | ||
30 | |||
31 | /** Specify chip revision. | ||
32 | * This provides for the case of a respin of a particular chip type; | ||
33 | * the normal value for this symbol is "0". | ||
34 | * This is intended for cross-compiling; native compilation should | ||
35 | * use the predefined __tile_chip_rev__ symbol. | ||
36 | */ | ||
37 | #define TILE_CHIP_REV 0 | ||
38 | |||
39 | /** The name of this architecture. */ | ||
40 | #define CHIP_ARCH_NAME "tilegx" | ||
41 | |||
42 | /** The ELF e_machine type for binaries for this chip. */ | ||
43 | #define CHIP_ELF_TYPE() EM_TILEGX | ||
44 | |||
45 | /** The alternate ELF e_machine type for binaries for this chip. */ | ||
46 | #define CHIP_COMPAT_ELF_TYPE() 0x2597 | ||
47 | |||
48 | /** What is the native word size of the machine? */ | ||
49 | #define CHIP_WORD_SIZE() 64 | ||
50 | |||
51 | /** How many bits of a virtual address are used. Extra bits must be | ||
52 | * the sign extension of the low bits. | ||
53 | */ | ||
54 | #define CHIP_VA_WIDTH() 42 | ||
55 | |||
56 | /** How many bits are in a physical address? */ | ||
57 | #define CHIP_PA_WIDTH() 40 | ||
58 | |||
59 | /** Size of the L2 cache, in bytes. */ | ||
60 | #define CHIP_L2_CACHE_SIZE() 262144 | ||
61 | |||
62 | /** Log size of an L2 cache line in bytes. */ | ||
63 | #define CHIP_L2_LOG_LINE_SIZE() 6 | ||
64 | |||
65 | /** Size of an L2 cache line, in bytes. */ | ||
66 | #define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE()) | ||
67 | |||
68 | /** Associativity of the L2 cache. */ | ||
69 | #define CHIP_L2_ASSOC() 8 | ||
70 | |||
71 | /** Size of the L1 data cache, in bytes. */ | ||
72 | #define CHIP_L1D_CACHE_SIZE() 32768 | ||
73 | |||
74 | /** Log size of an L1 data cache line in bytes. */ | ||
75 | #define CHIP_L1D_LOG_LINE_SIZE() 6 | ||
76 | |||
77 | /** Size of an L1 data cache line, in bytes. */ | ||
78 | #define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE()) | ||
79 | |||
80 | /** Associativity of the L1 data cache. */ | ||
81 | #define CHIP_L1D_ASSOC() 2 | ||
82 | |||
83 | /** Size of the L1 instruction cache, in bytes. */ | ||
84 | #define CHIP_L1I_CACHE_SIZE() 32768 | ||
85 | |||
86 | /** Log size of an L1 instruction cache line in bytes. */ | ||
87 | #define CHIP_L1I_LOG_LINE_SIZE() 6 | ||
88 | |||
89 | /** Size of an L1 instruction cache line, in bytes. */ | ||
90 | #define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE()) | ||
91 | |||
92 | /** Associativity of the L1 instruction cache. */ | ||
93 | #define CHIP_L1I_ASSOC() 2 | ||
94 | |||
95 | /** Stride with which flush instructions must be issued. */ | ||
96 | #define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE() | ||
97 | |||
98 | /** Stride with which inv instructions must be issued. */ | ||
99 | #define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE() | ||
100 | |||
101 | /** Stride with which finv instructions must be issued. */ | ||
102 | #define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE() | ||
103 | |||
104 | /** Can the local cache coherently cache data that is homed elsewhere? */ | ||
105 | #define CHIP_HAS_COHERENT_LOCAL_CACHE() 1 | ||
106 | |||
107 | /** How many simultaneous outstanding victims can the L2 cache have? */ | ||
108 | #define CHIP_MAX_OUTSTANDING_VICTIMS() 128 | ||
109 | |||
110 | /** Does the TLB support the NC and NOALLOC bits? */ | ||
111 | #define CHIP_HAS_NC_AND_NOALLOC_BITS() 1 | ||
112 | |||
113 | /** Does the chip support hash-for-home caching? */ | ||
114 | #define CHIP_HAS_CBOX_HOME_MAP() 1 | ||
115 | |||
116 | /** Number of entries in the chip's home map tables. */ | ||
117 | #define CHIP_CBOX_HOME_MAP_SIZE() 128 | ||
118 | |||
119 | /** Do uncacheable requests miss in the cache regardless of whether | ||
120 | * there is matching data? */ | ||
121 | #define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1 | ||
122 | |||
123 | /** Does the mf instruction wait for victims? */ | ||
124 | #define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0 | ||
125 | |||
126 | /** Does the chip have an "inv" instruction that doesn't also flush? */ | ||
127 | #define CHIP_HAS_INV() 1 | ||
128 | |||
129 | /** Does the chip have a "wh64" instruction? */ | ||
130 | #define CHIP_HAS_WH64() 1 | ||
131 | |||
132 | /** Does this chip have a 'dword_align' instruction? */ | ||
133 | #define CHIP_HAS_DWORD_ALIGN() 0 | ||
134 | |||
135 | /** Number of performance counters. */ | ||
136 | #define CHIP_PERFORMANCE_COUNTERS() 4 | ||
137 | |||
138 | /** Does this chip have auxiliary performance counters? */ | ||
139 | #define CHIP_HAS_AUX_PERF_COUNTERS() 1 | ||
140 | |||
141 | /** Is the CBOX_MSR1 SPR supported? */ | ||
142 | #define CHIP_HAS_CBOX_MSR1() 0 | ||
143 | |||
144 | /** Is the TILE_RTF_HWM SPR supported? */ | ||
145 | #define CHIP_HAS_TILE_RTF_HWM() 1 | ||
146 | |||
147 | /** Is the TILE_WRITE_PENDING SPR supported? */ | ||
148 | #define CHIP_HAS_TILE_WRITE_PENDING() 0 | ||
149 | |||
150 | /** Is the PROC_STATUS SPR supported? */ | ||
151 | #define CHIP_HAS_PROC_STATUS_SPR() 1 | ||
152 | |||
153 | /** Is the DSTREAM_PF SPR supported? */ | ||
154 | #define CHIP_HAS_DSTREAM_PF() 1 | ||
155 | |||
156 | /** Log of the number of mshims we have. */ | ||
157 | #define CHIP_LOG_NUM_MSHIMS() 2 | ||
158 | |||
159 | /** Are the bases of the interrupt vector areas fixed? */ | ||
160 | #define CHIP_HAS_FIXED_INTVEC_BASE() 0 | ||
161 | |||
162 | /** Are the interrupt masks split up into 2 SPRs? */ | ||
163 | #define CHIP_HAS_SPLIT_INTR_MASK() 0 | ||
164 | |||
165 | /** Is the cycle count split up into 2 SPRs? */ | ||
166 | #define CHIP_HAS_SPLIT_CYCLE() 0 | ||
167 | |||
168 | /** Does the chip have a static network? */ | ||
169 | #define CHIP_HAS_SN() 0 | ||
170 | |||
171 | /** Does the chip have a static network processor? */ | ||
172 | #define CHIP_HAS_SN_PROC() 0 | ||
173 | |||
174 | /** Size of the L1 static network processor instruction cache, in bytes. */ | ||
175 | /* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 10 */ | ||
176 | |||
177 | /** Does the chip have DMA support in each tile? */ | ||
178 | #define CHIP_HAS_TILE_DMA() 0 | ||
179 | |||
180 | /** Does the chip have the second revision of the directly accessible | ||
181 | * dynamic networks? This encapsulates a number of characteristics, | ||
182 | * including the absence of the catch-all, the absence of inline message | ||
183 | * tags, the absence of support for network context-switching, and so on. | ||
184 | */ | ||
185 | #define CHIP_HAS_REV1_XDN() 1 | ||
186 | |||
187 | /** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */ | ||
188 | #define CHIP_HAS_CMPEXCH() 1 | ||
189 | |||
190 | /** Does the chip have memory-mapped I/O support? */ | ||
191 | #define CHIP_HAS_MMIO() 1 | ||
192 | |||
193 | /** Does the chip have post-completion interrupts? */ | ||
194 | #define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 1 | ||
195 | |||
196 | /** Does the chip have native single step support? */ | ||
197 | #define CHIP_HAS_SINGLE_STEP() 1 | ||
198 | |||
199 | #ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */ | ||
200 | |||
201 | /** How many entries are present in the instruction TLB? */ | ||
202 | #define CHIP_ITLB_ENTRIES() 16 | ||
203 | |||
204 | /** How many entries are present in the data TLB? */ | ||
205 | #define CHIP_DTLB_ENTRIES() 32 | ||
206 | |||
207 | /** How many MAF entries does the XAUI shim have? */ | ||
208 | #define CHIP_XAUI_MAF_ENTRIES() 32 | ||
209 | |||
210 | /** Does the memory shim have a source-id table? */ | ||
211 | #define CHIP_HAS_MSHIM_SRCID_TABLE() 0 | ||
212 | |||
213 | /** Does the L1 instruction cache clear on reset? */ | ||
214 | #define CHIP_HAS_L1I_CLEAR_ON_RESET() 1 | ||
215 | |||
216 | /** Does the chip come out of reset with valid coordinates on all tiles? | ||
217 | * Note that if defined, this also implies that the upper left is 1,1. | ||
218 | */ | ||
219 | #define CHIP_HAS_VALID_TILE_COORD_RESET() 1 | ||
220 | |||
221 | /** Does the chip have unified packet formats? */ | ||
222 | #define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1 | ||
223 | |||
224 | /** Does the chip support write reordering? */ | ||
225 | #define CHIP_HAS_WRITE_REORDERING() 1 | ||
226 | |||
227 | /** Does the chip support Y-X routing as well as X-Y? */ | ||
228 | #define CHIP_HAS_Y_X_ROUTING() 1 | ||
229 | |||
230 | /** Is INTCTRL_3 managed with the correct MPL? */ | ||
231 | #define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1 | ||
232 | |||
233 | /** Is it possible to configure the chip to be big-endian? */ | ||
234 | #define CHIP_HAS_BIG_ENDIAN_CONFIG() 1 | ||
235 | |||
236 | /** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */ | ||
237 | #define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0 | ||
238 | |||
239 | /** Is the DIAG_TRACE_WAY SPR supported? */ | ||
240 | #define CHIP_HAS_DIAG_TRACE_WAY() 0 | ||
241 | |||
242 | /** Is the MEM_STRIPE_CONFIG SPR supported? */ | ||
243 | #define CHIP_HAS_MEM_STRIPE_CONFIG() 1 | ||
244 | |||
245 | /** Are the TLB_PERF SPRs supported? */ | ||
246 | #define CHIP_HAS_TLB_PERF() 1 | ||
247 | |||
248 | /** Is the VDN_SNOOP_SHIM_CTL SPR supported? */ | ||
249 | #define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0 | ||
250 | |||
251 | /** Does the chip support rev1 DMA packets? */ | ||
252 | #define CHIP_HAS_REV1_DMA_PACKETS() 1 | ||
253 | |||
254 | /** Does the chip have an IPI shim? */ | ||
255 | #define CHIP_HAS_IPI() 1 | ||
256 | |||
257 | #endif /* !__OPEN_SOURCE__ */ | ||
258 | #endif /* __ARCH_CHIP_H__ */ | ||
diff --git a/arch/tile/include/uapi/arch/chip_tilepro.h b/arch/tile/include/uapi/arch/chip_tilepro.h new file mode 100644 index 000000000000..70017699a74c --- /dev/null +++ b/arch/tile/include/uapi/arch/chip_tilepro.h | |||
@@ -0,0 +1,258 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | /* | ||
16 | * @file | ||
17 | * Global header file. | ||
18 | * This header file specifies defines for TILEPro. | ||
19 | */ | ||
20 | |||
21 | #ifndef __ARCH_CHIP_H__ | ||
22 | #define __ARCH_CHIP_H__ | ||
23 | |||
24 | /** Specify chip version. | ||
25 | * When possible, prefer the CHIP_xxx symbols below for future-proofing. | ||
26 | * This is intended for cross-compiling; native compilation should | ||
27 | * use the predefined __tile_chip__ symbol. | ||
28 | */ | ||
29 | #define TILE_CHIP 1 | ||
30 | |||
31 | /** Specify chip revision. | ||
32 | * This provides for the case of a respin of a particular chip type; | ||
33 | * the normal value for this symbol is "0". | ||
34 | * This is intended for cross-compiling; native compilation should | ||
35 | * use the predefined __tile_chip_rev__ symbol. | ||
36 | */ | ||
37 | #define TILE_CHIP_REV 0 | ||
38 | |||
39 | /** The name of this architecture. */ | ||
40 | #define CHIP_ARCH_NAME "tilepro" | ||
41 | |||
42 | /** The ELF e_machine type for binaries for this chip. */ | ||
43 | #define CHIP_ELF_TYPE() EM_TILEPRO | ||
44 | |||
45 | /** The alternate ELF e_machine type for binaries for this chip. */ | ||
46 | #define CHIP_COMPAT_ELF_TYPE() 0x2507 | ||
47 | |||
48 | /** What is the native word size of the machine? */ | ||
49 | #define CHIP_WORD_SIZE() 32 | ||
50 | |||
51 | /** How many bits of a virtual address are used. Extra bits must be | ||
52 | * the sign extension of the low bits. | ||
53 | */ | ||
54 | #define CHIP_VA_WIDTH() 32 | ||
55 | |||
56 | /** How many bits are in a physical address? */ | ||
57 | #define CHIP_PA_WIDTH() 36 | ||
58 | |||
59 | /** Size of the L2 cache, in bytes. */ | ||
60 | #define CHIP_L2_CACHE_SIZE() 65536 | ||
61 | |||
62 | /** Log size of an L2 cache line in bytes. */ | ||
63 | #define CHIP_L2_LOG_LINE_SIZE() 6 | ||
64 | |||
65 | /** Size of an L2 cache line, in bytes. */ | ||
66 | #define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE()) | ||
67 | |||
68 | /** Associativity of the L2 cache. */ | ||
69 | #define CHIP_L2_ASSOC() 4 | ||
70 | |||
71 | /** Size of the L1 data cache, in bytes. */ | ||
72 | #define CHIP_L1D_CACHE_SIZE() 8192 | ||
73 | |||
74 | /** Log size of an L1 data cache line in bytes. */ | ||
75 | #define CHIP_L1D_LOG_LINE_SIZE() 4 | ||
76 | |||
77 | /** Size of an L1 data cache line, in bytes. */ | ||
78 | #define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE()) | ||
79 | |||
80 | /** Associativity of the L1 data cache. */ | ||
81 | #define CHIP_L1D_ASSOC() 2 | ||
82 | |||
83 | /** Size of the L1 instruction cache, in bytes. */ | ||
84 | #define CHIP_L1I_CACHE_SIZE() 16384 | ||
85 | |||
86 | /** Log size of an L1 instruction cache line in bytes. */ | ||
87 | #define CHIP_L1I_LOG_LINE_SIZE() 6 | ||
88 | |||
89 | /** Size of an L1 instruction cache line, in bytes. */ | ||
90 | #define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE()) | ||
91 | |||
92 | /** Associativity of the L1 instruction cache. */ | ||
93 | #define CHIP_L1I_ASSOC() 1 | ||
94 | |||
95 | /** Stride with which flush instructions must be issued. */ | ||
96 | #define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE() | ||
97 | |||
98 | /** Stride with which inv instructions must be issued. */ | ||
99 | #define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE() | ||
100 | |||
101 | /** Stride with which finv instructions must be issued. */ | ||
102 | #define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE() | ||
103 | |||
104 | /** Can the local cache coherently cache data that is homed elsewhere? */ | ||
105 | #define CHIP_HAS_COHERENT_LOCAL_CACHE() 1 | ||
106 | |||
107 | /** How many simultaneous outstanding victims can the L2 cache have? */ | ||
108 | #define CHIP_MAX_OUTSTANDING_VICTIMS() 4 | ||
109 | |||
110 | /** Does the TLB support the NC and NOALLOC bits? */ | ||
111 | #define CHIP_HAS_NC_AND_NOALLOC_BITS() 1 | ||
112 | |||
113 | /** Does the chip support hash-for-home caching? */ | ||
114 | #define CHIP_HAS_CBOX_HOME_MAP() 1 | ||
115 | |||
116 | /** Number of entries in the chip's home map tables. */ | ||
117 | #define CHIP_CBOX_HOME_MAP_SIZE() 64 | ||
118 | |||
119 | /** Do uncacheable requests miss in the cache regardless of whether | ||
120 | * there is matching data? */ | ||
121 | #define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1 | ||
122 | |||
123 | /** Does the mf instruction wait for victims? */ | ||
124 | #define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0 | ||
125 | |||
126 | /** Does the chip have an "inv" instruction that doesn't also flush? */ | ||
127 | #define CHIP_HAS_INV() 1 | ||
128 | |||
129 | /** Does the chip have a "wh64" instruction? */ | ||
130 | #define CHIP_HAS_WH64() 1 | ||
131 | |||
132 | /** Does this chip have a 'dword_align' instruction? */ | ||
133 | #define CHIP_HAS_DWORD_ALIGN() 1 | ||
134 | |||
135 | /** Number of performance counters. */ | ||
136 | #define CHIP_PERFORMANCE_COUNTERS() 4 | ||
137 | |||
138 | /** Does this chip have auxiliary performance counters? */ | ||
139 | #define CHIP_HAS_AUX_PERF_COUNTERS() 1 | ||
140 | |||
141 | /** Is the CBOX_MSR1 SPR supported? */ | ||
142 | #define CHIP_HAS_CBOX_MSR1() 1 | ||
143 | |||
144 | /** Is the TILE_RTF_HWM SPR supported? */ | ||
145 | #define CHIP_HAS_TILE_RTF_HWM() 1 | ||
146 | |||
147 | /** Is the TILE_WRITE_PENDING SPR supported? */ | ||
148 | #define CHIP_HAS_TILE_WRITE_PENDING() 1 | ||
149 | |||
150 | /** Is the PROC_STATUS SPR supported? */ | ||
151 | #define CHIP_HAS_PROC_STATUS_SPR() 1 | ||
152 | |||
153 | /** Is the DSTREAM_PF SPR supported? */ | ||
154 | #define CHIP_HAS_DSTREAM_PF() 0 | ||
155 | |||
156 | /** Log of the number of mshims we have. */ | ||
157 | #define CHIP_LOG_NUM_MSHIMS() 2 | ||
158 | |||
159 | /** Are the bases of the interrupt vector areas fixed? */ | ||
160 | #define CHIP_HAS_FIXED_INTVEC_BASE() 1 | ||
161 | |||
162 | /** Are the interrupt masks split up into 2 SPRs? */ | ||
163 | #define CHIP_HAS_SPLIT_INTR_MASK() 1 | ||
164 | |||
165 | /** Is the cycle count split up into 2 SPRs? */ | ||
166 | #define CHIP_HAS_SPLIT_CYCLE() 1 | ||
167 | |||
168 | /** Does the chip have a static network? */ | ||
169 | #define CHIP_HAS_SN() 1 | ||
170 | |||
171 | /** Does the chip have a static network processor? */ | ||
172 | #define CHIP_HAS_SN_PROC() 0 | ||
173 | |||
174 | /** Size of the L1 static network processor instruction cache, in bytes. */ | ||
175 | /* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 1 */ | ||
176 | |||
177 | /** Does the chip have DMA support in each tile? */ | ||
178 | #define CHIP_HAS_TILE_DMA() 1 | ||
179 | |||
180 | /** Does the chip have the second revision of the directly accessible | ||
181 | * dynamic networks? This encapsulates a number of characteristics, | ||
182 | * including the absence of the catch-all, the absence of inline message | ||
183 | * tags, the absence of support for network context-switching, and so on. | ||
184 | */ | ||
185 | #define CHIP_HAS_REV1_XDN() 0 | ||
186 | |||
187 | /** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */ | ||
188 | #define CHIP_HAS_CMPEXCH() 0 | ||
189 | |||
190 | /** Does the chip have memory-mapped I/O support? */ | ||
191 | #define CHIP_HAS_MMIO() 0 | ||
192 | |||
193 | /** Does the chip have post-completion interrupts? */ | ||
194 | #define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 0 | ||
195 | |||
196 | /** Does the chip have native single step support? */ | ||
197 | #define CHIP_HAS_SINGLE_STEP() 0 | ||
198 | |||
199 | #ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */ | ||
200 | |||
201 | /** How many entries are present in the instruction TLB? */ | ||
202 | #define CHIP_ITLB_ENTRIES() 16 | ||
203 | |||
204 | /** How many entries are present in the data TLB? */ | ||
205 | #define CHIP_DTLB_ENTRIES() 16 | ||
206 | |||
207 | /** How many MAF entries does the XAUI shim have? */ | ||
208 | #define CHIP_XAUI_MAF_ENTRIES() 32 | ||
209 | |||
210 | /** Does the memory shim have a source-id table? */ | ||
211 | #define CHIP_HAS_MSHIM_SRCID_TABLE() 0 | ||
212 | |||
213 | /** Does the L1 instruction cache clear on reset? */ | ||
214 | #define CHIP_HAS_L1I_CLEAR_ON_RESET() 1 | ||
215 | |||
216 | /** Does the chip come out of reset with valid coordinates on all tiles? | ||
217 | * Note that if defined, this also implies that the upper left is 1,1. | ||
218 | */ | ||
219 | #define CHIP_HAS_VALID_TILE_COORD_RESET() 1 | ||
220 | |||
221 | /** Does the chip have unified packet formats? */ | ||
222 | #define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1 | ||
223 | |||
224 | /** Does the chip support write reordering? */ | ||
225 | #define CHIP_HAS_WRITE_REORDERING() 1 | ||
226 | |||
227 | /** Does the chip support Y-X routing as well as X-Y? */ | ||
228 | #define CHIP_HAS_Y_X_ROUTING() 1 | ||
229 | |||
230 | /** Is INTCTRL_3 managed with the correct MPL? */ | ||
231 | #define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1 | ||
232 | |||
233 | /** Is it possible to configure the chip to be big-endian? */ | ||
234 | #define CHIP_HAS_BIG_ENDIAN_CONFIG() 1 | ||
235 | |||
236 | /** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */ | ||
237 | #define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 1 | ||
238 | |||
239 | /** Is the DIAG_TRACE_WAY SPR supported? */ | ||
240 | #define CHIP_HAS_DIAG_TRACE_WAY() 1 | ||
241 | |||
242 | /** Is the MEM_STRIPE_CONFIG SPR supported? */ | ||
243 | #define CHIP_HAS_MEM_STRIPE_CONFIG() 1 | ||
244 | |||
245 | /** Are the TLB_PERF SPRs supported? */ | ||
246 | #define CHIP_HAS_TLB_PERF() 1 | ||
247 | |||
248 | /** Is the VDN_SNOOP_SHIM_CTL SPR supported? */ | ||
249 | #define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 1 | ||
250 | |||
251 | /** Does the chip support rev1 DMA packets? */ | ||
252 | #define CHIP_HAS_REV1_DMA_PACKETS() 1 | ||
253 | |||
254 | /** Does the chip have an IPI shim? */ | ||
255 | #define CHIP_HAS_IPI() 0 | ||
256 | |||
257 | #endif /* !__OPEN_SOURCE__ */ | ||
258 | #endif /* __ARCH_CHIP_H__ */ | ||
diff --git a/arch/tile/include/uapi/arch/icache.h b/arch/tile/include/uapi/arch/icache.h new file mode 100644 index 000000000000..762eafa8a11e --- /dev/null +++ b/arch/tile/include/uapi/arch/icache.h | |||
@@ -0,0 +1,93 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | /** | ||
17 | * @file | ||
18 | * | ||
19 | * Support for invalidating bytes in the instruction cache. | ||
20 | */ | ||
21 | |||
22 | #ifndef __ARCH_ICACHE_H__ | ||
23 | #define __ARCH_ICACHE_H__ | ||
24 | |||
25 | #include <arch/chip.h> | ||
26 | |||
27 | |||
28 | /** | ||
29 | * Invalidate the instruction cache for the given range of memory. | ||
30 | * | ||
31 | * @param addr The start of memory to be invalidated. | ||
32 | * @param size The number of bytes to be invalidated. | ||
33 | * @param page_size The system's page size, e.g. getpagesize() in userspace. | ||
34 | * This value must be a power of two no larger than the page containing | ||
35 | * the code to be invalidated. If the value is smaller than the actual page | ||
36 | * size, this function will still work, but may run slower than necessary. | ||
37 | */ | ||
38 | static __inline void | ||
39 | invalidate_icache(const void* addr, unsigned long size, | ||
40 | unsigned long page_size) | ||
41 | { | ||
42 | const unsigned long cache_way_size = | ||
43 | CHIP_L1I_CACHE_SIZE() / CHIP_L1I_ASSOC(); | ||
44 | unsigned long max_useful_size; | ||
45 | const char* start, *end; | ||
46 | long num_passes; | ||
47 | |||
48 | if (__builtin_expect(size == 0, 0)) | ||
49 | return; | ||
50 | |||
51 | #ifdef __tilegx__ | ||
52 | /* Limit the number of bytes visited to avoid redundant iterations. */ | ||
53 | max_useful_size = (page_size < cache_way_size) ? page_size : cache_way_size; | ||
54 | |||
55 | /* No PA aliasing is possible, so one pass always suffices. */ | ||
56 | num_passes = 1; | ||
57 | #else | ||
58 | /* Limit the number of bytes visited to avoid redundant iterations. */ | ||
59 | max_useful_size = cache_way_size; | ||
60 | |||
61 | /* | ||
62 | * Compute how many passes we need (we'll treat 0 as if it were 1). | ||
63 | * This works because we know the page size is a power of two. | ||
64 | */ | ||
65 | num_passes = cache_way_size >> __builtin_ctzl(page_size); | ||
66 | #endif | ||
67 | |||
68 | if (__builtin_expect(size > max_useful_size, 0)) | ||
69 | size = max_useful_size; | ||
70 | |||
71 | /* Locate the first and last bytes to be invalidated. */ | ||
72 | start = (const char *)((unsigned long)addr & -CHIP_L1I_LINE_SIZE()); | ||
73 | end = (const char*)addr + size - 1; | ||
74 | |||
75 | __insn_mf(); | ||
76 | |||
77 | do | ||
78 | { | ||
79 | const char* p; | ||
80 | |||
81 | for (p = start; p <= end; p += CHIP_L1I_LINE_SIZE()) | ||
82 | __insn_icoh(p); | ||
83 | |||
84 | start += page_size; | ||
85 | end += page_size; | ||
86 | } | ||
87 | while (--num_passes > 0); | ||
88 | |||
89 | __insn_drain(); | ||
90 | } | ||
91 | |||
92 | |||
93 | #endif /* __ARCH_ICACHE_H__ */ | ||
diff --git a/arch/tile/include/uapi/arch/interrupts.h b/arch/tile/include/uapi/arch/interrupts.h new file mode 100644 index 000000000000..20f8f07d2de9 --- /dev/null +++ b/arch/tile/include/uapi/arch/interrupts.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | #ifdef __tilegx__ | ||
16 | #include <arch/interrupts_64.h> | ||
17 | #else | ||
18 | #include <arch/interrupts_32.h> | ||
19 | #endif | ||
diff --git a/arch/tile/include/uapi/arch/interrupts_32.h b/arch/tile/include/uapi/arch/interrupts_32.h new file mode 100644 index 000000000000..96b5710505b6 --- /dev/null +++ b/arch/tile/include/uapi/arch/interrupts_32.h | |||
@@ -0,0 +1,307 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ARCH_INTERRUPTS_H__ | ||
16 | #define __ARCH_INTERRUPTS_H__ | ||
17 | |||
18 | /** Mask for an interrupt. */ | ||
19 | /* Note: must handle breaking interrupts into high and low words manually. */ | ||
20 | #define INT_MASK_LO(intno) (1 << (intno)) | ||
21 | #define INT_MASK_HI(intno) (1 << ((intno) - 32)) | ||
22 | |||
23 | #ifndef __ASSEMBLER__ | ||
24 | #define INT_MASK(intno) (1ULL << (intno)) | ||
25 | #endif | ||
26 | |||
27 | |||
28 | /** Where a given interrupt executes */ | ||
29 | #define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8)) | ||
30 | |||
31 | /** Where to store a vector for a given interrupt. */ | ||
32 | #define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0) | ||
33 | |||
34 | /** The base address of user-level interrupts. */ | ||
35 | #define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0) | ||
36 | |||
37 | |||
38 | /** Additional synthetic interrupt. */ | ||
39 | #define INT_BREAKPOINT (63) | ||
40 | |||
41 | #define INT_ITLB_MISS 0 | ||
42 | #define INT_MEM_ERROR 1 | ||
43 | #define INT_ILL 2 | ||
44 | #define INT_GPV 3 | ||
45 | #define INT_SN_ACCESS 4 | ||
46 | #define INT_IDN_ACCESS 5 | ||
47 | #define INT_UDN_ACCESS 6 | ||
48 | #define INT_IDN_REFILL 7 | ||
49 | #define INT_UDN_REFILL 8 | ||
50 | #define INT_IDN_COMPLETE 9 | ||
51 | #define INT_UDN_COMPLETE 10 | ||
52 | #define INT_SWINT_3 11 | ||
53 | #define INT_SWINT_2 12 | ||
54 | #define INT_SWINT_1 13 | ||
55 | #define INT_SWINT_0 14 | ||
56 | #define INT_UNALIGN_DATA 15 | ||
57 | #define INT_DTLB_MISS 16 | ||
58 | #define INT_DTLB_ACCESS 17 | ||
59 | #define INT_DMATLB_MISS 18 | ||
60 | #define INT_DMATLB_ACCESS 19 | ||
61 | #define INT_SNITLB_MISS 20 | ||
62 | #define INT_SN_NOTIFY 21 | ||
63 | #define INT_SN_FIREWALL 22 | ||
64 | #define INT_IDN_FIREWALL 23 | ||
65 | #define INT_UDN_FIREWALL 24 | ||
66 | #define INT_TILE_TIMER 25 | ||
67 | #define INT_IDN_TIMER 26 | ||
68 | #define INT_UDN_TIMER 27 | ||
69 | #define INT_DMA_NOTIFY 28 | ||
70 | #define INT_IDN_CA 29 | ||
71 | #define INT_UDN_CA 30 | ||
72 | #define INT_IDN_AVAIL 31 | ||
73 | #define INT_UDN_AVAIL 32 | ||
74 | #define INT_PERF_COUNT 33 | ||
75 | #define INT_INTCTRL_3 34 | ||
76 | #define INT_INTCTRL_2 35 | ||
77 | #define INT_INTCTRL_1 36 | ||
78 | #define INT_INTCTRL_0 37 | ||
79 | #define INT_BOOT_ACCESS 38 | ||
80 | #define INT_WORLD_ACCESS 39 | ||
81 | #define INT_I_ASID 40 | ||
82 | #define INT_D_ASID 41 | ||
83 | #define INT_DMA_ASID 42 | ||
84 | #define INT_SNI_ASID 43 | ||
85 | #define INT_DMA_CPL 44 | ||
86 | #define INT_SN_CPL 45 | ||
87 | #define INT_DOUBLE_FAULT 46 | ||
88 | #define INT_SN_STATIC_ACCESS 47 | ||
89 | #define INT_AUX_PERF_COUNT 48 | ||
90 | |||
91 | #define NUM_INTERRUPTS 49 | ||
92 | |||
93 | #ifndef __ASSEMBLER__ | ||
94 | #define QUEUED_INTERRUPTS ( \ | ||
95 | INT_MASK(INT_MEM_ERROR) | \ | ||
96 | INT_MASK(INT_DMATLB_MISS) | \ | ||
97 | INT_MASK(INT_DMATLB_ACCESS) | \ | ||
98 | INT_MASK(INT_SNITLB_MISS) | \ | ||
99 | INT_MASK(INT_SN_NOTIFY) | \ | ||
100 | INT_MASK(INT_SN_FIREWALL) | \ | ||
101 | INT_MASK(INT_IDN_FIREWALL) | \ | ||
102 | INT_MASK(INT_UDN_FIREWALL) | \ | ||
103 | INT_MASK(INT_TILE_TIMER) | \ | ||
104 | INT_MASK(INT_IDN_TIMER) | \ | ||
105 | INT_MASK(INT_UDN_TIMER) | \ | ||
106 | INT_MASK(INT_DMA_NOTIFY) | \ | ||
107 | INT_MASK(INT_IDN_CA) | \ | ||
108 | INT_MASK(INT_UDN_CA) | \ | ||
109 | INT_MASK(INT_IDN_AVAIL) | \ | ||
110 | INT_MASK(INT_UDN_AVAIL) | \ | ||
111 | INT_MASK(INT_PERF_COUNT) | \ | ||
112 | INT_MASK(INT_INTCTRL_3) | \ | ||
113 | INT_MASK(INT_INTCTRL_2) | \ | ||
114 | INT_MASK(INT_INTCTRL_1) | \ | ||
115 | INT_MASK(INT_INTCTRL_0) | \ | ||
116 | INT_MASK(INT_BOOT_ACCESS) | \ | ||
117 | INT_MASK(INT_WORLD_ACCESS) | \ | ||
118 | INT_MASK(INT_I_ASID) | \ | ||
119 | INT_MASK(INT_D_ASID) | \ | ||
120 | INT_MASK(INT_DMA_ASID) | \ | ||
121 | INT_MASK(INT_SNI_ASID) | \ | ||
122 | INT_MASK(INT_DMA_CPL) | \ | ||
123 | INT_MASK(INT_SN_CPL) | \ | ||
124 | INT_MASK(INT_DOUBLE_FAULT) | \ | ||
125 | INT_MASK(INT_AUX_PERF_COUNT) | \ | ||
126 | 0) | ||
127 | #define NONQUEUED_INTERRUPTS ( \ | ||
128 | INT_MASK(INT_ITLB_MISS) | \ | ||
129 | INT_MASK(INT_ILL) | \ | ||
130 | INT_MASK(INT_GPV) | \ | ||
131 | INT_MASK(INT_SN_ACCESS) | \ | ||
132 | INT_MASK(INT_IDN_ACCESS) | \ | ||
133 | INT_MASK(INT_UDN_ACCESS) | \ | ||
134 | INT_MASK(INT_IDN_REFILL) | \ | ||
135 | INT_MASK(INT_UDN_REFILL) | \ | ||
136 | INT_MASK(INT_IDN_COMPLETE) | \ | ||
137 | INT_MASK(INT_UDN_COMPLETE) | \ | ||
138 | INT_MASK(INT_SWINT_3) | \ | ||
139 | INT_MASK(INT_SWINT_2) | \ | ||
140 | INT_MASK(INT_SWINT_1) | \ | ||
141 | INT_MASK(INT_SWINT_0) | \ | ||
142 | INT_MASK(INT_UNALIGN_DATA) | \ | ||
143 | INT_MASK(INT_DTLB_MISS) | \ | ||
144 | INT_MASK(INT_DTLB_ACCESS) | \ | ||
145 | INT_MASK(INT_SN_STATIC_ACCESS) | \ | ||
146 | 0) | ||
147 | #define CRITICAL_MASKED_INTERRUPTS ( \ | ||
148 | INT_MASK(INT_MEM_ERROR) | \ | ||
149 | INT_MASK(INT_DMATLB_MISS) | \ | ||
150 | INT_MASK(INT_DMATLB_ACCESS) | \ | ||
151 | INT_MASK(INT_SNITLB_MISS) | \ | ||
152 | INT_MASK(INT_SN_NOTIFY) | \ | ||
153 | INT_MASK(INT_SN_FIREWALL) | \ | ||
154 | INT_MASK(INT_IDN_FIREWALL) | \ | ||
155 | INT_MASK(INT_UDN_FIREWALL) | \ | ||
156 | INT_MASK(INT_TILE_TIMER) | \ | ||
157 | INT_MASK(INT_IDN_TIMER) | \ | ||
158 | INT_MASK(INT_UDN_TIMER) | \ | ||
159 | INT_MASK(INT_DMA_NOTIFY) | \ | ||
160 | INT_MASK(INT_IDN_CA) | \ | ||
161 | INT_MASK(INT_UDN_CA) | \ | ||
162 | INT_MASK(INT_IDN_AVAIL) | \ | ||
163 | INT_MASK(INT_UDN_AVAIL) | \ | ||
164 | INT_MASK(INT_PERF_COUNT) | \ | ||
165 | INT_MASK(INT_INTCTRL_3) | \ | ||
166 | INT_MASK(INT_INTCTRL_2) | \ | ||
167 | INT_MASK(INT_INTCTRL_1) | \ | ||
168 | INT_MASK(INT_INTCTRL_0) | \ | ||
169 | INT_MASK(INT_AUX_PERF_COUNT) | \ | ||
170 | 0) | ||
171 | #define CRITICAL_UNMASKED_INTERRUPTS ( \ | ||
172 | INT_MASK(INT_ITLB_MISS) | \ | ||
173 | INT_MASK(INT_ILL) | \ | ||
174 | INT_MASK(INT_GPV) | \ | ||
175 | INT_MASK(INT_SN_ACCESS) | \ | ||
176 | INT_MASK(INT_IDN_ACCESS) | \ | ||
177 | INT_MASK(INT_UDN_ACCESS) | \ | ||
178 | INT_MASK(INT_IDN_REFILL) | \ | ||
179 | INT_MASK(INT_UDN_REFILL) | \ | ||
180 | INT_MASK(INT_IDN_COMPLETE) | \ | ||
181 | INT_MASK(INT_UDN_COMPLETE) | \ | ||
182 | INT_MASK(INT_SWINT_3) | \ | ||
183 | INT_MASK(INT_SWINT_2) | \ | ||
184 | INT_MASK(INT_SWINT_1) | \ | ||
185 | INT_MASK(INT_SWINT_0) | \ | ||
186 | INT_MASK(INT_UNALIGN_DATA) | \ | ||
187 | INT_MASK(INT_DTLB_MISS) | \ | ||
188 | INT_MASK(INT_DTLB_ACCESS) | \ | ||
189 | INT_MASK(INT_BOOT_ACCESS) | \ | ||
190 | INT_MASK(INT_WORLD_ACCESS) | \ | ||
191 | INT_MASK(INT_I_ASID) | \ | ||
192 | INT_MASK(INT_D_ASID) | \ | ||
193 | INT_MASK(INT_DMA_ASID) | \ | ||
194 | INT_MASK(INT_SNI_ASID) | \ | ||
195 | INT_MASK(INT_DMA_CPL) | \ | ||
196 | INT_MASK(INT_SN_CPL) | \ | ||
197 | INT_MASK(INT_DOUBLE_FAULT) | \ | ||
198 | INT_MASK(INT_SN_STATIC_ACCESS) | \ | ||
199 | 0) | ||
200 | #define MASKABLE_INTERRUPTS ( \ | ||
201 | INT_MASK(INT_MEM_ERROR) | \ | ||
202 | INT_MASK(INT_IDN_REFILL) | \ | ||
203 | INT_MASK(INT_UDN_REFILL) | \ | ||
204 | INT_MASK(INT_IDN_COMPLETE) | \ | ||
205 | INT_MASK(INT_UDN_COMPLETE) | \ | ||
206 | INT_MASK(INT_DMATLB_MISS) | \ | ||
207 | INT_MASK(INT_DMATLB_ACCESS) | \ | ||
208 | INT_MASK(INT_SNITLB_MISS) | \ | ||
209 | INT_MASK(INT_SN_NOTIFY) | \ | ||
210 | INT_MASK(INT_SN_FIREWALL) | \ | ||
211 | INT_MASK(INT_IDN_FIREWALL) | \ | ||
212 | INT_MASK(INT_UDN_FIREWALL) | \ | ||
213 | INT_MASK(INT_TILE_TIMER) | \ | ||
214 | INT_MASK(INT_IDN_TIMER) | \ | ||
215 | INT_MASK(INT_UDN_TIMER) | \ | ||
216 | INT_MASK(INT_DMA_NOTIFY) | \ | ||
217 | INT_MASK(INT_IDN_CA) | \ | ||
218 | INT_MASK(INT_UDN_CA) | \ | ||
219 | INT_MASK(INT_IDN_AVAIL) | \ | ||
220 | INT_MASK(INT_UDN_AVAIL) | \ | ||
221 | INT_MASK(INT_PERF_COUNT) | \ | ||
222 | INT_MASK(INT_INTCTRL_3) | \ | ||
223 | INT_MASK(INT_INTCTRL_2) | \ | ||
224 | INT_MASK(INT_INTCTRL_1) | \ | ||
225 | INT_MASK(INT_INTCTRL_0) | \ | ||
226 | INT_MASK(INT_AUX_PERF_COUNT) | \ | ||
227 | 0) | ||
228 | #define UNMASKABLE_INTERRUPTS ( \ | ||
229 | INT_MASK(INT_ITLB_MISS) | \ | ||
230 | INT_MASK(INT_ILL) | \ | ||
231 | INT_MASK(INT_GPV) | \ | ||
232 | INT_MASK(INT_SN_ACCESS) | \ | ||
233 | INT_MASK(INT_IDN_ACCESS) | \ | ||
234 | INT_MASK(INT_UDN_ACCESS) | \ | ||
235 | INT_MASK(INT_SWINT_3) | \ | ||
236 | INT_MASK(INT_SWINT_2) | \ | ||
237 | INT_MASK(INT_SWINT_1) | \ | ||
238 | INT_MASK(INT_SWINT_0) | \ | ||
239 | INT_MASK(INT_UNALIGN_DATA) | \ | ||
240 | INT_MASK(INT_DTLB_MISS) | \ | ||
241 | INT_MASK(INT_DTLB_ACCESS) | \ | ||
242 | INT_MASK(INT_BOOT_ACCESS) | \ | ||
243 | INT_MASK(INT_WORLD_ACCESS) | \ | ||
244 | INT_MASK(INT_I_ASID) | \ | ||
245 | INT_MASK(INT_D_ASID) | \ | ||
246 | INT_MASK(INT_DMA_ASID) | \ | ||
247 | INT_MASK(INT_SNI_ASID) | \ | ||
248 | INT_MASK(INT_DMA_CPL) | \ | ||
249 | INT_MASK(INT_SN_CPL) | \ | ||
250 | INT_MASK(INT_DOUBLE_FAULT) | \ | ||
251 | INT_MASK(INT_SN_STATIC_ACCESS) | \ | ||
252 | 0) | ||
253 | #define SYNC_INTERRUPTS ( \ | ||
254 | INT_MASK(INT_ITLB_MISS) | \ | ||
255 | INT_MASK(INT_ILL) | \ | ||
256 | INT_MASK(INT_GPV) | \ | ||
257 | INT_MASK(INT_SN_ACCESS) | \ | ||
258 | INT_MASK(INT_IDN_ACCESS) | \ | ||
259 | INT_MASK(INT_UDN_ACCESS) | \ | ||
260 | INT_MASK(INT_IDN_REFILL) | \ | ||
261 | INT_MASK(INT_UDN_REFILL) | \ | ||
262 | INT_MASK(INT_IDN_COMPLETE) | \ | ||
263 | INT_MASK(INT_UDN_COMPLETE) | \ | ||
264 | INT_MASK(INT_SWINT_3) | \ | ||
265 | INT_MASK(INT_SWINT_2) | \ | ||
266 | INT_MASK(INT_SWINT_1) | \ | ||
267 | INT_MASK(INT_SWINT_0) | \ | ||
268 | INT_MASK(INT_UNALIGN_DATA) | \ | ||
269 | INT_MASK(INT_DTLB_MISS) | \ | ||
270 | INT_MASK(INT_DTLB_ACCESS) | \ | ||
271 | INT_MASK(INT_SN_STATIC_ACCESS) | \ | ||
272 | 0) | ||
273 | #define NON_SYNC_INTERRUPTS ( \ | ||
274 | INT_MASK(INT_MEM_ERROR) | \ | ||
275 | INT_MASK(INT_DMATLB_MISS) | \ | ||
276 | INT_MASK(INT_DMATLB_ACCESS) | \ | ||
277 | INT_MASK(INT_SNITLB_MISS) | \ | ||
278 | INT_MASK(INT_SN_NOTIFY) | \ | ||
279 | INT_MASK(INT_SN_FIREWALL) | \ | ||
280 | INT_MASK(INT_IDN_FIREWALL) | \ | ||
281 | INT_MASK(INT_UDN_FIREWALL) | \ | ||
282 | INT_MASK(INT_TILE_TIMER) | \ | ||
283 | INT_MASK(INT_IDN_TIMER) | \ | ||
284 | INT_MASK(INT_UDN_TIMER) | \ | ||
285 | INT_MASK(INT_DMA_NOTIFY) | \ | ||
286 | INT_MASK(INT_IDN_CA) | \ | ||
287 | INT_MASK(INT_UDN_CA) | \ | ||
288 | INT_MASK(INT_IDN_AVAIL) | \ | ||
289 | INT_MASK(INT_UDN_AVAIL) | \ | ||
290 | INT_MASK(INT_PERF_COUNT) | \ | ||
291 | INT_MASK(INT_INTCTRL_3) | \ | ||
292 | INT_MASK(INT_INTCTRL_2) | \ | ||
293 | INT_MASK(INT_INTCTRL_1) | \ | ||
294 | INT_MASK(INT_INTCTRL_0) | \ | ||
295 | INT_MASK(INT_BOOT_ACCESS) | \ | ||
296 | INT_MASK(INT_WORLD_ACCESS) | \ | ||
297 | INT_MASK(INT_I_ASID) | \ | ||
298 | INT_MASK(INT_D_ASID) | \ | ||
299 | INT_MASK(INT_DMA_ASID) | \ | ||
300 | INT_MASK(INT_SNI_ASID) | \ | ||
301 | INT_MASK(INT_DMA_CPL) | \ | ||
302 | INT_MASK(INT_SN_CPL) | \ | ||
303 | INT_MASK(INT_DOUBLE_FAULT) | \ | ||
304 | INT_MASK(INT_AUX_PERF_COUNT) | \ | ||
305 | 0) | ||
306 | #endif /* !__ASSEMBLER__ */ | ||
307 | #endif /* !__ARCH_INTERRUPTS_H__ */ | ||
diff --git a/arch/tile/include/uapi/arch/interrupts_64.h b/arch/tile/include/uapi/arch/interrupts_64.h new file mode 100644 index 000000000000..5bb58b2e4e6f --- /dev/null +++ b/arch/tile/include/uapi/arch/interrupts_64.h | |||
@@ -0,0 +1,276 @@ | |||
1 | /* | ||
2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ARCH_INTERRUPTS_H__ | ||
16 | #define __ARCH_INTERRUPTS_H__ | ||
17 | |||
18 | /** Mask for an interrupt. */ | ||
19 | #ifdef __ASSEMBLER__ | ||
20 | /* Note: must handle breaking interrupts into high and low words manually. */ | ||
21 | #define INT_MASK(intno) (1 << (intno)) | ||
22 | #else | ||
23 | #define INT_MASK(intno) (1ULL << (intno)) | ||
24 | #endif | ||
25 | |||
26 | |||
27 | /** Where a given interrupt executes */ | ||
28 | #define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8)) | ||
29 | |||
30 | /** Where to store a vector for a given interrupt. */ | ||
31 | #define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0) | ||
32 | |||
33 | /** The base address of user-level interrupts. */ | ||
34 | #define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0) | ||
35 | |||
36 | |||
37 | /** Additional synthetic interrupt. */ | ||
38 | #define INT_BREAKPOINT (63) | ||
39 | |||
40 | #define INT_MEM_ERROR 0 | ||
41 | #define INT_SINGLE_STEP_3 1 | ||
42 | #define INT_SINGLE_STEP_2 2 | ||
43 | #define INT_SINGLE_STEP_1 3 | ||
44 | #define INT_SINGLE_STEP_0 4 | ||
45 | #define INT_IDN_COMPLETE 5 | ||
46 | #define INT_UDN_COMPLETE 6 | ||
47 | #define INT_ITLB_MISS 7 | ||
48 | #define INT_ILL 8 | ||
49 | #define INT_GPV 9 | ||
50 | #define INT_IDN_ACCESS 10 | ||
51 | #define INT_UDN_ACCESS 11 | ||
52 | #define INT_SWINT_3 12 | ||
53 | #define INT_SWINT_2 13 | ||
54 | #define INT_SWINT_1 14 | ||
55 | #define INT_SWINT_0 15 | ||
56 | #define INT_ILL_TRANS 16 | ||
57 | #define INT_UNALIGN_DATA 17 | ||
58 | #define INT_DTLB_MISS 18 | ||
59 | #define INT_DTLB_ACCESS 19 | ||
60 | #define INT_IDN_FIREWALL 20 | ||
61 | #define INT_UDN_FIREWALL 21 | ||
62 | #define INT_TILE_TIMER 22 | ||
63 | #define INT_AUX_TILE_TIMER 23 | ||
64 | #define INT_IDN_TIMER 24 | ||
65 | #define INT_UDN_TIMER 25 | ||
66 | #define INT_IDN_AVAIL 26 | ||
67 | #define INT_UDN_AVAIL 27 | ||
68 | #define INT_IPI_3 28 | ||
69 | #define INT_IPI_2 29 | ||
70 | #define INT_IPI_1 30 | ||
71 | #define INT_IPI_0 31 | ||
72 | #define INT_PERF_COUNT 32 | ||
73 | #define INT_AUX_PERF_COUNT 33 | ||
74 | #define INT_INTCTRL_3 34 | ||
75 | #define INT_INTCTRL_2 35 | ||
76 | #define INT_INTCTRL_1 36 | ||
77 | #define INT_INTCTRL_0 37 | ||
78 | #define INT_BOOT_ACCESS 38 | ||
79 | #define INT_WORLD_ACCESS 39 | ||
80 | #define INT_I_ASID 40 | ||
81 | #define INT_D_ASID 41 | ||
82 | #define INT_DOUBLE_FAULT 42 | ||
83 | |||
84 | #define NUM_INTERRUPTS 43 | ||
85 | |||
86 | #ifndef __ASSEMBLER__ | ||
87 | #define QUEUED_INTERRUPTS ( \ | ||
88 | INT_MASK(INT_MEM_ERROR) | \ | ||
89 | INT_MASK(INT_IDN_COMPLETE) | \ | ||
90 | INT_MASK(INT_UDN_COMPLETE) | \ | ||
91 | INT_MASK(INT_IDN_FIREWALL) | \ | ||
92 | INT_MASK(INT_UDN_FIREWALL) | \ | ||
93 | INT_MASK(INT_TILE_TIMER) | \ | ||
94 | INT_MASK(INT_AUX_TILE_TIMER) | \ | ||
95 | INT_MASK(INT_IDN_TIMER) | \ | ||
96 | INT_MASK(INT_UDN_TIMER) | \ | ||
97 | INT_MASK(INT_IDN_AVAIL) | \ | ||
98 | INT_MASK(INT_UDN_AVAIL) | \ | ||
99 | INT_MASK(INT_IPI_3) | \ | ||
100 | INT_MASK(INT_IPI_2) | \ | ||
101 | INT_MASK(INT_IPI_1) | \ | ||
102 | INT_MASK(INT_IPI_0) | \ | ||
103 | INT_MASK(INT_PERF_COUNT) | \ | ||
104 | INT_MASK(INT_AUX_PERF_COUNT) | \ | ||
105 | INT_MASK(INT_INTCTRL_3) | \ | ||
106 | INT_MASK(INT_INTCTRL_2) | \ | ||
107 | INT_MASK(INT_INTCTRL_1) | \ | ||
108 | INT_MASK(INT_INTCTRL_0) | \ | ||
109 | INT_MASK(INT_BOOT_ACCESS) | \ | ||
110 | INT_MASK(INT_WORLD_ACCESS) | \ | ||
111 | INT_MASK(INT_I_ASID) | \ | ||
112 | INT_MASK(INT_D_ASID) | \ | ||
113 | INT_MASK(INT_DOUBLE_FAULT) | \ | ||
114 | 0) | ||
115 | #define NONQUEUED_INTERRUPTS ( \ | ||
116 | INT_MASK(INT_SINGLE_STEP_3) | \ | ||
117 | INT_MASK(INT_SINGLE_STEP_2) | \ | ||
118 | INT_MASK(INT_SINGLE_STEP_1) | \ | ||
119 | INT_MASK(INT_SINGLE_STEP_0) | \ | ||
120 | INT_MASK(INT_ITLB_MISS) | \ | ||
121 | INT_MASK(INT_ILL) | \ | ||
122 | INT_MASK(INT_GPV) | \ | ||
123 | INT_MASK(INT_IDN_ACCESS) | \ | ||
124 | INT_MASK(INT_UDN_ACCESS) | \ | ||
125 | INT_MASK(INT_SWINT_3) | \ | ||
126 | INT_MASK(INT_SWINT_2) | \ | ||
127 | INT_MASK(INT_SWINT_1) | \ | ||
128 | INT_MASK(INT_SWINT_0) | \ | ||
129 | INT_MASK(INT_ILL_TRANS) | \ | ||
130 | INT_MASK(INT_UNALIGN_DATA) | \ | ||
131 | INT_MASK(INT_DTLB_MISS) | \ | ||
132 | INT_MASK(INT_DTLB_ACCESS) | \ | ||
133 | 0) | ||
134 | #define CRITICAL_MASKED_INTERRUPTS ( \ | ||
135 | INT_MASK(INT_MEM_ERROR) | \ | ||
136 | INT_MASK(INT_SINGLE_STEP_3) | \ | ||
137 | INT_MASK(INT_SINGLE_STEP_2) | \ | ||
138 | INT_MASK(INT_SINGLE_STEP_1) | \ | ||
139 | INT_MASK(INT_SINGLE_STEP_0) | \ | ||
140 | INT_MASK(INT_IDN_COMPLETE) | \ | ||
141 | INT_MASK(INT_UDN_COMPLETE) | \ | ||
142 | INT_MASK(INT_IDN_FIREWALL) | \ | ||
143 | INT_MASK(INT_UDN_FIREWALL) | \ | ||
144 | INT_MASK(INT_TILE_TIMER) | \ | ||
145 | INT_MASK(INT_AUX_TILE_TIMER) | \ | ||
146 | INT_MASK(INT_IDN_TIMER) | \ | ||
147 | INT_MASK(INT_UDN_TIMER) | \ | ||
148 | INT_MASK(INT_IDN_AVAIL) | \ | ||
149 | INT_MASK(INT_UDN_AVAIL) | \ | ||
150 | INT_MASK(INT_IPI_3) | \ | ||
151 | INT_MASK(INT_IPI_2) | \ | ||
152 | INT_MASK(INT_IPI_1) | \ | ||
153 | INT_MASK(INT_IPI_0) | \ | ||
154 | INT_MASK(INT_PERF_COUNT) | \ | ||
155 | INT_MASK(INT_AUX_PERF_COUNT) | \ | ||
156 | INT_MASK(INT_INTCTRL_3) | \ | ||
157 | INT_MASK(INT_INTCTRL_2) | \ | ||
158 | INT_MASK(INT_INTCTRL_1) | \ | ||
159 | INT_MASK(INT_INTCTRL_0) | \ | ||
160 | 0) | ||
161 | #define CRITICAL_UNMASKED_INTERRUPTS ( \ | ||
162 | INT_MASK(INT_ITLB_MISS) | \ | ||
163 | INT_MASK(INT_ILL) | \ | ||
164 | INT_MASK(INT_GPV) | \ | ||
165 | INT_MASK(INT_IDN_ACCESS) | \ | ||
166 | INT_MASK(INT_UDN_ACCESS) | \ | ||
167 | INT_MASK(INT_SWINT_3) | \ | ||
168 | INT_MASK(INT_SWINT_2) | \ | ||
169 | INT_MASK(INT_SWINT_1) | \ | ||
170 | INT_MASK(INT_SWINT_0) | \ | ||
171 | INT_MASK(INT_ILL_TRANS) | \ | ||
172 | INT_MASK(INT_UNALIGN_DATA) | \ | ||
173 | INT_MASK(INT_DTLB_MISS) | \ | ||
174 | INT_MASK(INT_DTLB_ACCESS) | \ | ||
175 | INT_MASK(INT_BOOT_ACCESS) | \ | ||
176 | INT_MASK(INT_WORLD_ACCESS) | \ | ||
177 | INT_MASK(INT_I_ASID) | \ | ||
178 | INT_MASK(INT_D_ASID) | \ | ||
179 | INT_MASK(INT_DOUBLE_FAULT) | \ | ||
180 | 0) | ||
181 | #define MASKABLE_INTERRUPTS ( \ | ||
182 | INT_MASK(INT_MEM_ERROR) | \ | ||
183 | INT_MASK(INT_SINGLE_STEP_3) | \ | ||
184 | INT_MASK(INT_SINGLE_STEP_2) | \ | ||
185 | INT_MASK(INT_SINGLE_STEP_1) | \ | ||
186 | INT_MASK(INT_SINGLE_STEP_0) | \ | ||
187 | INT_MASK(INT_IDN_COMPLETE) | \ | ||
188 | INT_MASK(INT_UDN_COMPLETE) | \ | ||
189 | INT_MASK(INT_IDN_FIREWALL) | \ | ||
190 | INT_MASK(INT_UDN_FIREWALL) | \ | ||
191 | INT_MASK(INT_TILE_TIMER) | \ | ||
192 | INT_MASK(INT_AUX_TILE_TIMER) | \ | ||
193 | INT_MASK(INT_IDN_TIMER) | \ | ||
194 | INT_MASK(INT_UDN_TIMER) | \ | ||
195 | INT_MASK(INT_IDN_AVAIL) | \ | ||
196 | INT_MASK(INT_UDN_AVAIL) | \ | ||
197 | INT_MASK(INT_IPI_3) | \ | ||
198 | INT_MASK(INT_IPI_2) | \ | ||
199 | INT_MASK(INT_IPI_1) | \ | ||
200 | INT_MASK(INT_IPI_0) | \ | ||
201 | INT_MASK(INT_PERF_COUNT) | \ | ||
202 | INT_MASK(INT_AUX_PERF_COUNT) | \ | ||
203 | INT_MASK(INT_INTCTRL_3) | \ | ||
204 | INT_MASK(INT_INTCTRL_2) | \ | ||
205 | INT_MASK(INT_INTCTRL_1) | \ | ||
206 | INT_MASK(INT_INTCTRL_0) | \ | ||
207 | 0) | ||
208 | #define UNMASKABLE_INTERRUPTS ( \ | ||
209 | INT_MASK(INT_ITLB_MISS) | \ | ||
210 | INT_MASK(INT_ILL) | \ | ||
211 | INT_MASK(INT_GPV) | \ | ||
212 | INT_MASK(INT_IDN_ACCESS) | \ | ||
213 | INT_MASK(INT_UDN_ACCESS) | \ | ||
214 | INT_MASK(INT_SWINT_3) | \ | ||
215 | INT_MASK(INT_SWINT_2) | \ | ||
216 | INT_MASK(INT_SWINT_1) | \ | ||
217 | INT_MASK(INT_SWINT_0) | \ | ||
218 | INT_MASK(INT_ILL_TRANS) | \ | ||
219 | INT_MASK(INT_UNALIGN_DATA) | \ | ||
220 | INT_MASK(INT_DTLB_MISS) | \ | ||
221 | INT_MASK(INT_DTLB_ACCESS) | \ | ||
222 | INT_MASK(INT_BOOT_ACCESS) | \ | ||
223 | INT_MASK(INT_WORLD_ACCESS) | \ | ||
224 | INT_MASK(INT_I_ASID) | \ | ||
225 | INT_MASK(INT_D_ASID) | \ | ||
226 | INT_MASK(INT_DOUBLE_FAULT) | \ | ||
227 | 0) | ||
228 | #define SYNC_INTERRUPTS ( \ | ||
229 | INT_MASK(INT_SINGLE_STEP_3) | \ | ||
230 | INT_MASK(INT_SINGLE_STEP_2) | \ | ||
231 | INT_MASK(INT_SINGLE_STEP_1) | \ | ||
232 | INT_MASK(INT_SINGLE_STEP_0) | \ | ||
233 | INT_MASK(INT_IDN_COMPLETE) | \ | ||
234 | INT_MASK(INT_UDN_COMPLETE) | \ | ||
235 | INT_MASK(INT_ITLB_MISS) | \ | ||
236 | INT_MASK(INT_ILL) | \ | ||
237 | INT_MASK(INT_GPV) | \ | ||
238 | INT_MASK(INT_IDN_ACCESS) | \ | ||
239 | INT_MASK(INT_UDN_ACCESS) | \ | ||
240 | INT_MASK(INT_SWINT_3) | \ | ||
241 | INT_MASK(INT_SWINT_2) | \ | ||
242 | INT_MASK(INT_SWINT_1) | \ | ||
243 | INT_MASK(INT_SWINT_0) | \ | ||
244 | INT_MASK(INT_ILL_TRANS) | \ | ||
245 | INT_MASK(INT_UNALIGN_DATA) | \ | ||
246 | INT_MASK(INT_DTLB_MISS) | \ | ||
247 | INT_MASK(INT_DTLB_ACCESS) | \ | ||
248 | 0) | ||
249 | #define NON_SYNC_INTERRUPTS ( \ | ||
250 | INT_MASK(INT_MEM_ERROR) | \ | ||
251 | INT_MASK(INT_IDN_FIREWALL) | \ | ||
252 | INT_MASK(INT_UDN_FIREWALL) | \ | ||
253 | INT_MASK(INT_TILE_TIMER) | \ | ||
254 | INT_MASK(INT_AUX_TILE_TIMER) | \ | ||
255 | INT_MASK(INT_IDN_TIMER) | \ | ||
256 | INT_MASK(INT_UDN_TIMER) | \ | ||
257 | INT_MASK(INT_IDN_AVAIL) | \ | ||
258 | INT_MASK(INT_UDN_AVAIL) | \ | ||
259 | INT_MASK(INT_IPI_3) | \ | ||
260 | INT_MASK(INT_IPI_2) | \ | ||
261 | INT_MASK(INT_IPI_1) | \ | ||
262 | INT_MASK(INT_IPI_0) | \ | ||
263 | INT_MASK(INT_PERF_COUNT) | \ | ||
264 | INT_MASK(INT_AUX_PERF_COUNT) | \ | ||
265 | INT_MASK(INT_INTCTRL_3) | \ | ||
266 | INT_MASK(INT_INTCTRL_2) | \ | ||
267 | INT_MASK(INT_INTCTRL_1) | \ | ||
268 | INT_MASK(INT_INTCTRL_0) | \ | ||
269 | INT_MASK(INT_BOOT_ACCESS) | \ | ||
270 | INT_MASK(INT_WORLD_ACCESS) | \ | ||
271 | INT_MASK(INT_I_ASID) | \ | ||
272 | INT_MASK(INT_D_ASID) | \ | ||
273 | INT_MASK(INT_DOUBLE_FAULT) | \ | ||
274 | 0) | ||
275 | #endif /* !__ASSEMBLER__ */ | ||
276 | #endif /* !__ARCH_INTERRUPTS_H__ */ | ||
diff --git a/arch/tile/include/uapi/arch/opcode.h b/arch/tile/include/uapi/arch/opcode.h new file mode 100644 index 000000000000..92d15229ecec --- /dev/null +++ b/arch/tile/include/uapi/arch/opcode.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | #if defined(__tilepro__) | ||
16 | #include <arch/opcode_tilepro.h> | ||
17 | #elif defined(__tilegx__) | ||
18 | #include <arch/opcode_tilegx.h> | ||
19 | #else | ||
20 | #error Unexpected Tilera chip type | ||
21 | #endif | ||
diff --git a/arch/tile/include/uapi/arch/opcode_tilegx.h b/arch/tile/include/uapi/arch/opcode_tilegx.h new file mode 100644 index 000000000000..c14d02c81600 --- /dev/null +++ b/arch/tile/include/uapi/arch/opcode_tilegx.h | |||
@@ -0,0 +1,1405 @@ | |||
1 | /* TILE-Gx opcode information. | ||
2 | * | ||
3 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * as published by the Free Software Foundation, version 2. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, but | ||
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
12 | * NON INFRINGEMENT. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * | ||
16 | * | ||
17 | * | ||
18 | * | ||
19 | */ | ||
20 | |||
21 | #ifndef __ARCH_OPCODE_H__ | ||
22 | #define __ARCH_OPCODE_H__ | ||
23 | |||
24 | #ifndef __ASSEMBLER__ | ||
25 | |||
26 | typedef unsigned long long tilegx_bundle_bits; | ||
27 | |||
28 | /* These are the bits that determine if a bundle is in the X encoding. */ | ||
29 | #define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62) | ||
30 | |||
31 | enum | ||
32 | { | ||
33 | /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ | ||
34 | TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3, | ||
35 | |||
36 | /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ | ||
37 | TILEGX_NUM_PIPELINE_ENCODINGS = 5, | ||
38 | |||
39 | /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */ | ||
40 | TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3, | ||
41 | |||
42 | /* Instructions take this many bytes. */ | ||
43 | TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES, | ||
44 | |||
45 | /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */ | ||
46 | TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, | ||
47 | |||
48 | /* Bundles should be aligned modulo this number of bytes. */ | ||
49 | TILEGX_BUNDLE_ALIGNMENT_IN_BYTES = | ||
50 | (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), | ||
51 | |||
52 | /* Number of registers (some are magic, such as network I/O). */ | ||
53 | TILEGX_NUM_REGISTERS = 64, | ||
54 | }; | ||
55 | |||
56 | /* Make a few "tile_" variables to simplify common code between | ||
57 | architectures. */ | ||
58 | |||
59 | typedef tilegx_bundle_bits tile_bundle_bits; | ||
60 | #define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES | ||
61 | #define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES | ||
62 | #define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \ | ||
63 | TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES | ||
64 | |||
65 | /* 64-bit pattern for a { bpt ; nop } bundle. */ | ||
66 | #define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL | ||
67 | |||
68 | static __inline unsigned int | ||
69 | get_BFEnd_X0(tilegx_bundle_bits num) | ||
70 | { | ||
71 | const unsigned int n = (unsigned int)num; | ||
72 | return (((n >> 12)) & 0x3f); | ||
73 | } | ||
74 | |||
75 | static __inline unsigned int | ||
76 | get_BFOpcodeExtension_X0(tilegx_bundle_bits num) | ||
77 | { | ||
78 | const unsigned int n = (unsigned int)num; | ||
79 | return (((n >> 24)) & 0xf); | ||
80 | } | ||
81 | |||
82 | static __inline unsigned int | ||
83 | get_BFStart_X0(tilegx_bundle_bits num) | ||
84 | { | ||
85 | const unsigned int n = (unsigned int)num; | ||
86 | return (((n >> 18)) & 0x3f); | ||
87 | } | ||
88 | |||
89 | static __inline unsigned int | ||
90 | get_BrOff_X1(tilegx_bundle_bits n) | ||
91 | { | ||
92 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
93 | (((unsigned int)(n >> 37)) & 0x0001ffc0); | ||
94 | } | ||
95 | |||
96 | static __inline unsigned int | ||
97 | get_BrType_X1(tilegx_bundle_bits n) | ||
98 | { | ||
99 | return (((unsigned int)(n >> 54)) & 0x1f); | ||
100 | } | ||
101 | |||
102 | static __inline unsigned int | ||
103 | get_Dest_Imm8_X1(tilegx_bundle_bits n) | ||
104 | { | ||
105 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
106 | (((unsigned int)(n >> 43)) & 0x000000c0); | ||
107 | } | ||
108 | |||
109 | static __inline unsigned int | ||
110 | get_Dest_X0(tilegx_bundle_bits num) | ||
111 | { | ||
112 | const unsigned int n = (unsigned int)num; | ||
113 | return (((n >> 0)) & 0x3f); | ||
114 | } | ||
115 | |||
116 | static __inline unsigned int | ||
117 | get_Dest_X1(tilegx_bundle_bits n) | ||
118 | { | ||
119 | return (((unsigned int)(n >> 31)) & 0x3f); | ||
120 | } | ||
121 | |||
122 | static __inline unsigned int | ||
123 | get_Dest_Y0(tilegx_bundle_bits num) | ||
124 | { | ||
125 | const unsigned int n = (unsigned int)num; | ||
126 | return (((n >> 0)) & 0x3f); | ||
127 | } | ||
128 | |||
129 | static __inline unsigned int | ||
130 | get_Dest_Y1(tilegx_bundle_bits n) | ||
131 | { | ||
132 | return (((unsigned int)(n >> 31)) & 0x3f); | ||
133 | } | ||
134 | |||
135 | static __inline unsigned int | ||
136 | get_Imm16_X0(tilegx_bundle_bits num) | ||
137 | { | ||
138 | const unsigned int n = (unsigned int)num; | ||
139 | return (((n >> 12)) & 0xffff); | ||
140 | } | ||
141 | |||
142 | static __inline unsigned int | ||
143 | get_Imm16_X1(tilegx_bundle_bits n) | ||
144 | { | ||
145 | return (((unsigned int)(n >> 43)) & 0xffff); | ||
146 | } | ||
147 | |||
148 | static __inline unsigned int | ||
149 | get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num) | ||
150 | { | ||
151 | const unsigned int n = (unsigned int)num; | ||
152 | return (((n >> 20)) & 0xff); | ||
153 | } | ||
154 | |||
155 | static __inline unsigned int | ||
156 | get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n) | ||
157 | { | ||
158 | return (((unsigned int)(n >> 51)) & 0xff); | ||
159 | } | ||
160 | |||
161 | static __inline unsigned int | ||
162 | get_Imm8_X0(tilegx_bundle_bits num) | ||
163 | { | ||
164 | const unsigned int n = (unsigned int)num; | ||
165 | return (((n >> 12)) & 0xff); | ||
166 | } | ||
167 | |||
168 | static __inline unsigned int | ||
169 | get_Imm8_X1(tilegx_bundle_bits n) | ||
170 | { | ||
171 | return (((unsigned int)(n >> 43)) & 0xff); | ||
172 | } | ||
173 | |||
174 | static __inline unsigned int | ||
175 | get_Imm8_Y0(tilegx_bundle_bits num) | ||
176 | { | ||
177 | const unsigned int n = (unsigned int)num; | ||
178 | return (((n >> 12)) & 0xff); | ||
179 | } | ||
180 | |||
181 | static __inline unsigned int | ||
182 | get_Imm8_Y1(tilegx_bundle_bits n) | ||
183 | { | ||
184 | return (((unsigned int)(n >> 43)) & 0xff); | ||
185 | } | ||
186 | |||
187 | static __inline unsigned int | ||
188 | get_JumpOff_X1(tilegx_bundle_bits n) | ||
189 | { | ||
190 | return (((unsigned int)(n >> 31)) & 0x7ffffff); | ||
191 | } | ||
192 | |||
193 | static __inline unsigned int | ||
194 | get_JumpOpcodeExtension_X1(tilegx_bundle_bits n) | ||
195 | { | ||
196 | return (((unsigned int)(n >> 58)) & 0x1); | ||
197 | } | ||
198 | |||
199 | static __inline unsigned int | ||
200 | get_MF_Imm14_X1(tilegx_bundle_bits n) | ||
201 | { | ||
202 | return (((unsigned int)(n >> 37)) & 0x3fff); | ||
203 | } | ||
204 | |||
205 | static __inline unsigned int | ||
206 | get_MT_Imm14_X1(tilegx_bundle_bits n) | ||
207 | { | ||
208 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
209 | (((unsigned int)(n >> 37)) & 0x00003fc0); | ||
210 | } | ||
211 | |||
212 | static __inline unsigned int | ||
213 | get_Mode(tilegx_bundle_bits n) | ||
214 | { | ||
215 | return (((unsigned int)(n >> 62)) & 0x3); | ||
216 | } | ||
217 | |||
218 | static __inline unsigned int | ||
219 | get_Opcode_X0(tilegx_bundle_bits num) | ||
220 | { | ||
221 | const unsigned int n = (unsigned int)num; | ||
222 | return (((n >> 28)) & 0x7); | ||
223 | } | ||
224 | |||
225 | static __inline unsigned int | ||
226 | get_Opcode_X1(tilegx_bundle_bits n) | ||
227 | { | ||
228 | return (((unsigned int)(n >> 59)) & 0x7); | ||
229 | } | ||
230 | |||
231 | static __inline unsigned int | ||
232 | get_Opcode_Y0(tilegx_bundle_bits num) | ||
233 | { | ||
234 | const unsigned int n = (unsigned int)num; | ||
235 | return (((n >> 27)) & 0xf); | ||
236 | } | ||
237 | |||
238 | static __inline unsigned int | ||
239 | get_Opcode_Y1(tilegx_bundle_bits n) | ||
240 | { | ||
241 | return (((unsigned int)(n >> 58)) & 0xf); | ||
242 | } | ||
243 | |||
244 | static __inline unsigned int | ||
245 | get_Opcode_Y2(tilegx_bundle_bits n) | ||
246 | { | ||
247 | return (((n >> 26)) & 0x00000001) | | ||
248 | (((unsigned int)(n >> 56)) & 0x00000002); | ||
249 | } | ||
250 | |||
251 | static __inline unsigned int | ||
252 | get_RRROpcodeExtension_X0(tilegx_bundle_bits num) | ||
253 | { | ||
254 | const unsigned int n = (unsigned int)num; | ||
255 | return (((n >> 18)) & 0x3ff); | ||
256 | } | ||
257 | |||
258 | static __inline unsigned int | ||
259 | get_RRROpcodeExtension_X1(tilegx_bundle_bits n) | ||
260 | { | ||
261 | return (((unsigned int)(n >> 49)) & 0x3ff); | ||
262 | } | ||
263 | |||
264 | static __inline unsigned int | ||
265 | get_RRROpcodeExtension_Y0(tilegx_bundle_bits num) | ||
266 | { | ||
267 | const unsigned int n = (unsigned int)num; | ||
268 | return (((n >> 18)) & 0x3); | ||
269 | } | ||
270 | |||
271 | static __inline unsigned int | ||
272 | get_RRROpcodeExtension_Y1(tilegx_bundle_bits n) | ||
273 | { | ||
274 | return (((unsigned int)(n >> 49)) & 0x3); | ||
275 | } | ||
276 | |||
277 | static __inline unsigned int | ||
278 | get_ShAmt_X0(tilegx_bundle_bits num) | ||
279 | { | ||
280 | const unsigned int n = (unsigned int)num; | ||
281 | return (((n >> 12)) & 0x3f); | ||
282 | } | ||
283 | |||
284 | static __inline unsigned int | ||
285 | get_ShAmt_X1(tilegx_bundle_bits n) | ||
286 | { | ||
287 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
288 | } | ||
289 | |||
290 | static __inline unsigned int | ||
291 | get_ShAmt_Y0(tilegx_bundle_bits num) | ||
292 | { | ||
293 | const unsigned int n = (unsigned int)num; | ||
294 | return (((n >> 12)) & 0x3f); | ||
295 | } | ||
296 | |||
297 | static __inline unsigned int | ||
298 | get_ShAmt_Y1(tilegx_bundle_bits n) | ||
299 | { | ||
300 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
301 | } | ||
302 | |||
303 | static __inline unsigned int | ||
304 | get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num) | ||
305 | { | ||
306 | const unsigned int n = (unsigned int)num; | ||
307 | return (((n >> 18)) & 0x3ff); | ||
308 | } | ||
309 | |||
310 | static __inline unsigned int | ||
311 | get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n) | ||
312 | { | ||
313 | return (((unsigned int)(n >> 49)) & 0x3ff); | ||
314 | } | ||
315 | |||
316 | static __inline unsigned int | ||
317 | get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num) | ||
318 | { | ||
319 | const unsigned int n = (unsigned int)num; | ||
320 | return (((n >> 18)) & 0x3); | ||
321 | } | ||
322 | |||
323 | static __inline unsigned int | ||
324 | get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n) | ||
325 | { | ||
326 | return (((unsigned int)(n >> 49)) & 0x3); | ||
327 | } | ||
328 | |||
329 | static __inline unsigned int | ||
330 | get_SrcA_X0(tilegx_bundle_bits num) | ||
331 | { | ||
332 | const unsigned int n = (unsigned int)num; | ||
333 | return (((n >> 6)) & 0x3f); | ||
334 | } | ||
335 | |||
336 | static __inline unsigned int | ||
337 | get_SrcA_X1(tilegx_bundle_bits n) | ||
338 | { | ||
339 | return (((unsigned int)(n >> 37)) & 0x3f); | ||
340 | } | ||
341 | |||
342 | static __inline unsigned int | ||
343 | get_SrcA_Y0(tilegx_bundle_bits num) | ||
344 | { | ||
345 | const unsigned int n = (unsigned int)num; | ||
346 | return (((n >> 6)) & 0x3f); | ||
347 | } | ||
348 | |||
349 | static __inline unsigned int | ||
350 | get_SrcA_Y1(tilegx_bundle_bits n) | ||
351 | { | ||
352 | return (((unsigned int)(n >> 37)) & 0x3f); | ||
353 | } | ||
354 | |||
355 | static __inline unsigned int | ||
356 | get_SrcA_Y2(tilegx_bundle_bits num) | ||
357 | { | ||
358 | const unsigned int n = (unsigned int)num; | ||
359 | return (((n >> 20)) & 0x3f); | ||
360 | } | ||
361 | |||
362 | static __inline unsigned int | ||
363 | get_SrcBDest_Y2(tilegx_bundle_bits n) | ||
364 | { | ||
365 | return (((unsigned int)(n >> 51)) & 0x3f); | ||
366 | } | ||
367 | |||
368 | static __inline unsigned int | ||
369 | get_SrcB_X0(tilegx_bundle_bits num) | ||
370 | { | ||
371 | const unsigned int n = (unsigned int)num; | ||
372 | return (((n >> 12)) & 0x3f); | ||
373 | } | ||
374 | |||
375 | static __inline unsigned int | ||
376 | get_SrcB_X1(tilegx_bundle_bits n) | ||
377 | { | ||
378 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
379 | } | ||
380 | |||
381 | static __inline unsigned int | ||
382 | get_SrcB_Y0(tilegx_bundle_bits num) | ||
383 | { | ||
384 | const unsigned int n = (unsigned int)num; | ||
385 | return (((n >> 12)) & 0x3f); | ||
386 | } | ||
387 | |||
388 | static __inline unsigned int | ||
389 | get_SrcB_Y1(tilegx_bundle_bits n) | ||
390 | { | ||
391 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
392 | } | ||
393 | |||
394 | static __inline unsigned int | ||
395 | get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num) | ||
396 | { | ||
397 | const unsigned int n = (unsigned int)num; | ||
398 | return (((n >> 12)) & 0x3f); | ||
399 | } | ||
400 | |||
401 | static __inline unsigned int | ||
402 | get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n) | ||
403 | { | ||
404 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
405 | } | ||
406 | |||
407 | static __inline unsigned int | ||
408 | get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num) | ||
409 | { | ||
410 | const unsigned int n = (unsigned int)num; | ||
411 | return (((n >> 12)) & 0x3f); | ||
412 | } | ||
413 | |||
414 | static __inline unsigned int | ||
415 | get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n) | ||
416 | { | ||
417 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
418 | } | ||
419 | |||
420 | |||
421 | static __inline int | ||
422 | sign_extend(int n, int num_bits) | ||
423 | { | ||
424 | int shift = (int)(sizeof(int) * 8 - num_bits); | ||
425 | return (n << shift) >> shift; | ||
426 | } | ||
427 | |||
428 | |||
429 | |||
430 | static __inline tilegx_bundle_bits | ||
431 | create_BFEnd_X0(int num) | ||
432 | { | ||
433 | const unsigned int n = (unsigned int)num; | ||
434 | return ((n & 0x3f) << 12); | ||
435 | } | ||
436 | |||
437 | static __inline tilegx_bundle_bits | ||
438 | create_BFOpcodeExtension_X0(int num) | ||
439 | { | ||
440 | const unsigned int n = (unsigned int)num; | ||
441 | return ((n & 0xf) << 24); | ||
442 | } | ||
443 | |||
444 | static __inline tilegx_bundle_bits | ||
445 | create_BFStart_X0(int num) | ||
446 | { | ||
447 | const unsigned int n = (unsigned int)num; | ||
448 | return ((n & 0x3f) << 18); | ||
449 | } | ||
450 | |||
451 | static __inline tilegx_bundle_bits | ||
452 | create_BrOff_X1(int num) | ||
453 | { | ||
454 | const unsigned int n = (unsigned int)num; | ||
455 | return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | | ||
456 | (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37); | ||
457 | } | ||
458 | |||
459 | static __inline tilegx_bundle_bits | ||
460 | create_BrType_X1(int num) | ||
461 | { | ||
462 | const unsigned int n = (unsigned int)num; | ||
463 | return (((tilegx_bundle_bits)(n & 0x1f)) << 54); | ||
464 | } | ||
465 | |||
466 | static __inline tilegx_bundle_bits | ||
467 | create_Dest_Imm8_X1(int num) | ||
468 | { | ||
469 | const unsigned int n = (unsigned int)num; | ||
470 | return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | | ||
471 | (((tilegx_bundle_bits)(n & 0x000000c0)) << 43); | ||
472 | } | ||
473 | |||
474 | static __inline tilegx_bundle_bits | ||
475 | create_Dest_X0(int num) | ||
476 | { | ||
477 | const unsigned int n = (unsigned int)num; | ||
478 | return ((n & 0x3f) << 0); | ||
479 | } | ||
480 | |||
481 | static __inline tilegx_bundle_bits | ||
482 | create_Dest_X1(int num) | ||
483 | { | ||
484 | const unsigned int n = (unsigned int)num; | ||
485 | return (((tilegx_bundle_bits)(n & 0x3f)) << 31); | ||
486 | } | ||
487 | |||
488 | static __inline tilegx_bundle_bits | ||
489 | create_Dest_Y0(int num) | ||
490 | { | ||
491 | const unsigned int n = (unsigned int)num; | ||
492 | return ((n & 0x3f) << 0); | ||
493 | } | ||
494 | |||
495 | static __inline tilegx_bundle_bits | ||
496 | create_Dest_Y1(int num) | ||
497 | { | ||
498 | const unsigned int n = (unsigned int)num; | ||
499 | return (((tilegx_bundle_bits)(n & 0x3f)) << 31); | ||
500 | } | ||
501 | |||
502 | static __inline tilegx_bundle_bits | ||
503 | create_Imm16_X0(int num) | ||
504 | { | ||
505 | const unsigned int n = (unsigned int)num; | ||
506 | return ((n & 0xffff) << 12); | ||
507 | } | ||
508 | |||
509 | static __inline tilegx_bundle_bits | ||
510 | create_Imm16_X1(int num) | ||
511 | { | ||
512 | const unsigned int n = (unsigned int)num; | ||
513 | return (((tilegx_bundle_bits)(n & 0xffff)) << 43); | ||
514 | } | ||
515 | |||
516 | static __inline tilegx_bundle_bits | ||
517 | create_Imm8OpcodeExtension_X0(int num) | ||
518 | { | ||
519 | const unsigned int n = (unsigned int)num; | ||
520 | return ((n & 0xff) << 20); | ||
521 | } | ||
522 | |||
523 | static __inline tilegx_bundle_bits | ||
524 | create_Imm8OpcodeExtension_X1(int num) | ||
525 | { | ||
526 | const unsigned int n = (unsigned int)num; | ||
527 | return (((tilegx_bundle_bits)(n & 0xff)) << 51); | ||
528 | } | ||
529 | |||
530 | static __inline tilegx_bundle_bits | ||
531 | create_Imm8_X0(int num) | ||
532 | { | ||
533 | const unsigned int n = (unsigned int)num; | ||
534 | return ((n & 0xff) << 12); | ||
535 | } | ||
536 | |||
537 | static __inline tilegx_bundle_bits | ||
538 | create_Imm8_X1(int num) | ||
539 | { | ||
540 | const unsigned int n = (unsigned int)num; | ||
541 | return (((tilegx_bundle_bits)(n & 0xff)) << 43); | ||
542 | } | ||
543 | |||
544 | static __inline tilegx_bundle_bits | ||
545 | create_Imm8_Y0(int num) | ||
546 | { | ||
547 | const unsigned int n = (unsigned int)num; | ||
548 | return ((n & 0xff) << 12); | ||
549 | } | ||
550 | |||
551 | static __inline tilegx_bundle_bits | ||
552 | create_Imm8_Y1(int num) | ||
553 | { | ||
554 | const unsigned int n = (unsigned int)num; | ||
555 | return (((tilegx_bundle_bits)(n & 0xff)) << 43); | ||
556 | } | ||
557 | |||
558 | static __inline tilegx_bundle_bits | ||
559 | create_JumpOff_X1(int num) | ||
560 | { | ||
561 | const unsigned int n = (unsigned int)num; | ||
562 | return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31); | ||
563 | } | ||
564 | |||
565 | static __inline tilegx_bundle_bits | ||
566 | create_JumpOpcodeExtension_X1(int num) | ||
567 | { | ||
568 | const unsigned int n = (unsigned int)num; | ||
569 | return (((tilegx_bundle_bits)(n & 0x1)) << 58); | ||
570 | } | ||
571 | |||
572 | static __inline tilegx_bundle_bits | ||
573 | create_MF_Imm14_X1(int num) | ||
574 | { | ||
575 | const unsigned int n = (unsigned int)num; | ||
576 | return (((tilegx_bundle_bits)(n & 0x3fff)) << 37); | ||
577 | } | ||
578 | |||
579 | static __inline tilegx_bundle_bits | ||
580 | create_MT_Imm14_X1(int num) | ||
581 | { | ||
582 | const unsigned int n = (unsigned int)num; | ||
583 | return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | | ||
584 | (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37); | ||
585 | } | ||
586 | |||
587 | static __inline tilegx_bundle_bits | ||
588 | create_Mode(int num) | ||
589 | { | ||
590 | const unsigned int n = (unsigned int)num; | ||
591 | return (((tilegx_bundle_bits)(n & 0x3)) << 62); | ||
592 | } | ||
593 | |||
594 | static __inline tilegx_bundle_bits | ||
595 | create_Opcode_X0(int num) | ||
596 | { | ||
597 | const unsigned int n = (unsigned int)num; | ||
598 | return ((n & 0x7) << 28); | ||
599 | } | ||
600 | |||
601 | static __inline tilegx_bundle_bits | ||
602 | create_Opcode_X1(int num) | ||
603 | { | ||
604 | const unsigned int n = (unsigned int)num; | ||
605 | return (((tilegx_bundle_bits)(n & 0x7)) << 59); | ||
606 | } | ||
607 | |||
608 | static __inline tilegx_bundle_bits | ||
609 | create_Opcode_Y0(int num) | ||
610 | { | ||
611 | const unsigned int n = (unsigned int)num; | ||
612 | return ((n & 0xf) << 27); | ||
613 | } | ||
614 | |||
615 | static __inline tilegx_bundle_bits | ||
616 | create_Opcode_Y1(int num) | ||
617 | { | ||
618 | const unsigned int n = (unsigned int)num; | ||
619 | return (((tilegx_bundle_bits)(n & 0xf)) << 58); | ||
620 | } | ||
621 | |||
622 | static __inline tilegx_bundle_bits | ||
623 | create_Opcode_Y2(int num) | ||
624 | { | ||
625 | const unsigned int n = (unsigned int)num; | ||
626 | return ((n & 0x00000001) << 26) | | ||
627 | (((tilegx_bundle_bits)(n & 0x00000002)) << 56); | ||
628 | } | ||
629 | |||
630 | static __inline tilegx_bundle_bits | ||
631 | create_RRROpcodeExtension_X0(int num) | ||
632 | { | ||
633 | const unsigned int n = (unsigned int)num; | ||
634 | return ((n & 0x3ff) << 18); | ||
635 | } | ||
636 | |||
637 | static __inline tilegx_bundle_bits | ||
638 | create_RRROpcodeExtension_X1(int num) | ||
639 | { | ||
640 | const unsigned int n = (unsigned int)num; | ||
641 | return (((tilegx_bundle_bits)(n & 0x3ff)) << 49); | ||
642 | } | ||
643 | |||
644 | static __inline tilegx_bundle_bits | ||
645 | create_RRROpcodeExtension_Y0(int num) | ||
646 | { | ||
647 | const unsigned int n = (unsigned int)num; | ||
648 | return ((n & 0x3) << 18); | ||
649 | } | ||
650 | |||
651 | static __inline tilegx_bundle_bits | ||
652 | create_RRROpcodeExtension_Y1(int num) | ||
653 | { | ||
654 | const unsigned int n = (unsigned int)num; | ||
655 | return (((tilegx_bundle_bits)(n & 0x3)) << 49); | ||
656 | } | ||
657 | |||
658 | static __inline tilegx_bundle_bits | ||
659 | create_ShAmt_X0(int num) | ||
660 | { | ||
661 | const unsigned int n = (unsigned int)num; | ||
662 | return ((n & 0x3f) << 12); | ||
663 | } | ||
664 | |||
665 | static __inline tilegx_bundle_bits | ||
666 | create_ShAmt_X1(int num) | ||
667 | { | ||
668 | const unsigned int n = (unsigned int)num; | ||
669 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
670 | } | ||
671 | |||
672 | static __inline tilegx_bundle_bits | ||
673 | create_ShAmt_Y0(int num) | ||
674 | { | ||
675 | const unsigned int n = (unsigned int)num; | ||
676 | return ((n & 0x3f) << 12); | ||
677 | } | ||
678 | |||
679 | static __inline tilegx_bundle_bits | ||
680 | create_ShAmt_Y1(int num) | ||
681 | { | ||
682 | const unsigned int n = (unsigned int)num; | ||
683 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
684 | } | ||
685 | |||
686 | static __inline tilegx_bundle_bits | ||
687 | create_ShiftOpcodeExtension_X0(int num) | ||
688 | { | ||
689 | const unsigned int n = (unsigned int)num; | ||
690 | return ((n & 0x3ff) << 18); | ||
691 | } | ||
692 | |||
693 | static __inline tilegx_bundle_bits | ||
694 | create_ShiftOpcodeExtension_X1(int num) | ||
695 | { | ||
696 | const unsigned int n = (unsigned int)num; | ||
697 | return (((tilegx_bundle_bits)(n & 0x3ff)) << 49); | ||
698 | } | ||
699 | |||
700 | static __inline tilegx_bundle_bits | ||
701 | create_ShiftOpcodeExtension_Y0(int num) | ||
702 | { | ||
703 | const unsigned int n = (unsigned int)num; | ||
704 | return ((n & 0x3) << 18); | ||
705 | } | ||
706 | |||
707 | static __inline tilegx_bundle_bits | ||
708 | create_ShiftOpcodeExtension_Y1(int num) | ||
709 | { | ||
710 | const unsigned int n = (unsigned int)num; | ||
711 | return (((tilegx_bundle_bits)(n & 0x3)) << 49); | ||
712 | } | ||
713 | |||
714 | static __inline tilegx_bundle_bits | ||
715 | create_SrcA_X0(int num) | ||
716 | { | ||
717 | const unsigned int n = (unsigned int)num; | ||
718 | return ((n & 0x3f) << 6); | ||
719 | } | ||
720 | |||
721 | static __inline tilegx_bundle_bits | ||
722 | create_SrcA_X1(int num) | ||
723 | { | ||
724 | const unsigned int n = (unsigned int)num; | ||
725 | return (((tilegx_bundle_bits)(n & 0x3f)) << 37); | ||
726 | } | ||
727 | |||
728 | static __inline tilegx_bundle_bits | ||
729 | create_SrcA_Y0(int num) | ||
730 | { | ||
731 | const unsigned int n = (unsigned int)num; | ||
732 | return ((n & 0x3f) << 6); | ||
733 | } | ||
734 | |||
735 | static __inline tilegx_bundle_bits | ||
736 | create_SrcA_Y1(int num) | ||
737 | { | ||
738 | const unsigned int n = (unsigned int)num; | ||
739 | return (((tilegx_bundle_bits)(n & 0x3f)) << 37); | ||
740 | } | ||
741 | |||
742 | static __inline tilegx_bundle_bits | ||
743 | create_SrcA_Y2(int num) | ||
744 | { | ||
745 | const unsigned int n = (unsigned int)num; | ||
746 | return ((n & 0x3f) << 20); | ||
747 | } | ||
748 | |||
749 | static __inline tilegx_bundle_bits | ||
750 | create_SrcBDest_Y2(int num) | ||
751 | { | ||
752 | const unsigned int n = (unsigned int)num; | ||
753 | return (((tilegx_bundle_bits)(n & 0x3f)) << 51); | ||
754 | } | ||
755 | |||
756 | static __inline tilegx_bundle_bits | ||
757 | create_SrcB_X0(int num) | ||
758 | { | ||
759 | const unsigned int n = (unsigned int)num; | ||
760 | return ((n & 0x3f) << 12); | ||
761 | } | ||
762 | |||
763 | static __inline tilegx_bundle_bits | ||
764 | create_SrcB_X1(int num) | ||
765 | { | ||
766 | const unsigned int n = (unsigned int)num; | ||
767 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
768 | } | ||
769 | |||
770 | static __inline tilegx_bundle_bits | ||
771 | create_SrcB_Y0(int num) | ||
772 | { | ||
773 | const unsigned int n = (unsigned int)num; | ||
774 | return ((n & 0x3f) << 12); | ||
775 | } | ||
776 | |||
777 | static __inline tilegx_bundle_bits | ||
778 | create_SrcB_Y1(int num) | ||
779 | { | ||
780 | const unsigned int n = (unsigned int)num; | ||
781 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
782 | } | ||
783 | |||
784 | static __inline tilegx_bundle_bits | ||
785 | create_UnaryOpcodeExtension_X0(int num) | ||
786 | { | ||
787 | const unsigned int n = (unsigned int)num; | ||
788 | return ((n & 0x3f) << 12); | ||
789 | } | ||
790 | |||
791 | static __inline tilegx_bundle_bits | ||
792 | create_UnaryOpcodeExtension_X1(int num) | ||
793 | { | ||
794 | const unsigned int n = (unsigned int)num; | ||
795 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
796 | } | ||
797 | |||
798 | static __inline tilegx_bundle_bits | ||
799 | create_UnaryOpcodeExtension_Y0(int num) | ||
800 | { | ||
801 | const unsigned int n = (unsigned int)num; | ||
802 | return ((n & 0x3f) << 12); | ||
803 | } | ||
804 | |||
805 | static __inline tilegx_bundle_bits | ||
806 | create_UnaryOpcodeExtension_Y1(int num) | ||
807 | { | ||
808 | const unsigned int n = (unsigned int)num; | ||
809 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
810 | } | ||
811 | |||
812 | |||
813 | enum | ||
814 | { | ||
815 | ADDI_IMM8_OPCODE_X0 = 1, | ||
816 | ADDI_IMM8_OPCODE_X1 = 1, | ||
817 | ADDI_OPCODE_Y0 = 0, | ||
818 | ADDI_OPCODE_Y1 = 1, | ||
819 | ADDLI_OPCODE_X0 = 1, | ||
820 | ADDLI_OPCODE_X1 = 0, | ||
821 | ADDXI_IMM8_OPCODE_X0 = 2, | ||
822 | ADDXI_IMM8_OPCODE_X1 = 2, | ||
823 | ADDXI_OPCODE_Y0 = 1, | ||
824 | ADDXI_OPCODE_Y1 = 2, | ||
825 | ADDXLI_OPCODE_X0 = 2, | ||
826 | ADDXLI_OPCODE_X1 = 1, | ||
827 | ADDXSC_RRR_0_OPCODE_X0 = 1, | ||
828 | ADDXSC_RRR_0_OPCODE_X1 = 1, | ||
829 | ADDX_RRR_0_OPCODE_X0 = 2, | ||
830 | ADDX_RRR_0_OPCODE_X1 = 2, | ||
831 | ADDX_RRR_0_OPCODE_Y0 = 0, | ||
832 | ADDX_SPECIAL_0_OPCODE_Y1 = 0, | ||
833 | ADD_RRR_0_OPCODE_X0 = 3, | ||
834 | ADD_RRR_0_OPCODE_X1 = 3, | ||
835 | ADD_RRR_0_OPCODE_Y0 = 1, | ||
836 | ADD_SPECIAL_0_OPCODE_Y1 = 1, | ||
837 | ANDI_IMM8_OPCODE_X0 = 3, | ||
838 | ANDI_IMM8_OPCODE_X1 = 3, | ||
839 | ANDI_OPCODE_Y0 = 2, | ||
840 | ANDI_OPCODE_Y1 = 3, | ||
841 | AND_RRR_0_OPCODE_X0 = 4, | ||
842 | AND_RRR_0_OPCODE_X1 = 4, | ||
843 | AND_RRR_5_OPCODE_Y0 = 0, | ||
844 | AND_RRR_5_OPCODE_Y1 = 0, | ||
845 | BEQZT_BRANCH_OPCODE_X1 = 16, | ||
846 | BEQZ_BRANCH_OPCODE_X1 = 17, | ||
847 | BFEXTS_BF_OPCODE_X0 = 4, | ||
848 | BFEXTU_BF_OPCODE_X0 = 5, | ||
849 | BFINS_BF_OPCODE_X0 = 6, | ||
850 | BF_OPCODE_X0 = 3, | ||
851 | BGEZT_BRANCH_OPCODE_X1 = 18, | ||
852 | BGEZ_BRANCH_OPCODE_X1 = 19, | ||
853 | BGTZT_BRANCH_OPCODE_X1 = 20, | ||
854 | BGTZ_BRANCH_OPCODE_X1 = 21, | ||
855 | BLBCT_BRANCH_OPCODE_X1 = 22, | ||
856 | BLBC_BRANCH_OPCODE_X1 = 23, | ||
857 | BLBST_BRANCH_OPCODE_X1 = 24, | ||
858 | BLBS_BRANCH_OPCODE_X1 = 25, | ||
859 | BLEZT_BRANCH_OPCODE_X1 = 26, | ||
860 | BLEZ_BRANCH_OPCODE_X1 = 27, | ||
861 | BLTZT_BRANCH_OPCODE_X1 = 28, | ||
862 | BLTZ_BRANCH_OPCODE_X1 = 29, | ||
863 | BNEZT_BRANCH_OPCODE_X1 = 30, | ||
864 | BNEZ_BRANCH_OPCODE_X1 = 31, | ||
865 | BRANCH_OPCODE_X1 = 2, | ||
866 | CMOVEQZ_RRR_0_OPCODE_X0 = 5, | ||
867 | CMOVEQZ_RRR_4_OPCODE_Y0 = 0, | ||
868 | CMOVNEZ_RRR_0_OPCODE_X0 = 6, | ||
869 | CMOVNEZ_RRR_4_OPCODE_Y0 = 1, | ||
870 | CMPEQI_IMM8_OPCODE_X0 = 4, | ||
871 | CMPEQI_IMM8_OPCODE_X1 = 4, | ||
872 | CMPEQI_OPCODE_Y0 = 3, | ||
873 | CMPEQI_OPCODE_Y1 = 4, | ||
874 | CMPEQ_RRR_0_OPCODE_X0 = 7, | ||
875 | CMPEQ_RRR_0_OPCODE_X1 = 5, | ||
876 | CMPEQ_RRR_3_OPCODE_Y0 = 0, | ||
877 | CMPEQ_RRR_3_OPCODE_Y1 = 2, | ||
878 | CMPEXCH4_RRR_0_OPCODE_X1 = 6, | ||
879 | CMPEXCH_RRR_0_OPCODE_X1 = 7, | ||
880 | CMPLES_RRR_0_OPCODE_X0 = 8, | ||
881 | CMPLES_RRR_0_OPCODE_X1 = 8, | ||
882 | CMPLES_RRR_2_OPCODE_Y0 = 0, | ||
883 | CMPLES_RRR_2_OPCODE_Y1 = 0, | ||
884 | CMPLEU_RRR_0_OPCODE_X0 = 9, | ||
885 | CMPLEU_RRR_0_OPCODE_X1 = 9, | ||
886 | CMPLEU_RRR_2_OPCODE_Y0 = 1, | ||
887 | CMPLEU_RRR_2_OPCODE_Y1 = 1, | ||
888 | CMPLTSI_IMM8_OPCODE_X0 = 5, | ||
889 | CMPLTSI_IMM8_OPCODE_X1 = 5, | ||
890 | CMPLTSI_OPCODE_Y0 = 4, | ||
891 | CMPLTSI_OPCODE_Y1 = 5, | ||
892 | CMPLTS_RRR_0_OPCODE_X0 = 10, | ||
893 | CMPLTS_RRR_0_OPCODE_X1 = 10, | ||
894 | CMPLTS_RRR_2_OPCODE_Y0 = 2, | ||
895 | CMPLTS_RRR_2_OPCODE_Y1 = 2, | ||
896 | CMPLTUI_IMM8_OPCODE_X0 = 6, | ||
897 | CMPLTUI_IMM8_OPCODE_X1 = 6, | ||
898 | CMPLTU_RRR_0_OPCODE_X0 = 11, | ||
899 | CMPLTU_RRR_0_OPCODE_X1 = 11, | ||
900 | CMPLTU_RRR_2_OPCODE_Y0 = 3, | ||
901 | CMPLTU_RRR_2_OPCODE_Y1 = 3, | ||
902 | CMPNE_RRR_0_OPCODE_X0 = 12, | ||
903 | CMPNE_RRR_0_OPCODE_X1 = 12, | ||
904 | CMPNE_RRR_3_OPCODE_Y0 = 1, | ||
905 | CMPNE_RRR_3_OPCODE_Y1 = 3, | ||
906 | CMULAF_RRR_0_OPCODE_X0 = 13, | ||
907 | CMULA_RRR_0_OPCODE_X0 = 14, | ||
908 | CMULFR_RRR_0_OPCODE_X0 = 15, | ||
909 | CMULF_RRR_0_OPCODE_X0 = 16, | ||
910 | CMULHR_RRR_0_OPCODE_X0 = 17, | ||
911 | CMULH_RRR_0_OPCODE_X0 = 18, | ||
912 | CMUL_RRR_0_OPCODE_X0 = 19, | ||
913 | CNTLZ_UNARY_OPCODE_X0 = 1, | ||
914 | CNTLZ_UNARY_OPCODE_Y0 = 1, | ||
915 | CNTTZ_UNARY_OPCODE_X0 = 2, | ||
916 | CNTTZ_UNARY_OPCODE_Y0 = 2, | ||
917 | CRC32_32_RRR_0_OPCODE_X0 = 20, | ||
918 | CRC32_8_RRR_0_OPCODE_X0 = 21, | ||
919 | DBLALIGN2_RRR_0_OPCODE_X0 = 22, | ||
920 | DBLALIGN2_RRR_0_OPCODE_X1 = 13, | ||
921 | DBLALIGN4_RRR_0_OPCODE_X0 = 23, | ||
922 | DBLALIGN4_RRR_0_OPCODE_X1 = 14, | ||
923 | DBLALIGN6_RRR_0_OPCODE_X0 = 24, | ||
924 | DBLALIGN6_RRR_0_OPCODE_X1 = 15, | ||
925 | DBLALIGN_RRR_0_OPCODE_X0 = 25, | ||
926 | DRAIN_UNARY_OPCODE_X1 = 1, | ||
927 | DTLBPR_UNARY_OPCODE_X1 = 2, | ||
928 | EXCH4_RRR_0_OPCODE_X1 = 16, | ||
929 | EXCH_RRR_0_OPCODE_X1 = 17, | ||
930 | FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26, | ||
931 | FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27, | ||
932 | FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28, | ||
933 | FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29, | ||
934 | FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30, | ||
935 | FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31, | ||
936 | FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32, | ||
937 | FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33, | ||
938 | FETCHADD4_RRR_0_OPCODE_X1 = 18, | ||
939 | FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19, | ||
940 | FETCHADDGEZ_RRR_0_OPCODE_X1 = 20, | ||
941 | FETCHADD_RRR_0_OPCODE_X1 = 21, | ||
942 | FETCHAND4_RRR_0_OPCODE_X1 = 22, | ||
943 | FETCHAND_RRR_0_OPCODE_X1 = 23, | ||
944 | FETCHOR4_RRR_0_OPCODE_X1 = 24, | ||
945 | FETCHOR_RRR_0_OPCODE_X1 = 25, | ||
946 | FINV_UNARY_OPCODE_X1 = 3, | ||
947 | FLUSHWB_UNARY_OPCODE_X1 = 4, | ||
948 | FLUSH_UNARY_OPCODE_X1 = 5, | ||
949 | FNOP_UNARY_OPCODE_X0 = 3, | ||
950 | FNOP_UNARY_OPCODE_X1 = 6, | ||
951 | FNOP_UNARY_OPCODE_Y0 = 3, | ||
952 | FNOP_UNARY_OPCODE_Y1 = 8, | ||
953 | FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34, | ||
954 | FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35, | ||
955 | FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36, | ||
956 | FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37, | ||
957 | FSINGLE_PACK1_UNARY_OPCODE_X0 = 4, | ||
958 | FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4, | ||
959 | FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38, | ||
960 | FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39, | ||
961 | ICOH_UNARY_OPCODE_X1 = 7, | ||
962 | ILL_UNARY_OPCODE_X1 = 8, | ||
963 | ILL_UNARY_OPCODE_Y1 = 9, | ||
964 | IMM8_OPCODE_X0 = 4, | ||
965 | IMM8_OPCODE_X1 = 3, | ||
966 | INV_UNARY_OPCODE_X1 = 9, | ||
967 | IRET_UNARY_OPCODE_X1 = 10, | ||
968 | JALRP_UNARY_OPCODE_X1 = 11, | ||
969 | JALRP_UNARY_OPCODE_Y1 = 10, | ||
970 | JALR_UNARY_OPCODE_X1 = 12, | ||
971 | JALR_UNARY_OPCODE_Y1 = 11, | ||
972 | JAL_JUMP_OPCODE_X1 = 0, | ||
973 | JRP_UNARY_OPCODE_X1 = 13, | ||
974 | JRP_UNARY_OPCODE_Y1 = 12, | ||
975 | JR_UNARY_OPCODE_X1 = 14, | ||
976 | JR_UNARY_OPCODE_Y1 = 13, | ||
977 | JUMP_OPCODE_X1 = 4, | ||
978 | J_JUMP_OPCODE_X1 = 1, | ||
979 | LD1S_ADD_IMM8_OPCODE_X1 = 7, | ||
980 | LD1S_OPCODE_Y2 = 0, | ||
981 | LD1S_UNARY_OPCODE_X1 = 15, | ||
982 | LD1U_ADD_IMM8_OPCODE_X1 = 8, | ||
983 | LD1U_OPCODE_Y2 = 1, | ||
984 | LD1U_UNARY_OPCODE_X1 = 16, | ||
985 | LD2S_ADD_IMM8_OPCODE_X1 = 9, | ||
986 | LD2S_OPCODE_Y2 = 2, | ||
987 | LD2S_UNARY_OPCODE_X1 = 17, | ||
988 | LD2U_ADD_IMM8_OPCODE_X1 = 10, | ||
989 | LD2U_OPCODE_Y2 = 3, | ||
990 | LD2U_UNARY_OPCODE_X1 = 18, | ||
991 | LD4S_ADD_IMM8_OPCODE_X1 = 11, | ||
992 | LD4S_OPCODE_Y2 = 1, | ||
993 | LD4S_UNARY_OPCODE_X1 = 19, | ||
994 | LD4U_ADD_IMM8_OPCODE_X1 = 12, | ||
995 | LD4U_OPCODE_Y2 = 2, | ||
996 | LD4U_UNARY_OPCODE_X1 = 20, | ||
997 | LDNA_UNARY_OPCODE_X1 = 21, | ||
998 | LDNT1S_ADD_IMM8_OPCODE_X1 = 13, | ||
999 | LDNT1S_UNARY_OPCODE_X1 = 22, | ||
1000 | LDNT1U_ADD_IMM8_OPCODE_X1 = 14, | ||
1001 | LDNT1U_UNARY_OPCODE_X1 = 23, | ||
1002 | LDNT2S_ADD_IMM8_OPCODE_X1 = 15, | ||
1003 | LDNT2S_UNARY_OPCODE_X1 = 24, | ||
1004 | LDNT2U_ADD_IMM8_OPCODE_X1 = 16, | ||
1005 | LDNT2U_UNARY_OPCODE_X1 = 25, | ||
1006 | LDNT4S_ADD_IMM8_OPCODE_X1 = 17, | ||
1007 | LDNT4S_UNARY_OPCODE_X1 = 26, | ||
1008 | LDNT4U_ADD_IMM8_OPCODE_X1 = 18, | ||
1009 | LDNT4U_UNARY_OPCODE_X1 = 27, | ||
1010 | LDNT_ADD_IMM8_OPCODE_X1 = 19, | ||
1011 | LDNT_UNARY_OPCODE_X1 = 28, | ||
1012 | LD_ADD_IMM8_OPCODE_X1 = 20, | ||
1013 | LD_OPCODE_Y2 = 3, | ||
1014 | LD_UNARY_OPCODE_X1 = 29, | ||
1015 | LNK_UNARY_OPCODE_X1 = 30, | ||
1016 | LNK_UNARY_OPCODE_Y1 = 14, | ||
1017 | LWNA_ADD_IMM8_OPCODE_X1 = 21, | ||
1018 | MFSPR_IMM8_OPCODE_X1 = 22, | ||
1019 | MF_UNARY_OPCODE_X1 = 31, | ||
1020 | MM_BF_OPCODE_X0 = 7, | ||
1021 | MNZ_RRR_0_OPCODE_X0 = 40, | ||
1022 | MNZ_RRR_0_OPCODE_X1 = 26, | ||
1023 | MNZ_RRR_4_OPCODE_Y0 = 2, | ||
1024 | MNZ_RRR_4_OPCODE_Y1 = 2, | ||
1025 | MODE_OPCODE_YA2 = 1, | ||
1026 | MODE_OPCODE_YB2 = 2, | ||
1027 | MODE_OPCODE_YC2 = 3, | ||
1028 | MTSPR_IMM8_OPCODE_X1 = 23, | ||
1029 | MULAX_RRR_0_OPCODE_X0 = 41, | ||
1030 | MULAX_RRR_3_OPCODE_Y0 = 2, | ||
1031 | MULA_HS_HS_RRR_0_OPCODE_X0 = 42, | ||
1032 | MULA_HS_HS_RRR_9_OPCODE_Y0 = 0, | ||
1033 | MULA_HS_HU_RRR_0_OPCODE_X0 = 43, | ||
1034 | MULA_HS_LS_RRR_0_OPCODE_X0 = 44, | ||
1035 | MULA_HS_LU_RRR_0_OPCODE_X0 = 45, | ||
1036 | MULA_HU_HU_RRR_0_OPCODE_X0 = 46, | ||
1037 | MULA_HU_HU_RRR_9_OPCODE_Y0 = 1, | ||
1038 | MULA_HU_LS_RRR_0_OPCODE_X0 = 47, | ||
1039 | MULA_HU_LU_RRR_0_OPCODE_X0 = 48, | ||
1040 | MULA_LS_LS_RRR_0_OPCODE_X0 = 49, | ||
1041 | MULA_LS_LS_RRR_9_OPCODE_Y0 = 2, | ||
1042 | MULA_LS_LU_RRR_0_OPCODE_X0 = 50, | ||
1043 | MULA_LU_LU_RRR_0_OPCODE_X0 = 51, | ||
1044 | MULA_LU_LU_RRR_9_OPCODE_Y0 = 3, | ||
1045 | MULX_RRR_0_OPCODE_X0 = 52, | ||
1046 | MULX_RRR_3_OPCODE_Y0 = 3, | ||
1047 | MUL_HS_HS_RRR_0_OPCODE_X0 = 53, | ||
1048 | MUL_HS_HS_RRR_8_OPCODE_Y0 = 0, | ||
1049 | MUL_HS_HU_RRR_0_OPCODE_X0 = 54, | ||
1050 | MUL_HS_LS_RRR_0_OPCODE_X0 = 55, | ||
1051 | MUL_HS_LU_RRR_0_OPCODE_X0 = 56, | ||
1052 | MUL_HU_HU_RRR_0_OPCODE_X0 = 57, | ||
1053 | MUL_HU_HU_RRR_8_OPCODE_Y0 = 1, | ||
1054 | MUL_HU_LS_RRR_0_OPCODE_X0 = 58, | ||
1055 | MUL_HU_LU_RRR_0_OPCODE_X0 = 59, | ||
1056 | MUL_LS_LS_RRR_0_OPCODE_X0 = 60, | ||
1057 | MUL_LS_LS_RRR_8_OPCODE_Y0 = 2, | ||
1058 | MUL_LS_LU_RRR_0_OPCODE_X0 = 61, | ||
1059 | MUL_LU_LU_RRR_0_OPCODE_X0 = 62, | ||
1060 | MUL_LU_LU_RRR_8_OPCODE_Y0 = 3, | ||
1061 | MZ_RRR_0_OPCODE_X0 = 63, | ||
1062 | MZ_RRR_0_OPCODE_X1 = 27, | ||
1063 | MZ_RRR_4_OPCODE_Y0 = 3, | ||
1064 | MZ_RRR_4_OPCODE_Y1 = 3, | ||
1065 | NAP_UNARY_OPCODE_X1 = 32, | ||
1066 | NOP_UNARY_OPCODE_X0 = 5, | ||
1067 | NOP_UNARY_OPCODE_X1 = 33, | ||
1068 | NOP_UNARY_OPCODE_Y0 = 5, | ||
1069 | NOP_UNARY_OPCODE_Y1 = 15, | ||
1070 | NOR_RRR_0_OPCODE_X0 = 64, | ||
1071 | NOR_RRR_0_OPCODE_X1 = 28, | ||
1072 | NOR_RRR_5_OPCODE_Y0 = 1, | ||
1073 | NOR_RRR_5_OPCODE_Y1 = 1, | ||
1074 | ORI_IMM8_OPCODE_X0 = 7, | ||
1075 | ORI_IMM8_OPCODE_X1 = 24, | ||
1076 | OR_RRR_0_OPCODE_X0 = 65, | ||
1077 | OR_RRR_0_OPCODE_X1 = 29, | ||
1078 | OR_RRR_5_OPCODE_Y0 = 2, | ||
1079 | OR_RRR_5_OPCODE_Y1 = 2, | ||
1080 | PCNT_UNARY_OPCODE_X0 = 6, | ||
1081 | PCNT_UNARY_OPCODE_Y0 = 6, | ||
1082 | REVBITS_UNARY_OPCODE_X0 = 7, | ||
1083 | REVBITS_UNARY_OPCODE_Y0 = 7, | ||
1084 | REVBYTES_UNARY_OPCODE_X0 = 8, | ||
1085 | REVBYTES_UNARY_OPCODE_Y0 = 8, | ||
1086 | ROTLI_SHIFT_OPCODE_X0 = 1, | ||
1087 | ROTLI_SHIFT_OPCODE_X1 = 1, | ||
1088 | ROTLI_SHIFT_OPCODE_Y0 = 0, | ||
1089 | ROTLI_SHIFT_OPCODE_Y1 = 0, | ||
1090 | ROTL_RRR_0_OPCODE_X0 = 66, | ||
1091 | ROTL_RRR_0_OPCODE_X1 = 30, | ||
1092 | ROTL_RRR_6_OPCODE_Y0 = 0, | ||
1093 | ROTL_RRR_6_OPCODE_Y1 = 0, | ||
1094 | RRR_0_OPCODE_X0 = 5, | ||
1095 | RRR_0_OPCODE_X1 = 5, | ||
1096 | RRR_0_OPCODE_Y0 = 5, | ||
1097 | RRR_0_OPCODE_Y1 = 6, | ||
1098 | RRR_1_OPCODE_Y0 = 6, | ||
1099 | RRR_1_OPCODE_Y1 = 7, | ||
1100 | RRR_2_OPCODE_Y0 = 7, | ||
1101 | RRR_2_OPCODE_Y1 = 8, | ||
1102 | RRR_3_OPCODE_Y0 = 8, | ||
1103 | RRR_3_OPCODE_Y1 = 9, | ||
1104 | RRR_4_OPCODE_Y0 = 9, | ||
1105 | RRR_4_OPCODE_Y1 = 10, | ||
1106 | RRR_5_OPCODE_Y0 = 10, | ||
1107 | RRR_5_OPCODE_Y1 = 11, | ||
1108 | RRR_6_OPCODE_Y0 = 11, | ||
1109 | RRR_6_OPCODE_Y1 = 12, | ||
1110 | RRR_7_OPCODE_Y0 = 12, | ||
1111 | RRR_7_OPCODE_Y1 = 13, | ||
1112 | RRR_8_OPCODE_Y0 = 13, | ||
1113 | RRR_9_OPCODE_Y0 = 14, | ||
1114 | SHIFT_OPCODE_X0 = 6, | ||
1115 | SHIFT_OPCODE_X1 = 6, | ||
1116 | SHIFT_OPCODE_Y0 = 15, | ||
1117 | SHIFT_OPCODE_Y1 = 14, | ||
1118 | SHL16INSLI_OPCODE_X0 = 7, | ||
1119 | SHL16INSLI_OPCODE_X1 = 7, | ||
1120 | SHL1ADDX_RRR_0_OPCODE_X0 = 67, | ||
1121 | SHL1ADDX_RRR_0_OPCODE_X1 = 31, | ||
1122 | SHL1ADDX_RRR_7_OPCODE_Y0 = 1, | ||
1123 | SHL1ADDX_RRR_7_OPCODE_Y1 = 1, | ||
1124 | SHL1ADD_RRR_0_OPCODE_X0 = 68, | ||
1125 | SHL1ADD_RRR_0_OPCODE_X1 = 32, | ||
1126 | SHL1ADD_RRR_1_OPCODE_Y0 = 0, | ||
1127 | SHL1ADD_RRR_1_OPCODE_Y1 = 0, | ||
1128 | SHL2ADDX_RRR_0_OPCODE_X0 = 69, | ||
1129 | SHL2ADDX_RRR_0_OPCODE_X1 = 33, | ||
1130 | SHL2ADDX_RRR_7_OPCODE_Y0 = 2, | ||
1131 | SHL2ADDX_RRR_7_OPCODE_Y1 = 2, | ||
1132 | SHL2ADD_RRR_0_OPCODE_X0 = 70, | ||
1133 | SHL2ADD_RRR_0_OPCODE_X1 = 34, | ||
1134 | SHL2ADD_RRR_1_OPCODE_Y0 = 1, | ||
1135 | SHL2ADD_RRR_1_OPCODE_Y1 = 1, | ||
1136 | SHL3ADDX_RRR_0_OPCODE_X0 = 71, | ||
1137 | SHL3ADDX_RRR_0_OPCODE_X1 = 35, | ||
1138 | SHL3ADDX_RRR_7_OPCODE_Y0 = 3, | ||
1139 | SHL3ADDX_RRR_7_OPCODE_Y1 = 3, | ||
1140 | SHL3ADD_RRR_0_OPCODE_X0 = 72, | ||
1141 | SHL3ADD_RRR_0_OPCODE_X1 = 36, | ||
1142 | SHL3ADD_RRR_1_OPCODE_Y0 = 2, | ||
1143 | SHL3ADD_RRR_1_OPCODE_Y1 = 2, | ||
1144 | SHLI_SHIFT_OPCODE_X0 = 2, | ||
1145 | SHLI_SHIFT_OPCODE_X1 = 2, | ||
1146 | SHLI_SHIFT_OPCODE_Y0 = 1, | ||
1147 | SHLI_SHIFT_OPCODE_Y1 = 1, | ||
1148 | SHLXI_SHIFT_OPCODE_X0 = 3, | ||
1149 | SHLXI_SHIFT_OPCODE_X1 = 3, | ||
1150 | SHLX_RRR_0_OPCODE_X0 = 73, | ||
1151 | SHLX_RRR_0_OPCODE_X1 = 37, | ||
1152 | SHL_RRR_0_OPCODE_X0 = 74, | ||
1153 | SHL_RRR_0_OPCODE_X1 = 38, | ||
1154 | SHL_RRR_6_OPCODE_Y0 = 1, | ||
1155 | SHL_RRR_6_OPCODE_Y1 = 1, | ||
1156 | SHRSI_SHIFT_OPCODE_X0 = 4, | ||
1157 | SHRSI_SHIFT_OPCODE_X1 = 4, | ||
1158 | SHRSI_SHIFT_OPCODE_Y0 = 2, | ||
1159 | SHRSI_SHIFT_OPCODE_Y1 = 2, | ||
1160 | SHRS_RRR_0_OPCODE_X0 = 75, | ||
1161 | SHRS_RRR_0_OPCODE_X1 = 39, | ||
1162 | SHRS_RRR_6_OPCODE_Y0 = 2, | ||
1163 | SHRS_RRR_6_OPCODE_Y1 = 2, | ||
1164 | SHRUI_SHIFT_OPCODE_X0 = 5, | ||
1165 | SHRUI_SHIFT_OPCODE_X1 = 5, | ||
1166 | SHRUI_SHIFT_OPCODE_Y0 = 3, | ||
1167 | SHRUI_SHIFT_OPCODE_Y1 = 3, | ||
1168 | SHRUXI_SHIFT_OPCODE_X0 = 6, | ||
1169 | SHRUXI_SHIFT_OPCODE_X1 = 6, | ||
1170 | SHRUX_RRR_0_OPCODE_X0 = 76, | ||
1171 | SHRUX_RRR_0_OPCODE_X1 = 40, | ||
1172 | SHRU_RRR_0_OPCODE_X0 = 77, | ||
1173 | SHRU_RRR_0_OPCODE_X1 = 41, | ||
1174 | SHRU_RRR_6_OPCODE_Y0 = 3, | ||
1175 | SHRU_RRR_6_OPCODE_Y1 = 3, | ||
1176 | SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78, | ||
1177 | ST1_ADD_IMM8_OPCODE_X1 = 25, | ||
1178 | ST1_OPCODE_Y2 = 0, | ||
1179 | ST1_RRR_0_OPCODE_X1 = 42, | ||
1180 | ST2_ADD_IMM8_OPCODE_X1 = 26, | ||
1181 | ST2_OPCODE_Y2 = 1, | ||
1182 | ST2_RRR_0_OPCODE_X1 = 43, | ||
1183 | ST4_ADD_IMM8_OPCODE_X1 = 27, | ||
1184 | ST4_OPCODE_Y2 = 2, | ||
1185 | ST4_RRR_0_OPCODE_X1 = 44, | ||
1186 | STNT1_ADD_IMM8_OPCODE_X1 = 28, | ||
1187 | STNT1_RRR_0_OPCODE_X1 = 45, | ||
1188 | STNT2_ADD_IMM8_OPCODE_X1 = 29, | ||
1189 | STNT2_RRR_0_OPCODE_X1 = 46, | ||
1190 | STNT4_ADD_IMM8_OPCODE_X1 = 30, | ||
1191 | STNT4_RRR_0_OPCODE_X1 = 47, | ||
1192 | STNT_ADD_IMM8_OPCODE_X1 = 31, | ||
1193 | STNT_RRR_0_OPCODE_X1 = 48, | ||
1194 | ST_ADD_IMM8_OPCODE_X1 = 32, | ||
1195 | ST_OPCODE_Y2 = 3, | ||
1196 | ST_RRR_0_OPCODE_X1 = 49, | ||
1197 | SUBXSC_RRR_0_OPCODE_X0 = 79, | ||
1198 | SUBXSC_RRR_0_OPCODE_X1 = 50, | ||
1199 | SUBX_RRR_0_OPCODE_X0 = 80, | ||
1200 | SUBX_RRR_0_OPCODE_X1 = 51, | ||
1201 | SUBX_RRR_0_OPCODE_Y0 = 2, | ||
1202 | SUBX_RRR_0_OPCODE_Y1 = 2, | ||
1203 | SUB_RRR_0_OPCODE_X0 = 81, | ||
1204 | SUB_RRR_0_OPCODE_X1 = 52, | ||
1205 | SUB_RRR_0_OPCODE_Y0 = 3, | ||
1206 | SUB_RRR_0_OPCODE_Y1 = 3, | ||
1207 | SWINT0_UNARY_OPCODE_X1 = 34, | ||
1208 | SWINT1_UNARY_OPCODE_X1 = 35, | ||
1209 | SWINT2_UNARY_OPCODE_X1 = 36, | ||
1210 | SWINT3_UNARY_OPCODE_X1 = 37, | ||
1211 | TBLIDXB0_UNARY_OPCODE_X0 = 9, | ||
1212 | TBLIDXB0_UNARY_OPCODE_Y0 = 9, | ||
1213 | TBLIDXB1_UNARY_OPCODE_X0 = 10, | ||
1214 | TBLIDXB1_UNARY_OPCODE_Y0 = 10, | ||
1215 | TBLIDXB2_UNARY_OPCODE_X0 = 11, | ||
1216 | TBLIDXB2_UNARY_OPCODE_Y0 = 11, | ||
1217 | TBLIDXB3_UNARY_OPCODE_X0 = 12, | ||
1218 | TBLIDXB3_UNARY_OPCODE_Y0 = 12, | ||
1219 | UNARY_RRR_0_OPCODE_X0 = 82, | ||
1220 | UNARY_RRR_0_OPCODE_X1 = 53, | ||
1221 | UNARY_RRR_1_OPCODE_Y0 = 3, | ||
1222 | UNARY_RRR_1_OPCODE_Y1 = 3, | ||
1223 | V1ADDI_IMM8_OPCODE_X0 = 8, | ||
1224 | V1ADDI_IMM8_OPCODE_X1 = 33, | ||
1225 | V1ADDUC_RRR_0_OPCODE_X0 = 83, | ||
1226 | V1ADDUC_RRR_0_OPCODE_X1 = 54, | ||
1227 | V1ADD_RRR_0_OPCODE_X0 = 84, | ||
1228 | V1ADD_RRR_0_OPCODE_X1 = 55, | ||
1229 | V1ADIFFU_RRR_0_OPCODE_X0 = 85, | ||
1230 | V1AVGU_RRR_0_OPCODE_X0 = 86, | ||
1231 | V1CMPEQI_IMM8_OPCODE_X0 = 9, | ||
1232 | V1CMPEQI_IMM8_OPCODE_X1 = 34, | ||
1233 | V1CMPEQ_RRR_0_OPCODE_X0 = 87, | ||
1234 | V1CMPEQ_RRR_0_OPCODE_X1 = 56, | ||
1235 | V1CMPLES_RRR_0_OPCODE_X0 = 88, | ||
1236 | V1CMPLES_RRR_0_OPCODE_X1 = 57, | ||
1237 | V1CMPLEU_RRR_0_OPCODE_X0 = 89, | ||
1238 | V1CMPLEU_RRR_0_OPCODE_X1 = 58, | ||
1239 | V1CMPLTSI_IMM8_OPCODE_X0 = 10, | ||
1240 | V1CMPLTSI_IMM8_OPCODE_X1 = 35, | ||
1241 | V1CMPLTS_RRR_0_OPCODE_X0 = 90, | ||
1242 | V1CMPLTS_RRR_0_OPCODE_X1 = 59, | ||
1243 | V1CMPLTUI_IMM8_OPCODE_X0 = 11, | ||
1244 | V1CMPLTUI_IMM8_OPCODE_X1 = 36, | ||
1245 | V1CMPLTU_RRR_0_OPCODE_X0 = 91, | ||
1246 | V1CMPLTU_RRR_0_OPCODE_X1 = 60, | ||
1247 | V1CMPNE_RRR_0_OPCODE_X0 = 92, | ||
1248 | V1CMPNE_RRR_0_OPCODE_X1 = 61, | ||
1249 | V1DDOTPUA_RRR_0_OPCODE_X0 = 161, | ||
1250 | V1DDOTPUSA_RRR_0_OPCODE_X0 = 93, | ||
1251 | V1DDOTPUS_RRR_0_OPCODE_X0 = 94, | ||
1252 | V1DDOTPU_RRR_0_OPCODE_X0 = 162, | ||
1253 | V1DOTPA_RRR_0_OPCODE_X0 = 95, | ||
1254 | V1DOTPUA_RRR_0_OPCODE_X0 = 163, | ||
1255 | V1DOTPUSA_RRR_0_OPCODE_X0 = 96, | ||
1256 | V1DOTPUS_RRR_0_OPCODE_X0 = 97, | ||
1257 | V1DOTPU_RRR_0_OPCODE_X0 = 164, | ||
1258 | V1DOTP_RRR_0_OPCODE_X0 = 98, | ||
1259 | V1INT_H_RRR_0_OPCODE_X0 = 99, | ||
1260 | V1INT_H_RRR_0_OPCODE_X1 = 62, | ||
1261 | V1INT_L_RRR_0_OPCODE_X0 = 100, | ||
1262 | V1INT_L_RRR_0_OPCODE_X1 = 63, | ||
1263 | V1MAXUI_IMM8_OPCODE_X0 = 12, | ||
1264 | V1MAXUI_IMM8_OPCODE_X1 = 37, | ||
1265 | V1MAXU_RRR_0_OPCODE_X0 = 101, | ||
1266 | V1MAXU_RRR_0_OPCODE_X1 = 64, | ||
1267 | V1MINUI_IMM8_OPCODE_X0 = 13, | ||
1268 | V1MINUI_IMM8_OPCODE_X1 = 38, | ||
1269 | V1MINU_RRR_0_OPCODE_X0 = 102, | ||
1270 | V1MINU_RRR_0_OPCODE_X1 = 65, | ||
1271 | V1MNZ_RRR_0_OPCODE_X0 = 103, | ||
1272 | V1MNZ_RRR_0_OPCODE_X1 = 66, | ||
1273 | V1MULTU_RRR_0_OPCODE_X0 = 104, | ||
1274 | V1MULUS_RRR_0_OPCODE_X0 = 105, | ||
1275 | V1MULU_RRR_0_OPCODE_X0 = 106, | ||
1276 | V1MZ_RRR_0_OPCODE_X0 = 107, | ||
1277 | V1MZ_RRR_0_OPCODE_X1 = 67, | ||
1278 | V1SADAU_RRR_0_OPCODE_X0 = 108, | ||
1279 | V1SADU_RRR_0_OPCODE_X0 = 109, | ||
1280 | V1SHLI_SHIFT_OPCODE_X0 = 7, | ||
1281 | V1SHLI_SHIFT_OPCODE_X1 = 7, | ||
1282 | V1SHL_RRR_0_OPCODE_X0 = 110, | ||
1283 | V1SHL_RRR_0_OPCODE_X1 = 68, | ||
1284 | V1SHRSI_SHIFT_OPCODE_X0 = 8, | ||
1285 | V1SHRSI_SHIFT_OPCODE_X1 = 8, | ||
1286 | V1SHRS_RRR_0_OPCODE_X0 = 111, | ||
1287 | V1SHRS_RRR_0_OPCODE_X1 = 69, | ||
1288 | V1SHRUI_SHIFT_OPCODE_X0 = 9, | ||
1289 | V1SHRUI_SHIFT_OPCODE_X1 = 9, | ||
1290 | V1SHRU_RRR_0_OPCODE_X0 = 112, | ||
1291 | V1SHRU_RRR_0_OPCODE_X1 = 70, | ||
1292 | V1SUBUC_RRR_0_OPCODE_X0 = 113, | ||
1293 | V1SUBUC_RRR_0_OPCODE_X1 = 71, | ||
1294 | V1SUB_RRR_0_OPCODE_X0 = 114, | ||
1295 | V1SUB_RRR_0_OPCODE_X1 = 72, | ||
1296 | V2ADDI_IMM8_OPCODE_X0 = 14, | ||
1297 | V2ADDI_IMM8_OPCODE_X1 = 39, | ||
1298 | V2ADDSC_RRR_0_OPCODE_X0 = 115, | ||
1299 | V2ADDSC_RRR_0_OPCODE_X1 = 73, | ||
1300 | V2ADD_RRR_0_OPCODE_X0 = 116, | ||
1301 | V2ADD_RRR_0_OPCODE_X1 = 74, | ||
1302 | V2ADIFFS_RRR_0_OPCODE_X0 = 117, | ||
1303 | V2AVGS_RRR_0_OPCODE_X0 = 118, | ||
1304 | V2CMPEQI_IMM8_OPCODE_X0 = 15, | ||
1305 | V2CMPEQI_IMM8_OPCODE_X1 = 40, | ||
1306 | V2CMPEQ_RRR_0_OPCODE_X0 = 119, | ||
1307 | V2CMPEQ_RRR_0_OPCODE_X1 = 75, | ||
1308 | V2CMPLES_RRR_0_OPCODE_X0 = 120, | ||
1309 | V2CMPLES_RRR_0_OPCODE_X1 = 76, | ||
1310 | V2CMPLEU_RRR_0_OPCODE_X0 = 121, | ||
1311 | V2CMPLEU_RRR_0_OPCODE_X1 = 77, | ||
1312 | V2CMPLTSI_IMM8_OPCODE_X0 = 16, | ||
1313 | V2CMPLTSI_IMM8_OPCODE_X1 = 41, | ||
1314 | V2CMPLTS_RRR_0_OPCODE_X0 = 122, | ||
1315 | V2CMPLTS_RRR_0_OPCODE_X1 = 78, | ||
1316 | V2CMPLTUI_IMM8_OPCODE_X0 = 17, | ||
1317 | V2CMPLTUI_IMM8_OPCODE_X1 = 42, | ||
1318 | V2CMPLTU_RRR_0_OPCODE_X0 = 123, | ||
1319 | V2CMPLTU_RRR_0_OPCODE_X1 = 79, | ||
1320 | V2CMPNE_RRR_0_OPCODE_X0 = 124, | ||
1321 | V2CMPNE_RRR_0_OPCODE_X1 = 80, | ||
1322 | V2DOTPA_RRR_0_OPCODE_X0 = 125, | ||
1323 | V2DOTP_RRR_0_OPCODE_X0 = 126, | ||
1324 | V2INT_H_RRR_0_OPCODE_X0 = 127, | ||
1325 | V2INT_H_RRR_0_OPCODE_X1 = 81, | ||
1326 | V2INT_L_RRR_0_OPCODE_X0 = 128, | ||
1327 | V2INT_L_RRR_0_OPCODE_X1 = 82, | ||
1328 | V2MAXSI_IMM8_OPCODE_X0 = 18, | ||
1329 | V2MAXSI_IMM8_OPCODE_X1 = 43, | ||
1330 | V2MAXS_RRR_0_OPCODE_X0 = 129, | ||
1331 | V2MAXS_RRR_0_OPCODE_X1 = 83, | ||
1332 | V2MINSI_IMM8_OPCODE_X0 = 19, | ||
1333 | V2MINSI_IMM8_OPCODE_X1 = 44, | ||
1334 | V2MINS_RRR_0_OPCODE_X0 = 130, | ||
1335 | V2MINS_RRR_0_OPCODE_X1 = 84, | ||
1336 | V2MNZ_RRR_0_OPCODE_X0 = 131, | ||
1337 | V2MNZ_RRR_0_OPCODE_X1 = 85, | ||
1338 | V2MULFSC_RRR_0_OPCODE_X0 = 132, | ||
1339 | V2MULS_RRR_0_OPCODE_X0 = 133, | ||
1340 | V2MULTS_RRR_0_OPCODE_X0 = 134, | ||
1341 | V2MZ_RRR_0_OPCODE_X0 = 135, | ||
1342 | V2MZ_RRR_0_OPCODE_X1 = 86, | ||
1343 | V2PACKH_RRR_0_OPCODE_X0 = 136, | ||
1344 | V2PACKH_RRR_0_OPCODE_X1 = 87, | ||
1345 | V2PACKL_RRR_0_OPCODE_X0 = 137, | ||
1346 | V2PACKL_RRR_0_OPCODE_X1 = 88, | ||
1347 | V2PACKUC_RRR_0_OPCODE_X0 = 138, | ||
1348 | V2PACKUC_RRR_0_OPCODE_X1 = 89, | ||
1349 | V2SADAS_RRR_0_OPCODE_X0 = 139, | ||
1350 | V2SADAU_RRR_0_OPCODE_X0 = 140, | ||
1351 | V2SADS_RRR_0_OPCODE_X0 = 141, | ||
1352 | V2SADU_RRR_0_OPCODE_X0 = 142, | ||
1353 | V2SHLI_SHIFT_OPCODE_X0 = 10, | ||
1354 | V2SHLI_SHIFT_OPCODE_X1 = 10, | ||
1355 | V2SHLSC_RRR_0_OPCODE_X0 = 143, | ||
1356 | V2SHLSC_RRR_0_OPCODE_X1 = 90, | ||
1357 | V2SHL_RRR_0_OPCODE_X0 = 144, | ||
1358 | V2SHL_RRR_0_OPCODE_X1 = 91, | ||
1359 | V2SHRSI_SHIFT_OPCODE_X0 = 11, | ||
1360 | V2SHRSI_SHIFT_OPCODE_X1 = 11, | ||
1361 | V2SHRS_RRR_0_OPCODE_X0 = 145, | ||
1362 | V2SHRS_RRR_0_OPCODE_X1 = 92, | ||
1363 | V2SHRUI_SHIFT_OPCODE_X0 = 12, | ||
1364 | V2SHRUI_SHIFT_OPCODE_X1 = 12, | ||
1365 | V2SHRU_RRR_0_OPCODE_X0 = 146, | ||
1366 | V2SHRU_RRR_0_OPCODE_X1 = 93, | ||
1367 | V2SUBSC_RRR_0_OPCODE_X0 = 147, | ||
1368 | V2SUBSC_RRR_0_OPCODE_X1 = 94, | ||
1369 | V2SUB_RRR_0_OPCODE_X0 = 148, | ||
1370 | V2SUB_RRR_0_OPCODE_X1 = 95, | ||
1371 | V4ADDSC_RRR_0_OPCODE_X0 = 149, | ||
1372 | V4ADDSC_RRR_0_OPCODE_X1 = 96, | ||
1373 | V4ADD_RRR_0_OPCODE_X0 = 150, | ||
1374 | V4ADD_RRR_0_OPCODE_X1 = 97, | ||
1375 | V4INT_H_RRR_0_OPCODE_X0 = 151, | ||
1376 | V4INT_H_RRR_0_OPCODE_X1 = 98, | ||
1377 | V4INT_L_RRR_0_OPCODE_X0 = 152, | ||
1378 | V4INT_L_RRR_0_OPCODE_X1 = 99, | ||
1379 | V4PACKSC_RRR_0_OPCODE_X0 = 153, | ||
1380 | V4PACKSC_RRR_0_OPCODE_X1 = 100, | ||
1381 | V4SHLSC_RRR_0_OPCODE_X0 = 154, | ||
1382 | V4SHLSC_RRR_0_OPCODE_X1 = 101, | ||
1383 | V4SHL_RRR_0_OPCODE_X0 = 155, | ||
1384 | V4SHL_RRR_0_OPCODE_X1 = 102, | ||
1385 | V4SHRS_RRR_0_OPCODE_X0 = 156, | ||
1386 | V4SHRS_RRR_0_OPCODE_X1 = 103, | ||
1387 | V4SHRU_RRR_0_OPCODE_X0 = 157, | ||
1388 | V4SHRU_RRR_0_OPCODE_X1 = 104, | ||
1389 | V4SUBSC_RRR_0_OPCODE_X0 = 158, | ||
1390 | V4SUBSC_RRR_0_OPCODE_X1 = 105, | ||
1391 | V4SUB_RRR_0_OPCODE_X0 = 159, | ||
1392 | V4SUB_RRR_0_OPCODE_X1 = 106, | ||
1393 | WH64_UNARY_OPCODE_X1 = 38, | ||
1394 | XORI_IMM8_OPCODE_X0 = 20, | ||
1395 | XORI_IMM8_OPCODE_X1 = 45, | ||
1396 | XOR_RRR_0_OPCODE_X0 = 160, | ||
1397 | XOR_RRR_0_OPCODE_X1 = 107, | ||
1398 | XOR_RRR_5_OPCODE_Y0 = 3, | ||
1399 | XOR_RRR_5_OPCODE_Y1 = 3 | ||
1400 | }; | ||
1401 | |||
1402 | |||
1403 | #endif /* __ASSEMBLER__ */ | ||
1404 | |||
1405 | #endif /* __ARCH_OPCODE_H__ */ | ||
diff --git a/arch/tile/include/uapi/arch/opcode_tilepro.h b/arch/tile/include/uapi/arch/opcode_tilepro.h new file mode 100644 index 000000000000..71b763b8ce83 --- /dev/null +++ b/arch/tile/include/uapi/arch/opcode_tilepro.h | |||
@@ -0,0 +1,1471 @@ | |||
1 | /* TILEPro opcode information. | ||
2 | * | ||
3 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * as published by the Free Software Foundation, version 2. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, but | ||
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
12 | * NON INFRINGEMENT. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * | ||
16 | * | ||
17 | * | ||
18 | * | ||
19 | */ | ||
20 | |||
21 | #ifndef __ARCH_OPCODE_H__ | ||
22 | #define __ARCH_OPCODE_H__ | ||
23 | |||
24 | #ifndef __ASSEMBLER__ | ||
25 | |||
26 | typedef unsigned long long tilepro_bundle_bits; | ||
27 | |||
28 | /* This is the bit that determines if a bundle is in the Y encoding. */ | ||
29 | #define TILEPRO_BUNDLE_Y_ENCODING_MASK ((tilepro_bundle_bits)1 << 63) | ||
30 | |||
31 | enum | ||
32 | { | ||
33 | /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ | ||
34 | TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE = 3, | ||
35 | |||
36 | /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ | ||
37 | TILEPRO_NUM_PIPELINE_ENCODINGS = 5, | ||
38 | |||
39 | /* Log base 2 of TILEPRO_BUNDLE_SIZE_IN_BYTES. */ | ||
40 | TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES = 3, | ||
41 | |||
42 | /* Instructions take this many bytes. */ | ||
43 | TILEPRO_BUNDLE_SIZE_IN_BYTES = 1 << TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES, | ||
44 | |||
45 | /* Log base 2 of TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES. */ | ||
46 | TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, | ||
47 | |||
48 | /* Bundles should be aligned modulo this number of bytes. */ | ||
49 | TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES = | ||
50 | (1 << TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), | ||
51 | |||
52 | /* Log base 2 of TILEPRO_SN_INSTRUCTION_SIZE_IN_BYTES. */ | ||
53 | TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1, | ||
54 | |||
55 | /* Static network instructions take this many bytes. */ | ||
56 | TILEPRO_SN_INSTRUCTION_SIZE_IN_BYTES = | ||
57 | (1 << TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES), | ||
58 | |||
59 | /* Number of registers (some are magic, such as network I/O). */ | ||
60 | TILEPRO_NUM_REGISTERS = 64, | ||
61 | |||
62 | /* Number of static network registers. */ | ||
63 | TILEPRO_NUM_SN_REGISTERS = 4 | ||
64 | }; | ||
65 | |||
66 | /* Make a few "tile_" variables to simplify common code between | ||
67 | architectures. */ | ||
68 | |||
69 | typedef tilepro_bundle_bits tile_bundle_bits; | ||
70 | #define TILE_BUNDLE_SIZE_IN_BYTES TILEPRO_BUNDLE_SIZE_IN_BYTES | ||
71 | #define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES | ||
72 | #define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \ | ||
73 | TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES | ||
74 | |||
75 | /* 64-bit pattern for a { bpt ; nop } bundle. */ | ||
76 | #define TILEPRO_BPT_BUNDLE 0x400b3cae70166000ULL | ||
77 | |||
78 | static __inline unsigned int | ||
79 | get_BrOff_SN(tilepro_bundle_bits num) | ||
80 | { | ||
81 | const unsigned int n = (unsigned int)num; | ||
82 | return (((n >> 0)) & 0x3ff); | ||
83 | } | ||
84 | |||
85 | static __inline unsigned int | ||
86 | get_BrOff_X1(tilepro_bundle_bits n) | ||
87 | { | ||
88 | return (((unsigned int)(n >> 43)) & 0x00007fff) | | ||
89 | (((unsigned int)(n >> 20)) & 0x00018000); | ||
90 | } | ||
91 | |||
92 | static __inline unsigned int | ||
93 | get_BrType_X1(tilepro_bundle_bits n) | ||
94 | { | ||
95 | return (((unsigned int)(n >> 31)) & 0xf); | ||
96 | } | ||
97 | |||
98 | static __inline unsigned int | ||
99 | get_Dest_Imm8_X1(tilepro_bundle_bits n) | ||
100 | { | ||
101 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
102 | (((unsigned int)(n >> 43)) & 0x000000c0); | ||
103 | } | ||
104 | |||
105 | static __inline unsigned int | ||
106 | get_Dest_SN(tilepro_bundle_bits num) | ||
107 | { | ||
108 | const unsigned int n = (unsigned int)num; | ||
109 | return (((n >> 2)) & 0x3); | ||
110 | } | ||
111 | |||
112 | static __inline unsigned int | ||
113 | get_Dest_X0(tilepro_bundle_bits num) | ||
114 | { | ||
115 | const unsigned int n = (unsigned int)num; | ||
116 | return (((n >> 0)) & 0x3f); | ||
117 | } | ||
118 | |||
119 | static __inline unsigned int | ||
120 | get_Dest_X1(tilepro_bundle_bits n) | ||
121 | { | ||
122 | return (((unsigned int)(n >> 31)) & 0x3f); | ||
123 | } | ||
124 | |||
125 | static __inline unsigned int | ||
126 | get_Dest_Y0(tilepro_bundle_bits num) | ||
127 | { | ||
128 | const unsigned int n = (unsigned int)num; | ||
129 | return (((n >> 0)) & 0x3f); | ||
130 | } | ||
131 | |||
132 | static __inline unsigned int | ||
133 | get_Dest_Y1(tilepro_bundle_bits n) | ||
134 | { | ||
135 | return (((unsigned int)(n >> 31)) & 0x3f); | ||
136 | } | ||
137 | |||
138 | static __inline unsigned int | ||
139 | get_Imm16_X0(tilepro_bundle_bits num) | ||
140 | { | ||
141 | const unsigned int n = (unsigned int)num; | ||
142 | return (((n >> 12)) & 0xffff); | ||
143 | } | ||
144 | |||
145 | static __inline unsigned int | ||
146 | get_Imm16_X1(tilepro_bundle_bits n) | ||
147 | { | ||
148 | return (((unsigned int)(n >> 43)) & 0xffff); | ||
149 | } | ||
150 | |||
151 | static __inline unsigned int | ||
152 | get_Imm8_SN(tilepro_bundle_bits num) | ||
153 | { | ||
154 | const unsigned int n = (unsigned int)num; | ||
155 | return (((n >> 0)) & 0xff); | ||
156 | } | ||
157 | |||
158 | static __inline unsigned int | ||
159 | get_Imm8_X0(tilepro_bundle_bits num) | ||
160 | { | ||
161 | const unsigned int n = (unsigned int)num; | ||
162 | return (((n >> 12)) & 0xff); | ||
163 | } | ||
164 | |||
165 | static __inline unsigned int | ||
166 | get_Imm8_X1(tilepro_bundle_bits n) | ||
167 | { | ||
168 | return (((unsigned int)(n >> 43)) & 0xff); | ||
169 | } | ||
170 | |||
171 | static __inline unsigned int | ||
172 | get_Imm8_Y0(tilepro_bundle_bits num) | ||
173 | { | ||
174 | const unsigned int n = (unsigned int)num; | ||
175 | return (((n >> 12)) & 0xff); | ||
176 | } | ||
177 | |||
178 | static __inline unsigned int | ||
179 | get_Imm8_Y1(tilepro_bundle_bits n) | ||
180 | { | ||
181 | return (((unsigned int)(n >> 43)) & 0xff); | ||
182 | } | ||
183 | |||
184 | static __inline unsigned int | ||
185 | get_ImmOpcodeExtension_X0(tilepro_bundle_bits num) | ||
186 | { | ||
187 | const unsigned int n = (unsigned int)num; | ||
188 | return (((n >> 20)) & 0x7f); | ||
189 | } | ||
190 | |||
191 | static __inline unsigned int | ||
192 | get_ImmOpcodeExtension_X1(tilepro_bundle_bits n) | ||
193 | { | ||
194 | return (((unsigned int)(n >> 51)) & 0x7f); | ||
195 | } | ||
196 | |||
197 | static __inline unsigned int | ||
198 | get_ImmRROpcodeExtension_SN(tilepro_bundle_bits num) | ||
199 | { | ||
200 | const unsigned int n = (unsigned int)num; | ||
201 | return (((n >> 8)) & 0x3); | ||
202 | } | ||
203 | |||
204 | static __inline unsigned int | ||
205 | get_JOffLong_X1(tilepro_bundle_bits n) | ||
206 | { | ||
207 | return (((unsigned int)(n >> 43)) & 0x00007fff) | | ||
208 | (((unsigned int)(n >> 20)) & 0x00018000) | | ||
209 | (((unsigned int)(n >> 14)) & 0x001e0000) | | ||
210 | (((unsigned int)(n >> 16)) & 0x07e00000) | | ||
211 | (((unsigned int)(n >> 31)) & 0x18000000); | ||
212 | } | ||
213 | |||
214 | static __inline unsigned int | ||
215 | get_JOff_X1(tilepro_bundle_bits n) | ||
216 | { | ||
217 | return (((unsigned int)(n >> 43)) & 0x00007fff) | | ||
218 | (((unsigned int)(n >> 20)) & 0x00018000) | | ||
219 | (((unsigned int)(n >> 14)) & 0x001e0000) | | ||
220 | (((unsigned int)(n >> 16)) & 0x07e00000) | | ||
221 | (((unsigned int)(n >> 31)) & 0x08000000); | ||
222 | } | ||
223 | |||
224 | static __inline unsigned int | ||
225 | get_MF_Imm15_X1(tilepro_bundle_bits n) | ||
226 | { | ||
227 | return (((unsigned int)(n >> 37)) & 0x00003fff) | | ||
228 | (((unsigned int)(n >> 44)) & 0x00004000); | ||
229 | } | ||
230 | |||
231 | static __inline unsigned int | ||
232 | get_MMEnd_X0(tilepro_bundle_bits num) | ||
233 | { | ||
234 | const unsigned int n = (unsigned int)num; | ||
235 | return (((n >> 18)) & 0x1f); | ||
236 | } | ||
237 | |||
238 | static __inline unsigned int | ||
239 | get_MMEnd_X1(tilepro_bundle_bits n) | ||
240 | { | ||
241 | return (((unsigned int)(n >> 49)) & 0x1f); | ||
242 | } | ||
243 | |||
244 | static __inline unsigned int | ||
245 | get_MMStart_X0(tilepro_bundle_bits num) | ||
246 | { | ||
247 | const unsigned int n = (unsigned int)num; | ||
248 | return (((n >> 23)) & 0x1f); | ||
249 | } | ||
250 | |||
251 | static __inline unsigned int | ||
252 | get_MMStart_X1(tilepro_bundle_bits n) | ||
253 | { | ||
254 | return (((unsigned int)(n >> 54)) & 0x1f); | ||
255 | } | ||
256 | |||
257 | static __inline unsigned int | ||
258 | get_MT_Imm15_X1(tilepro_bundle_bits n) | ||
259 | { | ||
260 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
261 | (((unsigned int)(n >> 37)) & 0x00003fc0) | | ||
262 | (((unsigned int)(n >> 44)) & 0x00004000); | ||
263 | } | ||
264 | |||
265 | static __inline unsigned int | ||
266 | get_Mode(tilepro_bundle_bits n) | ||
267 | { | ||
268 | return (((unsigned int)(n >> 63)) & 0x1); | ||
269 | } | ||
270 | |||
271 | static __inline unsigned int | ||
272 | get_NoRegOpcodeExtension_SN(tilepro_bundle_bits num) | ||
273 | { | ||
274 | const unsigned int n = (unsigned int)num; | ||
275 | return (((n >> 0)) & 0xf); | ||
276 | } | ||
277 | |||
278 | static __inline unsigned int | ||
279 | get_Opcode_SN(tilepro_bundle_bits num) | ||
280 | { | ||
281 | const unsigned int n = (unsigned int)num; | ||
282 | return (((n >> 10)) & 0x3f); | ||
283 | } | ||
284 | |||
285 | static __inline unsigned int | ||
286 | get_Opcode_X0(tilepro_bundle_bits num) | ||
287 | { | ||
288 | const unsigned int n = (unsigned int)num; | ||
289 | return (((n >> 28)) & 0x7); | ||
290 | } | ||
291 | |||
292 | static __inline unsigned int | ||
293 | get_Opcode_X1(tilepro_bundle_bits n) | ||
294 | { | ||
295 | return (((unsigned int)(n >> 59)) & 0xf); | ||
296 | } | ||
297 | |||
298 | static __inline unsigned int | ||
299 | get_Opcode_Y0(tilepro_bundle_bits num) | ||
300 | { | ||
301 | const unsigned int n = (unsigned int)num; | ||
302 | return (((n >> 27)) & 0xf); | ||
303 | } | ||
304 | |||
305 | static __inline unsigned int | ||
306 | get_Opcode_Y1(tilepro_bundle_bits n) | ||
307 | { | ||
308 | return (((unsigned int)(n >> 59)) & 0xf); | ||
309 | } | ||
310 | |||
311 | static __inline unsigned int | ||
312 | get_Opcode_Y2(tilepro_bundle_bits n) | ||
313 | { | ||
314 | return (((unsigned int)(n >> 56)) & 0x7); | ||
315 | } | ||
316 | |||
317 | static __inline unsigned int | ||
318 | get_RROpcodeExtension_SN(tilepro_bundle_bits num) | ||
319 | { | ||
320 | const unsigned int n = (unsigned int)num; | ||
321 | return (((n >> 4)) & 0xf); | ||
322 | } | ||
323 | |||
324 | static __inline unsigned int | ||
325 | get_RRROpcodeExtension_X0(tilepro_bundle_bits num) | ||
326 | { | ||
327 | const unsigned int n = (unsigned int)num; | ||
328 | return (((n >> 18)) & 0x1ff); | ||
329 | } | ||
330 | |||
331 | static __inline unsigned int | ||
332 | get_RRROpcodeExtension_X1(tilepro_bundle_bits n) | ||
333 | { | ||
334 | return (((unsigned int)(n >> 49)) & 0x1ff); | ||
335 | } | ||
336 | |||
337 | static __inline unsigned int | ||
338 | get_RRROpcodeExtension_Y0(tilepro_bundle_bits num) | ||
339 | { | ||
340 | const unsigned int n = (unsigned int)num; | ||
341 | return (((n >> 18)) & 0x3); | ||
342 | } | ||
343 | |||
344 | static __inline unsigned int | ||
345 | get_RRROpcodeExtension_Y1(tilepro_bundle_bits n) | ||
346 | { | ||
347 | return (((unsigned int)(n >> 49)) & 0x3); | ||
348 | } | ||
349 | |||
350 | static __inline unsigned int | ||
351 | get_RouteOpcodeExtension_SN(tilepro_bundle_bits num) | ||
352 | { | ||
353 | const unsigned int n = (unsigned int)num; | ||
354 | return (((n >> 0)) & 0x3ff); | ||
355 | } | ||
356 | |||
357 | static __inline unsigned int | ||
358 | get_S_X0(tilepro_bundle_bits num) | ||
359 | { | ||
360 | const unsigned int n = (unsigned int)num; | ||
361 | return (((n >> 27)) & 0x1); | ||
362 | } | ||
363 | |||
364 | static __inline unsigned int | ||
365 | get_S_X1(tilepro_bundle_bits n) | ||
366 | { | ||
367 | return (((unsigned int)(n >> 58)) & 0x1); | ||
368 | } | ||
369 | |||
370 | static __inline unsigned int | ||
371 | get_ShAmt_X0(tilepro_bundle_bits num) | ||
372 | { | ||
373 | const unsigned int n = (unsigned int)num; | ||
374 | return (((n >> 12)) & 0x1f); | ||
375 | } | ||
376 | |||
377 | static __inline unsigned int | ||
378 | get_ShAmt_X1(tilepro_bundle_bits n) | ||
379 | { | ||
380 | return (((unsigned int)(n >> 43)) & 0x1f); | ||
381 | } | ||
382 | |||
383 | static __inline unsigned int | ||
384 | get_ShAmt_Y0(tilepro_bundle_bits num) | ||
385 | { | ||
386 | const unsigned int n = (unsigned int)num; | ||
387 | return (((n >> 12)) & 0x1f); | ||
388 | } | ||
389 | |||
390 | static __inline unsigned int | ||
391 | get_ShAmt_Y1(tilepro_bundle_bits n) | ||
392 | { | ||
393 | return (((unsigned int)(n >> 43)) & 0x1f); | ||
394 | } | ||
395 | |||
396 | static __inline unsigned int | ||
397 | get_SrcA_X0(tilepro_bundle_bits num) | ||
398 | { | ||
399 | const unsigned int n = (unsigned int)num; | ||
400 | return (((n >> 6)) & 0x3f); | ||
401 | } | ||
402 | |||
403 | static __inline unsigned int | ||
404 | get_SrcA_X1(tilepro_bundle_bits n) | ||
405 | { | ||
406 | return (((unsigned int)(n >> 37)) & 0x3f); | ||
407 | } | ||
408 | |||
409 | static __inline unsigned int | ||
410 | get_SrcA_Y0(tilepro_bundle_bits num) | ||
411 | { | ||
412 | const unsigned int n = (unsigned int)num; | ||
413 | return (((n >> 6)) & 0x3f); | ||
414 | } | ||
415 | |||
416 | static __inline unsigned int | ||
417 | get_SrcA_Y1(tilepro_bundle_bits n) | ||
418 | { | ||
419 | return (((unsigned int)(n >> 37)) & 0x3f); | ||
420 | } | ||
421 | |||
422 | static __inline unsigned int | ||
423 | get_SrcA_Y2(tilepro_bundle_bits n) | ||
424 | { | ||
425 | return (((n >> 26)) & 0x00000001) | | ||
426 | (((unsigned int)(n >> 50)) & 0x0000003e); | ||
427 | } | ||
428 | |||
429 | static __inline unsigned int | ||
430 | get_SrcBDest_Y2(tilepro_bundle_bits num) | ||
431 | { | ||
432 | const unsigned int n = (unsigned int)num; | ||
433 | return (((n >> 20)) & 0x3f); | ||
434 | } | ||
435 | |||
436 | static __inline unsigned int | ||
437 | get_SrcB_X0(tilepro_bundle_bits num) | ||
438 | { | ||
439 | const unsigned int n = (unsigned int)num; | ||
440 | return (((n >> 12)) & 0x3f); | ||
441 | } | ||
442 | |||
443 | static __inline unsigned int | ||
444 | get_SrcB_X1(tilepro_bundle_bits n) | ||
445 | { | ||
446 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
447 | } | ||
448 | |||
449 | static __inline unsigned int | ||
450 | get_SrcB_Y0(tilepro_bundle_bits num) | ||
451 | { | ||
452 | const unsigned int n = (unsigned int)num; | ||
453 | return (((n >> 12)) & 0x3f); | ||
454 | } | ||
455 | |||
456 | static __inline unsigned int | ||
457 | get_SrcB_Y1(tilepro_bundle_bits n) | ||
458 | { | ||
459 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
460 | } | ||
461 | |||
462 | static __inline unsigned int | ||
463 | get_Src_SN(tilepro_bundle_bits num) | ||
464 | { | ||
465 | const unsigned int n = (unsigned int)num; | ||
466 | return (((n >> 0)) & 0x3); | ||
467 | } | ||
468 | |||
469 | static __inline unsigned int | ||
470 | get_UnOpcodeExtension_X0(tilepro_bundle_bits num) | ||
471 | { | ||
472 | const unsigned int n = (unsigned int)num; | ||
473 | return (((n >> 12)) & 0x1f); | ||
474 | } | ||
475 | |||
476 | static __inline unsigned int | ||
477 | get_UnOpcodeExtension_X1(tilepro_bundle_bits n) | ||
478 | { | ||
479 | return (((unsigned int)(n >> 43)) & 0x1f); | ||
480 | } | ||
481 | |||
482 | static __inline unsigned int | ||
483 | get_UnOpcodeExtension_Y0(tilepro_bundle_bits num) | ||
484 | { | ||
485 | const unsigned int n = (unsigned int)num; | ||
486 | return (((n >> 12)) & 0x1f); | ||
487 | } | ||
488 | |||
489 | static __inline unsigned int | ||
490 | get_UnOpcodeExtension_Y1(tilepro_bundle_bits n) | ||
491 | { | ||
492 | return (((unsigned int)(n >> 43)) & 0x1f); | ||
493 | } | ||
494 | |||
495 | static __inline unsigned int | ||
496 | get_UnShOpcodeExtension_X0(tilepro_bundle_bits num) | ||
497 | { | ||
498 | const unsigned int n = (unsigned int)num; | ||
499 | return (((n >> 17)) & 0x3ff); | ||
500 | } | ||
501 | |||
502 | static __inline unsigned int | ||
503 | get_UnShOpcodeExtension_X1(tilepro_bundle_bits n) | ||
504 | { | ||
505 | return (((unsigned int)(n >> 48)) & 0x3ff); | ||
506 | } | ||
507 | |||
508 | static __inline unsigned int | ||
509 | get_UnShOpcodeExtension_Y0(tilepro_bundle_bits num) | ||
510 | { | ||
511 | const unsigned int n = (unsigned int)num; | ||
512 | return (((n >> 17)) & 0x7); | ||
513 | } | ||
514 | |||
515 | static __inline unsigned int | ||
516 | get_UnShOpcodeExtension_Y1(tilepro_bundle_bits n) | ||
517 | { | ||
518 | return (((unsigned int)(n >> 48)) & 0x7); | ||
519 | } | ||
520 | |||
521 | |||
522 | static __inline int | ||
523 | sign_extend(int n, int num_bits) | ||
524 | { | ||
525 | int shift = (int)(sizeof(int) * 8 - num_bits); | ||
526 | return (n << shift) >> shift; | ||
527 | } | ||
528 | |||
529 | |||
530 | |||
531 | static __inline tilepro_bundle_bits | ||
532 | create_BrOff_SN(int num) | ||
533 | { | ||
534 | const unsigned int n = (unsigned int)num; | ||
535 | return ((n & 0x3ff) << 0); | ||
536 | } | ||
537 | |||
538 | static __inline tilepro_bundle_bits | ||
539 | create_BrOff_X1(int num) | ||
540 | { | ||
541 | const unsigned int n = (unsigned int)num; | ||
542 | return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) | | ||
543 | (((tilepro_bundle_bits)(n & 0x00018000)) << 20); | ||
544 | } | ||
545 | |||
546 | static __inline tilepro_bundle_bits | ||
547 | create_BrType_X1(int num) | ||
548 | { | ||
549 | const unsigned int n = (unsigned int)num; | ||
550 | return (((tilepro_bundle_bits)(n & 0xf)) << 31); | ||
551 | } | ||
552 | |||
553 | static __inline tilepro_bundle_bits | ||
554 | create_Dest_Imm8_X1(int num) | ||
555 | { | ||
556 | const unsigned int n = (unsigned int)num; | ||
557 | return (((tilepro_bundle_bits)(n & 0x0000003f)) << 31) | | ||
558 | (((tilepro_bundle_bits)(n & 0x000000c0)) << 43); | ||
559 | } | ||
560 | |||
561 | static __inline tilepro_bundle_bits | ||
562 | create_Dest_SN(int num) | ||
563 | { | ||
564 | const unsigned int n = (unsigned int)num; | ||
565 | return ((n & 0x3) << 2); | ||
566 | } | ||
567 | |||
568 | static __inline tilepro_bundle_bits | ||
569 | create_Dest_X0(int num) | ||
570 | { | ||
571 | const unsigned int n = (unsigned int)num; | ||
572 | return ((n & 0x3f) << 0); | ||
573 | } | ||
574 | |||
575 | static __inline tilepro_bundle_bits | ||
576 | create_Dest_X1(int num) | ||
577 | { | ||
578 | const unsigned int n = (unsigned int)num; | ||
579 | return (((tilepro_bundle_bits)(n & 0x3f)) << 31); | ||
580 | } | ||
581 | |||
582 | static __inline tilepro_bundle_bits | ||
583 | create_Dest_Y0(int num) | ||
584 | { | ||
585 | const unsigned int n = (unsigned int)num; | ||
586 | return ((n & 0x3f) << 0); | ||
587 | } | ||
588 | |||
589 | static __inline tilepro_bundle_bits | ||
590 | create_Dest_Y1(int num) | ||
591 | { | ||
592 | const unsigned int n = (unsigned int)num; | ||
593 | return (((tilepro_bundle_bits)(n & 0x3f)) << 31); | ||
594 | } | ||
595 | |||
596 | static __inline tilepro_bundle_bits | ||
597 | create_Imm16_X0(int num) | ||
598 | { | ||
599 | const unsigned int n = (unsigned int)num; | ||
600 | return ((n & 0xffff) << 12); | ||
601 | } | ||
602 | |||
603 | static __inline tilepro_bundle_bits | ||
604 | create_Imm16_X1(int num) | ||
605 | { | ||
606 | const unsigned int n = (unsigned int)num; | ||
607 | return (((tilepro_bundle_bits)(n & 0xffff)) << 43); | ||
608 | } | ||
609 | |||
610 | static __inline tilepro_bundle_bits | ||
611 | create_Imm8_SN(int num) | ||
612 | { | ||
613 | const unsigned int n = (unsigned int)num; | ||
614 | return ((n & 0xff) << 0); | ||
615 | } | ||
616 | |||
617 | static __inline tilepro_bundle_bits | ||
618 | create_Imm8_X0(int num) | ||
619 | { | ||
620 | const unsigned int n = (unsigned int)num; | ||
621 | return ((n & 0xff) << 12); | ||
622 | } | ||
623 | |||
624 | static __inline tilepro_bundle_bits | ||
625 | create_Imm8_X1(int num) | ||
626 | { | ||
627 | const unsigned int n = (unsigned int)num; | ||
628 | return (((tilepro_bundle_bits)(n & 0xff)) << 43); | ||
629 | } | ||
630 | |||
631 | static __inline tilepro_bundle_bits | ||
632 | create_Imm8_Y0(int num) | ||
633 | { | ||
634 | const unsigned int n = (unsigned int)num; | ||
635 | return ((n & 0xff) << 12); | ||
636 | } | ||
637 | |||
638 | static __inline tilepro_bundle_bits | ||
639 | create_Imm8_Y1(int num) | ||
640 | { | ||
641 | const unsigned int n = (unsigned int)num; | ||
642 | return (((tilepro_bundle_bits)(n & 0xff)) << 43); | ||
643 | } | ||
644 | |||
645 | static __inline tilepro_bundle_bits | ||
646 | create_ImmOpcodeExtension_X0(int num) | ||
647 | { | ||
648 | const unsigned int n = (unsigned int)num; | ||
649 | return ((n & 0x7f) << 20); | ||
650 | } | ||
651 | |||
652 | static __inline tilepro_bundle_bits | ||
653 | create_ImmOpcodeExtension_X1(int num) | ||
654 | { | ||
655 | const unsigned int n = (unsigned int)num; | ||
656 | return (((tilepro_bundle_bits)(n & 0x7f)) << 51); | ||
657 | } | ||
658 | |||
659 | static __inline tilepro_bundle_bits | ||
660 | create_ImmRROpcodeExtension_SN(int num) | ||
661 | { | ||
662 | const unsigned int n = (unsigned int)num; | ||
663 | return ((n & 0x3) << 8); | ||
664 | } | ||
665 | |||
666 | static __inline tilepro_bundle_bits | ||
667 | create_JOffLong_X1(int num) | ||
668 | { | ||
669 | const unsigned int n = (unsigned int)num; | ||
670 | return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) | | ||
671 | (((tilepro_bundle_bits)(n & 0x00018000)) << 20) | | ||
672 | (((tilepro_bundle_bits)(n & 0x001e0000)) << 14) | | ||
673 | (((tilepro_bundle_bits)(n & 0x07e00000)) << 16) | | ||
674 | (((tilepro_bundle_bits)(n & 0x18000000)) << 31); | ||
675 | } | ||
676 | |||
677 | static __inline tilepro_bundle_bits | ||
678 | create_JOff_X1(int num) | ||
679 | { | ||
680 | const unsigned int n = (unsigned int)num; | ||
681 | return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) | | ||
682 | (((tilepro_bundle_bits)(n & 0x00018000)) << 20) | | ||
683 | (((tilepro_bundle_bits)(n & 0x001e0000)) << 14) | | ||
684 | (((tilepro_bundle_bits)(n & 0x07e00000)) << 16) | | ||
685 | (((tilepro_bundle_bits)(n & 0x08000000)) << 31); | ||
686 | } | ||
687 | |||
688 | static __inline tilepro_bundle_bits | ||
689 | create_MF_Imm15_X1(int num) | ||
690 | { | ||
691 | const unsigned int n = (unsigned int)num; | ||
692 | return (((tilepro_bundle_bits)(n & 0x00003fff)) << 37) | | ||
693 | (((tilepro_bundle_bits)(n & 0x00004000)) << 44); | ||
694 | } | ||
695 | |||
696 | static __inline tilepro_bundle_bits | ||
697 | create_MMEnd_X0(int num) | ||
698 | { | ||
699 | const unsigned int n = (unsigned int)num; | ||
700 | return ((n & 0x1f) << 18); | ||
701 | } | ||
702 | |||
703 | static __inline tilepro_bundle_bits | ||
704 | create_MMEnd_X1(int num) | ||
705 | { | ||
706 | const unsigned int n = (unsigned int)num; | ||
707 | return (((tilepro_bundle_bits)(n & 0x1f)) << 49); | ||
708 | } | ||
709 | |||
710 | static __inline tilepro_bundle_bits | ||
711 | create_MMStart_X0(int num) | ||
712 | { | ||
713 | const unsigned int n = (unsigned int)num; | ||
714 | return ((n & 0x1f) << 23); | ||
715 | } | ||
716 | |||
717 | static __inline tilepro_bundle_bits | ||
718 | create_MMStart_X1(int num) | ||
719 | { | ||
720 | const unsigned int n = (unsigned int)num; | ||
721 | return (((tilepro_bundle_bits)(n & 0x1f)) << 54); | ||
722 | } | ||
723 | |||
724 | static __inline tilepro_bundle_bits | ||
725 | create_MT_Imm15_X1(int num) | ||
726 | { | ||
727 | const unsigned int n = (unsigned int)num; | ||
728 | return (((tilepro_bundle_bits)(n & 0x0000003f)) << 31) | | ||
729 | (((tilepro_bundle_bits)(n & 0x00003fc0)) << 37) | | ||
730 | (((tilepro_bundle_bits)(n & 0x00004000)) << 44); | ||
731 | } | ||
732 | |||
733 | static __inline tilepro_bundle_bits | ||
734 | create_Mode(int num) | ||
735 | { | ||
736 | const unsigned int n = (unsigned int)num; | ||
737 | return (((tilepro_bundle_bits)(n & 0x1)) << 63); | ||
738 | } | ||
739 | |||
740 | static __inline tilepro_bundle_bits | ||
741 | create_NoRegOpcodeExtension_SN(int num) | ||
742 | { | ||
743 | const unsigned int n = (unsigned int)num; | ||
744 | return ((n & 0xf) << 0); | ||
745 | } | ||
746 | |||
747 | static __inline tilepro_bundle_bits | ||
748 | create_Opcode_SN(int num) | ||
749 | { | ||
750 | const unsigned int n = (unsigned int)num; | ||
751 | return ((n & 0x3f) << 10); | ||
752 | } | ||
753 | |||
754 | static __inline tilepro_bundle_bits | ||
755 | create_Opcode_X0(int num) | ||
756 | { | ||
757 | const unsigned int n = (unsigned int)num; | ||
758 | return ((n & 0x7) << 28); | ||
759 | } | ||
760 | |||
761 | static __inline tilepro_bundle_bits | ||
762 | create_Opcode_X1(int num) | ||
763 | { | ||
764 | const unsigned int n = (unsigned int)num; | ||
765 | return (((tilepro_bundle_bits)(n & 0xf)) << 59); | ||
766 | } | ||
767 | |||
768 | static __inline tilepro_bundle_bits | ||
769 | create_Opcode_Y0(int num) | ||
770 | { | ||
771 | const unsigned int n = (unsigned int)num; | ||
772 | return ((n & 0xf) << 27); | ||
773 | } | ||
774 | |||
775 | static __inline tilepro_bundle_bits | ||
776 | create_Opcode_Y1(int num) | ||
777 | { | ||
778 | const unsigned int n = (unsigned int)num; | ||
779 | return (((tilepro_bundle_bits)(n & 0xf)) << 59); | ||
780 | } | ||
781 | |||
782 | static __inline tilepro_bundle_bits | ||
783 | create_Opcode_Y2(int num) | ||
784 | { | ||
785 | const unsigned int n = (unsigned int)num; | ||
786 | return (((tilepro_bundle_bits)(n & 0x7)) << 56); | ||
787 | } | ||
788 | |||
789 | static __inline tilepro_bundle_bits | ||
790 | create_RROpcodeExtension_SN(int num) | ||
791 | { | ||
792 | const unsigned int n = (unsigned int)num; | ||
793 | return ((n & 0xf) << 4); | ||
794 | } | ||
795 | |||
796 | static __inline tilepro_bundle_bits | ||
797 | create_RRROpcodeExtension_X0(int num) | ||
798 | { | ||
799 | const unsigned int n = (unsigned int)num; | ||
800 | return ((n & 0x1ff) << 18); | ||
801 | } | ||
802 | |||
803 | static __inline tilepro_bundle_bits | ||
804 | create_RRROpcodeExtension_X1(int num) | ||
805 | { | ||
806 | const unsigned int n = (unsigned int)num; | ||
807 | return (((tilepro_bundle_bits)(n & 0x1ff)) << 49); | ||
808 | } | ||
809 | |||
810 | static __inline tilepro_bundle_bits | ||
811 | create_RRROpcodeExtension_Y0(int num) | ||
812 | { | ||
813 | const unsigned int n = (unsigned int)num; | ||
814 | return ((n & 0x3) << 18); | ||
815 | } | ||
816 | |||
817 | static __inline tilepro_bundle_bits | ||
818 | create_RRROpcodeExtension_Y1(int num) | ||
819 | { | ||
820 | const unsigned int n = (unsigned int)num; | ||
821 | return (((tilepro_bundle_bits)(n & 0x3)) << 49); | ||
822 | } | ||
823 | |||
824 | static __inline tilepro_bundle_bits | ||
825 | create_RouteOpcodeExtension_SN(int num) | ||
826 | { | ||
827 | const unsigned int n = (unsigned int)num; | ||
828 | return ((n & 0x3ff) << 0); | ||
829 | } | ||
830 | |||
831 | static __inline tilepro_bundle_bits | ||
832 | create_S_X0(int num) | ||
833 | { | ||
834 | const unsigned int n = (unsigned int)num; | ||
835 | return ((n & 0x1) << 27); | ||
836 | } | ||
837 | |||
838 | static __inline tilepro_bundle_bits | ||
839 | create_S_X1(int num) | ||
840 | { | ||
841 | const unsigned int n = (unsigned int)num; | ||
842 | return (((tilepro_bundle_bits)(n & 0x1)) << 58); | ||
843 | } | ||
844 | |||
845 | static __inline tilepro_bundle_bits | ||
846 | create_ShAmt_X0(int num) | ||
847 | { | ||
848 | const unsigned int n = (unsigned int)num; | ||
849 | return ((n & 0x1f) << 12); | ||
850 | } | ||
851 | |||
852 | static __inline tilepro_bundle_bits | ||
853 | create_ShAmt_X1(int num) | ||
854 | { | ||
855 | const unsigned int n = (unsigned int)num; | ||
856 | return (((tilepro_bundle_bits)(n & 0x1f)) << 43); | ||
857 | } | ||
858 | |||
859 | static __inline tilepro_bundle_bits | ||
860 | create_ShAmt_Y0(int num) | ||
861 | { | ||
862 | const unsigned int n = (unsigned int)num; | ||
863 | return ((n & 0x1f) << 12); | ||
864 | } | ||
865 | |||
866 | static __inline tilepro_bundle_bits | ||
867 | create_ShAmt_Y1(int num) | ||
868 | { | ||
869 | const unsigned int n = (unsigned int)num; | ||
870 | return (((tilepro_bundle_bits)(n & 0x1f)) << 43); | ||
871 | } | ||
872 | |||
873 | static __inline tilepro_bundle_bits | ||
874 | create_SrcA_X0(int num) | ||
875 | { | ||
876 | const unsigned int n = (unsigned int)num; | ||
877 | return ((n & 0x3f) << 6); | ||
878 | } | ||
879 | |||
880 | static __inline tilepro_bundle_bits | ||
881 | create_SrcA_X1(int num) | ||
882 | { | ||
883 | const unsigned int n = (unsigned int)num; | ||
884 | return (((tilepro_bundle_bits)(n & 0x3f)) << 37); | ||
885 | } | ||
886 | |||
887 | static __inline tilepro_bundle_bits | ||
888 | create_SrcA_Y0(int num) | ||
889 | { | ||
890 | const unsigned int n = (unsigned int)num; | ||
891 | return ((n & 0x3f) << 6); | ||
892 | } | ||
893 | |||
894 | static __inline tilepro_bundle_bits | ||
895 | create_SrcA_Y1(int num) | ||
896 | { | ||
897 | const unsigned int n = (unsigned int)num; | ||
898 | return (((tilepro_bundle_bits)(n & 0x3f)) << 37); | ||
899 | } | ||
900 | |||
901 | static __inline tilepro_bundle_bits | ||
902 | create_SrcA_Y2(int num) | ||
903 | { | ||
904 | const unsigned int n = (unsigned int)num; | ||
905 | return ((n & 0x00000001) << 26) | | ||
906 | (((tilepro_bundle_bits)(n & 0x0000003e)) << 50); | ||
907 | } | ||
908 | |||
909 | static __inline tilepro_bundle_bits | ||
910 | create_SrcBDest_Y2(int num) | ||
911 | { | ||
912 | const unsigned int n = (unsigned int)num; | ||
913 | return ((n & 0x3f) << 20); | ||
914 | } | ||
915 | |||
916 | static __inline tilepro_bundle_bits | ||
917 | create_SrcB_X0(int num) | ||
918 | { | ||
919 | const unsigned int n = (unsigned int)num; | ||
920 | return ((n & 0x3f) << 12); | ||
921 | } | ||
922 | |||
923 | static __inline tilepro_bundle_bits | ||
924 | create_SrcB_X1(int num) | ||
925 | { | ||
926 | const unsigned int n = (unsigned int)num; | ||
927 | return (((tilepro_bundle_bits)(n & 0x3f)) << 43); | ||
928 | } | ||
929 | |||
930 | static __inline tilepro_bundle_bits | ||
931 | create_SrcB_Y0(int num) | ||
932 | { | ||
933 | const unsigned int n = (unsigned int)num; | ||
934 | return ((n & 0x3f) << 12); | ||
935 | } | ||
936 | |||
937 | static __inline tilepro_bundle_bits | ||
938 | create_SrcB_Y1(int num) | ||
939 | { | ||
940 | const unsigned int n = (unsigned int)num; | ||
941 | return (((tilepro_bundle_bits)(n & 0x3f)) << 43); | ||
942 | } | ||
943 | |||
944 | static __inline tilepro_bundle_bits | ||
945 | create_Src_SN(int num) | ||
946 | { | ||
947 | const unsigned int n = (unsigned int)num; | ||
948 | return ((n & 0x3) << 0); | ||
949 | } | ||
950 | |||
951 | static __inline tilepro_bundle_bits | ||
952 | create_UnOpcodeExtension_X0(int num) | ||
953 | { | ||
954 | const unsigned int n = (unsigned int)num; | ||
955 | return ((n & 0x1f) << 12); | ||
956 | } | ||
957 | |||
958 | static __inline tilepro_bundle_bits | ||
959 | create_UnOpcodeExtension_X1(int num) | ||
960 | { | ||
961 | const unsigned int n = (unsigned int)num; | ||
962 | return (((tilepro_bundle_bits)(n & 0x1f)) << 43); | ||
963 | } | ||
964 | |||
965 | static __inline tilepro_bundle_bits | ||
966 | create_UnOpcodeExtension_Y0(int num) | ||
967 | { | ||
968 | const unsigned int n = (unsigned int)num; | ||
969 | return ((n & 0x1f) << 12); | ||
970 | } | ||
971 | |||
972 | static __inline tilepro_bundle_bits | ||
973 | create_UnOpcodeExtension_Y1(int num) | ||
974 | { | ||
975 | const unsigned int n = (unsigned int)num; | ||
976 | return (((tilepro_bundle_bits)(n & 0x1f)) << 43); | ||
977 | } | ||
978 | |||
979 | static __inline tilepro_bundle_bits | ||
980 | create_UnShOpcodeExtension_X0(int num) | ||
981 | { | ||
982 | const unsigned int n = (unsigned int)num; | ||
983 | return ((n & 0x3ff) << 17); | ||
984 | } | ||
985 | |||
986 | static __inline tilepro_bundle_bits | ||
987 | create_UnShOpcodeExtension_X1(int num) | ||
988 | { | ||
989 | const unsigned int n = (unsigned int)num; | ||
990 | return (((tilepro_bundle_bits)(n & 0x3ff)) << 48); | ||
991 | } | ||
992 | |||
993 | static __inline tilepro_bundle_bits | ||
994 | create_UnShOpcodeExtension_Y0(int num) | ||
995 | { | ||
996 | const unsigned int n = (unsigned int)num; | ||
997 | return ((n & 0x7) << 17); | ||
998 | } | ||
999 | |||
1000 | static __inline tilepro_bundle_bits | ||
1001 | create_UnShOpcodeExtension_Y1(int num) | ||
1002 | { | ||
1003 | const unsigned int n = (unsigned int)num; | ||
1004 | return (((tilepro_bundle_bits)(n & 0x7)) << 48); | ||
1005 | } | ||
1006 | |||
1007 | |||
1008 | enum | ||
1009 | { | ||
1010 | ADDBS_U_SPECIAL_0_OPCODE_X0 = 98, | ||
1011 | ADDBS_U_SPECIAL_0_OPCODE_X1 = 68, | ||
1012 | ADDB_SPECIAL_0_OPCODE_X0 = 1, | ||
1013 | ADDB_SPECIAL_0_OPCODE_X1 = 1, | ||
1014 | ADDHS_SPECIAL_0_OPCODE_X0 = 99, | ||
1015 | ADDHS_SPECIAL_0_OPCODE_X1 = 69, | ||
1016 | ADDH_SPECIAL_0_OPCODE_X0 = 2, | ||
1017 | ADDH_SPECIAL_0_OPCODE_X1 = 2, | ||
1018 | ADDIB_IMM_0_OPCODE_X0 = 1, | ||
1019 | ADDIB_IMM_0_OPCODE_X1 = 1, | ||
1020 | ADDIH_IMM_0_OPCODE_X0 = 2, | ||
1021 | ADDIH_IMM_0_OPCODE_X1 = 2, | ||
1022 | ADDI_IMM_0_OPCODE_X0 = 3, | ||
1023 | ADDI_IMM_0_OPCODE_X1 = 3, | ||
1024 | ADDI_IMM_1_OPCODE_SN = 1, | ||
1025 | ADDI_OPCODE_Y0 = 9, | ||
1026 | ADDI_OPCODE_Y1 = 7, | ||
1027 | ADDLIS_OPCODE_X0 = 1, | ||
1028 | ADDLIS_OPCODE_X1 = 2, | ||
1029 | ADDLI_OPCODE_X0 = 2, | ||
1030 | ADDLI_OPCODE_X1 = 3, | ||
1031 | ADDS_SPECIAL_0_OPCODE_X0 = 96, | ||
1032 | ADDS_SPECIAL_0_OPCODE_X1 = 66, | ||
1033 | ADD_SPECIAL_0_OPCODE_X0 = 3, | ||
1034 | ADD_SPECIAL_0_OPCODE_X1 = 3, | ||
1035 | ADD_SPECIAL_0_OPCODE_Y0 = 0, | ||
1036 | ADD_SPECIAL_0_OPCODE_Y1 = 0, | ||
1037 | ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4, | ||
1038 | ADIFFH_SPECIAL_0_OPCODE_X0 = 5, | ||
1039 | ANDI_IMM_0_OPCODE_X0 = 1, | ||
1040 | ANDI_IMM_0_OPCODE_X1 = 4, | ||
1041 | ANDI_OPCODE_Y0 = 10, | ||
1042 | ANDI_OPCODE_Y1 = 8, | ||
1043 | AND_SPECIAL_0_OPCODE_X0 = 6, | ||
1044 | AND_SPECIAL_0_OPCODE_X1 = 4, | ||
1045 | AND_SPECIAL_2_OPCODE_Y0 = 0, | ||
1046 | AND_SPECIAL_2_OPCODE_Y1 = 0, | ||
1047 | AULI_OPCODE_X0 = 3, | ||
1048 | AULI_OPCODE_X1 = 4, | ||
1049 | AVGB_U_SPECIAL_0_OPCODE_X0 = 7, | ||
1050 | AVGH_SPECIAL_0_OPCODE_X0 = 8, | ||
1051 | BBNST_BRANCH_OPCODE_X1 = 15, | ||
1052 | BBNS_BRANCH_OPCODE_X1 = 14, | ||
1053 | BBNS_OPCODE_SN = 63, | ||
1054 | BBST_BRANCH_OPCODE_X1 = 13, | ||
1055 | BBS_BRANCH_OPCODE_X1 = 12, | ||
1056 | BBS_OPCODE_SN = 62, | ||
1057 | BGEZT_BRANCH_OPCODE_X1 = 7, | ||
1058 | BGEZ_BRANCH_OPCODE_X1 = 6, | ||
1059 | BGEZ_OPCODE_SN = 61, | ||
1060 | BGZT_BRANCH_OPCODE_X1 = 5, | ||
1061 | BGZ_BRANCH_OPCODE_X1 = 4, | ||
1062 | BGZ_OPCODE_SN = 58, | ||
1063 | BITX_UN_0_SHUN_0_OPCODE_X0 = 1, | ||
1064 | BITX_UN_0_SHUN_0_OPCODE_Y0 = 1, | ||
1065 | BLEZT_BRANCH_OPCODE_X1 = 11, | ||
1066 | BLEZ_BRANCH_OPCODE_X1 = 10, | ||
1067 | BLEZ_OPCODE_SN = 59, | ||
1068 | BLZT_BRANCH_OPCODE_X1 = 9, | ||
1069 | BLZ_BRANCH_OPCODE_X1 = 8, | ||
1070 | BLZ_OPCODE_SN = 60, | ||
1071 | BNZT_BRANCH_OPCODE_X1 = 3, | ||
1072 | BNZ_BRANCH_OPCODE_X1 = 2, | ||
1073 | BNZ_OPCODE_SN = 57, | ||
1074 | BPT_NOREG_RR_IMM_0_OPCODE_SN = 1, | ||
1075 | BRANCH_OPCODE_X1 = 5, | ||
1076 | BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2, | ||
1077 | BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2, | ||
1078 | BZT_BRANCH_OPCODE_X1 = 1, | ||
1079 | BZ_BRANCH_OPCODE_X1 = 0, | ||
1080 | BZ_OPCODE_SN = 56, | ||
1081 | CLZ_UN_0_SHUN_0_OPCODE_X0 = 3, | ||
1082 | CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3, | ||
1083 | CRC32_32_SPECIAL_0_OPCODE_X0 = 9, | ||
1084 | CRC32_8_SPECIAL_0_OPCODE_X0 = 10, | ||
1085 | CTZ_UN_0_SHUN_0_OPCODE_X0 = 4, | ||
1086 | CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4, | ||
1087 | DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1, | ||
1088 | DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2, | ||
1089 | DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95, | ||
1090 | FINV_UN_0_SHUN_0_OPCODE_X1 = 3, | ||
1091 | FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4, | ||
1092 | FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3, | ||
1093 | FNOP_UN_0_SHUN_0_OPCODE_X0 = 5, | ||
1094 | FNOP_UN_0_SHUN_0_OPCODE_X1 = 5, | ||
1095 | FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5, | ||
1096 | FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1, | ||
1097 | HALT_NOREG_RR_IMM_0_OPCODE_SN = 0, | ||
1098 | ICOH_UN_0_SHUN_0_OPCODE_X1 = 6, | ||
1099 | ILL_UN_0_SHUN_0_OPCODE_X1 = 7, | ||
1100 | ILL_UN_0_SHUN_0_OPCODE_Y1 = 2, | ||
1101 | IMM_0_OPCODE_SN = 0, | ||
1102 | IMM_0_OPCODE_X0 = 4, | ||
1103 | IMM_0_OPCODE_X1 = 6, | ||
1104 | IMM_1_OPCODE_SN = 1, | ||
1105 | IMM_OPCODE_0_X0 = 5, | ||
1106 | INTHB_SPECIAL_0_OPCODE_X0 = 11, | ||
1107 | INTHB_SPECIAL_0_OPCODE_X1 = 5, | ||
1108 | INTHH_SPECIAL_0_OPCODE_X0 = 12, | ||
1109 | INTHH_SPECIAL_0_OPCODE_X1 = 6, | ||
1110 | INTLB_SPECIAL_0_OPCODE_X0 = 13, | ||
1111 | INTLB_SPECIAL_0_OPCODE_X1 = 7, | ||
1112 | INTLH_SPECIAL_0_OPCODE_X0 = 14, | ||
1113 | INTLH_SPECIAL_0_OPCODE_X1 = 8, | ||
1114 | INV_UN_0_SHUN_0_OPCODE_X1 = 8, | ||
1115 | IRET_UN_0_SHUN_0_OPCODE_X1 = 9, | ||
1116 | JALB_OPCODE_X1 = 13, | ||
1117 | JALF_OPCODE_X1 = 12, | ||
1118 | JALRP_SPECIAL_0_OPCODE_X1 = 9, | ||
1119 | JALRR_IMM_1_OPCODE_SN = 3, | ||
1120 | JALR_RR_IMM_0_OPCODE_SN = 5, | ||
1121 | JALR_SPECIAL_0_OPCODE_X1 = 10, | ||
1122 | JB_OPCODE_X1 = 11, | ||
1123 | JF_OPCODE_X1 = 10, | ||
1124 | JRP_SPECIAL_0_OPCODE_X1 = 11, | ||
1125 | JRR_IMM_1_OPCODE_SN = 2, | ||
1126 | JR_RR_IMM_0_OPCODE_SN = 4, | ||
1127 | JR_SPECIAL_0_OPCODE_X1 = 12, | ||
1128 | LBADD_IMM_0_OPCODE_X1 = 22, | ||
1129 | LBADD_U_IMM_0_OPCODE_X1 = 23, | ||
1130 | LB_OPCODE_Y2 = 0, | ||
1131 | LB_UN_0_SHUN_0_OPCODE_X1 = 10, | ||
1132 | LB_U_OPCODE_Y2 = 1, | ||
1133 | LB_U_UN_0_SHUN_0_OPCODE_X1 = 11, | ||
1134 | LHADD_IMM_0_OPCODE_X1 = 24, | ||
1135 | LHADD_U_IMM_0_OPCODE_X1 = 25, | ||
1136 | LH_OPCODE_Y2 = 2, | ||
1137 | LH_UN_0_SHUN_0_OPCODE_X1 = 12, | ||
1138 | LH_U_OPCODE_Y2 = 3, | ||
1139 | LH_U_UN_0_SHUN_0_OPCODE_X1 = 13, | ||
1140 | LNK_SPECIAL_0_OPCODE_X1 = 13, | ||
1141 | LWADD_IMM_0_OPCODE_X1 = 26, | ||
1142 | LWADD_NA_IMM_0_OPCODE_X1 = 27, | ||
1143 | LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24, | ||
1144 | LW_OPCODE_Y2 = 4, | ||
1145 | LW_UN_0_SHUN_0_OPCODE_X1 = 14, | ||
1146 | MAXB_U_SPECIAL_0_OPCODE_X0 = 15, | ||
1147 | MAXB_U_SPECIAL_0_OPCODE_X1 = 14, | ||
1148 | MAXH_SPECIAL_0_OPCODE_X0 = 16, | ||
1149 | MAXH_SPECIAL_0_OPCODE_X1 = 15, | ||
1150 | MAXIB_U_IMM_0_OPCODE_X0 = 4, | ||
1151 | MAXIB_U_IMM_0_OPCODE_X1 = 5, | ||
1152 | MAXIH_IMM_0_OPCODE_X0 = 5, | ||
1153 | MAXIH_IMM_0_OPCODE_X1 = 6, | ||
1154 | MFSPR_IMM_0_OPCODE_X1 = 7, | ||
1155 | MF_UN_0_SHUN_0_OPCODE_X1 = 15, | ||
1156 | MINB_U_SPECIAL_0_OPCODE_X0 = 17, | ||
1157 | MINB_U_SPECIAL_0_OPCODE_X1 = 16, | ||
1158 | MINH_SPECIAL_0_OPCODE_X0 = 18, | ||
1159 | MINH_SPECIAL_0_OPCODE_X1 = 17, | ||
1160 | MINIB_U_IMM_0_OPCODE_X0 = 6, | ||
1161 | MINIB_U_IMM_0_OPCODE_X1 = 8, | ||
1162 | MINIH_IMM_0_OPCODE_X0 = 7, | ||
1163 | MINIH_IMM_0_OPCODE_X1 = 9, | ||
1164 | MM_OPCODE_X0 = 6, | ||
1165 | MM_OPCODE_X1 = 7, | ||
1166 | MNZB_SPECIAL_0_OPCODE_X0 = 19, | ||
1167 | MNZB_SPECIAL_0_OPCODE_X1 = 18, | ||
1168 | MNZH_SPECIAL_0_OPCODE_X0 = 20, | ||
1169 | MNZH_SPECIAL_0_OPCODE_X1 = 19, | ||
1170 | MNZ_SPECIAL_0_OPCODE_X0 = 21, | ||
1171 | MNZ_SPECIAL_0_OPCODE_X1 = 20, | ||
1172 | MNZ_SPECIAL_1_OPCODE_Y0 = 0, | ||
1173 | MNZ_SPECIAL_1_OPCODE_Y1 = 1, | ||
1174 | MOVEI_IMM_1_OPCODE_SN = 0, | ||
1175 | MOVE_RR_IMM_0_OPCODE_SN = 8, | ||
1176 | MTSPR_IMM_0_OPCODE_X1 = 10, | ||
1177 | MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22, | ||
1178 | MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0, | ||
1179 | MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23, | ||
1180 | MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24, | ||
1181 | MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1, | ||
1182 | MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25, | ||
1183 | MULHH_SS_SPECIAL_0_OPCODE_X0 = 26, | ||
1184 | MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0, | ||
1185 | MULHH_SU_SPECIAL_0_OPCODE_X0 = 27, | ||
1186 | MULHH_UU_SPECIAL_0_OPCODE_X0 = 28, | ||
1187 | MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1, | ||
1188 | MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29, | ||
1189 | MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30, | ||
1190 | MULHLA_US_SPECIAL_0_OPCODE_X0 = 31, | ||
1191 | MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32, | ||
1192 | MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33, | ||
1193 | MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0, | ||
1194 | MULHL_SS_SPECIAL_0_OPCODE_X0 = 34, | ||
1195 | MULHL_SU_SPECIAL_0_OPCODE_X0 = 35, | ||
1196 | MULHL_US_SPECIAL_0_OPCODE_X0 = 36, | ||
1197 | MULHL_UU_SPECIAL_0_OPCODE_X0 = 37, | ||
1198 | MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38, | ||
1199 | MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2, | ||
1200 | MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39, | ||
1201 | MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40, | ||
1202 | MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3, | ||
1203 | MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41, | ||
1204 | MULLL_SS_SPECIAL_0_OPCODE_X0 = 42, | ||
1205 | MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2, | ||
1206 | MULLL_SU_SPECIAL_0_OPCODE_X0 = 43, | ||
1207 | MULLL_UU_SPECIAL_0_OPCODE_X0 = 44, | ||
1208 | MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3, | ||
1209 | MVNZ_SPECIAL_0_OPCODE_X0 = 45, | ||
1210 | MVNZ_SPECIAL_1_OPCODE_Y0 = 1, | ||
1211 | MVZ_SPECIAL_0_OPCODE_X0 = 46, | ||
1212 | MVZ_SPECIAL_1_OPCODE_Y0 = 2, | ||
1213 | MZB_SPECIAL_0_OPCODE_X0 = 47, | ||
1214 | MZB_SPECIAL_0_OPCODE_X1 = 21, | ||
1215 | MZH_SPECIAL_0_OPCODE_X0 = 48, | ||
1216 | MZH_SPECIAL_0_OPCODE_X1 = 22, | ||
1217 | MZ_SPECIAL_0_OPCODE_X0 = 49, | ||
1218 | MZ_SPECIAL_0_OPCODE_X1 = 23, | ||
1219 | MZ_SPECIAL_1_OPCODE_Y0 = 3, | ||
1220 | MZ_SPECIAL_1_OPCODE_Y1 = 2, | ||
1221 | NAP_UN_0_SHUN_0_OPCODE_X1 = 16, | ||
1222 | NOP_NOREG_RR_IMM_0_OPCODE_SN = 2, | ||
1223 | NOP_UN_0_SHUN_0_OPCODE_X0 = 6, | ||
1224 | NOP_UN_0_SHUN_0_OPCODE_X1 = 17, | ||
1225 | NOP_UN_0_SHUN_0_OPCODE_Y0 = 6, | ||
1226 | NOP_UN_0_SHUN_0_OPCODE_Y1 = 3, | ||
1227 | NOREG_RR_IMM_0_OPCODE_SN = 0, | ||
1228 | NOR_SPECIAL_0_OPCODE_X0 = 50, | ||
1229 | NOR_SPECIAL_0_OPCODE_X1 = 24, | ||
1230 | NOR_SPECIAL_2_OPCODE_Y0 = 1, | ||
1231 | NOR_SPECIAL_2_OPCODE_Y1 = 1, | ||
1232 | ORI_IMM_0_OPCODE_X0 = 8, | ||
1233 | ORI_IMM_0_OPCODE_X1 = 11, | ||
1234 | ORI_OPCODE_Y0 = 11, | ||
1235 | ORI_OPCODE_Y1 = 9, | ||
1236 | OR_SPECIAL_0_OPCODE_X0 = 51, | ||
1237 | OR_SPECIAL_0_OPCODE_X1 = 25, | ||
1238 | OR_SPECIAL_2_OPCODE_Y0 = 2, | ||
1239 | OR_SPECIAL_2_OPCODE_Y1 = 2, | ||
1240 | PACKBS_U_SPECIAL_0_OPCODE_X0 = 103, | ||
1241 | PACKBS_U_SPECIAL_0_OPCODE_X1 = 73, | ||
1242 | PACKHB_SPECIAL_0_OPCODE_X0 = 52, | ||
1243 | PACKHB_SPECIAL_0_OPCODE_X1 = 26, | ||
1244 | PACKHS_SPECIAL_0_OPCODE_X0 = 102, | ||
1245 | PACKHS_SPECIAL_0_OPCODE_X1 = 72, | ||
1246 | PACKLB_SPECIAL_0_OPCODE_X0 = 53, | ||
1247 | PACKLB_SPECIAL_0_OPCODE_X1 = 27, | ||
1248 | PCNT_UN_0_SHUN_0_OPCODE_X0 = 7, | ||
1249 | PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7, | ||
1250 | RLI_SHUN_0_OPCODE_X0 = 1, | ||
1251 | RLI_SHUN_0_OPCODE_X1 = 1, | ||
1252 | RLI_SHUN_0_OPCODE_Y0 = 1, | ||
1253 | RLI_SHUN_0_OPCODE_Y1 = 1, | ||
1254 | RL_SPECIAL_0_OPCODE_X0 = 54, | ||
1255 | RL_SPECIAL_0_OPCODE_X1 = 28, | ||
1256 | RL_SPECIAL_3_OPCODE_Y0 = 0, | ||
1257 | RL_SPECIAL_3_OPCODE_Y1 = 0, | ||
1258 | RR_IMM_0_OPCODE_SN = 0, | ||
1259 | S1A_SPECIAL_0_OPCODE_X0 = 55, | ||
1260 | S1A_SPECIAL_0_OPCODE_X1 = 29, | ||
1261 | S1A_SPECIAL_0_OPCODE_Y0 = 1, | ||
1262 | S1A_SPECIAL_0_OPCODE_Y1 = 1, | ||
1263 | S2A_SPECIAL_0_OPCODE_X0 = 56, | ||
1264 | S2A_SPECIAL_0_OPCODE_X1 = 30, | ||
1265 | S2A_SPECIAL_0_OPCODE_Y0 = 2, | ||
1266 | S2A_SPECIAL_0_OPCODE_Y1 = 2, | ||
1267 | S3A_SPECIAL_0_OPCODE_X0 = 57, | ||
1268 | S3A_SPECIAL_0_OPCODE_X1 = 31, | ||
1269 | S3A_SPECIAL_5_OPCODE_Y0 = 1, | ||
1270 | S3A_SPECIAL_5_OPCODE_Y1 = 1, | ||
1271 | SADAB_U_SPECIAL_0_OPCODE_X0 = 58, | ||
1272 | SADAH_SPECIAL_0_OPCODE_X0 = 59, | ||
1273 | SADAH_U_SPECIAL_0_OPCODE_X0 = 60, | ||
1274 | SADB_U_SPECIAL_0_OPCODE_X0 = 61, | ||
1275 | SADH_SPECIAL_0_OPCODE_X0 = 62, | ||
1276 | SADH_U_SPECIAL_0_OPCODE_X0 = 63, | ||
1277 | SBADD_IMM_0_OPCODE_X1 = 28, | ||
1278 | SB_OPCODE_Y2 = 5, | ||
1279 | SB_SPECIAL_0_OPCODE_X1 = 32, | ||
1280 | SEQB_SPECIAL_0_OPCODE_X0 = 64, | ||
1281 | SEQB_SPECIAL_0_OPCODE_X1 = 33, | ||
1282 | SEQH_SPECIAL_0_OPCODE_X0 = 65, | ||
1283 | SEQH_SPECIAL_0_OPCODE_X1 = 34, | ||
1284 | SEQIB_IMM_0_OPCODE_X0 = 9, | ||
1285 | SEQIB_IMM_0_OPCODE_X1 = 12, | ||
1286 | SEQIH_IMM_0_OPCODE_X0 = 10, | ||
1287 | SEQIH_IMM_0_OPCODE_X1 = 13, | ||
1288 | SEQI_IMM_0_OPCODE_X0 = 11, | ||
1289 | SEQI_IMM_0_OPCODE_X1 = 14, | ||
1290 | SEQI_OPCODE_Y0 = 12, | ||
1291 | SEQI_OPCODE_Y1 = 10, | ||
1292 | SEQ_SPECIAL_0_OPCODE_X0 = 66, | ||
1293 | SEQ_SPECIAL_0_OPCODE_X1 = 35, | ||
1294 | SEQ_SPECIAL_5_OPCODE_Y0 = 2, | ||
1295 | SEQ_SPECIAL_5_OPCODE_Y1 = 2, | ||
1296 | SHADD_IMM_0_OPCODE_X1 = 29, | ||
1297 | SHL8II_IMM_0_OPCODE_SN = 3, | ||
1298 | SHLB_SPECIAL_0_OPCODE_X0 = 67, | ||
1299 | SHLB_SPECIAL_0_OPCODE_X1 = 36, | ||
1300 | SHLH_SPECIAL_0_OPCODE_X0 = 68, | ||
1301 | SHLH_SPECIAL_0_OPCODE_X1 = 37, | ||
1302 | SHLIB_SHUN_0_OPCODE_X0 = 2, | ||
1303 | SHLIB_SHUN_0_OPCODE_X1 = 2, | ||
1304 | SHLIH_SHUN_0_OPCODE_X0 = 3, | ||
1305 | SHLIH_SHUN_0_OPCODE_X1 = 3, | ||
1306 | SHLI_SHUN_0_OPCODE_X0 = 4, | ||
1307 | SHLI_SHUN_0_OPCODE_X1 = 4, | ||
1308 | SHLI_SHUN_0_OPCODE_Y0 = 2, | ||
1309 | SHLI_SHUN_0_OPCODE_Y1 = 2, | ||
1310 | SHL_SPECIAL_0_OPCODE_X0 = 69, | ||
1311 | SHL_SPECIAL_0_OPCODE_X1 = 38, | ||
1312 | SHL_SPECIAL_3_OPCODE_Y0 = 1, | ||
1313 | SHL_SPECIAL_3_OPCODE_Y1 = 1, | ||
1314 | SHR1_RR_IMM_0_OPCODE_SN = 9, | ||
1315 | SHRB_SPECIAL_0_OPCODE_X0 = 70, | ||
1316 | SHRB_SPECIAL_0_OPCODE_X1 = 39, | ||
1317 | SHRH_SPECIAL_0_OPCODE_X0 = 71, | ||
1318 | SHRH_SPECIAL_0_OPCODE_X1 = 40, | ||
1319 | SHRIB_SHUN_0_OPCODE_X0 = 5, | ||
1320 | SHRIB_SHUN_0_OPCODE_X1 = 5, | ||
1321 | SHRIH_SHUN_0_OPCODE_X0 = 6, | ||
1322 | SHRIH_SHUN_0_OPCODE_X1 = 6, | ||
1323 | SHRI_SHUN_0_OPCODE_X0 = 7, | ||
1324 | SHRI_SHUN_0_OPCODE_X1 = 7, | ||
1325 | SHRI_SHUN_0_OPCODE_Y0 = 3, | ||
1326 | SHRI_SHUN_0_OPCODE_Y1 = 3, | ||
1327 | SHR_SPECIAL_0_OPCODE_X0 = 72, | ||
1328 | SHR_SPECIAL_0_OPCODE_X1 = 41, | ||
1329 | SHR_SPECIAL_3_OPCODE_Y0 = 2, | ||
1330 | SHR_SPECIAL_3_OPCODE_Y1 = 2, | ||
1331 | SHUN_0_OPCODE_X0 = 7, | ||
1332 | SHUN_0_OPCODE_X1 = 8, | ||
1333 | SHUN_0_OPCODE_Y0 = 13, | ||
1334 | SHUN_0_OPCODE_Y1 = 11, | ||
1335 | SH_OPCODE_Y2 = 6, | ||
1336 | SH_SPECIAL_0_OPCODE_X1 = 42, | ||
1337 | SLTB_SPECIAL_0_OPCODE_X0 = 73, | ||
1338 | SLTB_SPECIAL_0_OPCODE_X1 = 43, | ||
1339 | SLTB_U_SPECIAL_0_OPCODE_X0 = 74, | ||
1340 | SLTB_U_SPECIAL_0_OPCODE_X1 = 44, | ||
1341 | SLTEB_SPECIAL_0_OPCODE_X0 = 75, | ||
1342 | SLTEB_SPECIAL_0_OPCODE_X1 = 45, | ||
1343 | SLTEB_U_SPECIAL_0_OPCODE_X0 = 76, | ||
1344 | SLTEB_U_SPECIAL_0_OPCODE_X1 = 46, | ||
1345 | SLTEH_SPECIAL_0_OPCODE_X0 = 77, | ||
1346 | SLTEH_SPECIAL_0_OPCODE_X1 = 47, | ||
1347 | SLTEH_U_SPECIAL_0_OPCODE_X0 = 78, | ||
1348 | SLTEH_U_SPECIAL_0_OPCODE_X1 = 48, | ||
1349 | SLTE_SPECIAL_0_OPCODE_X0 = 79, | ||
1350 | SLTE_SPECIAL_0_OPCODE_X1 = 49, | ||
1351 | SLTE_SPECIAL_4_OPCODE_Y0 = 0, | ||
1352 | SLTE_SPECIAL_4_OPCODE_Y1 = 0, | ||
1353 | SLTE_U_SPECIAL_0_OPCODE_X0 = 80, | ||
1354 | SLTE_U_SPECIAL_0_OPCODE_X1 = 50, | ||
1355 | SLTE_U_SPECIAL_4_OPCODE_Y0 = 1, | ||
1356 | SLTE_U_SPECIAL_4_OPCODE_Y1 = 1, | ||
1357 | SLTH_SPECIAL_0_OPCODE_X0 = 81, | ||
1358 | SLTH_SPECIAL_0_OPCODE_X1 = 51, | ||
1359 | SLTH_U_SPECIAL_0_OPCODE_X0 = 82, | ||
1360 | SLTH_U_SPECIAL_0_OPCODE_X1 = 52, | ||
1361 | SLTIB_IMM_0_OPCODE_X0 = 12, | ||
1362 | SLTIB_IMM_0_OPCODE_X1 = 15, | ||
1363 | SLTIB_U_IMM_0_OPCODE_X0 = 13, | ||
1364 | SLTIB_U_IMM_0_OPCODE_X1 = 16, | ||
1365 | SLTIH_IMM_0_OPCODE_X0 = 14, | ||
1366 | SLTIH_IMM_0_OPCODE_X1 = 17, | ||
1367 | SLTIH_U_IMM_0_OPCODE_X0 = 15, | ||
1368 | SLTIH_U_IMM_0_OPCODE_X1 = 18, | ||
1369 | SLTI_IMM_0_OPCODE_X0 = 16, | ||
1370 | SLTI_IMM_0_OPCODE_X1 = 19, | ||
1371 | SLTI_OPCODE_Y0 = 14, | ||
1372 | SLTI_OPCODE_Y1 = 12, | ||
1373 | SLTI_U_IMM_0_OPCODE_X0 = 17, | ||
1374 | SLTI_U_IMM_0_OPCODE_X1 = 20, | ||
1375 | SLTI_U_OPCODE_Y0 = 15, | ||
1376 | SLTI_U_OPCODE_Y1 = 13, | ||
1377 | SLT_SPECIAL_0_OPCODE_X0 = 83, | ||
1378 | SLT_SPECIAL_0_OPCODE_X1 = 53, | ||
1379 | SLT_SPECIAL_4_OPCODE_Y0 = 2, | ||
1380 | SLT_SPECIAL_4_OPCODE_Y1 = 2, | ||
1381 | SLT_U_SPECIAL_0_OPCODE_X0 = 84, | ||
1382 | SLT_U_SPECIAL_0_OPCODE_X1 = 54, | ||
1383 | SLT_U_SPECIAL_4_OPCODE_Y0 = 3, | ||
1384 | SLT_U_SPECIAL_4_OPCODE_Y1 = 3, | ||
1385 | SNEB_SPECIAL_0_OPCODE_X0 = 85, | ||
1386 | SNEB_SPECIAL_0_OPCODE_X1 = 55, | ||
1387 | SNEH_SPECIAL_0_OPCODE_X0 = 86, | ||
1388 | SNEH_SPECIAL_0_OPCODE_X1 = 56, | ||
1389 | SNE_SPECIAL_0_OPCODE_X0 = 87, | ||
1390 | SNE_SPECIAL_0_OPCODE_X1 = 57, | ||
1391 | SNE_SPECIAL_5_OPCODE_Y0 = 3, | ||
1392 | SNE_SPECIAL_5_OPCODE_Y1 = 3, | ||
1393 | SPECIAL_0_OPCODE_X0 = 0, | ||
1394 | SPECIAL_0_OPCODE_X1 = 1, | ||
1395 | SPECIAL_0_OPCODE_Y0 = 1, | ||
1396 | SPECIAL_0_OPCODE_Y1 = 1, | ||
1397 | SPECIAL_1_OPCODE_Y0 = 2, | ||
1398 | SPECIAL_1_OPCODE_Y1 = 2, | ||
1399 | SPECIAL_2_OPCODE_Y0 = 3, | ||
1400 | SPECIAL_2_OPCODE_Y1 = 3, | ||
1401 | SPECIAL_3_OPCODE_Y0 = 4, | ||
1402 | SPECIAL_3_OPCODE_Y1 = 4, | ||
1403 | SPECIAL_4_OPCODE_Y0 = 5, | ||
1404 | SPECIAL_4_OPCODE_Y1 = 5, | ||
1405 | SPECIAL_5_OPCODE_Y0 = 6, | ||
1406 | SPECIAL_5_OPCODE_Y1 = 6, | ||
1407 | SPECIAL_6_OPCODE_Y0 = 7, | ||
1408 | SPECIAL_7_OPCODE_Y0 = 8, | ||
1409 | SRAB_SPECIAL_0_OPCODE_X0 = 88, | ||
1410 | SRAB_SPECIAL_0_OPCODE_X1 = 58, | ||
1411 | SRAH_SPECIAL_0_OPCODE_X0 = 89, | ||
1412 | SRAH_SPECIAL_0_OPCODE_X1 = 59, | ||
1413 | SRAIB_SHUN_0_OPCODE_X0 = 8, | ||
1414 | SRAIB_SHUN_0_OPCODE_X1 = 8, | ||
1415 | SRAIH_SHUN_0_OPCODE_X0 = 9, | ||
1416 | SRAIH_SHUN_0_OPCODE_X1 = 9, | ||
1417 | SRAI_SHUN_0_OPCODE_X0 = 10, | ||
1418 | SRAI_SHUN_0_OPCODE_X1 = 10, | ||
1419 | SRAI_SHUN_0_OPCODE_Y0 = 4, | ||
1420 | SRAI_SHUN_0_OPCODE_Y1 = 4, | ||
1421 | SRA_SPECIAL_0_OPCODE_X0 = 90, | ||
1422 | SRA_SPECIAL_0_OPCODE_X1 = 60, | ||
1423 | SRA_SPECIAL_3_OPCODE_Y0 = 3, | ||
1424 | SRA_SPECIAL_3_OPCODE_Y1 = 3, | ||
1425 | SUBBS_U_SPECIAL_0_OPCODE_X0 = 100, | ||
1426 | SUBBS_U_SPECIAL_0_OPCODE_X1 = 70, | ||
1427 | SUBB_SPECIAL_0_OPCODE_X0 = 91, | ||
1428 | SUBB_SPECIAL_0_OPCODE_X1 = 61, | ||
1429 | SUBHS_SPECIAL_0_OPCODE_X0 = 101, | ||
1430 | SUBHS_SPECIAL_0_OPCODE_X1 = 71, | ||
1431 | SUBH_SPECIAL_0_OPCODE_X0 = 92, | ||
1432 | SUBH_SPECIAL_0_OPCODE_X1 = 62, | ||
1433 | SUBS_SPECIAL_0_OPCODE_X0 = 97, | ||
1434 | SUBS_SPECIAL_0_OPCODE_X1 = 67, | ||
1435 | SUB_SPECIAL_0_OPCODE_X0 = 93, | ||
1436 | SUB_SPECIAL_0_OPCODE_X1 = 63, | ||
1437 | SUB_SPECIAL_0_OPCODE_Y0 = 3, | ||
1438 | SUB_SPECIAL_0_OPCODE_Y1 = 3, | ||
1439 | SWADD_IMM_0_OPCODE_X1 = 30, | ||
1440 | SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18, | ||
1441 | SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19, | ||
1442 | SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20, | ||
1443 | SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21, | ||
1444 | SW_OPCODE_Y2 = 7, | ||
1445 | SW_SPECIAL_0_OPCODE_X1 = 64, | ||
1446 | TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8, | ||
1447 | TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8, | ||
1448 | TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9, | ||
1449 | TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9, | ||
1450 | TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10, | ||
1451 | TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10, | ||
1452 | TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11, | ||
1453 | TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11, | ||
1454 | TNS_UN_0_SHUN_0_OPCODE_X1 = 22, | ||
1455 | UN_0_SHUN_0_OPCODE_X0 = 11, | ||
1456 | UN_0_SHUN_0_OPCODE_X1 = 11, | ||
1457 | UN_0_SHUN_0_OPCODE_Y0 = 5, | ||
1458 | UN_0_SHUN_0_OPCODE_Y1 = 5, | ||
1459 | WH64_UN_0_SHUN_0_OPCODE_X1 = 23, | ||
1460 | XORI_IMM_0_OPCODE_X0 = 2, | ||
1461 | XORI_IMM_0_OPCODE_X1 = 21, | ||
1462 | XOR_SPECIAL_0_OPCODE_X0 = 94, | ||
1463 | XOR_SPECIAL_0_OPCODE_X1 = 65, | ||
1464 | XOR_SPECIAL_2_OPCODE_Y0 = 3, | ||
1465 | XOR_SPECIAL_2_OPCODE_Y1 = 3 | ||
1466 | }; | ||
1467 | |||
1468 | |||
1469 | #endif /* __ASSEMBLER__ */ | ||
1470 | |||
1471 | #endif /* __ARCH_OPCODE_H__ */ | ||
diff --git a/arch/tile/include/uapi/arch/sim.h b/arch/tile/include/uapi/arch/sim.h new file mode 100644 index 000000000000..e54b7b0527f3 --- /dev/null +++ b/arch/tile/include/uapi/arch/sim.h | |||
@@ -0,0 +1,643 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | /** | ||
16 | * @file | ||
17 | * | ||
18 | * Provides an API for controlling the simulator at runtime. | ||
19 | */ | ||
20 | |||
21 | /** | ||
22 | * @addtogroup arch_sim | ||
23 | * @{ | ||
24 | * | ||
25 | * An API for controlling the simulator at runtime. | ||
26 | * | ||
27 | * The simulator's behavior can be modified while it is running. | ||
28 | * For example, human-readable trace output can be enabled and disabled | ||
29 | * around code of interest. | ||
30 | * | ||
31 | * There are two ways to modify simulator behavior: | ||
32 | * programmatically, by calling various sim_* functions, and | ||
33 | * interactively, by entering commands like "sim set functional true" | ||
34 | * at the tile-monitor prompt. Typing "sim help" at that prompt provides | ||
35 | * a list of interactive commands. | ||
36 | * | ||
37 | * All interactive commands can also be executed programmatically by | ||
38 | * passing a string to the sim_command function. | ||
39 | */ | ||
40 | |||
41 | #ifndef __ARCH_SIM_H__ | ||
42 | #define __ARCH_SIM_H__ | ||
43 | |||
44 | #include <arch/sim_def.h> | ||
45 | #include <arch/abi.h> | ||
46 | |||
47 | #ifndef __ASSEMBLER__ | ||
48 | |||
49 | #include <arch/spr_def.h> | ||
50 | |||
51 | |||
52 | /** | ||
53 | * Return true if the current program is running under a simulator, | ||
54 | * rather than on real hardware. If running on hardware, other "sim_xxx()" | ||
55 | * calls have no useful effect. | ||
56 | */ | ||
57 | static inline int | ||
58 | sim_is_simulator(void) | ||
59 | { | ||
60 | return __insn_mfspr(SPR_SIM_CONTROL) != 0; | ||
61 | } | ||
62 | |||
63 | |||
64 | /** | ||
65 | * Checkpoint the simulator state to a checkpoint file. | ||
66 | * | ||
67 | * The checkpoint file name is either the default or the name specified | ||
68 | * on the command line with "--checkpoint-file". | ||
69 | */ | ||
70 | static __inline void | ||
71 | sim_checkpoint(void) | ||
72 | { | ||
73 | __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_CHECKPOINT); | ||
74 | } | ||
75 | |||
76 | |||
77 | /** | ||
78 | * Report whether or not various kinds of simulator tracing are enabled. | ||
79 | * | ||
80 | * @return The bitwise OR of these values: | ||
81 | * | ||
82 | * SIM_TRACE_CYCLES (--trace-cycles), | ||
83 | * SIM_TRACE_ROUTER (--trace-router), | ||
84 | * SIM_TRACE_REGISTER_WRITES (--trace-register-writes), | ||
85 | * SIM_TRACE_DISASM (--trace-disasm), | ||
86 | * SIM_TRACE_STALL_INFO (--trace-stall-info) | ||
87 | * SIM_TRACE_MEMORY_CONTROLLER (--trace-memory-controller) | ||
88 | * SIM_TRACE_L2_CACHE (--trace-l2) | ||
89 | * SIM_TRACE_LINES (--trace-lines) | ||
90 | */ | ||
91 | static __inline unsigned int | ||
92 | sim_get_tracing(void) | ||
93 | { | ||
94 | return __insn_mfspr(SPR_SIM_CONTROL) & SIM_TRACE_FLAG_MASK; | ||
95 | } | ||
96 | |||
97 | |||
98 | /** | ||
99 | * Turn on or off different kinds of simulator tracing. | ||
100 | * | ||
101 | * @param mask Either one of these special values: | ||
102 | * | ||
103 | * SIM_TRACE_NONE (turns off tracing), | ||
104 | * SIM_TRACE_ALL (turns on all possible tracing). | ||
105 | * | ||
106 | * or the bitwise OR of these values: | ||
107 | * | ||
108 | * SIM_TRACE_CYCLES (--trace-cycles), | ||
109 | * SIM_TRACE_ROUTER (--trace-router), | ||
110 | * SIM_TRACE_REGISTER_WRITES (--trace-register-writes), | ||
111 | * SIM_TRACE_DISASM (--trace-disasm), | ||
112 | * SIM_TRACE_STALL_INFO (--trace-stall-info) | ||
113 | * SIM_TRACE_MEMORY_CONTROLLER (--trace-memory-controller) | ||
114 | * SIM_TRACE_L2_CACHE (--trace-l2) | ||
115 | * SIM_TRACE_LINES (--trace-lines) | ||
116 | */ | ||
117 | static __inline void | ||
118 | sim_set_tracing(unsigned int mask) | ||
119 | { | ||
120 | __insn_mtspr(SPR_SIM_CONTROL, SIM_TRACE_SPR_ARG(mask)); | ||
121 | } | ||
122 | |||
123 | |||
124 | /** | ||
125 | * Request dumping of different kinds of simulator state. | ||
126 | * | ||
127 | * @param mask Either this special value: | ||
128 | * | ||
129 | * SIM_DUMP_ALL (dump all known state) | ||
130 | * | ||
131 | * or the bitwise OR of these values: | ||
132 | * | ||
133 | * SIM_DUMP_REGS (the register file), | ||
134 | * SIM_DUMP_SPRS (the SPRs), | ||
135 | * SIM_DUMP_ITLB (the iTLB), | ||
136 | * SIM_DUMP_DTLB (the dTLB), | ||
137 | * SIM_DUMP_L1I (the L1 I-cache), | ||
138 | * SIM_DUMP_L1D (the L1 D-cache), | ||
139 | * SIM_DUMP_L2 (the L2 cache), | ||
140 | * SIM_DUMP_SNREGS (the switch register file), | ||
141 | * SIM_DUMP_SNITLB (the switch iTLB), | ||
142 | * SIM_DUMP_SNL1I (the switch L1 I-cache), | ||
143 | * SIM_DUMP_BACKTRACE (the current backtrace) | ||
144 | */ | ||
145 | static __inline void | ||
146 | sim_dump(unsigned int mask) | ||
147 | { | ||
148 | __insn_mtspr(SPR_SIM_CONTROL, SIM_DUMP_SPR_ARG(mask)); | ||
149 | } | ||
150 | |||
151 | |||
152 | /** | ||
153 | * Print a string to the simulator stdout. | ||
154 | * | ||
155 | * @param str The string to be written. | ||
156 | */ | ||
157 | static __inline void | ||
158 | sim_print(const char* str) | ||
159 | { | ||
160 | for ( ; *str != '\0'; str++) | ||
161 | { | ||
162 | __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC | | ||
163 | (*str << _SIM_CONTROL_OPERATOR_BITS)); | ||
164 | } | ||
165 | __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC | | ||
166 | (SIM_PUTC_FLUSH_BINARY << _SIM_CONTROL_OPERATOR_BITS)); | ||
167 | } | ||
168 | |||
169 | |||
170 | /** | ||
171 | * Print a string to the simulator stdout. | ||
172 | * | ||
173 | * @param str The string to be written (a newline is automatically added). | ||
174 | */ | ||
175 | static __inline void | ||
176 | sim_print_string(const char* str) | ||
177 | { | ||
178 | for ( ; *str != '\0'; str++) | ||
179 | { | ||
180 | __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC | | ||
181 | (*str << _SIM_CONTROL_OPERATOR_BITS)); | ||
182 | } | ||
183 | __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PUTC | | ||
184 | (SIM_PUTC_FLUSH_STRING << _SIM_CONTROL_OPERATOR_BITS)); | ||
185 | } | ||
186 | |||
187 | |||
188 | /** | ||
189 | * Execute a simulator command string. | ||
190 | * | ||
191 | * Type 'sim help' at the tile-monitor prompt to learn what commands | ||
192 | * are available. Note the use of the tile-monitor "sim" command to | ||
193 | * pass commands to the simulator. | ||
194 | * | ||
195 | * The argument to sim_command() does not include the leading "sim" | ||
196 | * prefix used at the tile-monitor prompt; for example, you might call | ||
197 | * sim_command("trace disasm"). | ||
198 | */ | ||
199 | static __inline void | ||
200 | sim_command(const char* str) | ||
201 | { | ||
202 | int c; | ||
203 | do | ||
204 | { | ||
205 | c = *str++; | ||
206 | __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_COMMAND | | ||
207 | (c << _SIM_CONTROL_OPERATOR_BITS)); | ||
208 | } | ||
209 | while (c); | ||
210 | } | ||
211 | |||
212 | |||
213 | |||
214 | #ifndef __DOXYGEN__ | ||
215 | |||
216 | /** | ||
217 | * The underlying implementation of "_sim_syscall()". | ||
218 | * | ||
219 | * We use extra "and" instructions to ensure that all the values | ||
220 | * we are passing to the simulator are actually valid in the registers | ||
221 | * (i.e. returned from memory) prior to the SIM_CONTROL spr. | ||
222 | */ | ||
223 | static __inline long _sim_syscall0(int val) | ||
224 | { | ||
225 | long result; | ||
226 | __asm__ __volatile__ ("mtspr SIM_CONTROL, r0" | ||
227 | : "=R00" (result) : "R00" (val)); | ||
228 | return result; | ||
229 | } | ||
230 | |||
231 | static __inline long _sim_syscall1(int val, long arg1) | ||
232 | { | ||
233 | long result; | ||
234 | __asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }" | ||
235 | : "=R00" (result) : "R00" (val), "R01" (arg1)); | ||
236 | return result; | ||
237 | } | ||
238 | |||
239 | static __inline long _sim_syscall2(int val, long arg1, long arg2) | ||
240 | { | ||
241 | long result; | ||
242 | __asm__ __volatile__ ("{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }" | ||
243 | : "=R00" (result) | ||
244 | : "R00" (val), "R01" (arg1), "R02" (arg2)); | ||
245 | return result; | ||
246 | } | ||
247 | |||
248 | /* Note that _sim_syscall3() and higher are technically at risk of | ||
249 | receiving an interrupt right before the mtspr bundle, in which case | ||
250 | the register values for arguments 3 and up may still be in flight | ||
251 | to the core from a stack frame reload. */ | ||
252 | |||
253 | static __inline long _sim_syscall3(int val, long arg1, long arg2, long arg3) | ||
254 | { | ||
255 | long result; | ||
256 | __asm__ __volatile__ ("{ and zero, r3, r3 };" | ||
257 | "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }" | ||
258 | : "=R00" (result) | ||
259 | : "R00" (val), "R01" (arg1), "R02" (arg2), | ||
260 | "R03" (arg3)); | ||
261 | return result; | ||
262 | } | ||
263 | |||
264 | static __inline long _sim_syscall4(int val, long arg1, long arg2, long arg3, | ||
265 | long arg4) | ||
266 | { | ||
267 | long result; | ||
268 | __asm__ __volatile__ ("{ and zero, r3, r4 };" | ||
269 | "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }" | ||
270 | : "=R00" (result) | ||
271 | : "R00" (val), "R01" (arg1), "R02" (arg2), | ||
272 | "R03" (arg3), "R04" (arg4)); | ||
273 | return result; | ||
274 | } | ||
275 | |||
276 | static __inline long _sim_syscall5(int val, long arg1, long arg2, long arg3, | ||
277 | long arg4, long arg5) | ||
278 | { | ||
279 | long result; | ||
280 | __asm__ __volatile__ ("{ and zero, r3, r4; and zero, r5, r5 };" | ||
281 | "{ and zero, r1, r2; mtspr SIM_CONTROL, r0 }" | ||
282 | : "=R00" (result) | ||
283 | : "R00" (val), "R01" (arg1), "R02" (arg2), | ||
284 | "R03" (arg3), "R04" (arg4), "R05" (arg5)); | ||
285 | return result; | ||
286 | } | ||
287 | |||
288 | /** | ||
289 | * Make a special syscall to the simulator itself, if running under | ||
290 | * simulation. This is used as the implementation of other functions | ||
291 | * and should not be used outside this file. | ||
292 | * | ||
293 | * @param syscall_num The simulator syscall number. | ||
294 | * @param nr The number of additional arguments provided. | ||
295 | * | ||
296 | * @return Varies by syscall. | ||
297 | */ | ||
298 | #define _sim_syscall(syscall_num, nr, args...) \ | ||
299 | _sim_syscall##nr( \ | ||
300 | ((syscall_num) << _SIM_CONTROL_OPERATOR_BITS) | SIM_CONTROL_SYSCALL, \ | ||
301 | ##args) | ||
302 | |||
303 | |||
304 | /* Values for the "access_mask" parameters below. */ | ||
305 | #define SIM_WATCHPOINT_READ 1 | ||
306 | #define SIM_WATCHPOINT_WRITE 2 | ||
307 | #define SIM_WATCHPOINT_EXECUTE 4 | ||
308 | |||
309 | |||
310 | static __inline int | ||
311 | sim_add_watchpoint(unsigned int process_id, | ||
312 | unsigned long address, | ||
313 | unsigned long size, | ||
314 | unsigned int access_mask, | ||
315 | unsigned long user_data) | ||
316 | { | ||
317 | return _sim_syscall(SIM_SYSCALL_ADD_WATCHPOINT, 5, process_id, | ||
318 | address, size, access_mask, user_data); | ||
319 | } | ||
320 | |||
321 | |||
322 | static __inline int | ||
323 | sim_remove_watchpoint(unsigned int process_id, | ||
324 | unsigned long address, | ||
325 | unsigned long size, | ||
326 | unsigned int access_mask, | ||
327 | unsigned long user_data) | ||
328 | { | ||
329 | return _sim_syscall(SIM_SYSCALL_REMOVE_WATCHPOINT, 5, process_id, | ||
330 | address, size, access_mask, user_data); | ||
331 | } | ||
332 | |||
333 | |||
334 | /** | ||
335 | * Return value from sim_query_watchpoint. | ||
336 | */ | ||
337 | struct SimQueryWatchpointStatus | ||
338 | { | ||
339 | /** | ||
340 | * 0 if a watchpoint fired, 1 if no watchpoint fired, or -1 for | ||
341 | * error (meaning a bad process_id). | ||
342 | */ | ||
343 | int syscall_status; | ||
344 | |||
345 | /** | ||
346 | * The address of the watchpoint that fired (this is the address | ||
347 | * passed to sim_add_watchpoint, not an address within that range | ||
348 | * that actually triggered the watchpoint). | ||
349 | */ | ||
350 | unsigned long address; | ||
351 | |||
352 | /** The arbitrary user_data installed by sim_add_watchpoint. */ | ||
353 | unsigned long user_data; | ||
354 | }; | ||
355 | |||
356 | |||
357 | static __inline struct SimQueryWatchpointStatus | ||
358 | sim_query_watchpoint(unsigned int process_id) | ||
359 | { | ||
360 | struct SimQueryWatchpointStatus status; | ||
361 | long val = SIM_CONTROL_SYSCALL | | ||
362 | (SIM_SYSCALL_QUERY_WATCHPOINT << _SIM_CONTROL_OPERATOR_BITS); | ||
363 | __asm__ __volatile__ ("{ and zero, r1, r1; mtspr SIM_CONTROL, r0 }" | ||
364 | : "=R00" (status.syscall_status), | ||
365 | "=R01" (status.address), | ||
366 | "=R02" (status.user_data) | ||
367 | : "R00" (val), "R01" (process_id)); | ||
368 | return status; | ||
369 | } | ||
370 | |||
371 | |||
372 | /* On the simulator, confirm lines have been evicted everywhere. */ | ||
373 | static __inline void | ||
374 | sim_validate_lines_evicted(unsigned long long pa, unsigned long length) | ||
375 | { | ||
376 | #ifdef __LP64__ | ||
377 | _sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, 2, pa, length); | ||
378 | #else | ||
379 | _sim_syscall(SIM_SYSCALL_VALIDATE_LINES_EVICTED, 4, | ||
380 | 0 /* dummy */, (long)(pa), (long)(pa >> 32), length); | ||
381 | #endif | ||
382 | } | ||
383 | |||
384 | |||
385 | /* Return the current CPU speed in cycles per second. */ | ||
386 | static __inline long | ||
387 | sim_query_cpu_speed(void) | ||
388 | { | ||
389 | return _sim_syscall(SIM_SYSCALL_QUERY_CPU_SPEED, 0); | ||
390 | } | ||
391 | |||
392 | #endif /* !__DOXYGEN__ */ | ||
393 | |||
394 | |||
395 | |||
396 | |||
397 | /** | ||
398 | * Modify the shaping parameters of a shim. | ||
399 | * | ||
400 | * @param shim The shim to modify. One of: | ||
401 | * SIM_CONTROL_SHAPING_GBE_0 | ||
402 | * SIM_CONTROL_SHAPING_GBE_1 | ||
403 | * SIM_CONTROL_SHAPING_GBE_2 | ||
404 | * SIM_CONTROL_SHAPING_GBE_3 | ||
405 | * SIM_CONTROL_SHAPING_XGBE_0 | ||
406 | * SIM_CONTROL_SHAPING_XGBE_1 | ||
407 | * | ||
408 | * @param type The type of shaping. This should be the same type of | ||
409 | * shaping that is already in place on the shim. One of: | ||
410 | * SIM_CONTROL_SHAPING_MULTIPLIER | ||
411 | * SIM_CONTROL_SHAPING_PPS | ||
412 | * SIM_CONTROL_SHAPING_BPS | ||
413 | * | ||
414 | * @param units The magnitude of the rate. One of: | ||
415 | * SIM_CONTROL_SHAPING_UNITS_SINGLE | ||
416 | * SIM_CONTROL_SHAPING_UNITS_KILO | ||
417 | * SIM_CONTROL_SHAPING_UNITS_MEGA | ||
418 | * SIM_CONTROL_SHAPING_UNITS_GIGA | ||
419 | * | ||
420 | * @param rate The rate to which to change it. This must fit in | ||
421 | * SIM_CONTROL_SHAPING_RATE_BITS bits or a warning is issued and | ||
422 | * the shaping is not changed. | ||
423 | * | ||
424 | * @return 0 if no problems were detected in the arguments to sim_set_shaping | ||
425 | * or 1 if problems were detected (for example, rate does not fit in 17 bits). | ||
426 | */ | ||
427 | static __inline int | ||
428 | sim_set_shaping(unsigned shim, | ||
429 | unsigned type, | ||
430 | unsigned units, | ||
431 | unsigned rate) | ||
432 | { | ||
433 | if ((rate & ~((1 << SIM_CONTROL_SHAPING_RATE_BITS) - 1)) != 0) | ||
434 | return 1; | ||
435 | |||
436 | __insn_mtspr(SPR_SIM_CONTROL, SIM_SHAPING_SPR_ARG(shim, type, units, rate)); | ||
437 | return 0; | ||
438 | } | ||
439 | |||
440 | #ifdef __tilegx__ | ||
441 | |||
442 | /** Enable a set of mPIPE links. Pass a -1 link_mask to enable all links. */ | ||
443 | static __inline void | ||
444 | sim_enable_mpipe_links(unsigned mpipe, unsigned long link_mask) | ||
445 | { | ||
446 | __insn_mtspr(SPR_SIM_CONTROL, | ||
447 | (SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE | | ||
448 | (mpipe << 8) | (1 << 16) | ((uint_reg_t)link_mask << 32))); | ||
449 | } | ||
450 | |||
451 | /** Disable a set of mPIPE links. Pass a -1 link_mask to disable all links. */ | ||
452 | static __inline void | ||
453 | sim_disable_mpipe_links(unsigned mpipe, unsigned long link_mask) | ||
454 | { | ||
455 | __insn_mtspr(SPR_SIM_CONTROL, | ||
456 | (SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE | | ||
457 | (mpipe << 8) | (0 << 16) | ((uint_reg_t)link_mask << 32))); | ||
458 | } | ||
459 | |||
460 | #endif /* __tilegx__ */ | ||
461 | |||
462 | |||
463 | /* | ||
464 | * An API for changing "functional" mode. | ||
465 | */ | ||
466 | |||
467 | #ifndef __DOXYGEN__ | ||
468 | |||
469 | #define sim_enable_functional() \ | ||
470 | __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_ENABLE_FUNCTIONAL) | ||
471 | |||
472 | #define sim_disable_functional() \ | ||
473 | __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_DISABLE_FUNCTIONAL) | ||
474 | |||
475 | #endif /* __DOXYGEN__ */ | ||
476 | |||
477 | |||
478 | /* | ||
479 | * Profiler support. | ||
480 | */ | ||
481 | |||
482 | /** | ||
483 | * Turn profiling on for the current task. | ||
484 | * | ||
485 | * Note that this has no effect if run in an environment without | ||
486 | * profiling support (thus, the proper flags to the simulator must | ||
487 | * be supplied). | ||
488 | */ | ||
489 | static __inline void | ||
490 | sim_profiler_enable(void) | ||
491 | { | ||
492 | __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_ENABLE); | ||
493 | } | ||
494 | |||
495 | |||
496 | /** Turn profiling off for the current task. */ | ||
497 | static __inline void | ||
498 | sim_profiler_disable(void) | ||
499 | { | ||
500 | __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_DISABLE); | ||
501 | } | ||
502 | |||
503 | |||
504 | /** | ||
505 | * Turn profiling on or off for the current task. | ||
506 | * | ||
507 | * @param enabled If true, turns on profiling. If false, turns it off. | ||
508 | * | ||
509 | * Note that this has no effect if run in an environment without | ||
510 | * profiling support (thus, the proper flags to the simulator must | ||
511 | * be supplied). | ||
512 | */ | ||
513 | static __inline void | ||
514 | sim_profiler_set_enabled(int enabled) | ||
515 | { | ||
516 | int val = | ||
517 | enabled ? SIM_CONTROL_PROFILER_ENABLE : SIM_CONTROL_PROFILER_DISABLE; | ||
518 | __insn_mtspr(SPR_SIM_CONTROL, val); | ||
519 | } | ||
520 | |||
521 | |||
522 | /** | ||
523 | * Return true if and only if profiling is currently enabled | ||
524 | * for the current task. | ||
525 | * | ||
526 | * This returns false even if sim_profiler_enable() was called | ||
527 | * if the current execution environment does not support profiling. | ||
528 | */ | ||
529 | static __inline int | ||
530 | sim_profiler_is_enabled(void) | ||
531 | { | ||
532 | return ((__insn_mfspr(SPR_SIM_CONTROL) & SIM_PROFILER_ENABLED_MASK) != 0); | ||
533 | } | ||
534 | |||
535 | |||
536 | /** | ||
537 | * Reset profiling counters to zero for the current task. | ||
538 | * | ||
539 | * Resetting can be done while profiling is enabled. It does not affect | ||
540 | * the chip-wide profiling counters. | ||
541 | */ | ||
542 | static __inline void | ||
543 | sim_profiler_clear(void) | ||
544 | { | ||
545 | __insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_PROFILER_CLEAR); | ||
546 | } | ||
547 | |||
548 | |||
549 | /** | ||
550 | * Enable specified chip-level profiling counters. | ||
551 | * | ||
552 | * Does not affect the per-task profiling counters. | ||
553 | * | ||
554 | * @param mask Either this special value: | ||
555 | * | ||
556 | * SIM_CHIP_ALL (enables all chip-level components). | ||
557 | * | ||
558 | * or the bitwise OR of these values: | ||
559 | * | ||
560 | * SIM_CHIP_MEMCTL (enable all memory controllers) | ||
561 | * SIM_CHIP_XAUI (enable all XAUI controllers) | ||
562 | * SIM_CHIP_MPIPE (enable all MPIPE controllers) | ||
563 | */ | ||
564 | static __inline void | ||
565 | sim_profiler_chip_enable(unsigned int mask) | ||
566 | { | ||
567 | __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask)); | ||
568 | } | ||
569 | |||
570 | |||
571 | /** | ||
572 | * Disable specified chip-level profiling counters. | ||
573 | * | ||
574 | * Does not affect the per-task profiling counters. | ||
575 | * | ||
576 | * @param mask Either this special value: | ||
577 | * | ||
578 | * SIM_CHIP_ALL (disables all chip-level components). | ||
579 | * | ||
580 | * or the bitwise OR of these values: | ||
581 | * | ||
582 | * SIM_CHIP_MEMCTL (disable all memory controllers) | ||
583 | * SIM_CHIP_XAUI (disable all XAUI controllers) | ||
584 | * SIM_CHIP_MPIPE (disable all MPIPE controllers) | ||
585 | */ | ||
586 | static __inline void | ||
587 | sim_profiler_chip_disable(unsigned int mask) | ||
588 | { | ||
589 | __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask)); | ||
590 | } | ||
591 | |||
592 | |||
593 | /** | ||
594 | * Reset specified chip-level profiling counters to zero. | ||
595 | * | ||
596 | * Does not affect the per-task profiling counters. | ||
597 | * | ||
598 | * @param mask Either this special value: | ||
599 | * | ||
600 | * SIM_CHIP_ALL (clears all chip-level components). | ||
601 | * | ||
602 | * or the bitwise OR of these values: | ||
603 | * | ||
604 | * SIM_CHIP_MEMCTL (clear all memory controllers) | ||
605 | * SIM_CHIP_XAUI (clear all XAUI controllers) | ||
606 | * SIM_CHIP_MPIPE (clear all MPIPE controllers) | ||
607 | */ | ||
608 | static __inline void | ||
609 | sim_profiler_chip_clear(unsigned int mask) | ||
610 | { | ||
611 | __insn_mtspr(SPR_SIM_CONTROL, SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask)); | ||
612 | } | ||
613 | |||
614 | |||
615 | /* | ||
616 | * Event support. | ||
617 | */ | ||
618 | |||
619 | #ifndef __DOXYGEN__ | ||
620 | |||
621 | static __inline void | ||
622 | sim_event_begin(unsigned int x) | ||
623 | { | ||
624 | #if defined(__tile__) && !defined(__NO_EVENT_SPR__) | ||
625 | __insn_mtspr(SPR_EVENT_BEGIN, x); | ||
626 | #endif | ||
627 | } | ||
628 | |||
629 | static __inline void | ||
630 | sim_event_end(unsigned int x) | ||
631 | { | ||
632 | #if defined(__tile__) && !defined(__NO_EVENT_SPR__) | ||
633 | __insn_mtspr(SPR_EVENT_END, x); | ||
634 | #endif | ||
635 | } | ||
636 | |||
637 | #endif /* !__DOXYGEN__ */ | ||
638 | |||
639 | #endif /* !__ASSEMBLER__ */ | ||
640 | |||
641 | #endif /* !__ARCH_SIM_H__ */ | ||
642 | |||
643 | /** @} */ | ||
diff --git a/arch/tile/include/uapi/arch/sim_def.h b/arch/tile/include/uapi/arch/sim_def.h new file mode 100644 index 000000000000..4b44a2b6a09a --- /dev/null +++ b/arch/tile/include/uapi/arch/sim_def.h | |||
@@ -0,0 +1,505 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | /** | ||
16 | * @file | ||
17 | * | ||
18 | * Some low-level simulator definitions. | ||
19 | */ | ||
20 | |||
21 | #ifndef __ARCH_SIM_DEF_H__ | ||
22 | #define __ARCH_SIM_DEF_H__ | ||
23 | |||
24 | |||
25 | /** | ||
26 | * Internal: the low bits of the SIM_CONTROL_* SPR values specify | ||
27 | * the operation to perform, and the remaining bits are | ||
28 | * an operation-specific parameter (often unused). | ||
29 | */ | ||
30 | #define _SIM_CONTROL_OPERATOR_BITS 8 | ||
31 | |||
32 | |||
33 | /* | ||
34 | * Values which can be written to SPR_SIM_CONTROL. | ||
35 | */ | ||
36 | |||
37 | /** If written to SPR_SIM_CONTROL, stops profiling. */ | ||
38 | #define SIM_CONTROL_PROFILER_DISABLE 0 | ||
39 | |||
40 | /** If written to SPR_SIM_CONTROL, starts profiling. */ | ||
41 | #define SIM_CONTROL_PROFILER_ENABLE 1 | ||
42 | |||
43 | /** If written to SPR_SIM_CONTROL, clears profiling counters. */ | ||
44 | #define SIM_CONTROL_PROFILER_CLEAR 2 | ||
45 | |||
46 | /** If written to SPR_SIM_CONTROL, checkpoints the simulator. */ | ||
47 | #define SIM_CONTROL_CHECKPOINT 3 | ||
48 | |||
49 | /** | ||
50 | * If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8), | ||
51 | * sets the tracing mask to the given mask. See "sim_set_tracing()". | ||
52 | */ | ||
53 | #define SIM_CONTROL_SET_TRACING 4 | ||
54 | |||
55 | /** | ||
56 | * If written to SPR_SIM_CONTROL, combined with a mask (shifted by 8), | ||
57 | * dumps the requested items of machine state to the log. | ||
58 | */ | ||
59 | #define SIM_CONTROL_DUMP 5 | ||
60 | |||
61 | /** If written to SPR_SIM_CONTROL, clears chip-level profiling counters. */ | ||
62 | #define SIM_CONTROL_PROFILER_CHIP_CLEAR 6 | ||
63 | |||
64 | /** If written to SPR_SIM_CONTROL, disables chip-level profiling. */ | ||
65 | #define SIM_CONTROL_PROFILER_CHIP_DISABLE 7 | ||
66 | |||
67 | /** If written to SPR_SIM_CONTROL, enables chip-level profiling. */ | ||
68 | #define SIM_CONTROL_PROFILER_CHIP_ENABLE 8 | ||
69 | |||
70 | /** If written to SPR_SIM_CONTROL, enables chip-level functional mode */ | ||
71 | #define SIM_CONTROL_ENABLE_FUNCTIONAL 9 | ||
72 | |||
73 | /** If written to SPR_SIM_CONTROL, disables chip-level functional mode. */ | ||
74 | #define SIM_CONTROL_DISABLE_FUNCTIONAL 10 | ||
75 | |||
76 | /** | ||
77 | * If written to SPR_SIM_CONTROL, enables chip-level functional mode. | ||
78 | * All tiles must perform this write for functional mode to be enabled. | ||
79 | * Ignored in naked boot mode unless --functional is specified. | ||
80 | * WARNING: Only the hypervisor startup code should use this! | ||
81 | */ | ||
82 | #define SIM_CONTROL_ENABLE_FUNCTIONAL_BARRIER 11 | ||
83 | |||
84 | /** | ||
85 | * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), | ||
86 | * writes a string directly to the simulator output. Written to once for | ||
87 | * each character in the string, plus a final NUL. Instead of NUL, | ||
88 | * you can also use "SIM_PUTC_FLUSH_STRING" or "SIM_PUTC_FLUSH_BINARY". | ||
89 | */ | ||
90 | /* ISSUE: Document the meaning of "newline", and the handling of NUL. */ | ||
91 | #define SIM_CONTROL_PUTC 12 | ||
92 | |||
93 | /** | ||
94 | * If written to SPR_SIM_CONTROL, clears the --grind-coherence state for | ||
95 | * this core. This is intended to be used before a loop that will | ||
96 | * invalidate the cache by loading new data and evicting all current data. | ||
97 | * Generally speaking, this API should only be used by system code. | ||
98 | */ | ||
99 | #define SIM_CONTROL_GRINDER_CLEAR 13 | ||
100 | |||
101 | /** If written to SPR_SIM_CONTROL, shuts down the simulator. */ | ||
102 | #define SIM_CONTROL_SHUTDOWN 14 | ||
103 | |||
104 | /** | ||
105 | * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), | ||
106 | * indicates that a fork syscall just created the given process. | ||
107 | */ | ||
108 | #define SIM_CONTROL_OS_FORK 15 | ||
109 | |||
110 | /** | ||
111 | * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), | ||
112 | * indicates that an exit syscall was just executed by the given process. | ||
113 | */ | ||
114 | #define SIM_CONTROL_OS_EXIT 16 | ||
115 | |||
116 | /** | ||
117 | * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), | ||
118 | * indicates that the OS just switched to the given process. | ||
119 | */ | ||
120 | #define SIM_CONTROL_OS_SWITCH 17 | ||
121 | |||
122 | /** | ||
123 | * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), | ||
124 | * indicates that an exec syscall was just executed. Written to once for | ||
125 | * each character in the executable name, plus a final NUL. | ||
126 | */ | ||
127 | #define SIM_CONTROL_OS_EXEC 18 | ||
128 | |||
129 | /** | ||
130 | * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), | ||
131 | * indicates that an interpreter (PT_INTERP) was loaded. Written to once | ||
132 | * for each character in "ADDR:PATH", plus a final NUL, where "ADDR" is a | ||
133 | * hex load address starting with "0x", and "PATH" is the executable name. | ||
134 | */ | ||
135 | #define SIM_CONTROL_OS_INTERP 19 | ||
136 | |||
137 | /** | ||
138 | * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), | ||
139 | * indicates that a dll was loaded. Written to once for each character | ||
140 | * in "ADDR:PATH", plus a final NUL, where "ADDR" is a hexadecimal load | ||
141 | * address starting with "0x", and "PATH" is the executable name. | ||
142 | */ | ||
143 | #define SIM_CONTROL_DLOPEN 20 | ||
144 | |||
145 | /** | ||
146 | * If written to SPR_SIM_CONTROL, combined with a character (shifted by 8), | ||
147 | * indicates that a dll was unloaded. Written to once for each character | ||
148 | * in "ADDR", plus a final NUL, where "ADDR" is a hexadecimal load | ||
149 | * address starting with "0x". | ||
150 | */ | ||
151 | #define SIM_CONTROL_DLCLOSE 21 | ||
152 | |||
153 | /** | ||
154 | * If written to SPR_SIM_CONTROL, combined with a flag (shifted by 8), | ||
155 | * indicates whether to allow data reads to remotely-cached | ||
156 | * dirty cache lines to be cached locally without grinder warnings or | ||
157 | * assertions (used by Linux kernel fast memcpy). | ||
158 | */ | ||
159 | #define SIM_CONTROL_ALLOW_MULTIPLE_CACHING 22 | ||
160 | |||
161 | /** If written to SPR_SIM_CONTROL, enables memory tracing. */ | ||
162 | #define SIM_CONTROL_ENABLE_MEM_LOGGING 23 | ||
163 | |||
164 | /** If written to SPR_SIM_CONTROL, disables memory tracing. */ | ||
165 | #define SIM_CONTROL_DISABLE_MEM_LOGGING 24 | ||
166 | |||
167 | /** | ||
168 | * If written to SPR_SIM_CONTROL, changes the shaping parameters of one of | ||
169 | * the gbe or xgbe shims. Must specify the shim id, the type, the units, and | ||
170 | * the rate, as defined in SIM_SHAPING_SPR_ARG. | ||
171 | */ | ||
172 | #define SIM_CONTROL_SHAPING 25 | ||
173 | |||
174 | /** | ||
175 | * If written to SPR_SIM_CONTROL, combined with character (shifted by 8), | ||
176 | * requests that a simulator command be executed. Written to once for each | ||
177 | * character in the command, plus a final NUL. | ||
178 | */ | ||
179 | #define SIM_CONTROL_COMMAND 26 | ||
180 | |||
181 | /** | ||
182 | * If written to SPR_SIM_CONTROL, indicates that the simulated system | ||
183 | * is panicking, to allow debugging via --debug-on-panic. | ||
184 | */ | ||
185 | #define SIM_CONTROL_PANIC 27 | ||
186 | |||
187 | /** | ||
188 | * If written to SPR_SIM_CONTROL, triggers a simulator syscall. | ||
189 | * See "sim_syscall()" for more info. | ||
190 | */ | ||
191 | #define SIM_CONTROL_SYSCALL 32 | ||
192 | |||
193 | /** | ||
194 | * If written to SPR_SIM_CONTROL, combined with a pid (shifted by 8), | ||
195 | * provides the pid that subsequent SIM_CONTROL_OS_FORK writes should | ||
196 | * use as the pid, rather than the default previous SIM_CONTROL_OS_SWITCH. | ||
197 | */ | ||
198 | #define SIM_CONTROL_OS_FORK_PARENT 33 | ||
199 | |||
200 | /** | ||
201 | * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number | ||
202 | * (shifted by 8), clears the pending magic data section. The cleared | ||
203 | * pending magic data section and any subsequently appended magic bytes | ||
204 | * will only take effect when the classifier blast programmer is run. | ||
205 | */ | ||
206 | #define SIM_CONTROL_CLEAR_MPIPE_MAGIC_BYTES 34 | ||
207 | |||
208 | /** | ||
209 | * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number | ||
210 | * (shifted by 8) and a byte of data (shifted by 16), appends that byte | ||
211 | * to the shim's pending magic data section. The pending magic data | ||
212 | * section takes effect when the classifier blast programmer is run. | ||
213 | */ | ||
214 | #define SIM_CONTROL_APPEND_MPIPE_MAGIC_BYTE 35 | ||
215 | |||
216 | /** | ||
217 | * If written to SPR_SIM_CONTROL, combined with a mPIPE shim number | ||
218 | * (shifted by 8), an enable=1/disable=0 bit (shifted by 16), and a | ||
219 | * mask of links (shifted by 32), enable or disable the corresponding | ||
220 | * mPIPE links. | ||
221 | */ | ||
222 | #define SIM_CONTROL_ENABLE_MPIPE_LINK_MAGIC_BYTE 36 | ||
223 | |||
224 | |||
225 | /* | ||
226 | * Syscall numbers for use with "sim_syscall()". | ||
227 | */ | ||
228 | |||
229 | /** Syscall number for sim_add_watchpoint(). */ | ||
230 | #define SIM_SYSCALL_ADD_WATCHPOINT 2 | ||
231 | |||
232 | /** Syscall number for sim_remove_watchpoint(). */ | ||
233 | #define SIM_SYSCALL_REMOVE_WATCHPOINT 3 | ||
234 | |||
235 | /** Syscall number for sim_query_watchpoint(). */ | ||
236 | #define SIM_SYSCALL_QUERY_WATCHPOINT 4 | ||
237 | |||
238 | /** | ||
239 | * Syscall number that asserts that the cache lines whose 64-bit PA | ||
240 | * is passed as the second argument to sim_syscall(), and over a | ||
241 | * range passed as the third argument, are no longer in cache. | ||
242 | * The simulator raises an error if this is not the case. | ||
243 | */ | ||
244 | #define SIM_SYSCALL_VALIDATE_LINES_EVICTED 5 | ||
245 | |||
246 | /** Syscall number for sim_query_cpu_speed(). */ | ||
247 | #define SIM_SYSCALL_QUERY_CPU_SPEED 6 | ||
248 | |||
249 | |||
250 | /* | ||
251 | * Bit masks which can be shifted by 8, combined with | ||
252 | * SIM_CONTROL_SET_TRACING, and written to SPR_SIM_CONTROL. | ||
253 | */ | ||
254 | |||
255 | /** | ||
256 | * @addtogroup arch_sim | ||
257 | * @{ | ||
258 | */ | ||
259 | |||
260 | /** Enable --trace-cycle when passed to simulator_set_tracing(). */ | ||
261 | #define SIM_TRACE_CYCLES 0x01 | ||
262 | |||
263 | /** Enable --trace-router when passed to simulator_set_tracing(). */ | ||
264 | #define SIM_TRACE_ROUTER 0x02 | ||
265 | |||
266 | /** Enable --trace-register-writes when passed to simulator_set_tracing(). */ | ||
267 | #define SIM_TRACE_REGISTER_WRITES 0x04 | ||
268 | |||
269 | /** Enable --trace-disasm when passed to simulator_set_tracing(). */ | ||
270 | #define SIM_TRACE_DISASM 0x08 | ||
271 | |||
272 | /** Enable --trace-stall-info when passed to simulator_set_tracing(). */ | ||
273 | #define SIM_TRACE_STALL_INFO 0x10 | ||
274 | |||
275 | /** Enable --trace-memory-controller when passed to simulator_set_tracing(). */ | ||
276 | #define SIM_TRACE_MEMORY_CONTROLLER 0x20 | ||
277 | |||
278 | /** Enable --trace-l2 when passed to simulator_set_tracing(). */ | ||
279 | #define SIM_TRACE_L2_CACHE 0x40 | ||
280 | |||
281 | /** Enable --trace-lines when passed to simulator_set_tracing(). */ | ||
282 | #define SIM_TRACE_LINES 0x80 | ||
283 | |||
284 | /** Turn off all tracing when passed to simulator_set_tracing(). */ | ||
285 | #define SIM_TRACE_NONE 0 | ||
286 | |||
287 | /** Turn on all tracing when passed to simulator_set_tracing(). */ | ||
288 | #define SIM_TRACE_ALL (-1) | ||
289 | |||
290 | /** @} */ | ||
291 | |||
292 | /** Computes the value to write to SPR_SIM_CONTROL to set tracing flags. */ | ||
293 | #define SIM_TRACE_SPR_ARG(mask) \ | ||
294 | (SIM_CONTROL_SET_TRACING | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) | ||
295 | |||
296 | |||
297 | /* | ||
298 | * Bit masks which can be shifted by 8, combined with | ||
299 | * SIM_CONTROL_DUMP, and written to SPR_SIM_CONTROL. | ||
300 | */ | ||
301 | |||
302 | /** | ||
303 | * @addtogroup arch_sim | ||
304 | * @{ | ||
305 | */ | ||
306 | |||
307 | /** Dump the general-purpose registers. */ | ||
308 | #define SIM_DUMP_REGS 0x001 | ||
309 | |||
310 | /** Dump the SPRs. */ | ||
311 | #define SIM_DUMP_SPRS 0x002 | ||
312 | |||
313 | /** Dump the ITLB. */ | ||
314 | #define SIM_DUMP_ITLB 0x004 | ||
315 | |||
316 | /** Dump the DTLB. */ | ||
317 | #define SIM_DUMP_DTLB 0x008 | ||
318 | |||
319 | /** Dump the L1 I-cache. */ | ||
320 | #define SIM_DUMP_L1I 0x010 | ||
321 | |||
322 | /** Dump the L1 D-cache. */ | ||
323 | #define SIM_DUMP_L1D 0x020 | ||
324 | |||
325 | /** Dump the L2 cache. */ | ||
326 | #define SIM_DUMP_L2 0x040 | ||
327 | |||
328 | /** Dump the switch registers. */ | ||
329 | #define SIM_DUMP_SNREGS 0x080 | ||
330 | |||
331 | /** Dump the switch ITLB. */ | ||
332 | #define SIM_DUMP_SNITLB 0x100 | ||
333 | |||
334 | /** Dump the switch L1 I-cache. */ | ||
335 | #define SIM_DUMP_SNL1I 0x200 | ||
336 | |||
337 | /** Dump the current backtrace. */ | ||
338 | #define SIM_DUMP_BACKTRACE 0x400 | ||
339 | |||
340 | /** Only dump valid lines in caches. */ | ||
341 | #define SIM_DUMP_VALID_LINES 0x800 | ||
342 | |||
343 | /** Dump everything that is dumpable. */ | ||
344 | #define SIM_DUMP_ALL (-1 & ~SIM_DUMP_VALID_LINES) | ||
345 | |||
346 | /** @} */ | ||
347 | |||
348 | /** Computes the value to write to SPR_SIM_CONTROL to dump machine state. */ | ||
349 | #define SIM_DUMP_SPR_ARG(mask) \ | ||
350 | (SIM_CONTROL_DUMP | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) | ||
351 | |||
352 | |||
353 | /* | ||
354 | * Bit masks which can be shifted by 8, combined with | ||
355 | * SIM_CONTROL_PROFILER_CHIP_xxx, and written to SPR_SIM_CONTROL. | ||
356 | */ | ||
357 | |||
358 | /** | ||
359 | * @addtogroup arch_sim | ||
360 | * @{ | ||
361 | */ | ||
362 | |||
363 | /** Use with with SIM_PROFILER_CHIP_xxx to control the memory controllers. */ | ||
364 | #define SIM_CHIP_MEMCTL 0x001 | ||
365 | |||
366 | /** Use with with SIM_PROFILER_CHIP_xxx to control the XAUI interface. */ | ||
367 | #define SIM_CHIP_XAUI 0x002 | ||
368 | |||
369 | /** Use with with SIM_PROFILER_CHIP_xxx to control the PCIe interface. */ | ||
370 | #define SIM_CHIP_PCIE 0x004 | ||
371 | |||
372 | /** Use with with SIM_PROFILER_CHIP_xxx to control the MPIPE interface. */ | ||
373 | #define SIM_CHIP_MPIPE 0x008 | ||
374 | |||
375 | /** Use with with SIM_PROFILER_CHIP_xxx to control the TRIO interface. */ | ||
376 | #define SIM_CHIP_TRIO 0x010 | ||
377 | |||
378 | /** Reference all chip devices. */ | ||
379 | #define SIM_CHIP_ALL (-1) | ||
380 | |||
381 | /** @} */ | ||
382 | |||
383 | /** Computes the value to write to SPR_SIM_CONTROL to clear chip statistics. */ | ||
384 | #define SIM_PROFILER_CHIP_CLEAR_SPR_ARG(mask) \ | ||
385 | (SIM_CONTROL_PROFILER_CHIP_CLEAR | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) | ||
386 | |||
387 | /** Computes the value to write to SPR_SIM_CONTROL to disable chip statistics.*/ | ||
388 | #define SIM_PROFILER_CHIP_DISABLE_SPR_ARG(mask) \ | ||
389 | (SIM_CONTROL_PROFILER_CHIP_DISABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) | ||
390 | |||
391 | /** Computes the value to write to SPR_SIM_CONTROL to enable chip statistics. */ | ||
392 | #define SIM_PROFILER_CHIP_ENABLE_SPR_ARG(mask) \ | ||
393 | (SIM_CONTROL_PROFILER_CHIP_ENABLE | ((mask) << _SIM_CONTROL_OPERATOR_BITS)) | ||
394 | |||
395 | |||
396 | |||
397 | /* Shim bitrate controls. */ | ||
398 | |||
399 | /** The number of bits used to store the shim id. */ | ||
400 | #define SIM_CONTROL_SHAPING_SHIM_ID_BITS 3 | ||
401 | |||
402 | /** | ||
403 | * @addtogroup arch_sim | ||
404 | * @{ | ||
405 | */ | ||
406 | |||
407 | /** Change the gbe 0 bitrate. */ | ||
408 | #define SIM_CONTROL_SHAPING_GBE_0 0x0 | ||
409 | |||
410 | /** Change the gbe 1 bitrate. */ | ||
411 | #define SIM_CONTROL_SHAPING_GBE_1 0x1 | ||
412 | |||
413 | /** Change the gbe 2 bitrate. */ | ||
414 | #define SIM_CONTROL_SHAPING_GBE_2 0x2 | ||
415 | |||
416 | /** Change the gbe 3 bitrate. */ | ||
417 | #define SIM_CONTROL_SHAPING_GBE_3 0x3 | ||
418 | |||
419 | /** Change the xgbe 0 bitrate. */ | ||
420 | #define SIM_CONTROL_SHAPING_XGBE_0 0x4 | ||
421 | |||
422 | /** Change the xgbe 1 bitrate. */ | ||
423 | #define SIM_CONTROL_SHAPING_XGBE_1 0x5 | ||
424 | |||
425 | /** The type of shaping to do. */ | ||
426 | #define SIM_CONTROL_SHAPING_TYPE_BITS 2 | ||
427 | |||
428 | /** Control the multiplier. */ | ||
429 | #define SIM_CONTROL_SHAPING_MULTIPLIER 0 | ||
430 | |||
431 | /** Control the PPS. */ | ||
432 | #define SIM_CONTROL_SHAPING_PPS 1 | ||
433 | |||
434 | /** Control the BPS. */ | ||
435 | #define SIM_CONTROL_SHAPING_BPS 2 | ||
436 | |||
437 | /** The number of bits for the units for the shaping parameter. */ | ||
438 | #define SIM_CONTROL_SHAPING_UNITS_BITS 2 | ||
439 | |||
440 | /** Provide a number in single units. */ | ||
441 | #define SIM_CONTROL_SHAPING_UNITS_SINGLE 0 | ||
442 | |||
443 | /** Provide a number in kilo units. */ | ||
444 | #define SIM_CONTROL_SHAPING_UNITS_KILO 1 | ||
445 | |||
446 | /** Provide a number in mega units. */ | ||
447 | #define SIM_CONTROL_SHAPING_UNITS_MEGA 2 | ||
448 | |||
449 | /** Provide a number in giga units. */ | ||
450 | #define SIM_CONTROL_SHAPING_UNITS_GIGA 3 | ||
451 | |||
452 | /** @} */ | ||
453 | |||
454 | /** How many bits are available for the rate. */ | ||
455 | #define SIM_CONTROL_SHAPING_RATE_BITS \ | ||
456 | (32 - (_SIM_CONTROL_OPERATOR_BITS + \ | ||
457 | SIM_CONTROL_SHAPING_SHIM_ID_BITS + \ | ||
458 | SIM_CONTROL_SHAPING_TYPE_BITS + \ | ||
459 | SIM_CONTROL_SHAPING_UNITS_BITS)) | ||
460 | |||
461 | /** Computes the value to write to SPR_SIM_CONTROL to change a bitrate. */ | ||
462 | #define SIM_SHAPING_SPR_ARG(shim, type, units, rate) \ | ||
463 | (SIM_CONTROL_SHAPING | \ | ||
464 | ((shim) | \ | ||
465 | ((type) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS)) | \ | ||
466 | ((units) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS + \ | ||
467 | SIM_CONTROL_SHAPING_TYPE_BITS)) | \ | ||
468 | ((rate) << (SIM_CONTROL_SHAPING_SHIM_ID_BITS + \ | ||
469 | SIM_CONTROL_SHAPING_TYPE_BITS + \ | ||
470 | SIM_CONTROL_SHAPING_UNITS_BITS))) << _SIM_CONTROL_OPERATOR_BITS) | ||
471 | |||
472 | |||
473 | /* | ||
474 | * Values returned when reading SPR_SIM_CONTROL. | ||
475 | * ISSUE: These names should share a longer common prefix. | ||
476 | */ | ||
477 | |||
478 | /** | ||
479 | * When reading SPR_SIM_CONTROL, the mask of simulator tracing bits | ||
480 | * (SIM_TRACE_xxx values). | ||
481 | */ | ||
482 | #define SIM_TRACE_FLAG_MASK 0xFFFF | ||
483 | |||
484 | /** When reading SPR_SIM_CONTROL, the mask for whether profiling is enabled. */ | ||
485 | #define SIM_PROFILER_ENABLED_MASK 0x10000 | ||
486 | |||
487 | |||
488 | /* | ||
489 | * Special arguments for "SIM_CONTROL_PUTC". | ||
490 | */ | ||
491 | |||
492 | /** | ||
493 | * Flag value for forcing a PUTC string-flush, including | ||
494 | * coordinate/cycle prefix and newline. | ||
495 | */ | ||
496 | #define SIM_PUTC_FLUSH_STRING 0x100 | ||
497 | |||
498 | /** | ||
499 | * Flag value for forcing a PUTC binary-data-flush, which skips the | ||
500 | * prefix and does not append a newline. | ||
501 | */ | ||
502 | #define SIM_PUTC_FLUSH_BINARY 0x101 | ||
503 | |||
504 | |||
505 | #endif /* __ARCH_SIM_DEF_H__ */ | ||
diff --git a/arch/tile/include/uapi/arch/spr_def.h b/arch/tile/include/uapi/arch/spr_def.h new file mode 100644 index 000000000000..c250c5adb1a6 --- /dev/null +++ b/arch/tile/include/uapi/arch/spr_def.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | #ifndef _UAPI__ARCH_SPR_DEF_H__ | ||
16 | #define _UAPI__ARCH_SPR_DEF_H__ | ||
17 | |||
18 | /* Include the proper base SPR definition file. */ | ||
19 | #ifdef __tilegx__ | ||
20 | #include <arch/spr_def_64.h> | ||
21 | #else | ||
22 | #include <arch/spr_def_32.h> | ||
23 | #endif | ||
24 | |||
25 | |||
26 | #endif /* _UAPI__ARCH_SPR_DEF_H__ */ | ||
diff --git a/arch/tile/include/uapi/arch/spr_def_32.h b/arch/tile/include/uapi/arch/spr_def_32.h new file mode 100644 index 000000000000..c689446e6284 --- /dev/null +++ b/arch/tile/include/uapi/arch/spr_def_32.h | |||
@@ -0,0 +1,257 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | #ifndef __DOXYGEN__ | ||
16 | |||
17 | #ifndef __ARCH_SPR_DEF_32_H__ | ||
18 | #define __ARCH_SPR_DEF_32_H__ | ||
19 | |||
20 | #define SPR_AUX_PERF_COUNT_0 0x6005 | ||
21 | #define SPR_AUX_PERF_COUNT_1 0x6006 | ||
22 | #define SPR_AUX_PERF_COUNT_CTL 0x6007 | ||
23 | #define SPR_AUX_PERF_COUNT_STS 0x6008 | ||
24 | #define SPR_CYCLE_HIGH 0x4e06 | ||
25 | #define SPR_CYCLE_LOW 0x4e07 | ||
26 | #define SPR_DMA_BYTE 0x3900 | ||
27 | #define SPR_DMA_CHUNK_SIZE 0x3901 | ||
28 | #define SPR_DMA_CTR 0x3902 | ||
29 | #define SPR_DMA_CTR__REQUEST_MASK 0x1 | ||
30 | #define SPR_DMA_CTR__SUSPEND_MASK 0x2 | ||
31 | #define SPR_DMA_DST_ADDR 0x3903 | ||
32 | #define SPR_DMA_DST_CHUNK_ADDR 0x3904 | ||
33 | #define SPR_DMA_SRC_ADDR 0x3905 | ||
34 | #define SPR_DMA_SRC_CHUNK_ADDR 0x3906 | ||
35 | #define SPR_DMA_STATUS__DONE_MASK 0x1 | ||
36 | #define SPR_DMA_STATUS__BUSY_MASK 0x2 | ||
37 | #define SPR_DMA_STATUS__RUNNING_MASK 0x10 | ||
38 | #define SPR_DMA_STRIDE 0x3907 | ||
39 | #define SPR_DMA_USER_STATUS 0x3908 | ||
40 | #define SPR_DONE 0x4e08 | ||
41 | #define SPR_EVENT_BEGIN 0x4e0d | ||
42 | #define SPR_EVENT_END 0x4e0e | ||
43 | #define SPR_EX_CONTEXT_0_0 0x4a05 | ||
44 | #define SPR_EX_CONTEXT_0_1 0x4a06 | ||
45 | #define SPR_EX_CONTEXT_0_1__PL_SHIFT 0 | ||
46 | #define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3 | ||
47 | #define SPR_EX_CONTEXT_0_1__PL_MASK 0x3 | ||
48 | #define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2 | ||
49 | #define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1 | ||
50 | #define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4 | ||
51 | #define SPR_EX_CONTEXT_1_0 0x4805 | ||
52 | #define SPR_EX_CONTEXT_1_1 0x4806 | ||
53 | #define SPR_EX_CONTEXT_1_1__PL_SHIFT 0 | ||
54 | #define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3 | ||
55 | #define SPR_EX_CONTEXT_1_1__PL_MASK 0x3 | ||
56 | #define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2 | ||
57 | #define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1 | ||
58 | #define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4 | ||
59 | #define SPR_EX_CONTEXT_2_0 0x4605 | ||
60 | #define SPR_EX_CONTEXT_2_1 0x4606 | ||
61 | #define SPR_EX_CONTEXT_2_1__PL_SHIFT 0 | ||
62 | #define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3 | ||
63 | #define SPR_EX_CONTEXT_2_1__PL_MASK 0x3 | ||
64 | #define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2 | ||
65 | #define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1 | ||
66 | #define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4 | ||
67 | #define SPR_FAIL 0x4e09 | ||
68 | #define SPR_IDN_AVAIL_EN 0x3e05 | ||
69 | #define SPR_IDN_CA_DATA 0x0b00 | ||
70 | #define SPR_IDN_DATA_AVAIL 0x0b03 | ||
71 | #define SPR_IDN_DEADLOCK_TIMEOUT 0x3406 | ||
72 | #define SPR_IDN_DEMUX_CA_COUNT 0x0a05 | ||
73 | #define SPR_IDN_DEMUX_COUNT_0 0x0a06 | ||
74 | #define SPR_IDN_DEMUX_COUNT_1 0x0a07 | ||
75 | #define SPR_IDN_DEMUX_CTL 0x0a08 | ||
76 | #define SPR_IDN_DEMUX_QUEUE_SEL 0x0a0a | ||
77 | #define SPR_IDN_DEMUX_STATUS 0x0a0b | ||
78 | #define SPR_IDN_DEMUX_WRITE_FIFO 0x0a0c | ||
79 | #define SPR_IDN_DIRECTION_PROTECT 0x2e05 | ||
80 | #define SPR_IDN_PENDING 0x0a0e | ||
81 | #define SPR_IDN_REFILL_EN 0x0e05 | ||
82 | #define SPR_IDN_SP_FIFO_DATA 0x0a0f | ||
83 | #define SPR_IDN_SP_FIFO_SEL 0x0a10 | ||
84 | #define SPR_IDN_SP_FREEZE 0x0a11 | ||
85 | #define SPR_IDN_SP_FREEZE__SP_FRZ_MASK 0x1 | ||
86 | #define SPR_IDN_SP_FREEZE__DEMUX_FRZ_MASK 0x2 | ||
87 | #define SPR_IDN_SP_FREEZE__NON_DEST_EXT_MASK 0x4 | ||
88 | #define SPR_IDN_SP_STATE 0x0a12 | ||
89 | #define SPR_IDN_TAG_0 0x0a13 | ||
90 | #define SPR_IDN_TAG_1 0x0a14 | ||
91 | #define SPR_IDN_TAG_VALID 0x0a15 | ||
92 | #define SPR_IDN_TILE_COORD 0x0a16 | ||
93 | #define SPR_INTCTRL_0_STATUS 0x4a07 | ||
94 | #define SPR_INTCTRL_1_STATUS 0x4807 | ||
95 | #define SPR_INTCTRL_2_STATUS 0x4607 | ||
96 | #define SPR_INTERRUPT_CRITICAL_SECTION 0x4e0a | ||
97 | #define SPR_INTERRUPT_MASK_0_0 0x4a08 | ||
98 | #define SPR_INTERRUPT_MASK_0_1 0x4a09 | ||
99 | #define SPR_INTERRUPT_MASK_1_0 0x4809 | ||
100 | #define SPR_INTERRUPT_MASK_1_1 0x480a | ||
101 | #define SPR_INTERRUPT_MASK_2_0 0x4608 | ||
102 | #define SPR_INTERRUPT_MASK_2_1 0x4609 | ||
103 | #define SPR_INTERRUPT_MASK_RESET_0_0 0x4a0a | ||
104 | #define SPR_INTERRUPT_MASK_RESET_0_1 0x4a0b | ||
105 | #define SPR_INTERRUPT_MASK_RESET_1_0 0x480b | ||
106 | #define SPR_INTERRUPT_MASK_RESET_1_1 0x480c | ||
107 | #define SPR_INTERRUPT_MASK_RESET_2_0 0x460a | ||
108 | #define SPR_INTERRUPT_MASK_RESET_2_1 0x460b | ||
109 | #define SPR_INTERRUPT_MASK_SET_0_0 0x4a0c | ||
110 | #define SPR_INTERRUPT_MASK_SET_0_1 0x4a0d | ||
111 | #define SPR_INTERRUPT_MASK_SET_1_0 0x480d | ||
112 | #define SPR_INTERRUPT_MASK_SET_1_1 0x480e | ||
113 | #define SPR_INTERRUPT_MASK_SET_2_0 0x460c | ||
114 | #define SPR_INTERRUPT_MASK_SET_2_1 0x460d | ||
115 | #define SPR_MPL_AUX_PERF_COUNT_SET_0 0x6000 | ||
116 | #define SPR_MPL_AUX_PERF_COUNT_SET_1 0x6001 | ||
117 | #define SPR_MPL_AUX_PERF_COUNT_SET_2 0x6002 | ||
118 | #define SPR_MPL_DMA_CPL_SET_0 0x5800 | ||
119 | #define SPR_MPL_DMA_CPL_SET_1 0x5801 | ||
120 | #define SPR_MPL_DMA_CPL_SET_2 0x5802 | ||
121 | #define SPR_MPL_DMA_NOTIFY_SET_0 0x3800 | ||
122 | #define SPR_MPL_DMA_NOTIFY_SET_1 0x3801 | ||
123 | #define SPR_MPL_DMA_NOTIFY_SET_2 0x3802 | ||
124 | #define SPR_MPL_IDN_ACCESS_SET_0 0x0a00 | ||
125 | #define SPR_MPL_IDN_ACCESS_SET_1 0x0a01 | ||
126 | #define SPR_MPL_IDN_ACCESS_SET_2 0x0a02 | ||
127 | #define SPR_MPL_IDN_AVAIL_SET_0 0x3e00 | ||
128 | #define SPR_MPL_IDN_AVAIL_SET_1 0x3e01 | ||
129 | #define SPR_MPL_IDN_AVAIL_SET_2 0x3e02 | ||
130 | #define SPR_MPL_IDN_CA_SET_0 0x3a00 | ||
131 | #define SPR_MPL_IDN_CA_SET_1 0x3a01 | ||
132 | #define SPR_MPL_IDN_CA_SET_2 0x3a02 | ||
133 | #define SPR_MPL_IDN_COMPLETE_SET_0 0x1200 | ||
134 | #define SPR_MPL_IDN_COMPLETE_SET_1 0x1201 | ||
135 | #define SPR_MPL_IDN_COMPLETE_SET_2 0x1202 | ||
136 | #define SPR_MPL_IDN_FIREWALL_SET_0 0x2e00 | ||
137 | #define SPR_MPL_IDN_FIREWALL_SET_1 0x2e01 | ||
138 | #define SPR_MPL_IDN_FIREWALL_SET_2 0x2e02 | ||
139 | #define SPR_MPL_IDN_REFILL_SET_0 0x0e00 | ||
140 | #define SPR_MPL_IDN_REFILL_SET_1 0x0e01 | ||
141 | #define SPR_MPL_IDN_REFILL_SET_2 0x0e02 | ||
142 | #define SPR_MPL_IDN_TIMER_SET_0 0x3400 | ||
143 | #define SPR_MPL_IDN_TIMER_SET_1 0x3401 | ||
144 | #define SPR_MPL_IDN_TIMER_SET_2 0x3402 | ||
145 | #define SPR_MPL_INTCTRL_0_SET_0 0x4a00 | ||
146 | #define SPR_MPL_INTCTRL_0_SET_1 0x4a01 | ||
147 | #define SPR_MPL_INTCTRL_0_SET_2 0x4a02 | ||
148 | #define SPR_MPL_INTCTRL_1_SET_0 0x4800 | ||
149 | #define SPR_MPL_INTCTRL_1_SET_1 0x4801 | ||
150 | #define SPR_MPL_INTCTRL_1_SET_2 0x4802 | ||
151 | #define SPR_MPL_INTCTRL_2_SET_0 0x4600 | ||
152 | #define SPR_MPL_INTCTRL_2_SET_1 0x4601 | ||
153 | #define SPR_MPL_INTCTRL_2_SET_2 0x4602 | ||
154 | #define SPR_MPL_PERF_COUNT_SET_0 0x4200 | ||
155 | #define SPR_MPL_PERF_COUNT_SET_1 0x4201 | ||
156 | #define SPR_MPL_PERF_COUNT_SET_2 0x4202 | ||
157 | #define SPR_MPL_SN_ACCESS_SET_0 0x0800 | ||
158 | #define SPR_MPL_SN_ACCESS_SET_1 0x0801 | ||
159 | #define SPR_MPL_SN_ACCESS_SET_2 0x0802 | ||
160 | #define SPR_MPL_SN_CPL_SET_0 0x5a00 | ||
161 | #define SPR_MPL_SN_CPL_SET_1 0x5a01 | ||
162 | #define SPR_MPL_SN_CPL_SET_2 0x5a02 | ||
163 | #define SPR_MPL_SN_FIREWALL_SET_0 0x2c00 | ||
164 | #define SPR_MPL_SN_FIREWALL_SET_1 0x2c01 | ||
165 | #define SPR_MPL_SN_FIREWALL_SET_2 0x2c02 | ||
166 | #define SPR_MPL_SN_NOTIFY_SET_0 0x2a00 | ||
167 | #define SPR_MPL_SN_NOTIFY_SET_1 0x2a01 | ||
168 | #define SPR_MPL_SN_NOTIFY_SET_2 0x2a02 | ||
169 | #define SPR_MPL_UDN_ACCESS_SET_0 0x0c00 | ||
170 | #define SPR_MPL_UDN_ACCESS_SET_1 0x0c01 | ||
171 | #define SPR_MPL_UDN_ACCESS_SET_2 0x0c02 | ||
172 | #define SPR_MPL_UDN_AVAIL_SET_0 0x4000 | ||
173 | #define SPR_MPL_UDN_AVAIL_SET_1 0x4001 | ||
174 | #define SPR_MPL_UDN_AVAIL_SET_2 0x4002 | ||
175 | #define SPR_MPL_UDN_CA_SET_0 0x3c00 | ||
176 | #define SPR_MPL_UDN_CA_SET_1 0x3c01 | ||
177 | #define SPR_MPL_UDN_CA_SET_2 0x3c02 | ||
178 | #define SPR_MPL_UDN_COMPLETE_SET_0 0x1400 | ||
179 | #define SPR_MPL_UDN_COMPLETE_SET_1 0x1401 | ||
180 | #define SPR_MPL_UDN_COMPLETE_SET_2 0x1402 | ||
181 | #define SPR_MPL_UDN_FIREWALL_SET_0 0x3000 | ||
182 | #define SPR_MPL_UDN_FIREWALL_SET_1 0x3001 | ||
183 | #define SPR_MPL_UDN_FIREWALL_SET_2 0x3002 | ||
184 | #define SPR_MPL_UDN_REFILL_SET_0 0x1000 | ||
185 | #define SPR_MPL_UDN_REFILL_SET_1 0x1001 | ||
186 | #define SPR_MPL_UDN_REFILL_SET_2 0x1002 | ||
187 | #define SPR_MPL_UDN_TIMER_SET_0 0x3600 | ||
188 | #define SPR_MPL_UDN_TIMER_SET_1 0x3601 | ||
189 | #define SPR_MPL_UDN_TIMER_SET_2 0x3602 | ||
190 | #define SPR_MPL_WORLD_ACCESS_SET_0 0x4e00 | ||
191 | #define SPR_MPL_WORLD_ACCESS_SET_1 0x4e01 | ||
192 | #define SPR_MPL_WORLD_ACCESS_SET_2 0x4e02 | ||
193 | #define SPR_PASS 0x4e0b | ||
194 | #define SPR_PERF_COUNT_0 0x4205 | ||
195 | #define SPR_PERF_COUNT_1 0x4206 | ||
196 | #define SPR_PERF_COUNT_CTL 0x4207 | ||
197 | #define SPR_PERF_COUNT_DN_CTL 0x4210 | ||
198 | #define SPR_PERF_COUNT_STS 0x4208 | ||
199 | #define SPR_PROC_STATUS 0x4f00 | ||
200 | #define SPR_SIM_CONTROL 0x4e0c | ||
201 | #define SPR_SNCTL 0x0805 | ||
202 | #define SPR_SNCTL__FRZFABRIC_MASK 0x1 | ||
203 | #define SPR_SNCTL__FRZPROC_MASK 0x2 | ||
204 | #define SPR_SNPC 0x080b | ||
205 | #define SPR_SNSTATIC 0x080c | ||
206 | #define SPR_SYSTEM_SAVE_0_0 0x4b00 | ||
207 | #define SPR_SYSTEM_SAVE_0_1 0x4b01 | ||
208 | #define SPR_SYSTEM_SAVE_0_2 0x4b02 | ||
209 | #define SPR_SYSTEM_SAVE_0_3 0x4b03 | ||
210 | #define SPR_SYSTEM_SAVE_1_0 0x4900 | ||
211 | #define SPR_SYSTEM_SAVE_1_1 0x4901 | ||
212 | #define SPR_SYSTEM_SAVE_1_2 0x4902 | ||
213 | #define SPR_SYSTEM_SAVE_1_3 0x4903 | ||
214 | #define SPR_SYSTEM_SAVE_2_0 0x4700 | ||
215 | #define SPR_SYSTEM_SAVE_2_1 0x4701 | ||
216 | #define SPR_SYSTEM_SAVE_2_2 0x4702 | ||
217 | #define SPR_SYSTEM_SAVE_2_3 0x4703 | ||
218 | #define SPR_TILE_COORD 0x4c17 | ||
219 | #define SPR_TILE_RTF_HWM 0x4e10 | ||
220 | #define SPR_TILE_TIMER_CONTROL 0x3205 | ||
221 | #define SPR_TILE_WRITE_PENDING 0x4e0f | ||
222 | #define SPR_UDN_AVAIL_EN 0x4005 | ||
223 | #define SPR_UDN_CA_DATA 0x0d00 | ||
224 | #define SPR_UDN_DATA_AVAIL 0x0d03 | ||
225 | #define SPR_UDN_DEADLOCK_TIMEOUT 0x3606 | ||
226 | #define SPR_UDN_DEMUX_CA_COUNT 0x0c05 | ||
227 | #define SPR_UDN_DEMUX_COUNT_0 0x0c06 | ||
228 | #define SPR_UDN_DEMUX_COUNT_1 0x0c07 | ||
229 | #define SPR_UDN_DEMUX_COUNT_2 0x0c08 | ||
230 | #define SPR_UDN_DEMUX_COUNT_3 0x0c09 | ||
231 | #define SPR_UDN_DEMUX_CTL 0x0c0a | ||
232 | #define SPR_UDN_DEMUX_QUEUE_SEL 0x0c0c | ||
233 | #define SPR_UDN_DEMUX_STATUS 0x0c0d | ||
234 | #define SPR_UDN_DEMUX_WRITE_FIFO 0x0c0e | ||
235 | #define SPR_UDN_DIRECTION_PROTECT 0x3005 | ||
236 | #define SPR_UDN_PENDING 0x0c10 | ||
237 | #define SPR_UDN_REFILL_EN 0x1005 | ||
238 | #define SPR_UDN_SP_FIFO_DATA 0x0c11 | ||
239 | #define SPR_UDN_SP_FIFO_SEL 0x0c12 | ||
240 | #define SPR_UDN_SP_FREEZE 0x0c13 | ||
241 | #define SPR_UDN_SP_FREEZE__SP_FRZ_MASK 0x1 | ||
242 | #define SPR_UDN_SP_FREEZE__DEMUX_FRZ_MASK 0x2 | ||
243 | #define SPR_UDN_SP_FREEZE__NON_DEST_EXT_MASK 0x4 | ||
244 | #define SPR_UDN_SP_STATE 0x0c14 | ||
245 | #define SPR_UDN_TAG_0 0x0c15 | ||
246 | #define SPR_UDN_TAG_1 0x0c16 | ||
247 | #define SPR_UDN_TAG_2 0x0c17 | ||
248 | #define SPR_UDN_TAG_3 0x0c18 | ||
249 | #define SPR_UDN_TAG_VALID 0x0c19 | ||
250 | #define SPR_UDN_TILE_COORD 0x0c1a | ||
251 | #define SPR_WATCH_CTL 0x4209 | ||
252 | #define SPR_WATCH_MASK 0x420a | ||
253 | #define SPR_WATCH_VAL 0x420b | ||
254 | |||
255 | #endif /* !defined(__ARCH_SPR_DEF_32_H__) */ | ||
256 | |||
257 | #endif /* !defined(__DOXYGEN__) */ | ||
diff --git a/arch/tile/include/uapi/arch/spr_def_64.h b/arch/tile/include/uapi/arch/spr_def_64.h new file mode 100644 index 000000000000..67a6c1751e3b --- /dev/null +++ b/arch/tile/include/uapi/arch/spr_def_64.h | |||
@@ -0,0 +1,216 @@ | |||
1 | /* | ||
2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | #ifndef __DOXYGEN__ | ||
16 | |||
17 | #ifndef __ARCH_SPR_DEF_64_H__ | ||
18 | #define __ARCH_SPR_DEF_64_H__ | ||
19 | |||
20 | #define SPR_AUX_PERF_COUNT_0 0x2105 | ||
21 | #define SPR_AUX_PERF_COUNT_1 0x2106 | ||
22 | #define SPR_AUX_PERF_COUNT_CTL 0x2107 | ||
23 | #define SPR_AUX_PERF_COUNT_STS 0x2108 | ||
24 | #define SPR_CMPEXCH_VALUE 0x2780 | ||
25 | #define SPR_CYCLE 0x2781 | ||
26 | #define SPR_DONE 0x2705 | ||
27 | #define SPR_DSTREAM_PF 0x2706 | ||
28 | #define SPR_EVENT_BEGIN 0x2782 | ||
29 | #define SPR_EVENT_END 0x2783 | ||
30 | #define SPR_EX_CONTEXT_0_0 0x2580 | ||
31 | #define SPR_EX_CONTEXT_0_1 0x2581 | ||
32 | #define SPR_EX_CONTEXT_0_1__PL_SHIFT 0 | ||
33 | #define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3 | ||
34 | #define SPR_EX_CONTEXT_0_1__PL_MASK 0x3 | ||
35 | #define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2 | ||
36 | #define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1 | ||
37 | #define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4 | ||
38 | #define SPR_EX_CONTEXT_1_0 0x2480 | ||
39 | #define SPR_EX_CONTEXT_1_1 0x2481 | ||
40 | #define SPR_EX_CONTEXT_1_1__PL_SHIFT 0 | ||
41 | #define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3 | ||
42 | #define SPR_EX_CONTEXT_1_1__PL_MASK 0x3 | ||
43 | #define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2 | ||
44 | #define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1 | ||
45 | #define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4 | ||
46 | #define SPR_EX_CONTEXT_2_0 0x2380 | ||
47 | #define SPR_EX_CONTEXT_2_1 0x2381 | ||
48 | #define SPR_EX_CONTEXT_2_1__PL_SHIFT 0 | ||
49 | #define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3 | ||
50 | #define SPR_EX_CONTEXT_2_1__PL_MASK 0x3 | ||
51 | #define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2 | ||
52 | #define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1 | ||
53 | #define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4 | ||
54 | #define SPR_FAIL 0x2707 | ||
55 | #define SPR_IDN_AVAIL_EN 0x1a05 | ||
56 | #define SPR_IDN_DATA_AVAIL 0x0a80 | ||
57 | #define SPR_IDN_DEADLOCK_TIMEOUT 0x1806 | ||
58 | #define SPR_IDN_DEMUX_COUNT_0 0x0a05 | ||
59 | #define SPR_IDN_DEMUX_COUNT_1 0x0a06 | ||
60 | #define SPR_IDN_DIRECTION_PROTECT 0x1405 | ||
61 | #define SPR_IDN_PENDING 0x0a08 | ||
62 | #define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1 | ||
63 | #define SPR_INTCTRL_0_STATUS 0x2505 | ||
64 | #define SPR_INTCTRL_1_STATUS 0x2405 | ||
65 | #define SPR_INTCTRL_2_STATUS 0x2305 | ||
66 | #define SPR_INTERRUPT_CRITICAL_SECTION 0x2708 | ||
67 | #define SPR_INTERRUPT_MASK_0 0x2506 | ||
68 | #define SPR_INTERRUPT_MASK_1 0x2406 | ||
69 | #define SPR_INTERRUPT_MASK_2 0x2306 | ||
70 | #define SPR_INTERRUPT_MASK_RESET_0 0x2507 | ||
71 | #define SPR_INTERRUPT_MASK_RESET_1 0x2407 | ||
72 | #define SPR_INTERRUPT_MASK_RESET_2 0x2307 | ||
73 | #define SPR_INTERRUPT_MASK_SET_0 0x2508 | ||
74 | #define SPR_INTERRUPT_MASK_SET_1 0x2408 | ||
75 | #define SPR_INTERRUPT_MASK_SET_2 0x2308 | ||
76 | #define SPR_INTERRUPT_VECTOR_BASE_0 0x2509 | ||
77 | #define SPR_INTERRUPT_VECTOR_BASE_1 0x2409 | ||
78 | #define SPR_INTERRUPT_VECTOR_BASE_2 0x2309 | ||
79 | #define SPR_INTERRUPT_VECTOR_BASE_3 0x2209 | ||
80 | #define SPR_IPI_EVENT_0 0x1f05 | ||
81 | #define SPR_IPI_EVENT_1 0x1e05 | ||
82 | #define SPR_IPI_EVENT_2 0x1d05 | ||
83 | #define SPR_IPI_EVENT_RESET_0 0x1f06 | ||
84 | #define SPR_IPI_EVENT_RESET_1 0x1e06 | ||
85 | #define SPR_IPI_EVENT_RESET_2 0x1d06 | ||
86 | #define SPR_IPI_EVENT_SET_0 0x1f07 | ||
87 | #define SPR_IPI_EVENT_SET_1 0x1e07 | ||
88 | #define SPR_IPI_EVENT_SET_2 0x1d07 | ||
89 | #define SPR_IPI_MASK_0 0x1f08 | ||
90 | #define SPR_IPI_MASK_1 0x1e08 | ||
91 | #define SPR_IPI_MASK_2 0x1d08 | ||
92 | #define SPR_IPI_MASK_RESET_0 0x1f09 | ||
93 | #define SPR_IPI_MASK_RESET_1 0x1e09 | ||
94 | #define SPR_IPI_MASK_RESET_2 0x1d09 | ||
95 | #define SPR_IPI_MASK_SET_0 0x1f0a | ||
96 | #define SPR_IPI_MASK_SET_1 0x1e0a | ||
97 | #define SPR_IPI_MASK_SET_2 0x1d0a | ||
98 | #define SPR_MPL_AUX_PERF_COUNT_SET_0 0x2100 | ||
99 | #define SPR_MPL_AUX_PERF_COUNT_SET_1 0x2101 | ||
100 | #define SPR_MPL_AUX_PERF_COUNT_SET_2 0x2102 | ||
101 | #define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700 | ||
102 | #define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701 | ||
103 | #define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702 | ||
104 | #define SPR_MPL_IDN_ACCESS_SET_0 0x0a00 | ||
105 | #define SPR_MPL_IDN_ACCESS_SET_1 0x0a01 | ||
106 | #define SPR_MPL_IDN_ACCESS_SET_2 0x0a02 | ||
107 | #define SPR_MPL_IDN_AVAIL_SET_0 0x1a00 | ||
108 | #define SPR_MPL_IDN_AVAIL_SET_1 0x1a01 | ||
109 | #define SPR_MPL_IDN_AVAIL_SET_2 0x1a02 | ||
110 | #define SPR_MPL_IDN_COMPLETE_SET_0 0x0500 | ||
111 | #define SPR_MPL_IDN_COMPLETE_SET_1 0x0501 | ||
112 | #define SPR_MPL_IDN_COMPLETE_SET_2 0x0502 | ||
113 | #define SPR_MPL_IDN_FIREWALL_SET_0 0x1400 | ||
114 | #define SPR_MPL_IDN_FIREWALL_SET_1 0x1401 | ||
115 | #define SPR_MPL_IDN_FIREWALL_SET_2 0x1402 | ||
116 | #define SPR_MPL_IDN_TIMER_SET_0 0x1800 | ||
117 | #define SPR_MPL_IDN_TIMER_SET_1 0x1801 | ||
118 | #define SPR_MPL_IDN_TIMER_SET_2 0x1802 | ||
119 | #define SPR_MPL_INTCTRL_0_SET_0 0x2500 | ||
120 | #define SPR_MPL_INTCTRL_0_SET_1 0x2501 | ||
121 | #define SPR_MPL_INTCTRL_0_SET_2 0x2502 | ||
122 | #define SPR_MPL_INTCTRL_1_SET_0 0x2400 | ||
123 | #define SPR_MPL_INTCTRL_1_SET_1 0x2401 | ||
124 | #define SPR_MPL_INTCTRL_1_SET_2 0x2402 | ||
125 | #define SPR_MPL_INTCTRL_2_SET_0 0x2300 | ||
126 | #define SPR_MPL_INTCTRL_2_SET_1 0x2301 | ||
127 | #define SPR_MPL_INTCTRL_2_SET_2 0x2302 | ||
128 | #define SPR_MPL_IPI_0 0x1f04 | ||
129 | #define SPR_MPL_IPI_0_SET_0 0x1f00 | ||
130 | #define SPR_MPL_IPI_0_SET_1 0x1f01 | ||
131 | #define SPR_MPL_IPI_0_SET_2 0x1f02 | ||
132 | #define SPR_MPL_IPI_1 0x1e04 | ||
133 | #define SPR_MPL_IPI_1_SET_0 0x1e00 | ||
134 | #define SPR_MPL_IPI_1_SET_1 0x1e01 | ||
135 | #define SPR_MPL_IPI_1_SET_2 0x1e02 | ||
136 | #define SPR_MPL_IPI_2 0x1d04 | ||
137 | #define SPR_MPL_IPI_2_SET_0 0x1d00 | ||
138 | #define SPR_MPL_IPI_2_SET_1 0x1d01 | ||
139 | #define SPR_MPL_IPI_2_SET_2 0x1d02 | ||
140 | #define SPR_MPL_PERF_COUNT_SET_0 0x2000 | ||
141 | #define SPR_MPL_PERF_COUNT_SET_1 0x2001 | ||
142 | #define SPR_MPL_PERF_COUNT_SET_2 0x2002 | ||
143 | #define SPR_MPL_UDN_ACCESS_SET_0 0x0b00 | ||
144 | #define SPR_MPL_UDN_ACCESS_SET_1 0x0b01 | ||
145 | #define SPR_MPL_UDN_ACCESS_SET_2 0x0b02 | ||
146 | #define SPR_MPL_UDN_AVAIL_SET_0 0x1b00 | ||
147 | #define SPR_MPL_UDN_AVAIL_SET_1 0x1b01 | ||
148 | #define SPR_MPL_UDN_AVAIL_SET_2 0x1b02 | ||
149 | #define SPR_MPL_UDN_COMPLETE_SET_0 0x0600 | ||
150 | #define SPR_MPL_UDN_COMPLETE_SET_1 0x0601 | ||
151 | #define SPR_MPL_UDN_COMPLETE_SET_2 0x0602 | ||
152 | #define SPR_MPL_UDN_FIREWALL_SET_0 0x1500 | ||
153 | #define SPR_MPL_UDN_FIREWALL_SET_1 0x1501 | ||
154 | #define SPR_MPL_UDN_FIREWALL_SET_2 0x1502 | ||
155 | #define SPR_MPL_UDN_TIMER_SET_0 0x1900 | ||
156 | #define SPR_MPL_UDN_TIMER_SET_1 0x1901 | ||
157 | #define SPR_MPL_UDN_TIMER_SET_2 0x1902 | ||
158 | #define SPR_MPL_WORLD_ACCESS_SET_0 0x2700 | ||
159 | #define SPR_MPL_WORLD_ACCESS_SET_1 0x2701 | ||
160 | #define SPR_MPL_WORLD_ACCESS_SET_2 0x2702 | ||
161 | #define SPR_PASS 0x2709 | ||
162 | #define SPR_PERF_COUNT_0 0x2005 | ||
163 | #define SPR_PERF_COUNT_1 0x2006 | ||
164 | #define SPR_PERF_COUNT_CTL 0x2007 | ||
165 | #define SPR_PERF_COUNT_DN_CTL 0x2008 | ||
166 | #define SPR_PERF_COUNT_STS 0x2009 | ||
167 | #define SPR_PROC_STATUS 0x2784 | ||
168 | #define SPR_SIM_CONTROL 0x2785 | ||
169 | #define SPR_SINGLE_STEP_CONTROL_0 0x0405 | ||
170 | #define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK 0x1 | ||
171 | #define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK 0x2 | ||
172 | #define SPR_SINGLE_STEP_CONTROL_1 0x0305 | ||
173 | #define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK 0x1 | ||
174 | #define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK 0x2 | ||
175 | #define SPR_SINGLE_STEP_CONTROL_2 0x0205 | ||
176 | #define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK 0x1 | ||
177 | #define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK 0x2 | ||
178 | #define SPR_SINGLE_STEP_EN_0_0 0x250a | ||
179 | #define SPR_SINGLE_STEP_EN_0_1 0x240a | ||
180 | #define SPR_SINGLE_STEP_EN_0_2 0x230a | ||
181 | #define SPR_SINGLE_STEP_EN_1_0 0x250b | ||
182 | #define SPR_SINGLE_STEP_EN_1_1 0x240b | ||
183 | #define SPR_SINGLE_STEP_EN_1_2 0x230b | ||
184 | #define SPR_SINGLE_STEP_EN_2_0 0x250c | ||
185 | #define SPR_SINGLE_STEP_EN_2_1 0x240c | ||
186 | #define SPR_SINGLE_STEP_EN_2_2 0x230c | ||
187 | #define SPR_SYSTEM_SAVE_0_0 0x2582 | ||
188 | #define SPR_SYSTEM_SAVE_0_1 0x2583 | ||
189 | #define SPR_SYSTEM_SAVE_0_2 0x2584 | ||
190 | #define SPR_SYSTEM_SAVE_0_3 0x2585 | ||
191 | #define SPR_SYSTEM_SAVE_1_0 0x2482 | ||
192 | #define SPR_SYSTEM_SAVE_1_1 0x2483 | ||
193 | #define SPR_SYSTEM_SAVE_1_2 0x2484 | ||
194 | #define SPR_SYSTEM_SAVE_1_3 0x2485 | ||
195 | #define SPR_SYSTEM_SAVE_2_0 0x2382 | ||
196 | #define SPR_SYSTEM_SAVE_2_1 0x2383 | ||
197 | #define SPR_SYSTEM_SAVE_2_2 0x2384 | ||
198 | #define SPR_SYSTEM_SAVE_2_3 0x2385 | ||
199 | #define SPR_TILE_COORD 0x270b | ||
200 | #define SPR_TILE_RTF_HWM 0x270c | ||
201 | #define SPR_TILE_TIMER_CONTROL 0x1605 | ||
202 | #define SPR_UDN_AVAIL_EN 0x1b05 | ||
203 | #define SPR_UDN_DATA_AVAIL 0x0b80 | ||
204 | #define SPR_UDN_DEADLOCK_TIMEOUT 0x1906 | ||
205 | #define SPR_UDN_DEMUX_COUNT_0 0x0b05 | ||
206 | #define SPR_UDN_DEMUX_COUNT_1 0x0b06 | ||
207 | #define SPR_UDN_DEMUX_COUNT_2 0x0b07 | ||
208 | #define SPR_UDN_DEMUX_COUNT_3 0x0b08 | ||
209 | #define SPR_UDN_DIRECTION_PROTECT 0x1505 | ||
210 | #define SPR_UDN_PENDING 0x0b0a | ||
211 | #define SPR_WATCH_MASK 0x200a | ||
212 | #define SPR_WATCH_VAL 0x200b | ||
213 | |||
214 | #endif /* !defined(__ARCH_SPR_DEF_64_H__) */ | ||
215 | |||
216 | #endif /* !defined(__DOXYGEN__) */ | ||