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authorChris Metcalf <cmetcalf@tilera.com>2013-07-23 17:32:04 -0400
committerChris Metcalf <cmetcalf@tilera.com>2013-07-31 11:51:19 -0400
commitdd78bc11fb2050b6a3990d0421feca4c68ca4335 (patch)
tree7147fe5e0b3815443eea608d3dd0950ba53bb47d /arch/tile/include/uapi/asm/cachectl.h
parent7d937719e3c5c6c9ad00584f6b62230d2ef7f9f1 (diff)
tile: convert uses of "inv" to "finv"
The "inv" (invalidate) instruction is generally less safe than "finv" (flush and invalidate), as it will drop dirty data from the cache. It turns out we have almost no need for "inv" (other than for the older 32-bit architecture in some limited cases), so convert to "finv" where possible and delete the extra "inv" infrastructure. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/include/uapi/asm/cachectl.h')
-rw-r--r--arch/tile/include/uapi/asm/cachectl.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/tile/include/uapi/asm/cachectl.h b/arch/tile/include/uapi/asm/cachectl.h
index af4c9f9154d1..572ddcad2090 100644
--- a/arch/tile/include/uapi/asm/cachectl.h
+++ b/arch/tile/include/uapi/asm/cachectl.h
@@ -29,8 +29,8 @@
29 * to honor the arguments at some point.) 29 * to honor the arguments at some point.)
30 * 30 *
31 * Flush and invalidation of memory can normally be performed with the 31 * Flush and invalidation of memory can normally be performed with the
32 * __insn_flush(), __insn_inv(), and __insn_finv() instructions from 32 * __insn_flush() and __insn_finv() instructions from userspace.
33 * userspace. The DCACHE option to the system call allows userspace 33 * The DCACHE option to the system call allows userspace
34 * to flush the entire L1+L2 data cache from the core. In this case, 34 * to flush the entire L1+L2 data cache from the core. In this case,
35 * the address and length arguments are not used. The DCACHE flush is 35 * the address and length arguments are not used. The DCACHE flush is
36 * restricted to the current core, not all cores in the address space. 36 * restricted to the current core, not all cores in the address space.