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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/tile/include/asm
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'arch/tile/include/asm')
-rw-r--r--arch/tile/include/asm/Kbuild1
-rw-r--r--arch/tile/include/asm/atomic.h51
-rw-r--r--arch/tile/include/asm/atomic_32.h10
-rw-r--r--arch/tile/include/asm/atomic_64.h156
-rw-r--r--arch/tile/include/asm/backtrace.h81
-rw-r--r--arch/tile/include/asm/bitops.h5
-rw-r--r--arch/tile/include/asm/bitops_32.h3
-rw-r--r--arch/tile/include/asm/bitops_64.h105
-rw-r--r--arch/tile/include/asm/cache.h2
-rw-r--r--arch/tile/include/asm/cacheflush.h27
-rw-r--r--arch/tile/include/asm/compat.h17
-rw-r--r--arch/tile/include/asm/dma-mapping.h3
-rw-r--r--arch/tile/include/asm/edac.h29
-rw-r--r--arch/tile/include/asm/fb.h1
-rw-r--r--arch/tile/include/asm/futex.h27
-rw-r--r--arch/tile/include/asm/hardwall.h15
-rw-r--r--arch/tile/include/asm/highmem.h11
-rw-r--r--arch/tile/include/asm/hugetlb.h2
-rw-r--r--arch/tile/include/asm/io.h33
-rw-r--r--arch/tile/include/asm/irq.h2
-rw-r--r--arch/tile/include/asm/irqflags.h118
-rw-r--r--arch/tile/include/asm/kmap_types.h34
-rw-r--r--arch/tile/include/asm/mman.h1
-rw-r--r--arch/tile/include/asm/mmu_context.h4
-rw-r--r--arch/tile/include/asm/mmzone.h11
-rw-r--r--arch/tile/include/asm/opcode-tile_32.h7
-rw-r--r--arch/tile/include/asm/opcode-tile_64.h1500
-rw-r--r--arch/tile/include/asm/opcode_constants_64.h1043
-rw-r--r--arch/tile/include/asm/page.h71
-rw-r--r--arch/tile/include/asm/parport.h1
-rw-r--r--arch/tile/include/asm/pci-bridge.h117
-rw-r--r--arch/tile/include/asm/pci.h110
-rw-r--r--arch/tile/include/asm/pgalloc.h7
-rw-r--r--arch/tile/include/asm/pgtable.h42
-rw-r--r--arch/tile/include/asm/pgtable_32.h8
-rw-r--r--arch/tile/include/asm/pgtable_64.h175
-rw-r--r--arch/tile/include/asm/processor.h31
-rw-r--r--arch/tile/include/asm/ptrace.h7
-rw-r--r--arch/tile/include/asm/serial.h1
-rw-r--r--arch/tile/include/asm/signal.h6
-rw-r--r--arch/tile/include/asm/spinlock_32.h83
-rw-r--r--arch/tile/include/asm/spinlock_64.h161
-rw-r--r--arch/tile/include/asm/stack.h3
-rw-r--r--arch/tile/include/asm/stat.h3
-rw-r--r--arch/tile/include/asm/swab.h6
-rw-r--r--arch/tile/include/asm/syscalls.h73
-rw-r--r--arch/tile/include/asm/system.h31
-rw-r--r--arch/tile/include/asm/thread_info.h8
-rw-r--r--arch/tile/include/asm/timex.h3
-rw-r--r--arch/tile/include/asm/topology.h75
-rw-r--r--arch/tile/include/asm/traps.h8
-rw-r--r--arch/tile/include/asm/unistd.h3
-rw-r--r--arch/tile/include/asm/vga.h39
53 files changed, 2406 insertions, 1965 deletions
diff --git a/arch/tile/include/asm/Kbuild b/arch/tile/include/asm/Kbuild
index 3b8f55b82dee..849ab2fa1f5c 100644
--- a/arch/tile/include/asm/Kbuild
+++ b/arch/tile/include/asm/Kbuild
@@ -1,3 +1,4 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2 2
3header-y += ucontext.h 3header-y += ucontext.h
4header-y += hardwall.h
diff --git a/arch/tile/include/asm/atomic.h b/arch/tile/include/asm/atomic.h
index b8c49f98a44c..739cfe0499d1 100644
--- a/arch/tile/include/asm/atomic.h
+++ b/arch/tile/include/asm/atomic.h
@@ -32,7 +32,7 @@
32 */ 32 */
33static inline int atomic_read(const atomic_t *v) 33static inline int atomic_read(const atomic_t *v)
34{ 34{
35 return v->counter; 35 return ACCESS_ONCE(v->counter);
36} 36}
37 37
38/** 38/**
@@ -130,17 +130,52 @@ static inline int atomic_read(const atomic_t *v)
130 */ 130 */
131#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) 131#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
132 132
133
134/*
135 * We define xchg() and cmpxchg() in the included headers.
136 * Note that we do not define __HAVE_ARCH_CMPXCHG, since that would imply
137 * that cmpxchg() is an efficient operation, which is not particularly true.
138 */
139
140/* Nonexistent functions intended to cause link errors. */ 133/* Nonexistent functions intended to cause link errors. */
141extern unsigned long __xchg_called_with_bad_pointer(void); 134extern unsigned long __xchg_called_with_bad_pointer(void);
142extern unsigned long __cmpxchg_called_with_bad_pointer(void); 135extern unsigned long __cmpxchg_called_with_bad_pointer(void);
143 136
137#define xchg(ptr, x) \
138 ({ \
139 typeof(*(ptr)) __x; \
140 switch (sizeof(*(ptr))) { \
141 case 4: \
142 __x = (typeof(__x))(typeof(__x-__x))atomic_xchg( \
143 (atomic_t *)(ptr), \
144 (u32)(typeof((x)-(x)))(x)); \
145 break; \
146 case 8: \
147 __x = (typeof(__x))(typeof(__x-__x))atomic64_xchg( \
148 (atomic64_t *)(ptr), \
149 (u64)(typeof((x)-(x)))(x)); \
150 break; \
151 default: \
152 __xchg_called_with_bad_pointer(); \
153 } \
154 __x; \
155 })
156
157#define cmpxchg(ptr, o, n) \
158 ({ \
159 typeof(*(ptr)) __x; \
160 switch (sizeof(*(ptr))) { \
161 case 4: \
162 __x = (typeof(__x))(typeof(__x-__x))atomic_cmpxchg( \
163 (atomic_t *)(ptr), \
164 (u32)(typeof((o)-(o)))(o), \
165 (u32)(typeof((n)-(n)))(n)); \
166 break; \
167 case 8: \
168 __x = (typeof(__x))(typeof(__x-__x))atomic64_cmpxchg( \
169 (atomic64_t *)(ptr), \
170 (u64)(typeof((o)-(o)))(o), \
171 (u64)(typeof((n)-(n)))(n)); \
172 break; \
173 default: \
174 __cmpxchg_called_with_bad_pointer(); \
175 } \
176 __x; \
177 })
178
144#define tas(ptr) (xchg((ptr), 1)) 179#define tas(ptr) (xchg((ptr), 1))
145 180
146#endif /* __ASSEMBLY__ */ 181#endif /* __ASSEMBLY__ */
diff --git a/arch/tile/include/asm/atomic_32.h b/arch/tile/include/asm/atomic_32.h
index ed359aee8837..92a8bee32311 100644
--- a/arch/tile/include/asm/atomic_32.h
+++ b/arch/tile/include/asm/atomic_32.h
@@ -110,16 +110,6 @@ static inline void atomic_set(atomic_t *v, int n)
110 _atomic_xchg(v, n); 110 _atomic_xchg(v, n);
111} 111}
112 112
113#define xchg(ptr, x) ((typeof(*(ptr))) \
114 ((sizeof(*(ptr)) == sizeof(atomic_t)) ? \
115 atomic_xchg((atomic_t *)(ptr), (long)(x)) : \
116 __xchg_called_with_bad_pointer()))
117
118#define cmpxchg(ptr, o, n) ((typeof(*(ptr))) \
119 ((sizeof(*(ptr)) == sizeof(atomic_t)) ? \
120 atomic_cmpxchg((atomic_t *)(ptr), (long)(o), (long)(n)) : \
121 __cmpxchg_called_with_bad_pointer()))
122
123/* A 64bit atomic type */ 113/* A 64bit atomic type */
124 114
125typedef struct { 115typedef struct {
diff --git a/arch/tile/include/asm/atomic_64.h b/arch/tile/include/asm/atomic_64.h
new file mode 100644
index 000000000000..1c1e60d8ccb6
--- /dev/null
+++ b/arch/tile/include/asm/atomic_64.h
@@ -0,0 +1,156 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * Do not include directly; use <asm/atomic.h>.
15 */
16
17#ifndef _ASM_TILE_ATOMIC_64_H
18#define _ASM_TILE_ATOMIC_64_H
19
20#ifndef __ASSEMBLY__
21
22#include <arch/spr_def.h>
23
24/* First, the 32-bit atomic ops that are "real" on our 64-bit platform. */
25
26#define atomic_set(v, i) ((v)->counter = (i))
27
28/*
29 * The smp_mb() operations throughout are to support the fact that
30 * Linux requires memory barriers before and after the operation,
31 * on any routine which updates memory and returns a value.
32 */
33
34static inline int atomic_cmpxchg(atomic_t *v, int o, int n)
35{
36 int val;
37 __insn_mtspr(SPR_CMPEXCH_VALUE, o);
38 smp_mb(); /* barrier for proper semantics */
39 val = __insn_cmpexch4((void *)&v->counter, n);
40 smp_mb(); /* barrier for proper semantics */
41 return val;
42}
43
44static inline int atomic_xchg(atomic_t *v, int n)
45{
46 int val;
47 smp_mb(); /* barrier for proper semantics */
48 val = __insn_exch4((void *)&v->counter, n);
49 smp_mb(); /* barrier for proper semantics */
50 return val;
51}
52
53static inline void atomic_add(int i, atomic_t *v)
54{
55 __insn_fetchadd4((void *)&v->counter, i);
56}
57
58static inline int atomic_add_return(int i, atomic_t *v)
59{
60 int val;
61 smp_mb(); /* barrier for proper semantics */
62 val = __insn_fetchadd4((void *)&v->counter, i) + i;
63 barrier(); /* the "+ i" above will wait on memory */
64 return val;
65}
66
67static inline int atomic_add_unless(atomic_t *v, int a, int u)
68{
69 int guess, oldval = v->counter;
70 do {
71 if (oldval == u)
72 break;
73 guess = oldval;
74 oldval = atomic_cmpxchg(v, guess, guess + a);
75 } while (guess != oldval);
76 return oldval != u;
77}
78
79/* Now the true 64-bit operations. */
80
81#define ATOMIC64_INIT(i) { (i) }
82
83#define atomic64_read(v) ((v)->counter)
84#define atomic64_set(v, i) ((v)->counter = (i))
85
86static inline long atomic64_cmpxchg(atomic64_t *v, long o, long n)
87{
88 long val;
89 smp_mb(); /* barrier for proper semantics */
90 __insn_mtspr(SPR_CMPEXCH_VALUE, o);
91 val = __insn_cmpexch((void *)&v->counter, n);
92 smp_mb(); /* barrier for proper semantics */
93 return val;
94}
95
96static inline long atomic64_xchg(atomic64_t *v, long n)
97{
98 long val;
99 smp_mb(); /* barrier for proper semantics */
100 val = __insn_exch((void *)&v->counter, n);
101 smp_mb(); /* barrier for proper semantics */
102 return val;
103}
104
105static inline void atomic64_add(long i, atomic64_t *v)
106{
107 __insn_fetchadd((void *)&v->counter, i);
108}
109
110static inline long atomic64_add_return(long i, atomic64_t *v)
111{
112 int val;
113 smp_mb(); /* barrier for proper semantics */
114 val = __insn_fetchadd((void *)&v->counter, i) + i;
115 barrier(); /* the "+ i" above will wait on memory */
116 return val;
117}
118
119static inline long atomic64_add_unless(atomic64_t *v, long a, long u)
120{
121 long guess, oldval = v->counter;
122 do {
123 if (oldval == u)
124 break;
125 guess = oldval;
126 oldval = atomic64_cmpxchg(v, guess, guess + a);
127 } while (guess != oldval);
128 return oldval != u;
129}
130
131#define atomic64_sub_return(i, v) atomic64_add_return(-(i), (v))
132#define atomic64_sub(i, v) atomic64_add(-(i), (v))
133#define atomic64_inc_return(v) atomic64_add_return(1, (v))
134#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
135#define atomic64_inc(v) atomic64_add(1, (v))
136#define atomic64_dec(v) atomic64_sub(1, (v))
137
138#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
139#define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0)
140#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
141#define atomic64_add_negative(i, v) (atomic64_add_return((i), (v)) < 0)
142
143#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
144
145/* Atomic dec and inc don't implement barrier, so provide them if needed. */
146#define smp_mb__before_atomic_dec() smp_mb()
147#define smp_mb__after_atomic_dec() smp_mb()
148#define smp_mb__before_atomic_inc() smp_mb()
149#define smp_mb__after_atomic_inc() smp_mb()
150
151/* Define this to indicate that cmpxchg is an efficient operation. */
152#define __HAVE_ARCH_CMPXCHG
153
154#endif /* !__ASSEMBLY__ */
155
156#endif /* _ASM_TILE_ATOMIC_64_H */
diff --git a/arch/tile/include/asm/backtrace.h b/arch/tile/include/asm/backtrace.h
index 758ca4619d50..bd5399a69edf 100644
--- a/arch/tile/include/asm/backtrace.h
+++ b/arch/tile/include/asm/backtrace.h
@@ -12,80 +12,41 @@
12 * more details. 12 * more details.
13 */ 13 */
14 14
15#ifndef _TILE_BACKTRACE_H 15#ifndef _ASM_TILE_BACKTRACE_H
16#define _TILE_BACKTRACE_H 16#define _ASM_TILE_BACKTRACE_H
17
18
19 17
20#include <linux/types.h> 18#include <linux/types.h>
21 19
22#include <arch/chip.h> 20/* Reads 'size' bytes from 'address' and writes the data to 'result'.
23
24#if defined(__tile__)
25typedef unsigned long VirtualAddress;
26#elif CHIP_VA_WIDTH() > 32
27typedef unsigned long long VirtualAddress;
28#else
29typedef unsigned int VirtualAddress;
30#endif
31
32
33/** Reads 'size' bytes from 'address' and writes the data to 'result'.
34 * Returns true if successful, else false (e.g. memory not readable). 21 * Returns true if successful, else false (e.g. memory not readable).
35 */ 22 */
36typedef bool (*BacktraceMemoryReader)(void *result, 23typedef bool (*BacktraceMemoryReader)(void *result,
37 VirtualAddress address, 24 unsigned long address,
38 unsigned int size, 25 unsigned int size,
39 void *extra); 26 void *extra);
40 27
41typedef struct { 28typedef struct {
42 /** Current PC. */ 29 /* Current PC. */
43 VirtualAddress pc; 30 unsigned long pc;
44 31
45 /** Current stack pointer value. */ 32 /* Current stack pointer value. */
46 VirtualAddress sp; 33 unsigned long sp;
47 34
48 /** Current frame pointer value (i.e. caller's stack pointer) */ 35 /* Current frame pointer value (i.e. caller's stack pointer) */
49 VirtualAddress fp; 36 unsigned long fp;
50 37
51 /** Internal use only: caller's PC for first frame. */ 38 /* Internal use only: caller's PC for first frame. */
52 VirtualAddress initial_frame_caller_pc; 39 unsigned long initial_frame_caller_pc;
53 40
54 /** Internal use only: callback to read memory. */ 41 /* Internal use only: callback to read memory. */
55 BacktraceMemoryReader read_memory_func; 42 BacktraceMemoryReader read_memory_func;
56 43
57 /** Internal use only: arbitrary argument to read_memory_func. */ 44 /* Internal use only: arbitrary argument to read_memory_func. */
58 void *read_memory_func_extra; 45 void *read_memory_func_extra;
59 46
60} BacktraceIterator; 47} BacktraceIterator;
61 48
62 49
63/** Initializes a backtracer to start from the given location.
64 *
65 * If the frame pointer cannot be determined it is set to -1.
66 *
67 * @param state The state to be filled in.
68 * @param read_memory_func A callback that reads memory. If NULL, a default
69 * value is provided.
70 * @param read_memory_func_extra An arbitrary argument to read_memory_func.
71 * @param pc The current PC.
72 * @param lr The current value of the 'lr' register.
73 * @param sp The current value of the 'sp' register.
74 * @param r52 The current value of the 'r52' register.
75 */
76extern void backtrace_init(BacktraceIterator *state,
77 BacktraceMemoryReader read_memory_func,
78 void *read_memory_func_extra,
79 VirtualAddress pc, VirtualAddress lr,
80 VirtualAddress sp, VirtualAddress r52);
81
82
83/** Advances the backtracing state to the calling frame, returning
84 * true iff successful.
85 */
86extern bool backtrace_next(BacktraceIterator *state);
87
88
89typedef enum { 50typedef enum {
90 51
91 /* We have no idea what the caller's pc is. */ 52 /* We have no idea what the caller's pc is. */
@@ -138,7 +99,7 @@ enum {
138}; 99};
139 100
140 101
141/** Internal constants used to define 'info' operands. */ 102/* Internal constants used to define 'info' operands. */
142enum { 103enum {
143 /* 0 and 1 are reserved, as are all negative numbers. */ 104 /* 0 and 1 are reserved, as are all negative numbers. */
144 105
@@ -146,11 +107,11 @@ enum {
146 107
147 CALLER_SP_IN_R52_BASE = 4, 108 CALLER_SP_IN_R52_BASE = 4,
148 109
149 CALLER_SP_OFFSET_BASE = 8 110 CALLER_SP_OFFSET_BASE = 8,
150}; 111};
151 112
152 113
153/** Current backtracer state describing where it thinks the caller is. */ 114/* Current backtracer state describing where it thinks the caller is. */
154typedef struct { 115typedef struct {
155 /* 116 /*
156 * Public fields 117 * Public fields
@@ -189,7 +150,13 @@ typedef struct {
189 150
190} CallerLocation; 151} CallerLocation;
191 152
153extern void backtrace_init(BacktraceIterator *state,
154 BacktraceMemoryReader read_memory_func,
155 void *read_memory_func_extra,
156 unsigned long pc, unsigned long lr,
157 unsigned long sp, unsigned long r52);
192 158
193 159
160extern bool backtrace_next(BacktraceIterator *state);
194 161
195#endif /* _TILE_BACKTRACE_H */ 162#endif /* _ASM_TILE_BACKTRACE_H */
diff --git a/arch/tile/include/asm/bitops.h b/arch/tile/include/asm/bitops.h
index 6832b4be8990..16f1fa51fea1 100644
--- a/arch/tile/include/asm/bitops.h
+++ b/arch/tile/include/asm/bitops.h
@@ -120,8 +120,9 @@ static inline unsigned long __arch_hweight64(__u64 w)
120 120
121#include <asm-generic/bitops/const_hweight.h> 121#include <asm-generic/bitops/const_hweight.h>
122#include <asm-generic/bitops/lock.h> 122#include <asm-generic/bitops/lock.h>
123#include <asm-generic/bitops/find.h>
123#include <asm-generic/bitops/sched.h> 124#include <asm-generic/bitops/sched.h>
124#include <asm-generic/bitops/ext2-non-atomic.h> 125#include <asm-generic/bitops/non-atomic.h>
125#include <asm-generic/bitops/minix.h> 126#include <asm-generic/bitops/le.h>
126 127
127#endif /* _ASM_TILE_BITOPS_H */ 128#endif /* _ASM_TILE_BITOPS_H */
diff --git a/arch/tile/include/asm/bitops_32.h b/arch/tile/include/asm/bitops_32.h
index 7a93c001ac19..d31ab905cfa7 100644
--- a/arch/tile/include/asm/bitops_32.h
+++ b/arch/tile/include/asm/bitops_32.h
@@ -122,11 +122,10 @@ static inline int test_and_change_bit(unsigned nr,
122 return (_atomic_xor(addr, mask) & mask) != 0; 122 return (_atomic_xor(addr, mask) & mask) != 0;
123} 123}
124 124
125/* See discussion at smp_mb__before_atomic_dec() in <asm/atomic.h>. */ 125/* See discussion at smp_mb__before_atomic_dec() in <asm/atomic_32.h>. */
126#define smp_mb__before_clear_bit() smp_mb() 126#define smp_mb__before_clear_bit() smp_mb()
127#define smp_mb__after_clear_bit() do {} while (0) 127#define smp_mb__after_clear_bit() do {} while (0)
128 128
129#include <asm-generic/bitops/non-atomic.h>
130#include <asm-generic/bitops/ext2-atomic.h> 129#include <asm-generic/bitops/ext2-atomic.h>
131 130
132#endif /* _ASM_TILE_BITOPS_32_H */ 131#endif /* _ASM_TILE_BITOPS_32_H */
diff --git a/arch/tile/include/asm/bitops_64.h b/arch/tile/include/asm/bitops_64.h
new file mode 100644
index 000000000000..99615e8d2d8b
--- /dev/null
+++ b/arch/tile/include/asm/bitops_64.h
@@ -0,0 +1,105 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_BITOPS_64_H
16#define _ASM_TILE_BITOPS_64_H
17
18#include <linux/compiler.h>
19#include <asm/atomic.h>
20#include <asm/system.h>
21
22/* See <asm/bitops.h> for API comments. */
23
24static inline void set_bit(unsigned nr, volatile unsigned long *addr)
25{
26 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
27 __insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask);
28}
29
30static inline void clear_bit(unsigned nr, volatile unsigned long *addr)
31{
32 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
33 __insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask);
34}
35
36#define smp_mb__before_clear_bit() smp_mb()
37#define smp_mb__after_clear_bit() smp_mb()
38
39
40static inline void change_bit(unsigned nr, volatile unsigned long *addr)
41{
42 unsigned long old, mask = (1UL << (nr % BITS_PER_LONG));
43 long guess, oldval;
44 addr += nr / BITS_PER_LONG;
45 old = *addr;
46 do {
47 guess = oldval;
48 oldval = atomic64_cmpxchg((atomic64_t *)addr,
49 guess, guess ^ mask);
50 } while (guess != oldval);
51}
52
53
54/*
55 * The test_and_xxx_bit() routines require a memory fence before we
56 * start the operation, and after the operation completes. We use
57 * smp_mb() before, and rely on the "!= 0" comparison, plus a compiler
58 * barrier(), to block until the atomic op is complete.
59 */
60
61static inline int test_and_set_bit(unsigned nr, volatile unsigned long *addr)
62{
63 int val;
64 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
65 smp_mb(); /* barrier for proper semantics */
66 val = (__insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask)
67 & mask) != 0;
68 barrier();
69 return val;
70}
71
72
73static inline int test_and_clear_bit(unsigned nr, volatile unsigned long *addr)
74{
75 int val;
76 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
77 smp_mb(); /* barrier for proper semantics */
78 val = (__insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask)
79 & mask) != 0;
80 barrier();
81 return val;
82}
83
84
85static inline int test_and_change_bit(unsigned nr,
86 volatile unsigned long *addr)
87{
88 unsigned long mask = (1UL << (nr % BITS_PER_LONG));
89 long guess, oldval = *addr;
90 addr += nr / BITS_PER_LONG;
91 oldval = *addr;
92 do {
93 guess = oldval;
94 oldval = atomic64_cmpxchg((atomic64_t *)addr,
95 guess, guess ^ mask);
96 } while (guess != oldval);
97 return (oldval & mask) != 0;
98}
99
100#define ext2_set_bit_atomic(lock, nr, addr) \
101 test_and_set_bit((nr), (unsigned long *)(addr))
102#define ext2_clear_bit_atomic(lock, nr, addr) \
103 test_and_clear_bit((nr), (unsigned long *)(addr))
104
105#endif /* _ASM_TILE_BITOPS_64_H */
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h
index 08a2815b5e4e..392e5333dd8b 100644
--- a/arch/tile/include/asm/cache.h
+++ b/arch/tile/include/asm/cache.h
@@ -40,7 +40,7 @@
40#define INTERNODE_CACHE_BYTES L2_CACHE_BYTES 40#define INTERNODE_CACHE_BYTES L2_CACHE_BYTES
41 41
42/* Group together read-mostly things to avoid cache false sharing */ 42/* Group together read-mostly things to avoid cache false sharing */
43#define __read_mostly __attribute__((__section__(".data.read_mostly"))) 43#define __read_mostly __attribute__((__section__(".data..read_mostly")))
44 44
45/* 45/*
46 * Attribute for data that is kept read/write coherent until the end of 46 * Attribute for data that is kept read/write coherent until the end of
diff --git a/arch/tile/include/asm/cacheflush.h b/arch/tile/include/asm/cacheflush.h
index c5741da4eeac..e925f4bb498f 100644
--- a/arch/tile/include/asm/cacheflush.h
+++ b/arch/tile/include/asm/cacheflush.h
@@ -116,25 +116,40 @@ static inline void __finv_buffer(void *buffer, size_t size)
116} 116}
117 117
118 118
119/* Invalidate a VA range, then memory fence. */ 119/* Invalidate a VA range and wait for it to be complete. */
120static inline void inv_buffer(void *buffer, size_t size) 120static inline void inv_buffer(void *buffer, size_t size)
121{ 121{
122 __inv_buffer(buffer, size); 122 __inv_buffer(buffer, size);
123 mb_incoherent(); 123 mb();
124} 124}
125 125
126/* Flush a VA range, then memory fence. */ 126/*
127static inline void flush_buffer(void *buffer, size_t size) 127 * Flush a locally-homecached VA range and wait for the evicted
128 * cachelines to hit memory.
129 */
130static inline void flush_buffer_local(void *buffer, size_t size)
128{ 131{
129 __flush_buffer(buffer, size); 132 __flush_buffer(buffer, size);
130 mb_incoherent(); 133 mb_incoherent();
131} 134}
132 135
133/* Flush & invalidate a VA range, then memory fence. */ 136/*
134static inline void finv_buffer(void *buffer, size_t size) 137 * Flush and invalidate a locally-homecached VA range and wait for the
138 * evicted cachelines to hit memory.
139 */
140static inline void finv_buffer_local(void *buffer, size_t size)
135{ 141{
136 __finv_buffer(buffer, size); 142 __finv_buffer(buffer, size);
137 mb_incoherent(); 143 mb_incoherent();
138} 144}
139 145
146/*
147 * Flush and invalidate a VA range that is homed remotely, waiting
148 * until the memory controller holds the flushed values. If "hfh" is
149 * true, we will do a more expensive flush involving additional loads
150 * to make sure we have touched all the possible home cpus of a buffer
151 * that is homed with "hash for home".
152 */
153void finv_buffer_remote(void *buffer, size_t size, int hfh);
154
140#endif /* _ASM_TILE_CACHEFLUSH_H */ 155#endif /* _ASM_TILE_CACHEFLUSH_H */
diff --git a/arch/tile/include/asm/compat.h b/arch/tile/include/asm/compat.h
index 8b60ec8b2d19..bf95f55b82b0 100644
--- a/arch/tile/include/asm/compat.h
+++ b/arch/tile/include/asm/compat.h
@@ -215,16 +215,17 @@ struct compat_sigaction;
215struct compat_siginfo; 215struct compat_siginfo;
216struct compat_sigaltstack; 216struct compat_sigaltstack;
217long compat_sys_execve(const char __user *path, 217long compat_sys_execve(const char __user *path,
218 const compat_uptr_t __user *argv, 218 compat_uptr_t __user *argv,
219 const compat_uptr_t __user *envp); 219 compat_uptr_t __user *envp, struct pt_regs *);
220long compat_sys_rt_sigaction(int sig, struct compat_sigaction __user *act, 220long compat_sys_rt_sigaction(int sig, struct compat_sigaction __user *act,
221 struct compat_sigaction __user *oact, 221 struct compat_sigaction __user *oact,
222 size_t sigsetsize); 222 size_t sigsetsize);
223long compat_sys_rt_sigqueueinfo(int pid, int sig, 223long compat_sys_rt_sigqueueinfo(int pid, int sig,
224 struct compat_siginfo __user *uinfo); 224 struct compat_siginfo __user *uinfo);
225long compat_sys_rt_sigreturn(void); 225long compat_sys_rt_sigreturn(struct pt_regs *);
226long compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr, 226long compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr,
227 struct compat_sigaltstack __user *uoss_ptr); 227 struct compat_sigaltstack __user *uoss_ptr,
228 struct pt_regs *);
228long compat_sys_truncate64(char __user *filename, u32 dummy, u32 low, u32 high); 229long compat_sys_truncate64(char __user *filename, u32 dummy, u32 low, u32 high);
229long compat_sys_ftruncate64(unsigned int fd, u32 dummy, u32 low, u32 high); 230long compat_sys_ftruncate64(unsigned int fd, u32 dummy, u32 low, u32 high);
230long compat_sys_pread64(unsigned int fd, char __user *ubuf, size_t count, 231long compat_sys_pread64(unsigned int fd, char __user *ubuf, size_t count,
@@ -255,4 +256,12 @@ long tile_compat_sys_ptrace(compat_long_t request, compat_long_t pid,
255/* Tilera Linux syscalls that don't have "compat" versions. */ 256/* Tilera Linux syscalls that don't have "compat" versions. */
256#define compat_sys_flush_cache sys_flush_cache 257#define compat_sys_flush_cache sys_flush_cache
257 258
259/* These are the intvec_64.S trampolines. */
260long _compat_sys_execve(const char __user *path,
261 const compat_uptr_t __user *argv,
262 const compat_uptr_t __user *envp);
263long _compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr,
264 struct compat_sigaltstack __user *uoss_ptr);
265long _compat_sys_rt_sigreturn(void);
266
258#endif /* _ASM_TILE_COMPAT_H */ 267#endif /* _ASM_TILE_COMPAT_H */
diff --git a/arch/tile/include/asm/dma-mapping.h b/arch/tile/include/asm/dma-mapping.h
index 15e1dceecc64..eaa06d175b39 100644
--- a/arch/tile/include/asm/dma-mapping.h
+++ b/arch/tile/include/asm/dma-mapping.h
@@ -65,7 +65,8 @@ extern void dma_sync_single_range_for_cpu(struct device *, dma_addr_t,
65extern void dma_sync_single_range_for_device(struct device *, dma_addr_t, 65extern void dma_sync_single_range_for_device(struct device *, dma_addr_t,
66 unsigned long offset, size_t, 66 unsigned long offset, size_t,
67 enum dma_data_direction); 67 enum dma_data_direction);
68extern void dma_cache_sync(void *vaddr, size_t, enum dma_data_direction); 68extern void dma_cache_sync(struct device *dev, void *vaddr, size_t,
69 enum dma_data_direction);
69 70
70static inline int 71static inline int
71dma_mapping_error(struct device *dev, dma_addr_t dma_addr) 72dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
diff --git a/arch/tile/include/asm/edac.h b/arch/tile/include/asm/edac.h
new file mode 100644
index 000000000000..87fc83eeaffd
--- /dev/null
+++ b/arch/tile/include/asm/edac.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_EDAC_H
16#define _ASM_TILE_EDAC_H
17
18/* ECC atomic, DMA, SMP and interrupt safe scrub function */
19
20static inline void atomic_scrub(void *va, u32 size)
21{
22 /*
23 * These is nothing to be done here because CE is
24 * corrected by the mshim.
25 */
26 return;
27}
28
29#endif /* _ASM_TILE_EDAC_H */
diff --git a/arch/tile/include/asm/fb.h b/arch/tile/include/asm/fb.h
new file mode 100644
index 000000000000..3a4988e8df45
--- /dev/null
+++ b/arch/tile/include/asm/fb.h
@@ -0,0 +1 @@
#include <asm-generic/fb.h>
diff --git a/arch/tile/include/asm/futex.h b/arch/tile/include/asm/futex.h
index fe0d10dcae57..d03ec124a598 100644
--- a/arch/tile/include/asm/futex.h
+++ b/arch/tile/include/asm/futex.h
@@ -29,16 +29,16 @@
29#include <linux/uaccess.h> 29#include <linux/uaccess.h>
30#include <linux/errno.h> 30#include <linux/errno.h>
31 31
32extern struct __get_user futex_set(int __user *v, int i); 32extern struct __get_user futex_set(u32 __user *v, int i);
33extern struct __get_user futex_add(int __user *v, int n); 33extern struct __get_user futex_add(u32 __user *v, int n);
34extern struct __get_user futex_or(int __user *v, int n); 34extern struct __get_user futex_or(u32 __user *v, int n);
35extern struct __get_user futex_andn(int __user *v, int n); 35extern struct __get_user futex_andn(u32 __user *v, int n);
36extern struct __get_user futex_cmpxchg(int __user *v, int o, int n); 36extern struct __get_user futex_cmpxchg(u32 __user *v, int o, int n);
37 37
38#ifndef __tilegx__ 38#ifndef __tilegx__
39extern struct __get_user futex_xor(int __user *v, int n); 39extern struct __get_user futex_xor(u32 __user *v, int n);
40#else 40#else
41static inline struct __get_user futex_xor(int __user *uaddr, int n) 41static inline struct __get_user futex_xor(u32 __user *uaddr, int n)
42{ 42{
43 struct __get_user asm_ret = __get_user_4(uaddr); 43 struct __get_user asm_ret = __get_user_4(uaddr);
44 if (!asm_ret.err) { 44 if (!asm_ret.err) {
@@ -53,7 +53,7 @@ static inline struct __get_user futex_xor(int __user *uaddr, int n)
53} 53}
54#endif 54#endif
55 55
56static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr) 56static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
57{ 57{
58 int op = (encoded_op >> 28) & 7; 58 int op = (encoded_op >> 28) & 7;
59 int cmp = (encoded_op >> 24) & 15; 59 int cmp = (encoded_op >> 24) & 15;
@@ -65,7 +65,7 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
65 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) 65 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
66 oparg = 1 << oparg; 66 oparg = 1 << oparg;
67 67
68 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) 68 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
69 return -EFAULT; 69 return -EFAULT;
70 70
71 pagefault_disable(); 71 pagefault_disable();
@@ -119,16 +119,17 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
119 return ret; 119 return ret;
120} 120}
121 121
122static inline int futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, 122static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
123 int newval) 123 u32 oldval, u32 newval)
124{ 124{
125 struct __get_user asm_ret; 125 struct __get_user asm_ret;
126 126
127 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int))) 127 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
128 return -EFAULT; 128 return -EFAULT;
129 129
130 asm_ret = futex_cmpxchg(uaddr, oldval, newval); 130 asm_ret = futex_cmpxchg(uaddr, oldval, newval);
131 return asm_ret.err ? asm_ret.err : asm_ret.val; 131 *uval = asm_ret.val;
132 return asm_ret.err;
132} 133}
133 134
134#ifndef __tilegx__ 135#ifndef __tilegx__
diff --git a/arch/tile/include/asm/hardwall.h b/arch/tile/include/asm/hardwall.h
index 0bed3ec7b42c..2ac422848c7d 100644
--- a/arch/tile/include/asm/hardwall.h
+++ b/arch/tile/include/asm/hardwall.h
@@ -40,6 +40,10 @@
40#define HARDWALL_DEACTIVATE \ 40#define HARDWALL_DEACTIVATE \
41 _IO(HARDWALL_IOCTL_BASE, _HARDWALL_DEACTIVATE) 41 _IO(HARDWALL_IOCTL_BASE, _HARDWALL_DEACTIVATE)
42 42
43#define _HARDWALL_GET_ID 4
44#define HARDWALL_GET_ID \
45 _IO(HARDWALL_IOCTL_BASE, _HARDWALL_GET_ID)
46
43#ifndef __KERNEL__ 47#ifndef __KERNEL__
44 48
45/* This is the canonical name expected by userspace. */ 49/* This is the canonical name expected by userspace. */
@@ -47,9 +51,14 @@
47 51
48#else 52#else
49 53
50/* Hook for /proc/tile/hardwall. */ 54/* /proc hooks for hardwall. */
51struct seq_file; 55struct proc_dir_entry;
52int proc_tile_hardwall_show(struct seq_file *sf, void *v); 56#ifdef CONFIG_HARDWALL
57void proc_tile_hardwall_init(struct proc_dir_entry *root);
58int proc_pid_hardwall(struct task_struct *task, char *buffer);
59#else
60static inline void proc_tile_hardwall_init(struct proc_dir_entry *root) {}
61#endif
53 62
54#endif 63#endif
55 64
diff --git a/arch/tile/include/asm/highmem.h b/arch/tile/include/asm/highmem.h
index d155db6fa9bd..b2a6c5de79ab 100644
--- a/arch/tile/include/asm/highmem.h
+++ b/arch/tile/include/asm/highmem.h
@@ -23,7 +23,6 @@
23 23
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/threads.h> 25#include <linux/threads.h>
26#include <asm/kmap_types.h>
27#include <asm/tlbflush.h> 26#include <asm/tlbflush.h>
28#include <asm/homecache.h> 27#include <asm/homecache.h>
29 28
@@ -60,12 +59,12 @@ void *kmap_fix_kpte(struct page *page, int finished);
60/* This macro is used only in map_new_virtual() to map "page". */ 59/* This macro is used only in map_new_virtual() to map "page". */
61#define kmap_prot page_to_kpgprot(page) 60#define kmap_prot page_to_kpgprot(page)
62 61
63void kunmap_atomic_notypecheck(void *kvaddr, enum km_type type); 62void *__kmap_atomic(struct page *page);
64void *kmap_atomic_pfn(unsigned long pfn, enum km_type type); 63void __kunmap_atomic(void *kvaddr);
65void *kmap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot); 64void *kmap_atomic_pfn(unsigned long pfn);
65void *kmap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot);
66struct page *kmap_atomic_to_page(void *ptr); 66struct page *kmap_atomic_to_page(void *ptr);
67void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot); 67void *kmap_atomic_prot(struct page *page, pgprot_t prot);
68void *kmap_atomic(struct page *page, enum km_type type);
69void kmap_atomic_fix_kpte(struct page *page, int finished); 68void kmap_atomic_fix_kpte(struct page *page, int finished);
70 69
71#define flush_cache_kmaps() do { } while (0) 70#define flush_cache_kmaps() do { } while (0)
diff --git a/arch/tile/include/asm/hugetlb.h b/arch/tile/include/asm/hugetlb.h
index 0521c277bbde..d396d1805163 100644
--- a/arch/tile/include/asm/hugetlb.h
+++ b/arch/tile/include/asm/hugetlb.h
@@ -54,7 +54,7 @@ static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
54static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, 54static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
55 pte_t *ptep, pte_t pte) 55 pte_t *ptep, pte_t pte)
56{ 56{
57 set_pte_order(ptep, pte, HUGETLB_PAGE_ORDER); 57 set_pte(ptep, pte);
58} 58}
59 59
60static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm, 60static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
diff --git a/arch/tile/include/asm/io.h b/arch/tile/include/asm/io.h
index ee43328713ab..c9ea1652af03 100644
--- a/arch/tile/include/asm/io.h
+++ b/arch/tile/include/asm/io.h
@@ -52,12 +52,10 @@ extern void iounmap(volatile void __iomem *addr);
52#endif 52#endif
53 53
54#define ioremap_nocache(physaddr, size) ioremap(physaddr, size) 54#define ioremap_nocache(physaddr, size) ioremap(physaddr, size)
55#define ioremap_wc(physaddr, size) ioremap(physaddr, size)
55#define ioremap_writethrough(physaddr, size) ioremap(physaddr, size) 56#define ioremap_writethrough(physaddr, size) ioremap(physaddr, size)
56#define ioremap_fullcache(physaddr, size) ioremap(physaddr, size) 57#define ioremap_fullcache(physaddr, size) ioremap(physaddr, size)
57 58
58void __iomem *ioport_map(unsigned long port, unsigned int len);
59extern inline void ioport_unmap(void __iomem *addr) {}
60
61#define mmiowb() 59#define mmiowb()
62 60
63/* Conversion between virtual and physical mappings. */ 61/* Conversion between virtual and physical mappings. */
@@ -164,6 +162,15 @@ static inline void _tile_writeq(u64 val, unsigned long addr)
164#define iowrite32 writel 162#define iowrite32 writel
165#define iowrite64 writeq 163#define iowrite64 writeq
166 164
165static inline void memset_io(void *dst, int val, size_t len)
166{
167 int x;
168 BUG_ON((unsigned long)dst & 0x3);
169 val = (val & 0xff) * 0x01010101;
170 for (x = 0; x < len; x += 4)
171 writel(val, dst + x);
172}
173
167static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, 174static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
168 size_t len) 175 size_t len)
169{ 176{
@@ -189,12 +196,22 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
189 * we never run, uses them unconditionally. 196 * we never run, uses them unconditionally.
190 */ 197 */
191 198
192static inline int ioport_panic(void) 199static inline long ioport_panic(void)
193{ 200{
194 panic("inb/outb and friends do not exist on tile"); 201 panic("inb/outb and friends do not exist on tile");
195 return 0; 202 return 0;
196} 203}
197 204
205static inline void __iomem *ioport_map(unsigned long port, unsigned int len)
206{
207 return (void __iomem *) ioport_panic();
208}
209
210static inline void ioport_unmap(void __iomem *addr)
211{
212 ioport_panic();
213}
214
198static inline u8 inb(unsigned long addr) 215static inline u8 inb(unsigned long addr)
199{ 216{
200 return ioport_panic(); 217 return ioport_panic();
@@ -262,6 +279,11 @@ static inline void outsl(unsigned long addr, const void *buffer, int count)
262 ioport_panic(); 279 ioport_panic();
263} 280}
264 281
282#define ioread16be(addr) be16_to_cpu(ioread16(addr))
283#define ioread32be(addr) be32_to_cpu(ioread32(addr))
284#define iowrite16be(v, addr) iowrite16(be16_to_cpu(v), (addr))
285#define iowrite32be(v, addr) iowrite32(be32_to_cpu(v), (addr))
286
265#define ioread8_rep(p, dst, count) \ 287#define ioread8_rep(p, dst, count) \
266 insb((unsigned long) (p), (dst), (count)) 288 insb((unsigned long) (p), (dst), (count))
267#define ioread16_rep(p, dst, count) \ 289#define ioread16_rep(p, dst, count) \
@@ -276,4 +298,7 @@ static inline void outsl(unsigned long addr, const void *buffer, int count)
276#define iowrite32_rep(p, src, count) \ 298#define iowrite32_rep(p, src, count) \
277 outsl((unsigned long) (p), (src), (count)) 299 outsl((unsigned long) (p), (src), (count))
278 300
301#define virt_to_bus virt_to_phys
302#define bus_to_virt phys_to_virt
303
279#endif /* _ASM_TILE_IO_H */ 304#endif /* _ASM_TILE_IO_H */
diff --git a/arch/tile/include/asm/irq.h b/arch/tile/include/asm/irq.h
index 572fd3ef1d73..94e9a511de84 100644
--- a/arch/tile/include/asm/irq.h
+++ b/arch/tile/include/asm/irq.h
@@ -23,6 +23,8 @@
23/* IRQ numbers used for linux IPIs. */ 23/* IRQ numbers used for linux IPIs. */
24#define IRQ_RESCHEDULE 1 24#define IRQ_RESCHEDULE 1
25 25
26#define irq_canonicalize(irq) (irq)
27
26void ack_bad_irq(unsigned int irq); 28void ack_bad_irq(unsigned int irq);
27 29
28/* 30/*
diff --git a/arch/tile/include/asm/irqflags.h b/arch/tile/include/asm/irqflags.h
index 45cf67c2f286..5db0ce54284d 100644
--- a/arch/tile/include/asm/irqflags.h
+++ b/arch/tile/include/asm/irqflags.h
@@ -18,6 +18,8 @@
18#include <arch/interrupts.h> 18#include <arch/interrupts.h>
19#include <arch/chip.h> 19#include <arch/chip.h>
20 20
21#if !defined(__tilegx__) && defined(__ASSEMBLY__)
22
21/* 23/*
22 * The set of interrupts we want to allow when interrupts are nominally 24 * The set of interrupts we want to allow when interrupts are nominally
23 * disabled. The remainder are effectively "NMI" interrupts from 25 * disabled. The remainder are effectively "NMI" interrupts from
@@ -25,6 +27,16 @@
25 * interrupts (aka "non-queued") are not blocked by the mask in any case. 27 * interrupts (aka "non-queued") are not blocked by the mask in any case.
26 */ 28 */
27#if CHIP_HAS_AUX_PERF_COUNTERS() 29#if CHIP_HAS_AUX_PERF_COUNTERS()
30#define LINUX_MASKABLE_INTERRUPTS_HI \
31 (~(INT_MASK_HI(INT_PERF_COUNT) | INT_MASK_HI(INT_AUX_PERF_COUNT)))
32#else
33#define LINUX_MASKABLE_INTERRUPTS_HI \
34 (~(INT_MASK_HI(INT_PERF_COUNT)))
35#endif
36
37#else
38
39#if CHIP_HAS_AUX_PERF_COUNTERS()
28#define LINUX_MASKABLE_INTERRUPTS \ 40#define LINUX_MASKABLE_INTERRUPTS \
29 (~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT))) 41 (~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT)))
30#else 42#else
@@ -32,6 +44,8 @@
32 (~(INT_MASK(INT_PERF_COUNT))) 44 (~(INT_MASK(INT_PERF_COUNT)))
33#endif 45#endif
34 46
47#endif
48
35#ifndef __ASSEMBLY__ 49#ifndef __ASSEMBLY__
36 50
37/* NOTE: we can't include <linux/percpu.h> due to #include dependencies. */ 51/* NOTE: we can't include <linux/percpu.h> due to #include dependencies. */
@@ -47,53 +61,53 @@
47 int __n = (n); \ 61 int __n = (n); \
48 int __mask = 1 << (__n & 0x1f); \ 62 int __mask = 1 << (__n & 0x1f); \
49 if (__n < 32) \ 63 if (__n < 32) \
50 __insn_mtspr(SPR_INTERRUPT_MASK_SET_1_0, __mask); \ 64 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, __mask); \
51 else \ 65 else \
52 __insn_mtspr(SPR_INTERRUPT_MASK_SET_1_1, __mask); \ 66 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, __mask); \
53} while (0) 67} while (0)
54#define interrupt_mask_reset(n) do { \ 68#define interrupt_mask_reset(n) do { \
55 int __n = (n); \ 69 int __n = (n); \
56 int __mask = 1 << (__n & 0x1f); \ 70 int __mask = 1 << (__n & 0x1f); \
57 if (__n < 32) \ 71 if (__n < 32) \
58 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1_0, __mask); \ 72 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, __mask); \
59 else \ 73 else \
60 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1_1, __mask); \ 74 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, __mask); \
61} while (0) 75} while (0)
62#define interrupt_mask_check(n) ({ \ 76#define interrupt_mask_check(n) ({ \
63 int __n = (n); \ 77 int __n = (n); \
64 (((__n < 32) ? \ 78 (((__n < 32) ? \
65 __insn_mfspr(SPR_INTERRUPT_MASK_1_0) : \ 79 __insn_mfspr(SPR_INTERRUPT_MASK_K_0) : \
66 __insn_mfspr(SPR_INTERRUPT_MASK_1_1)) \ 80 __insn_mfspr(SPR_INTERRUPT_MASK_K_1)) \
67 >> (__n & 0x1f)) & 1; \ 81 >> (__n & 0x1f)) & 1; \
68}) 82})
69#define interrupt_mask_set_mask(mask) do { \ 83#define interrupt_mask_set_mask(mask) do { \
70 unsigned long long __m = (mask); \ 84 unsigned long long __m = (mask); \
71 __insn_mtspr(SPR_INTERRUPT_MASK_SET_1_0, (unsigned long)(__m)); \ 85 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, (unsigned long)(__m)); \
72 __insn_mtspr(SPR_INTERRUPT_MASK_SET_1_1, (unsigned long)(__m>>32)); \ 86 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, (unsigned long)(__m>>32)); \
73} while (0) 87} while (0)
74#define interrupt_mask_reset_mask(mask) do { \ 88#define interrupt_mask_reset_mask(mask) do { \
75 unsigned long long __m = (mask); \ 89 unsigned long long __m = (mask); \
76 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1_0, (unsigned long)(__m)); \ 90 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, (unsigned long)(__m)); \
77 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1_1, (unsigned long)(__m>>32)); \ 91 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, (unsigned long)(__m>>32)); \
78} while (0) 92} while (0)
79#else 93#else
80#define interrupt_mask_set(n) \ 94#define interrupt_mask_set(n) \
81 __insn_mtspr(SPR_INTERRUPT_MASK_SET_1, (1UL << (n))) 95 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (1UL << (n)))
82#define interrupt_mask_reset(n) \ 96#define interrupt_mask_reset(n) \
83 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1, (1UL << (n))) 97 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (1UL << (n)))
84#define interrupt_mask_check(n) \ 98#define interrupt_mask_check(n) \
85 ((__insn_mfspr(SPR_INTERRUPT_MASK_1) >> (n)) & 1) 99 ((__insn_mfspr(SPR_INTERRUPT_MASK_K) >> (n)) & 1)
86#define interrupt_mask_set_mask(mask) \ 100#define interrupt_mask_set_mask(mask) \
87 __insn_mtspr(SPR_INTERRUPT_MASK_SET_1, (mask)) 101 __insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (mask))
88#define interrupt_mask_reset_mask(mask) \ 102#define interrupt_mask_reset_mask(mask) \
89 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_1, (mask)) 103 __insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (mask))
90#endif 104#endif
91 105
92/* 106/*
93 * The set of interrupts we want active if irqs are enabled. 107 * The set of interrupts we want active if irqs are enabled.
94 * Note that in particular, the tile timer interrupt comes and goes 108 * Note that in particular, the tile timer interrupt comes and goes
95 * from this set, since we have no other way to turn off the timer. 109 * from this set, since we have no other way to turn off the timer.
96 * Likewise, INTCTRL_1 is removed and re-added during device 110 * Likewise, INTCTRL_K is removed and re-added during device
97 * interrupts, as is the the hardwall UDN_FIREWALL interrupt. 111 * interrupts, as is the the hardwall UDN_FIREWALL interrupt.
98 * We use a low bit (MEM_ERROR) as our sentinel value and make sure it 112 * We use a low bit (MEM_ERROR) as our sentinel value and make sure it
99 * is always claimed as an "active interrupt" so we can query that bit 113 * is always claimed as an "active interrupt" so we can query that bit
@@ -103,55 +117,57 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
103#define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR) 117#define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR)
104 118
105/* Disable interrupts. */ 119/* Disable interrupts. */
106#define raw_local_irq_disable() \ 120#define arch_local_irq_disable() \
107 interrupt_mask_set_mask(LINUX_MASKABLE_INTERRUPTS) 121 interrupt_mask_set_mask(LINUX_MASKABLE_INTERRUPTS)
108 122
109/* Disable all interrupts, including NMIs. */ 123/* Disable all interrupts, including NMIs. */
110#define raw_local_irq_disable_all() \ 124#define arch_local_irq_disable_all() \
111 interrupt_mask_set_mask(-1UL) 125 interrupt_mask_set_mask(-1UL)
112 126
113/* Re-enable all maskable interrupts. */ 127/* Re-enable all maskable interrupts. */
114#define raw_local_irq_enable() \ 128#define arch_local_irq_enable() \
115 interrupt_mask_reset_mask(__get_cpu_var(interrupts_enabled_mask)) 129 interrupt_mask_reset_mask(__get_cpu_var(interrupts_enabled_mask))
116 130
117/* Disable or enable interrupts based on flag argument. */ 131/* Disable or enable interrupts based on flag argument. */
118#define raw_local_irq_restore(disabled) do { \ 132#define arch_local_irq_restore(disabled) do { \
119 if (disabled) \ 133 if (disabled) \
120 raw_local_irq_disable(); \ 134 arch_local_irq_disable(); \
121 else \ 135 else \
122 raw_local_irq_enable(); \ 136 arch_local_irq_enable(); \
123} while (0) 137} while (0)
124 138
125/* Return true if "flags" argument means interrupts are disabled. */ 139/* Return true if "flags" argument means interrupts are disabled. */
126#define raw_irqs_disabled_flags(flags) ((flags) != 0) 140#define arch_irqs_disabled_flags(flags) ((flags) != 0)
127 141
128/* Return true if interrupts are currently disabled. */ 142/* Return true if interrupts are currently disabled. */
129#define raw_irqs_disabled() interrupt_mask_check(INT_MEM_ERROR) 143#define arch_irqs_disabled() interrupt_mask_check(INT_MEM_ERROR)
130 144
131/* Save whether interrupts are currently disabled. */ 145/* Save whether interrupts are currently disabled. */
132#define raw_local_save_flags(flags) ((flags) = raw_irqs_disabled()) 146#define arch_local_save_flags() arch_irqs_disabled()
133 147
134/* Save whether interrupts are currently disabled, then disable them. */ 148/* Save whether interrupts are currently disabled, then disable them. */
135#define raw_local_irq_save(flags) \ 149#define arch_local_irq_save() ({ \
136 do { raw_local_save_flags(flags); raw_local_irq_disable(); } while (0) 150 unsigned long __flags = arch_local_save_flags(); \
151 arch_local_irq_disable(); \
152 __flags; })
137 153
138/* Prevent the given interrupt from being enabled next time we enable irqs. */ 154/* Prevent the given interrupt from being enabled next time we enable irqs. */
139#define raw_local_irq_mask(interrupt) \ 155#define arch_local_irq_mask(interrupt) \
140 (__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt)) 156 (__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt))
141 157
142/* Prevent the given interrupt from being enabled immediately. */ 158/* Prevent the given interrupt from being enabled immediately. */
143#define raw_local_irq_mask_now(interrupt) do { \ 159#define arch_local_irq_mask_now(interrupt) do { \
144 raw_local_irq_mask(interrupt); \ 160 arch_local_irq_mask(interrupt); \
145 interrupt_mask_set(interrupt); \ 161 interrupt_mask_set(interrupt); \
146} while (0) 162} while (0)
147 163
148/* Allow the given interrupt to be enabled next time we enable irqs. */ 164/* Allow the given interrupt to be enabled next time we enable irqs. */
149#define raw_local_irq_unmask(interrupt) \ 165#define arch_local_irq_unmask(interrupt) \
150 (__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt)) 166 (__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt))
151 167
152/* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */ 168/* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
153#define raw_local_irq_unmask_now(interrupt) do { \ 169#define arch_local_irq_unmask_now(interrupt) do { \
154 raw_local_irq_unmask(interrupt); \ 170 arch_local_irq_unmask(interrupt); \
155 if (!irqs_disabled()) \ 171 if (!irqs_disabled()) \
156 interrupt_mask_reset(interrupt); \ 172 interrupt_mask_reset(interrupt); \
157} while (0) 173} while (0)
@@ -168,14 +184,14 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
168 184
169/* Return 0 or 1 to indicate whether interrupts are currently disabled. */ 185/* Return 0 or 1 to indicate whether interrupts are currently disabled. */
170#define IRQS_DISABLED(tmp) \ 186#define IRQS_DISABLED(tmp) \
171 mfspr tmp, INTERRUPT_MASK_1; \ 187 mfspr tmp, SPR_INTERRUPT_MASK_K; \
172 andi tmp, tmp, 1 188 andi tmp, tmp, 1
173 189
174/* Load up a pointer to &interrupts_enabled_mask. */ 190/* Load up a pointer to &interrupts_enabled_mask. */
175#define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \ 191#define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \
176 moveli reg, hw2_last(interrupts_enabled_mask); \ 192 moveli reg, hw2_last(interrupts_enabled_mask); \
177 shl16insli reg, reg, hw1(interrupts_enabled_mask); \ 193 shl16insli reg, reg, hw1(interrupts_enabled_mask); \
178 shl16insli reg, reg, hw0(interrupts_enabled_mask); \ 194 shl16insli reg, reg, hw0(interrupts_enabled_mask); \
179 add reg, reg, tp 195 add reg, reg, tp
180 196
181/* Disable interrupts. */ 197/* Disable interrupts. */
@@ -183,18 +199,18 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
183 moveli tmp0, hw2_last(LINUX_MASKABLE_INTERRUPTS); \ 199 moveli tmp0, hw2_last(LINUX_MASKABLE_INTERRUPTS); \
184 shl16insli tmp0, tmp0, hw1(LINUX_MASKABLE_INTERRUPTS); \ 200 shl16insli tmp0, tmp0, hw1(LINUX_MASKABLE_INTERRUPTS); \
185 shl16insli tmp0, tmp0, hw0(LINUX_MASKABLE_INTERRUPTS); \ 201 shl16insli tmp0, tmp0, hw0(LINUX_MASKABLE_INTERRUPTS); \
186 mtspr INTERRUPT_MASK_SET_1, tmp0 202 mtspr SPR_INTERRUPT_MASK_SET_K, tmp0
187 203
188/* Disable ALL synchronous interrupts (used by NMI entry). */ 204/* Disable ALL synchronous interrupts (used by NMI entry). */
189#define IRQ_DISABLE_ALL(tmp) \ 205#define IRQ_DISABLE_ALL(tmp) \
190 movei tmp, -1; \ 206 movei tmp, -1; \
191 mtspr INTERRUPT_MASK_SET_1, tmp 207 mtspr SPR_INTERRUPT_MASK_SET_K, tmp
192 208
193/* Enable interrupts. */ 209/* Enable interrupts. */
194#define IRQ_ENABLE(tmp0, tmp1) \ 210#define IRQ_ENABLE(tmp0, tmp1) \
195 GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0); \ 211 GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0); \
196 ld tmp0, tmp0; \ 212 ld tmp0, tmp0; \
197 mtspr INTERRUPT_MASK_RESET_1, tmp0 213 mtspr SPR_INTERRUPT_MASK_RESET_K, tmp0
198 214
199#else /* !__tilegx__ */ 215#else /* !__tilegx__ */
200 216
@@ -208,33 +224,33 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
208 * (making the original code's write of the "high" mask word idempotent). 224 * (making the original code's write of the "high" mask word idempotent).
209 */ 225 */
210#define IRQS_DISABLED(tmp) \ 226#define IRQS_DISABLED(tmp) \
211 mfspr tmp, INTERRUPT_MASK_1_0; \ 227 mfspr tmp, SPR_INTERRUPT_MASK_K_0; \
212 shri tmp, tmp, INT_MEM_ERROR; \ 228 shri tmp, tmp, INT_MEM_ERROR; \
213 andi tmp, tmp, 1 229 andi tmp, tmp, 1
214 230
215/* Load up a pointer to &interrupts_enabled_mask. */ 231/* Load up a pointer to &interrupts_enabled_mask. */
216#define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \ 232#define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \
217 moveli reg, lo16(interrupts_enabled_mask); \ 233 moveli reg, lo16(interrupts_enabled_mask); \
218 auli reg, reg, ha16(interrupts_enabled_mask);\ 234 auli reg, reg, ha16(interrupts_enabled_mask); \
219 add reg, reg, tp 235 add reg, reg, tp
220 236
221/* Disable interrupts. */ 237/* Disable interrupts. */
222#define IRQ_DISABLE(tmp0, tmp1) \ 238#define IRQ_DISABLE(tmp0, tmp1) \
223 { \ 239 { \
224 movei tmp0, -1; \ 240 movei tmp0, -1; \
225 moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS) \ 241 moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS_HI) \
226 }; \ 242 }; \
227 { \ 243 { \
228 mtspr INTERRUPT_MASK_SET_1_0, tmp0; \ 244 mtspr SPR_INTERRUPT_MASK_SET_K_0, tmp0; \
229 auli tmp1, tmp1, ha16(LINUX_MASKABLE_INTERRUPTS) \ 245 auli tmp1, tmp1, ha16(LINUX_MASKABLE_INTERRUPTS_HI) \
230 }; \ 246 }; \
231 mtspr INTERRUPT_MASK_SET_1_1, tmp1 247 mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp1
232 248
233/* Disable ALL synchronous interrupts (used by NMI entry). */ 249/* Disable ALL synchronous interrupts (used by NMI entry). */
234#define IRQ_DISABLE_ALL(tmp) \ 250#define IRQ_DISABLE_ALL(tmp) \
235 movei tmp, -1; \ 251 movei tmp, -1; \
236 mtspr INTERRUPT_MASK_SET_1_0, tmp; \ 252 mtspr SPR_INTERRUPT_MASK_SET_K_0, tmp; \
237 mtspr INTERRUPT_MASK_SET_1_1, tmp 253 mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp
238 254
239/* Enable interrupts. */ 255/* Enable interrupts. */
240#define IRQ_ENABLE(tmp0, tmp1) \ 256#define IRQ_ENABLE(tmp0, tmp1) \
@@ -244,8 +260,8 @@ DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
244 addi tmp1, tmp0, 4 \ 260 addi tmp1, tmp0, 4 \
245 }; \ 261 }; \
246 lw tmp1, tmp1; \ 262 lw tmp1, tmp1; \
247 mtspr INTERRUPT_MASK_RESET_1_0, tmp0; \ 263 mtspr SPR_INTERRUPT_MASK_RESET_K_0, tmp0; \
248 mtspr INTERRUPT_MASK_RESET_1_1, tmp1 264 mtspr SPR_INTERRUPT_MASK_RESET_K_1, tmp1
249#endif 265#endif
250 266
251/* 267/*
diff --git a/arch/tile/include/asm/kmap_types.h b/arch/tile/include/asm/kmap_types.h
index 1480106d1c05..3d0f20246260 100644
--- a/arch/tile/include/asm/kmap_types.h
+++ b/arch/tile/include/asm/kmap_types.h
@@ -16,28 +16,42 @@
16#define _ASM_TILE_KMAP_TYPES_H 16#define _ASM_TILE_KMAP_TYPES_H
17 17
18/* 18/*
19 * In TILE Linux each set of four of these uses another 16MB chunk of 19 * In 32-bit TILE Linux we have to balance the desire to have a lot of
20 * address space, given 64 tiles and 64KB pages, so we only enable 20 * nested atomic mappings with the fact that large page sizes and many
21 * ones that are required by the kernel configuration. 21 * processors chew up address space quickly. In a typical
22 * 64-processor, 64KB-page layout build, making KM_TYPE_NR one larger
23 * adds 4MB of required address-space. For now we leave KM_TYPE_NR
24 * set to depth 8.
22 */ 25 */
23enum km_type { 26enum km_type {
27 KM_TYPE_NR = 8
28};
29
30/*
31 * We provide dummy definitions of all the stray values that used to be
32 * required for kmap_atomic() and no longer are.
33 */
34enum {
24 KM_BOUNCE_READ, 35 KM_BOUNCE_READ,
25 KM_SKB_SUNRPC_DATA, 36 KM_SKB_SUNRPC_DATA,
26 KM_SKB_DATA_SOFTIRQ, 37 KM_SKB_DATA_SOFTIRQ,
27 KM_USER0, 38 KM_USER0,
28 KM_USER1, 39 KM_USER1,
29 KM_BIO_SRC_IRQ, 40 KM_BIO_SRC_IRQ,
41 KM_BIO_DST_IRQ,
42 KM_PTE0,
43 KM_PTE1,
30 KM_IRQ0, 44 KM_IRQ0,
31 KM_IRQ1, 45 KM_IRQ1,
32 KM_SOFTIRQ0, 46 KM_SOFTIRQ0,
33 KM_SOFTIRQ1, 47 KM_SOFTIRQ1,
34 KM_MEMCPY0, 48 KM_SYNC_ICACHE,
35 KM_MEMCPY1, 49 KM_SYNC_DCACHE,
36#if defined(CONFIG_HIGHPTE) 50 KM_UML_USERCOPY,
37 KM_PTE0, 51 KM_IRQ_PTE,
38 KM_PTE1, 52 KM_NMI,
39#endif 53 KM_NMI_PTE,
40 KM_TYPE_NR 54 KM_KDB
41}; 55};
42 56
43#endif /* _ASM_TILE_KMAP_TYPES_H */ 57#endif /* _ASM_TILE_KMAP_TYPES_H */
diff --git a/arch/tile/include/asm/mman.h b/arch/tile/include/asm/mman.h
index 4c6811e3e8dc..81b8fc348d63 100644
--- a/arch/tile/include/asm/mman.h
+++ b/arch/tile/include/asm/mman.h
@@ -23,6 +23,7 @@
23#define MAP_POPULATE 0x0040 /* populate (prefault) pagetables */ 23#define MAP_POPULATE 0x0040 /* populate (prefault) pagetables */
24#define MAP_NONBLOCK 0x0080 /* do not block on IO */ 24#define MAP_NONBLOCK 0x0080 /* do not block on IO */
25#define MAP_GROWSDOWN 0x0100 /* stack-like segment */ 25#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
26#define MAP_STACK MAP_GROWSDOWN /* provide convenience alias */
26#define MAP_LOCKED 0x0200 /* pages are locked */ 27#define MAP_LOCKED 0x0200 /* pages are locked */
27#define MAP_NORESERVE 0x0400 /* don't check for reservations */ 28#define MAP_NORESERVE 0x0400 /* don't check for reservations */
28#define MAP_DENYWRITE 0x0800 /* ETXTBSY */ 29#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
diff --git a/arch/tile/include/asm/mmu_context.h b/arch/tile/include/asm/mmu_context.h
index 9bc0d0725c28..15fb24641120 100644
--- a/arch/tile/include/asm/mmu_context.h
+++ b/arch/tile/include/asm/mmu_context.h
@@ -100,8 +100,8 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
100 __get_cpu_var(current_asid) = asid; 100 __get_cpu_var(current_asid) = asid;
101 101
102 /* Clear cpu from the old mm, and set it in the new one. */ 102 /* Clear cpu from the old mm, and set it in the new one. */
103 cpumask_clear_cpu(cpu, &prev->cpu_vm_mask); 103 cpumask_clear_cpu(cpu, mm_cpumask(prev));
104 cpumask_set_cpu(cpu, &next->cpu_vm_mask); 104 cpumask_set_cpu(cpu, mm_cpumask(next));
105 105
106 /* Re-load page tables */ 106 /* Re-load page tables */
107 install_page_table(next->pgd, asid); 107 install_page_table(next->pgd, asid);
diff --git a/arch/tile/include/asm/mmzone.h b/arch/tile/include/asm/mmzone.h
index c6344c4f32ac..9d3dbce8f953 100644
--- a/arch/tile/include/asm/mmzone.h
+++ b/arch/tile/include/asm/mmzone.h
@@ -40,17 +40,6 @@ static inline int pfn_to_nid(unsigned long pfn)
40 return highbits_to_node[__pfn_to_highbits(pfn)]; 40 return highbits_to_node[__pfn_to_highbits(pfn)];
41} 41}
42 42
43/*
44 * Following are macros that each numa implmentation must define.
45 */
46
47#define node_start_pfn(nid) (NODE_DATA(nid)->node_start_pfn)
48#define node_end_pfn(nid) \
49({ \
50 pg_data_t *__pgdat = NODE_DATA(nid); \
51 __pgdat->node_start_pfn + __pgdat->node_spanned_pages; \
52})
53
54#define kern_addr_valid(kaddr) virt_addr_valid((void *)kaddr) 43#define kern_addr_valid(kaddr) virt_addr_valid((void *)kaddr)
55 44
56static inline int pfn_valid(int pfn) 45static inline int pfn_valid(int pfn)
diff --git a/arch/tile/include/asm/opcode-tile_32.h b/arch/tile/include/asm/opcode-tile_32.h
index eda60ecbae3d..03df7b1e77bf 100644
--- a/arch/tile/include/asm/opcode-tile_32.h
+++ b/arch/tile/include/asm/opcode-tile_32.h
@@ -1502,5 +1502,12 @@ extern int parse_insn_tile(tile_bundle_bits bits,
1502 decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]); 1502 decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]);
1503 1503
1504 1504
1505/* Given a set of bundle bits and a specific pipe, returns which
1506 * instruction the bundle contains in that pipe.
1507 */
1508extern const struct tile_opcode *
1509find_opcode(tile_bundle_bits bits, tile_pipeline pipe);
1510
1511
1505 1512
1506#endif /* opcode_tile_h */ 1513#endif /* opcode_tile_h */
diff --git a/arch/tile/include/asm/opcode-tile_64.h b/arch/tile/include/asm/opcode-tile_64.h
index eda60ecbae3d..c0633466cd5c 100644
--- a/arch/tile/include/asm/opcode-tile_64.h
+++ b/arch/tile/include/asm/opcode-tile_64.h
@@ -5,863 +5,711 @@
5#ifndef opcode_tile_h 5#ifndef opcode_tile_h
6#define opcode_tile_h 6#define opcode_tile_h
7 7
8typedef unsigned long long tile_bundle_bits; 8typedef unsigned long long tilegx_bundle_bits;
9 9
10 10
11enum 11enum
12{ 12{
13 TILE_MAX_OPERANDS = 5 /* mm */ 13 TILEGX_MAX_OPERANDS = 4 /* bfexts */
14}; 14};
15 15
16typedef enum 16typedef enum
17{ 17{
18 TILE_OPC_BPT, 18 TILEGX_OPC_BPT,
19 TILE_OPC_INFO, 19 TILEGX_OPC_INFO,
20 TILE_OPC_INFOL, 20 TILEGX_OPC_INFOL,
21 TILE_OPC_J, 21 TILEGX_OPC_MOVE,
22 TILE_OPC_JAL, 22 TILEGX_OPC_MOVEI,
23 TILE_OPC_MOVE, 23 TILEGX_OPC_MOVELI,
24 TILE_OPC_MOVE_SN, 24 TILEGX_OPC_PREFETCH,
25 TILE_OPC_MOVEI, 25 TILEGX_OPC_PREFETCH_ADD_L1,
26 TILE_OPC_MOVEI_SN, 26 TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
27 TILE_OPC_MOVELI, 27 TILEGX_OPC_PREFETCH_ADD_L2,
28 TILE_OPC_MOVELI_SN, 28 TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
29 TILE_OPC_MOVELIS, 29 TILEGX_OPC_PREFETCH_ADD_L3,
30 TILE_OPC_PREFETCH, 30 TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
31 TILE_OPC_RAISE, 31 TILEGX_OPC_PREFETCH_L1,
32 TILE_OPC_ADD, 32 TILEGX_OPC_PREFETCH_L1_FAULT,
33 TILE_OPC_ADD_SN, 33 TILEGX_OPC_PREFETCH_L2,
34 TILE_OPC_ADDB, 34 TILEGX_OPC_PREFETCH_L2_FAULT,
35 TILE_OPC_ADDB_SN, 35 TILEGX_OPC_PREFETCH_L3,
36 TILE_OPC_ADDBS_U, 36 TILEGX_OPC_PREFETCH_L3_FAULT,
37 TILE_OPC_ADDBS_U_SN, 37 TILEGX_OPC_RAISE,
38 TILE_OPC_ADDH, 38 TILEGX_OPC_ADD,
39 TILE_OPC_ADDH_SN, 39 TILEGX_OPC_ADDI,
40 TILE_OPC_ADDHS, 40 TILEGX_OPC_ADDLI,
41 TILE_OPC_ADDHS_SN, 41 TILEGX_OPC_ADDX,
42 TILE_OPC_ADDI, 42 TILEGX_OPC_ADDXI,
43 TILE_OPC_ADDI_SN, 43 TILEGX_OPC_ADDXLI,
44 TILE_OPC_ADDIB, 44 TILEGX_OPC_ADDXSC,
45 TILE_OPC_ADDIB_SN, 45 TILEGX_OPC_AND,
46 TILE_OPC_ADDIH, 46 TILEGX_OPC_ANDI,
47 TILE_OPC_ADDIH_SN, 47 TILEGX_OPC_BEQZ,
48 TILE_OPC_ADDLI, 48 TILEGX_OPC_BEQZT,
49 TILE_OPC_ADDLI_SN, 49 TILEGX_OPC_BFEXTS,
50 TILE_OPC_ADDLIS, 50 TILEGX_OPC_BFEXTU,
51 TILE_OPC_ADDS, 51 TILEGX_OPC_BFINS,
52 TILE_OPC_ADDS_SN, 52 TILEGX_OPC_BGEZ,
53 TILE_OPC_ADIFFB_U, 53 TILEGX_OPC_BGEZT,
54 TILE_OPC_ADIFFB_U_SN, 54 TILEGX_OPC_BGTZ,
55 TILE_OPC_ADIFFH, 55 TILEGX_OPC_BGTZT,
56 TILE_OPC_ADIFFH_SN, 56 TILEGX_OPC_BLBC,
57 TILE_OPC_AND, 57 TILEGX_OPC_BLBCT,
58 TILE_OPC_AND_SN, 58 TILEGX_OPC_BLBS,
59 TILE_OPC_ANDI, 59 TILEGX_OPC_BLBST,
60 TILE_OPC_ANDI_SN, 60 TILEGX_OPC_BLEZ,
61 TILE_OPC_AULI, 61 TILEGX_OPC_BLEZT,
62 TILE_OPC_AVGB_U, 62 TILEGX_OPC_BLTZ,
63 TILE_OPC_AVGB_U_SN, 63 TILEGX_OPC_BLTZT,
64 TILE_OPC_AVGH, 64 TILEGX_OPC_BNEZ,
65 TILE_OPC_AVGH_SN, 65 TILEGX_OPC_BNEZT,
66 TILE_OPC_BBNS, 66 TILEGX_OPC_CLZ,
67 TILE_OPC_BBNS_SN, 67 TILEGX_OPC_CMOVEQZ,
68 TILE_OPC_BBNST, 68 TILEGX_OPC_CMOVNEZ,
69 TILE_OPC_BBNST_SN, 69 TILEGX_OPC_CMPEQ,
70 TILE_OPC_BBS, 70 TILEGX_OPC_CMPEQI,
71 TILE_OPC_BBS_SN, 71 TILEGX_OPC_CMPEXCH,
72 TILE_OPC_BBST, 72 TILEGX_OPC_CMPEXCH4,
73 TILE_OPC_BBST_SN, 73 TILEGX_OPC_CMPLES,
74 TILE_OPC_BGEZ, 74 TILEGX_OPC_CMPLEU,
75 TILE_OPC_BGEZ_SN, 75 TILEGX_OPC_CMPLTS,
76 TILE_OPC_BGEZT, 76 TILEGX_OPC_CMPLTSI,
77 TILE_OPC_BGEZT_SN, 77 TILEGX_OPC_CMPLTU,
78 TILE_OPC_BGZ, 78 TILEGX_OPC_CMPLTUI,
79 TILE_OPC_BGZ_SN, 79 TILEGX_OPC_CMPNE,
80 TILE_OPC_BGZT, 80 TILEGX_OPC_CMUL,
81 TILE_OPC_BGZT_SN, 81 TILEGX_OPC_CMULA,
82 TILE_OPC_BITX, 82 TILEGX_OPC_CMULAF,
83 TILE_OPC_BITX_SN, 83 TILEGX_OPC_CMULF,
84 TILE_OPC_BLEZ, 84 TILEGX_OPC_CMULFR,
85 TILE_OPC_BLEZ_SN, 85 TILEGX_OPC_CMULH,
86 TILE_OPC_BLEZT, 86 TILEGX_OPC_CMULHR,
87 TILE_OPC_BLEZT_SN, 87 TILEGX_OPC_CRC32_32,
88 TILE_OPC_BLZ, 88 TILEGX_OPC_CRC32_8,
89 TILE_OPC_BLZ_SN, 89 TILEGX_OPC_CTZ,
90 TILE_OPC_BLZT, 90 TILEGX_OPC_DBLALIGN,
91 TILE_OPC_BLZT_SN, 91 TILEGX_OPC_DBLALIGN2,
92 TILE_OPC_BNZ, 92 TILEGX_OPC_DBLALIGN4,
93 TILE_OPC_BNZ_SN, 93 TILEGX_OPC_DBLALIGN6,
94 TILE_OPC_BNZT, 94 TILEGX_OPC_DRAIN,
95 TILE_OPC_BNZT_SN, 95 TILEGX_OPC_DTLBPR,
96 TILE_OPC_BYTEX, 96 TILEGX_OPC_EXCH,
97 TILE_OPC_BYTEX_SN, 97 TILEGX_OPC_EXCH4,
98 TILE_OPC_BZ, 98 TILEGX_OPC_FDOUBLE_ADD_FLAGS,
99 TILE_OPC_BZ_SN, 99 TILEGX_OPC_FDOUBLE_ADDSUB,
100 TILE_OPC_BZT, 100 TILEGX_OPC_FDOUBLE_MUL_FLAGS,
101 TILE_OPC_BZT_SN, 101 TILEGX_OPC_FDOUBLE_PACK1,
102 TILE_OPC_CLZ, 102 TILEGX_OPC_FDOUBLE_PACK2,
103 TILE_OPC_CLZ_SN, 103 TILEGX_OPC_FDOUBLE_SUB_FLAGS,
104 TILE_OPC_CRC32_32, 104 TILEGX_OPC_FDOUBLE_UNPACK_MAX,
105 TILE_OPC_CRC32_32_SN, 105 TILEGX_OPC_FDOUBLE_UNPACK_MIN,
106 TILE_OPC_CRC32_8, 106 TILEGX_OPC_FETCHADD,
107 TILE_OPC_CRC32_8_SN, 107 TILEGX_OPC_FETCHADD4,
108 TILE_OPC_CTZ, 108 TILEGX_OPC_FETCHADDGEZ,
109 TILE_OPC_CTZ_SN, 109 TILEGX_OPC_FETCHADDGEZ4,
110 TILE_OPC_DRAIN, 110 TILEGX_OPC_FETCHAND,
111 TILE_OPC_DTLBPR, 111 TILEGX_OPC_FETCHAND4,
112 TILE_OPC_DWORD_ALIGN, 112 TILEGX_OPC_FETCHOR,
113 TILE_OPC_DWORD_ALIGN_SN, 113 TILEGX_OPC_FETCHOR4,
114 TILE_OPC_FINV, 114 TILEGX_OPC_FINV,
115 TILE_OPC_FLUSH, 115 TILEGX_OPC_FLUSH,
116 TILE_OPC_FNOP, 116 TILEGX_OPC_FLUSHWB,
117 TILE_OPC_ICOH, 117 TILEGX_OPC_FNOP,
118 TILE_OPC_ILL, 118 TILEGX_OPC_FSINGLE_ADD1,
119 TILE_OPC_INTHB, 119 TILEGX_OPC_FSINGLE_ADDSUB2,
120 TILE_OPC_INTHB_SN, 120 TILEGX_OPC_FSINGLE_MUL1,
121 TILE_OPC_INTHH, 121 TILEGX_OPC_FSINGLE_MUL2,
122 TILE_OPC_INTHH_SN, 122 TILEGX_OPC_FSINGLE_PACK1,
123 TILE_OPC_INTLB, 123 TILEGX_OPC_FSINGLE_PACK2,
124 TILE_OPC_INTLB_SN, 124 TILEGX_OPC_FSINGLE_SUB1,
125 TILE_OPC_INTLH, 125 TILEGX_OPC_ICOH,
126 TILE_OPC_INTLH_SN, 126 TILEGX_OPC_ILL,
127 TILE_OPC_INV, 127 TILEGX_OPC_INV,
128 TILE_OPC_IRET, 128 TILEGX_OPC_IRET,
129 TILE_OPC_JALB, 129 TILEGX_OPC_J,
130 TILE_OPC_JALF, 130 TILEGX_OPC_JAL,
131 TILE_OPC_JALR, 131 TILEGX_OPC_JALR,
132 TILE_OPC_JALRP, 132 TILEGX_OPC_JALRP,
133 TILE_OPC_JB, 133 TILEGX_OPC_JR,
134 TILE_OPC_JF, 134 TILEGX_OPC_JRP,
135 TILE_OPC_JR, 135 TILEGX_OPC_LD,
136 TILE_OPC_JRP, 136 TILEGX_OPC_LD1S,
137 TILE_OPC_LB, 137 TILEGX_OPC_LD1S_ADD,
138 TILE_OPC_LB_SN, 138 TILEGX_OPC_LD1U,
139 TILE_OPC_LB_U, 139 TILEGX_OPC_LD1U_ADD,
140 TILE_OPC_LB_U_SN, 140 TILEGX_OPC_LD2S,
141 TILE_OPC_LBADD, 141 TILEGX_OPC_LD2S_ADD,
142 TILE_OPC_LBADD_SN, 142 TILEGX_OPC_LD2U,
143 TILE_OPC_LBADD_U, 143 TILEGX_OPC_LD2U_ADD,
144 TILE_OPC_LBADD_U_SN, 144 TILEGX_OPC_LD4S,
145 TILE_OPC_LH, 145 TILEGX_OPC_LD4S_ADD,
146 TILE_OPC_LH_SN, 146 TILEGX_OPC_LD4U,
147 TILE_OPC_LH_U, 147 TILEGX_OPC_LD4U_ADD,
148 TILE_OPC_LH_U_SN, 148 TILEGX_OPC_LD_ADD,
149 TILE_OPC_LHADD, 149 TILEGX_OPC_LDNA,
150 TILE_OPC_LHADD_SN, 150 TILEGX_OPC_LDNA_ADD,
151 TILE_OPC_LHADD_U, 151 TILEGX_OPC_LDNT,
152 TILE_OPC_LHADD_U_SN, 152 TILEGX_OPC_LDNT1S,
153 TILE_OPC_LNK, 153 TILEGX_OPC_LDNT1S_ADD,
154 TILE_OPC_LNK_SN, 154 TILEGX_OPC_LDNT1U,
155 TILE_OPC_LW, 155 TILEGX_OPC_LDNT1U_ADD,
156 TILE_OPC_LW_SN, 156 TILEGX_OPC_LDNT2S,
157 TILE_OPC_LW_NA, 157 TILEGX_OPC_LDNT2S_ADD,
158 TILE_OPC_LW_NA_SN, 158 TILEGX_OPC_LDNT2U,
159 TILE_OPC_LWADD, 159 TILEGX_OPC_LDNT2U_ADD,
160 TILE_OPC_LWADD_SN, 160 TILEGX_OPC_LDNT4S,
161 TILE_OPC_LWADD_NA, 161 TILEGX_OPC_LDNT4S_ADD,
162 TILE_OPC_LWADD_NA_SN, 162 TILEGX_OPC_LDNT4U,
163 TILE_OPC_MAXB_U, 163 TILEGX_OPC_LDNT4U_ADD,
164 TILE_OPC_MAXB_U_SN, 164 TILEGX_OPC_LDNT_ADD,
165 TILE_OPC_MAXH, 165 TILEGX_OPC_LNK,
166 TILE_OPC_MAXH_SN, 166 TILEGX_OPC_MF,
167 TILE_OPC_MAXIB_U, 167 TILEGX_OPC_MFSPR,
168 TILE_OPC_MAXIB_U_SN, 168 TILEGX_OPC_MM,
169 TILE_OPC_MAXIH, 169 TILEGX_OPC_MNZ,
170 TILE_OPC_MAXIH_SN, 170 TILEGX_OPC_MTSPR,
171 TILE_OPC_MF, 171 TILEGX_OPC_MUL_HS_HS,
172 TILE_OPC_MFSPR, 172 TILEGX_OPC_MUL_HS_HU,
173 TILE_OPC_MINB_U, 173 TILEGX_OPC_MUL_HS_LS,
174 TILE_OPC_MINB_U_SN, 174 TILEGX_OPC_MUL_HS_LU,
175 TILE_OPC_MINH, 175 TILEGX_OPC_MUL_HU_HU,
176 TILE_OPC_MINH_SN, 176 TILEGX_OPC_MUL_HU_LS,
177 TILE_OPC_MINIB_U, 177 TILEGX_OPC_MUL_HU_LU,
178 TILE_OPC_MINIB_U_SN, 178 TILEGX_OPC_MUL_LS_LS,
179 TILE_OPC_MINIH, 179 TILEGX_OPC_MUL_LS_LU,
180 TILE_OPC_MINIH_SN, 180 TILEGX_OPC_MUL_LU_LU,
181 TILE_OPC_MM, 181 TILEGX_OPC_MULA_HS_HS,
182 TILE_OPC_MNZ, 182 TILEGX_OPC_MULA_HS_HU,
183 TILE_OPC_MNZ_SN, 183 TILEGX_OPC_MULA_HS_LS,
184 TILE_OPC_MNZB, 184 TILEGX_OPC_MULA_HS_LU,
185 TILE_OPC_MNZB_SN, 185 TILEGX_OPC_MULA_HU_HU,
186 TILE_OPC_MNZH, 186 TILEGX_OPC_MULA_HU_LS,
187 TILE_OPC_MNZH_SN, 187 TILEGX_OPC_MULA_HU_LU,
188 TILE_OPC_MTSPR, 188 TILEGX_OPC_MULA_LS_LS,
189 TILE_OPC_MULHH_SS, 189 TILEGX_OPC_MULA_LS_LU,
190 TILE_OPC_MULHH_SS_SN, 190 TILEGX_OPC_MULA_LU_LU,
191 TILE_OPC_MULHH_SU, 191 TILEGX_OPC_MULAX,
192 TILE_OPC_MULHH_SU_SN, 192 TILEGX_OPC_MULX,
193 TILE_OPC_MULHH_UU, 193 TILEGX_OPC_MZ,
194 TILE_OPC_MULHH_UU_SN, 194 TILEGX_OPC_NAP,
195 TILE_OPC_MULHHA_SS, 195 TILEGX_OPC_NOP,
196 TILE_OPC_MULHHA_SS_SN, 196 TILEGX_OPC_NOR,
197 TILE_OPC_MULHHA_SU, 197 TILEGX_OPC_OR,
198 TILE_OPC_MULHHA_SU_SN, 198 TILEGX_OPC_ORI,
199 TILE_OPC_MULHHA_UU, 199 TILEGX_OPC_PCNT,
200 TILE_OPC_MULHHA_UU_SN, 200 TILEGX_OPC_REVBITS,
201 TILE_OPC_MULHHSA_UU, 201 TILEGX_OPC_REVBYTES,
202 TILE_OPC_MULHHSA_UU_SN, 202 TILEGX_OPC_ROTL,
203 TILE_OPC_MULHL_SS, 203 TILEGX_OPC_ROTLI,
204 TILE_OPC_MULHL_SS_SN, 204 TILEGX_OPC_SHL,
205 TILE_OPC_MULHL_SU, 205 TILEGX_OPC_SHL16INSLI,
206 TILE_OPC_MULHL_SU_SN, 206 TILEGX_OPC_SHL1ADD,
207 TILE_OPC_MULHL_US, 207 TILEGX_OPC_SHL1ADDX,
208 TILE_OPC_MULHL_US_SN, 208 TILEGX_OPC_SHL2ADD,
209 TILE_OPC_MULHL_UU, 209 TILEGX_OPC_SHL2ADDX,
210 TILE_OPC_MULHL_UU_SN, 210 TILEGX_OPC_SHL3ADD,
211 TILE_OPC_MULHLA_SS, 211 TILEGX_OPC_SHL3ADDX,
212 TILE_OPC_MULHLA_SS_SN, 212 TILEGX_OPC_SHLI,
213 TILE_OPC_MULHLA_SU, 213 TILEGX_OPC_SHLX,
214 TILE_OPC_MULHLA_SU_SN, 214 TILEGX_OPC_SHLXI,
215 TILE_OPC_MULHLA_US, 215 TILEGX_OPC_SHRS,
216 TILE_OPC_MULHLA_US_SN, 216 TILEGX_OPC_SHRSI,
217 TILE_OPC_MULHLA_UU, 217 TILEGX_OPC_SHRU,
218 TILE_OPC_MULHLA_UU_SN, 218 TILEGX_OPC_SHRUI,
219 TILE_OPC_MULHLSA_UU, 219 TILEGX_OPC_SHRUX,
220 TILE_OPC_MULHLSA_UU_SN, 220 TILEGX_OPC_SHRUXI,
221 TILE_OPC_MULLL_SS, 221 TILEGX_OPC_SHUFFLEBYTES,
222 TILE_OPC_MULLL_SS_SN, 222 TILEGX_OPC_ST,
223 TILE_OPC_MULLL_SU, 223 TILEGX_OPC_ST1,
224 TILE_OPC_MULLL_SU_SN, 224 TILEGX_OPC_ST1_ADD,
225 TILE_OPC_MULLL_UU, 225 TILEGX_OPC_ST2,
226 TILE_OPC_MULLL_UU_SN, 226 TILEGX_OPC_ST2_ADD,
227 TILE_OPC_MULLLA_SS, 227 TILEGX_OPC_ST4,
228 TILE_OPC_MULLLA_SS_SN, 228 TILEGX_OPC_ST4_ADD,
229 TILE_OPC_MULLLA_SU, 229 TILEGX_OPC_ST_ADD,
230 TILE_OPC_MULLLA_SU_SN, 230 TILEGX_OPC_STNT,
231 TILE_OPC_MULLLA_UU, 231 TILEGX_OPC_STNT1,
232 TILE_OPC_MULLLA_UU_SN, 232 TILEGX_OPC_STNT1_ADD,
233 TILE_OPC_MULLLSA_UU, 233 TILEGX_OPC_STNT2,
234 TILE_OPC_MULLLSA_UU_SN, 234 TILEGX_OPC_STNT2_ADD,
235 TILE_OPC_MVNZ, 235 TILEGX_OPC_STNT4,
236 TILE_OPC_MVNZ_SN, 236 TILEGX_OPC_STNT4_ADD,
237 TILE_OPC_MVZ, 237 TILEGX_OPC_STNT_ADD,
238 TILE_OPC_MVZ_SN, 238 TILEGX_OPC_SUB,
239 TILE_OPC_MZ, 239 TILEGX_OPC_SUBX,
240 TILE_OPC_MZ_SN, 240 TILEGX_OPC_SUBXSC,
241 TILE_OPC_MZB, 241 TILEGX_OPC_SWINT0,
242 TILE_OPC_MZB_SN, 242 TILEGX_OPC_SWINT1,
243 TILE_OPC_MZH, 243 TILEGX_OPC_SWINT2,
244 TILE_OPC_MZH_SN, 244 TILEGX_OPC_SWINT3,
245 TILE_OPC_NAP, 245 TILEGX_OPC_TBLIDXB0,
246 TILE_OPC_NOP, 246 TILEGX_OPC_TBLIDXB1,
247 TILE_OPC_NOR, 247 TILEGX_OPC_TBLIDXB2,
248 TILE_OPC_NOR_SN, 248 TILEGX_OPC_TBLIDXB3,
249 TILE_OPC_OR, 249 TILEGX_OPC_V1ADD,
250 TILE_OPC_OR_SN, 250 TILEGX_OPC_V1ADDI,
251 TILE_OPC_ORI, 251 TILEGX_OPC_V1ADDUC,
252 TILE_OPC_ORI_SN, 252 TILEGX_OPC_V1ADIFFU,
253 TILE_OPC_PACKBS_U, 253 TILEGX_OPC_V1AVGU,
254 TILE_OPC_PACKBS_U_SN, 254 TILEGX_OPC_V1CMPEQ,
255 TILE_OPC_PACKHB, 255 TILEGX_OPC_V1CMPEQI,
256 TILE_OPC_PACKHB_SN, 256 TILEGX_OPC_V1CMPLES,
257 TILE_OPC_PACKHS, 257 TILEGX_OPC_V1CMPLEU,
258 TILE_OPC_PACKHS_SN, 258 TILEGX_OPC_V1CMPLTS,
259 TILE_OPC_PACKLB, 259 TILEGX_OPC_V1CMPLTSI,
260 TILE_OPC_PACKLB_SN, 260 TILEGX_OPC_V1CMPLTU,
261 TILE_OPC_PCNT, 261 TILEGX_OPC_V1CMPLTUI,
262 TILE_OPC_PCNT_SN, 262 TILEGX_OPC_V1CMPNE,
263 TILE_OPC_RL, 263 TILEGX_OPC_V1DDOTPU,
264 TILE_OPC_RL_SN, 264 TILEGX_OPC_V1DDOTPUA,
265 TILE_OPC_RLI, 265 TILEGX_OPC_V1DDOTPUS,
266 TILE_OPC_RLI_SN, 266 TILEGX_OPC_V1DDOTPUSA,
267 TILE_OPC_S1A, 267 TILEGX_OPC_V1DOTP,
268 TILE_OPC_S1A_SN, 268 TILEGX_OPC_V1DOTPA,
269 TILE_OPC_S2A, 269 TILEGX_OPC_V1DOTPU,
270 TILE_OPC_S2A_SN, 270 TILEGX_OPC_V1DOTPUA,
271 TILE_OPC_S3A, 271 TILEGX_OPC_V1DOTPUS,
272 TILE_OPC_S3A_SN, 272 TILEGX_OPC_V1DOTPUSA,
273 TILE_OPC_SADAB_U, 273 TILEGX_OPC_V1INT_H,
274 TILE_OPC_SADAB_U_SN, 274 TILEGX_OPC_V1INT_L,
275 TILE_OPC_SADAH, 275 TILEGX_OPC_V1MAXU,
276 TILE_OPC_SADAH_SN, 276 TILEGX_OPC_V1MAXUI,
277 TILE_OPC_SADAH_U, 277 TILEGX_OPC_V1MINU,
278 TILE_OPC_SADAH_U_SN, 278 TILEGX_OPC_V1MINUI,
279 TILE_OPC_SADB_U, 279 TILEGX_OPC_V1MNZ,
280 TILE_OPC_SADB_U_SN, 280 TILEGX_OPC_V1MULTU,
281 TILE_OPC_SADH, 281 TILEGX_OPC_V1MULU,
282 TILE_OPC_SADH_SN, 282 TILEGX_OPC_V1MULUS,
283 TILE_OPC_SADH_U, 283 TILEGX_OPC_V1MZ,
284 TILE_OPC_SADH_U_SN, 284 TILEGX_OPC_V1SADAU,
285 TILE_OPC_SB, 285 TILEGX_OPC_V1SADU,
286 TILE_OPC_SBADD, 286 TILEGX_OPC_V1SHL,
287 TILE_OPC_SEQ, 287 TILEGX_OPC_V1SHLI,
288 TILE_OPC_SEQ_SN, 288 TILEGX_OPC_V1SHRS,
289 TILE_OPC_SEQB, 289 TILEGX_OPC_V1SHRSI,
290 TILE_OPC_SEQB_SN, 290 TILEGX_OPC_V1SHRU,
291 TILE_OPC_SEQH, 291 TILEGX_OPC_V1SHRUI,
292 TILE_OPC_SEQH_SN, 292 TILEGX_OPC_V1SUB,
293 TILE_OPC_SEQI, 293 TILEGX_OPC_V1SUBUC,
294 TILE_OPC_SEQI_SN, 294 TILEGX_OPC_V2ADD,
295 TILE_OPC_SEQIB, 295 TILEGX_OPC_V2ADDI,
296 TILE_OPC_SEQIB_SN, 296 TILEGX_OPC_V2ADDSC,
297 TILE_OPC_SEQIH, 297 TILEGX_OPC_V2ADIFFS,
298 TILE_OPC_SEQIH_SN, 298 TILEGX_OPC_V2AVGS,
299 TILE_OPC_SH, 299 TILEGX_OPC_V2CMPEQ,
300 TILE_OPC_SHADD, 300 TILEGX_OPC_V2CMPEQI,
301 TILE_OPC_SHL, 301 TILEGX_OPC_V2CMPLES,
302 TILE_OPC_SHL_SN, 302 TILEGX_OPC_V2CMPLEU,
303 TILE_OPC_SHLB, 303 TILEGX_OPC_V2CMPLTS,
304 TILE_OPC_SHLB_SN, 304 TILEGX_OPC_V2CMPLTSI,
305 TILE_OPC_SHLH, 305 TILEGX_OPC_V2CMPLTU,
306 TILE_OPC_SHLH_SN, 306 TILEGX_OPC_V2CMPLTUI,
307 TILE_OPC_SHLI, 307 TILEGX_OPC_V2CMPNE,
308 TILE_OPC_SHLI_SN, 308 TILEGX_OPC_V2DOTP,
309 TILE_OPC_SHLIB, 309 TILEGX_OPC_V2DOTPA,
310 TILE_OPC_SHLIB_SN, 310 TILEGX_OPC_V2INT_H,
311 TILE_OPC_SHLIH, 311 TILEGX_OPC_V2INT_L,
312 TILE_OPC_SHLIH_SN, 312 TILEGX_OPC_V2MAXS,
313 TILE_OPC_SHR, 313 TILEGX_OPC_V2MAXSI,
314 TILE_OPC_SHR_SN, 314 TILEGX_OPC_V2MINS,
315 TILE_OPC_SHRB, 315 TILEGX_OPC_V2MINSI,
316 TILE_OPC_SHRB_SN, 316 TILEGX_OPC_V2MNZ,
317 TILE_OPC_SHRH, 317 TILEGX_OPC_V2MULFSC,
318 TILE_OPC_SHRH_SN, 318 TILEGX_OPC_V2MULS,
319 TILE_OPC_SHRI, 319 TILEGX_OPC_V2MULTS,
320 TILE_OPC_SHRI_SN, 320 TILEGX_OPC_V2MZ,
321 TILE_OPC_SHRIB, 321 TILEGX_OPC_V2PACKH,
322 TILE_OPC_SHRIB_SN, 322 TILEGX_OPC_V2PACKL,
323 TILE_OPC_SHRIH, 323 TILEGX_OPC_V2PACKUC,
324 TILE_OPC_SHRIH_SN, 324 TILEGX_OPC_V2SADAS,
325 TILE_OPC_SLT, 325 TILEGX_OPC_V2SADAU,
326 TILE_OPC_SLT_SN, 326 TILEGX_OPC_V2SADS,
327 TILE_OPC_SLT_U, 327 TILEGX_OPC_V2SADU,
328 TILE_OPC_SLT_U_SN, 328 TILEGX_OPC_V2SHL,
329 TILE_OPC_SLTB, 329 TILEGX_OPC_V2SHLI,
330 TILE_OPC_SLTB_SN, 330 TILEGX_OPC_V2SHLSC,
331 TILE_OPC_SLTB_U, 331 TILEGX_OPC_V2SHRS,
332 TILE_OPC_SLTB_U_SN, 332 TILEGX_OPC_V2SHRSI,
333 TILE_OPC_SLTE, 333 TILEGX_OPC_V2SHRU,
334 TILE_OPC_SLTE_SN, 334 TILEGX_OPC_V2SHRUI,
335 TILE_OPC_SLTE_U, 335 TILEGX_OPC_V2SUB,
336 TILE_OPC_SLTE_U_SN, 336 TILEGX_OPC_V2SUBSC,
337 TILE_OPC_SLTEB, 337 TILEGX_OPC_V4ADD,
338 TILE_OPC_SLTEB_SN, 338 TILEGX_OPC_V4ADDSC,
339 TILE_OPC_SLTEB_U, 339 TILEGX_OPC_V4INT_H,
340 TILE_OPC_SLTEB_U_SN, 340 TILEGX_OPC_V4INT_L,
341 TILE_OPC_SLTEH, 341 TILEGX_OPC_V4PACKSC,
342 TILE_OPC_SLTEH_SN, 342 TILEGX_OPC_V4SHL,
343 TILE_OPC_SLTEH_U, 343 TILEGX_OPC_V4SHLSC,
344 TILE_OPC_SLTEH_U_SN, 344 TILEGX_OPC_V4SHRS,
345 TILE_OPC_SLTH, 345 TILEGX_OPC_V4SHRU,
346 TILE_OPC_SLTH_SN, 346 TILEGX_OPC_V4SUB,
347 TILE_OPC_SLTH_U, 347 TILEGX_OPC_V4SUBSC,
348 TILE_OPC_SLTH_U_SN, 348 TILEGX_OPC_WH64,
349 TILE_OPC_SLTI, 349 TILEGX_OPC_XOR,
350 TILE_OPC_SLTI_SN, 350 TILEGX_OPC_XORI,
351 TILE_OPC_SLTI_U, 351 TILEGX_OPC_NONE
352 TILE_OPC_SLTI_U_SN, 352} tilegx_mnemonic;
353 TILE_OPC_SLTIB,
354 TILE_OPC_SLTIB_SN,
355 TILE_OPC_SLTIB_U,
356 TILE_OPC_SLTIB_U_SN,
357 TILE_OPC_SLTIH,
358 TILE_OPC_SLTIH_SN,
359 TILE_OPC_SLTIH_U,
360 TILE_OPC_SLTIH_U_SN,
361 TILE_OPC_SNE,
362 TILE_OPC_SNE_SN,
363 TILE_OPC_SNEB,
364 TILE_OPC_SNEB_SN,
365 TILE_OPC_SNEH,
366 TILE_OPC_SNEH_SN,
367 TILE_OPC_SRA,
368 TILE_OPC_SRA_SN,
369 TILE_OPC_SRAB,
370 TILE_OPC_SRAB_SN,
371 TILE_OPC_SRAH,
372 TILE_OPC_SRAH_SN,
373 TILE_OPC_SRAI,
374 TILE_OPC_SRAI_SN,
375 TILE_OPC_SRAIB,
376 TILE_OPC_SRAIB_SN,
377 TILE_OPC_SRAIH,
378 TILE_OPC_SRAIH_SN,
379 TILE_OPC_SUB,
380 TILE_OPC_SUB_SN,
381 TILE_OPC_SUBB,
382 TILE_OPC_SUBB_SN,
383 TILE_OPC_SUBBS_U,
384 TILE_OPC_SUBBS_U_SN,
385 TILE_OPC_SUBH,
386 TILE_OPC_SUBH_SN,
387 TILE_OPC_SUBHS,
388 TILE_OPC_SUBHS_SN,
389 TILE_OPC_SUBS,
390 TILE_OPC_SUBS_SN,
391 TILE_OPC_SW,
392 TILE_OPC_SWADD,
393 TILE_OPC_SWINT0,
394 TILE_OPC_SWINT1,
395 TILE_OPC_SWINT2,
396 TILE_OPC_SWINT3,
397 TILE_OPC_TBLIDXB0,
398 TILE_OPC_TBLIDXB0_SN,
399 TILE_OPC_TBLIDXB1,
400 TILE_OPC_TBLIDXB1_SN,
401 TILE_OPC_TBLIDXB2,
402 TILE_OPC_TBLIDXB2_SN,
403 TILE_OPC_TBLIDXB3,
404 TILE_OPC_TBLIDXB3_SN,
405 TILE_OPC_TNS,
406 TILE_OPC_TNS_SN,
407 TILE_OPC_WH64,
408 TILE_OPC_XOR,
409 TILE_OPC_XOR_SN,
410 TILE_OPC_XORI,
411 TILE_OPC_XORI_SN,
412 TILE_OPC_NONE
413} tile_mnemonic;
414 353
415/* 64-bit pattern for a { bpt ; nop } bundle. */ 354/* 64-bit pattern for a { bpt ; nop } bundle. */
416#define TILE_BPT_BUNDLE 0x400b3cae70166000ULL 355#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
417 356
418 357
419#define TILE_ELF_MACHINE_CODE EM_TILEPRO 358#define TILE_ELF_MACHINE_CODE EM_TILE64
420 359
421#define TILE_ELF_NAME "elf32-tilepro" 360#define TILE_ELF_NAME "elf32-tile64"
422 361
423 362
424static __inline unsigned int 363static __inline unsigned int
425get_BrOff_SN(tile_bundle_bits num) 364get_BFEnd_X0(tilegx_bundle_bits num)
426{ 365{
427 const unsigned int n = (unsigned int)num; 366 const unsigned int n = (unsigned int)num;
428 return (((n >> 0)) & 0x3ff); 367 return (((n >> 12)) & 0x3f);
429} 368}
430 369
431static __inline unsigned int 370static __inline unsigned int
432get_BrOff_X1(tile_bundle_bits n) 371get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
433{ 372{
434 return (((unsigned int)(n >> 43)) & 0x00007fff) | 373 const unsigned int n = (unsigned int)num;
435 (((unsigned int)(n >> 20)) & 0x00018000); 374 return (((n >> 24)) & 0xf);
436} 375}
437 376
438static __inline unsigned int 377static __inline unsigned int
439get_BrType_X1(tile_bundle_bits n) 378get_BFStart_X0(tilegx_bundle_bits num)
440{ 379{
441 return (((unsigned int)(n >> 31)) & 0xf); 380 const unsigned int n = (unsigned int)num;
381 return (((n >> 18)) & 0x3f);
442} 382}
443 383
444static __inline unsigned int 384static __inline unsigned int
445get_Dest_Imm8_X1(tile_bundle_bits n) 385get_BrOff_X1(tilegx_bundle_bits n)
446{ 386{
447 return (((unsigned int)(n >> 31)) & 0x0000003f) | 387 return (((unsigned int)(n >> 31)) & 0x0000003f) |
448 (((unsigned int)(n >> 43)) & 0x000000c0); 388 (((unsigned int)(n >> 37)) & 0x0001ffc0);
449} 389}
450 390
451static __inline unsigned int 391static __inline unsigned int
452get_Dest_SN(tile_bundle_bits num) 392get_BrType_X1(tilegx_bundle_bits n)
453{ 393{
454 const unsigned int n = (unsigned int)num; 394 return (((unsigned int)(n >> 54)) & 0x1f);
455 return (((n >> 2)) & 0x3);
456} 395}
457 396
458static __inline unsigned int 397static __inline unsigned int
459get_Dest_X0(tile_bundle_bits num) 398get_Dest_Imm8_X1(tilegx_bundle_bits n)
399{
400 return (((unsigned int)(n >> 31)) & 0x0000003f) |
401 (((unsigned int)(n >> 43)) & 0x000000c0);
402}
403
404static __inline unsigned int
405get_Dest_X0(tilegx_bundle_bits num)
460{ 406{
461 const unsigned int n = (unsigned int)num; 407 const unsigned int n = (unsigned int)num;
462 return (((n >> 0)) & 0x3f); 408 return (((n >> 0)) & 0x3f);
463} 409}
464 410
465static __inline unsigned int 411static __inline unsigned int
466get_Dest_X1(tile_bundle_bits n) 412get_Dest_X1(tilegx_bundle_bits n)
467{ 413{
468 return (((unsigned int)(n >> 31)) & 0x3f); 414 return (((unsigned int)(n >> 31)) & 0x3f);
469} 415}
470 416
471static __inline unsigned int 417static __inline unsigned int
472get_Dest_Y0(tile_bundle_bits num) 418get_Dest_Y0(tilegx_bundle_bits num)
473{ 419{
474 const unsigned int n = (unsigned int)num; 420 const unsigned int n = (unsigned int)num;
475 return (((n >> 0)) & 0x3f); 421 return (((n >> 0)) & 0x3f);
476} 422}
477 423
478static __inline unsigned int 424static __inline unsigned int
479get_Dest_Y1(tile_bundle_bits n) 425get_Dest_Y1(tilegx_bundle_bits n)
480{ 426{
481 return (((unsigned int)(n >> 31)) & 0x3f); 427 return (((unsigned int)(n >> 31)) & 0x3f);
482} 428}
483 429
484static __inline unsigned int 430static __inline unsigned int
485get_Imm16_X0(tile_bundle_bits num) 431get_Imm16_X0(tilegx_bundle_bits num)
486{ 432{
487 const unsigned int n = (unsigned int)num; 433 const unsigned int n = (unsigned int)num;
488 return (((n >> 12)) & 0xffff); 434 return (((n >> 12)) & 0xffff);
489} 435}
490 436
491static __inline unsigned int 437static __inline unsigned int
492get_Imm16_X1(tile_bundle_bits n) 438get_Imm16_X1(tilegx_bundle_bits n)
493{ 439{
494 return (((unsigned int)(n >> 43)) & 0xffff); 440 return (((unsigned int)(n >> 43)) & 0xffff);
495} 441}
496 442
497static __inline unsigned int 443static __inline unsigned int
498get_Imm8_SN(tile_bundle_bits num) 444get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
499{
500 const unsigned int n = (unsigned int)num;
501 return (((n >> 0)) & 0xff);
502}
503
504static __inline unsigned int
505get_Imm8_X0(tile_bundle_bits num)
506{ 445{
507 const unsigned int n = (unsigned int)num; 446 const unsigned int n = (unsigned int)num;
508 return (((n >> 12)) & 0xff); 447 return (((n >> 20)) & 0xff);
509} 448}
510 449
511static __inline unsigned int 450static __inline unsigned int
512get_Imm8_X1(tile_bundle_bits n) 451get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
513{ 452{
514 return (((unsigned int)(n >> 43)) & 0xff); 453 return (((unsigned int)(n >> 51)) & 0xff);
515} 454}
516 455
517static __inline unsigned int 456static __inline unsigned int
518get_Imm8_Y0(tile_bundle_bits num) 457get_Imm8_X0(tilegx_bundle_bits num)
519{ 458{
520 const unsigned int n = (unsigned int)num; 459 const unsigned int n = (unsigned int)num;
521 return (((n >> 12)) & 0xff); 460 return (((n >> 12)) & 0xff);
522} 461}
523 462
524static __inline unsigned int 463static __inline unsigned int
525get_Imm8_Y1(tile_bundle_bits n) 464get_Imm8_X1(tilegx_bundle_bits n)
526{ 465{
527 return (((unsigned int)(n >> 43)) & 0xff); 466 return (((unsigned int)(n >> 43)) & 0xff);
528} 467}
529 468
530static __inline unsigned int 469static __inline unsigned int
531get_ImmOpcodeExtension_X0(tile_bundle_bits num) 470get_Imm8_Y0(tilegx_bundle_bits num)
532{
533 const unsigned int n = (unsigned int)num;
534 return (((n >> 20)) & 0x7f);
535}
536
537static __inline unsigned int
538get_ImmOpcodeExtension_X1(tile_bundle_bits n)
539{
540 return (((unsigned int)(n >> 51)) & 0x7f);
541}
542
543static __inline unsigned int
544get_ImmRROpcodeExtension_SN(tile_bundle_bits num)
545{ 471{
546 const unsigned int n = (unsigned int)num; 472 const unsigned int n = (unsigned int)num;
547 return (((n >> 8)) & 0x3); 473 return (((n >> 12)) & 0xff);
548}
549
550static __inline unsigned int
551get_JOffLong_X1(tile_bundle_bits n)
552{
553 return (((unsigned int)(n >> 43)) & 0x00007fff) |
554 (((unsigned int)(n >> 20)) & 0x00018000) |
555 (((unsigned int)(n >> 14)) & 0x001e0000) |
556 (((unsigned int)(n >> 16)) & 0x07e00000) |
557 (((unsigned int)(n >> 31)) & 0x18000000);
558}
559
560static __inline unsigned int
561get_JOff_X1(tile_bundle_bits n)
562{
563 return (((unsigned int)(n >> 43)) & 0x00007fff) |
564 (((unsigned int)(n >> 20)) & 0x00018000) |
565 (((unsigned int)(n >> 14)) & 0x001e0000) |
566 (((unsigned int)(n >> 16)) & 0x07e00000) |
567 (((unsigned int)(n >> 31)) & 0x08000000);
568}
569
570static __inline unsigned int
571get_MF_Imm15_X1(tile_bundle_bits n)
572{
573 return (((unsigned int)(n >> 37)) & 0x00003fff) |
574 (((unsigned int)(n >> 44)) & 0x00004000);
575} 474}
576 475
577static __inline unsigned int 476static __inline unsigned int
578get_MMEnd_X0(tile_bundle_bits num) 477get_Imm8_Y1(tilegx_bundle_bits n)
579{ 478{
580 const unsigned int n = (unsigned int)num; 479 return (((unsigned int)(n >> 43)) & 0xff);
581 return (((n >> 18)) & 0x1f);
582} 480}
583 481
584static __inline unsigned int 482static __inline unsigned int
585get_MMEnd_X1(tile_bundle_bits n) 483get_JumpOff_X1(tilegx_bundle_bits n)
586{ 484{
587 return (((unsigned int)(n >> 49)) & 0x1f); 485 return (((unsigned int)(n >> 31)) & 0x7ffffff);
588} 486}
589 487
590static __inline unsigned int 488static __inline unsigned int
591get_MMStart_X0(tile_bundle_bits num) 489get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
592{ 490{
593 const unsigned int n = (unsigned int)num; 491 return (((unsigned int)(n >> 58)) & 0x1);
594 return (((n >> 23)) & 0x1f);
595} 492}
596 493
597static __inline unsigned int 494static __inline unsigned int
598get_MMStart_X1(tile_bundle_bits n) 495get_MF_Imm14_X1(tilegx_bundle_bits n)
599{ 496{
600 return (((unsigned int)(n >> 54)) & 0x1f); 497 return (((unsigned int)(n >> 37)) & 0x3fff);
601} 498}
602 499
603static __inline unsigned int 500static __inline unsigned int
604get_MT_Imm15_X1(tile_bundle_bits n) 501get_MT_Imm14_X1(tilegx_bundle_bits n)
605{ 502{
606 return (((unsigned int)(n >> 31)) & 0x0000003f) | 503 return (((unsigned int)(n >> 31)) & 0x0000003f) |
607 (((unsigned int)(n >> 37)) & 0x00003fc0) | 504 (((unsigned int)(n >> 37)) & 0x00003fc0);
608 (((unsigned int)(n >> 44)) & 0x00004000);
609} 505}
610 506
611static __inline unsigned int 507static __inline unsigned int
612get_Mode(tile_bundle_bits n) 508get_Mode(tilegx_bundle_bits n)
613{ 509{
614 return (((unsigned int)(n >> 63)) & 0x1); 510 return (((unsigned int)(n >> 62)) & 0x3);
615} 511}
616 512
617static __inline unsigned int 513static __inline unsigned int
618get_NoRegOpcodeExtension_SN(tile_bundle_bits num) 514get_Opcode_X0(tilegx_bundle_bits num)
619{
620 const unsigned int n = (unsigned int)num;
621 return (((n >> 0)) & 0xf);
622}
623
624static __inline unsigned int
625get_Opcode_SN(tile_bundle_bits num)
626{
627 const unsigned int n = (unsigned int)num;
628 return (((n >> 10)) & 0x3f);
629}
630
631static __inline unsigned int
632get_Opcode_X0(tile_bundle_bits num)
633{ 515{
634 const unsigned int n = (unsigned int)num; 516 const unsigned int n = (unsigned int)num;
635 return (((n >> 28)) & 0x7); 517 return (((n >> 28)) & 0x7);
636} 518}
637 519
638static __inline unsigned int 520static __inline unsigned int
639get_Opcode_X1(tile_bundle_bits n) 521get_Opcode_X1(tilegx_bundle_bits n)
640{ 522{
641 return (((unsigned int)(n >> 59)) & 0xf); 523 return (((unsigned int)(n >> 59)) & 0x7);
642} 524}
643 525
644static __inline unsigned int 526static __inline unsigned int
645get_Opcode_Y0(tile_bundle_bits num) 527get_Opcode_Y0(tilegx_bundle_bits num)
646{ 528{
647 const unsigned int n = (unsigned int)num; 529 const unsigned int n = (unsigned int)num;
648 return (((n >> 27)) & 0xf); 530 return (((n >> 27)) & 0xf);
649} 531}
650 532
651static __inline unsigned int 533static __inline unsigned int
652get_Opcode_Y1(tile_bundle_bits n) 534get_Opcode_Y1(tilegx_bundle_bits n)
653{ 535{
654 return (((unsigned int)(n >> 59)) & 0xf); 536 return (((unsigned int)(n >> 58)) & 0xf);
655} 537}
656 538
657static __inline unsigned int 539static __inline unsigned int
658get_Opcode_Y2(tile_bundle_bits n) 540get_Opcode_Y2(tilegx_bundle_bits n)
659{ 541{
660 return (((unsigned int)(n >> 56)) & 0x7); 542 return (((n >> 26)) & 0x00000001) |
661} 543 (((unsigned int)(n >> 56)) & 0x00000002);
662
663static __inline unsigned int
664get_RROpcodeExtension_SN(tile_bundle_bits num)
665{
666 const unsigned int n = (unsigned int)num;
667 return (((n >> 4)) & 0xf);
668} 544}
669 545
670static __inline unsigned int 546static __inline unsigned int
671get_RRROpcodeExtension_X0(tile_bundle_bits num) 547get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
672{ 548{
673 const unsigned int n = (unsigned int)num; 549 const unsigned int n = (unsigned int)num;
674 return (((n >> 18)) & 0x1ff); 550 return (((n >> 18)) & 0x3ff);
675} 551}
676 552
677static __inline unsigned int 553static __inline unsigned int
678get_RRROpcodeExtension_X1(tile_bundle_bits n) 554get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
679{ 555{
680 return (((unsigned int)(n >> 49)) & 0x1ff); 556 return (((unsigned int)(n >> 49)) & 0x3ff);
681} 557}
682 558
683static __inline unsigned int 559static __inline unsigned int
684get_RRROpcodeExtension_Y0(tile_bundle_bits num) 560get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
685{ 561{
686 const unsigned int n = (unsigned int)num; 562 const unsigned int n = (unsigned int)num;
687 return (((n >> 18)) & 0x3); 563 return (((n >> 18)) & 0x3);
688} 564}
689 565
690static __inline unsigned int 566static __inline unsigned int
691get_RRROpcodeExtension_Y1(tile_bundle_bits n) 567get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
692{ 568{
693 return (((unsigned int)(n >> 49)) & 0x3); 569 return (((unsigned int)(n >> 49)) & 0x3);
694} 570}
695 571
696static __inline unsigned int 572static __inline unsigned int
697get_RouteOpcodeExtension_SN(tile_bundle_bits num) 573get_ShAmt_X0(tilegx_bundle_bits num)
698{
699 const unsigned int n = (unsigned int)num;
700 return (((n >> 0)) & 0x3ff);
701}
702
703static __inline unsigned int
704get_S_X0(tile_bundle_bits num)
705{ 574{
706 const unsigned int n = (unsigned int)num; 575 const unsigned int n = (unsigned int)num;
707 return (((n >> 27)) & 0x1); 576 return (((n >> 12)) & 0x3f);
708} 577}
709 578
710static __inline unsigned int 579static __inline unsigned int
711get_S_X1(tile_bundle_bits n) 580get_ShAmt_X1(tilegx_bundle_bits n)
712{ 581{
713 return (((unsigned int)(n >> 58)) & 0x1); 582 return (((unsigned int)(n >> 43)) & 0x3f);
714} 583}
715 584
716static __inline unsigned int 585static __inline unsigned int
717get_ShAmt_X0(tile_bundle_bits num) 586get_ShAmt_Y0(tilegx_bundle_bits num)
718{ 587{
719 const unsigned int n = (unsigned int)num; 588 const unsigned int n = (unsigned int)num;
720 return (((n >> 12)) & 0x1f); 589 return (((n >> 12)) & 0x3f);
721} 590}
722 591
723static __inline unsigned int 592static __inline unsigned int
724get_ShAmt_X1(tile_bundle_bits n) 593get_ShAmt_Y1(tilegx_bundle_bits n)
725{ 594{
726 return (((unsigned int)(n >> 43)) & 0x1f); 595 return (((unsigned int)(n >> 43)) & 0x3f);
727} 596}
728 597
729static __inline unsigned int 598static __inline unsigned int
730get_ShAmt_Y0(tile_bundle_bits num) 599get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
731{ 600{
732 const unsigned int n = (unsigned int)num; 601 const unsigned int n = (unsigned int)num;
733 return (((n >> 12)) & 0x1f); 602 return (((n >> 18)) & 0x3ff);
734} 603}
735 604
736static __inline unsigned int 605static __inline unsigned int
737get_ShAmt_Y1(tile_bundle_bits n) 606get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
738{ 607{
739 return (((unsigned int)(n >> 43)) & 0x1f); 608 return (((unsigned int)(n >> 49)) & 0x3ff);
740} 609}
741 610
742static __inline unsigned int 611static __inline unsigned int
743get_SrcA_X0(tile_bundle_bits num) 612get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
744{ 613{
745 const unsigned int n = (unsigned int)num; 614 const unsigned int n = (unsigned int)num;
746 return (((n >> 6)) & 0x3f); 615 return (((n >> 18)) & 0x3);
747} 616}
748 617
749static __inline unsigned int 618static __inline unsigned int
750get_SrcA_X1(tile_bundle_bits n) 619get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
751{ 620{
752 return (((unsigned int)(n >> 37)) & 0x3f); 621 return (((unsigned int)(n >> 49)) & 0x3);
753} 622}
754 623
755static __inline unsigned int 624static __inline unsigned int
756get_SrcA_Y0(tile_bundle_bits num) 625get_SrcA_X0(tilegx_bundle_bits num)
757{ 626{
758 const unsigned int n = (unsigned int)num; 627 const unsigned int n = (unsigned int)num;
759 return (((n >> 6)) & 0x3f); 628 return (((n >> 6)) & 0x3f);
760} 629}
761 630
762static __inline unsigned int 631static __inline unsigned int
763get_SrcA_Y1(tile_bundle_bits n) 632get_SrcA_X1(tilegx_bundle_bits n)
764{ 633{
765 return (((unsigned int)(n >> 37)) & 0x3f); 634 return (((unsigned int)(n >> 37)) & 0x3f);
766} 635}
767 636
768static __inline unsigned int 637static __inline unsigned int
769get_SrcA_Y2(tile_bundle_bits n) 638get_SrcA_Y0(tilegx_bundle_bits num)
770{ 639{
771 return (((n >> 26)) & 0x00000001) | 640 const unsigned int n = (unsigned int)num;
772 (((unsigned int)(n >> 50)) & 0x0000003e); 641 return (((n >> 6)) & 0x3f);
773} 642}
774 643
775static __inline unsigned int 644static __inline unsigned int
776get_SrcBDest_Y2(tile_bundle_bits num) 645get_SrcA_Y1(tilegx_bundle_bits n)
777{ 646{
778 const unsigned int n = (unsigned int)num; 647 return (((unsigned int)(n >> 37)) & 0x3f);
779 return (((n >> 20)) & 0x3f);
780} 648}
781 649
782static __inline unsigned int 650static __inline unsigned int
783get_SrcB_X0(tile_bundle_bits num) 651get_SrcA_Y2(tilegx_bundle_bits num)
784{ 652{
785 const unsigned int n = (unsigned int)num; 653 const unsigned int n = (unsigned int)num;
786 return (((n >> 12)) & 0x3f); 654 return (((n >> 20)) & 0x3f);
787} 655}
788 656
789static __inline unsigned int 657static __inline unsigned int
790get_SrcB_X1(tile_bundle_bits n) 658get_SrcBDest_Y2(tilegx_bundle_bits n)
791{ 659{
792 return (((unsigned int)(n >> 43)) & 0x3f); 660 return (((unsigned int)(n >> 51)) & 0x3f);
793} 661}
794 662
795static __inline unsigned int 663static __inline unsigned int
796get_SrcB_Y0(tile_bundle_bits num) 664get_SrcB_X0(tilegx_bundle_bits num)
797{ 665{
798 const unsigned int n = (unsigned int)num; 666 const unsigned int n = (unsigned int)num;
799 return (((n >> 12)) & 0x3f); 667 return (((n >> 12)) & 0x3f);
800} 668}
801 669
802static __inline unsigned int 670static __inline unsigned int
803get_SrcB_Y1(tile_bundle_bits n) 671get_SrcB_X1(tilegx_bundle_bits n)
804{ 672{
805 return (((unsigned int)(n >> 43)) & 0x3f); 673 return (((unsigned int)(n >> 43)) & 0x3f);
806} 674}
807 675
808static __inline unsigned int 676static __inline unsigned int
809get_Src_SN(tile_bundle_bits num) 677get_SrcB_Y0(tilegx_bundle_bits num)
810{ 678{
811 const unsigned int n = (unsigned int)num; 679 const unsigned int n = (unsigned int)num;
812 return (((n >> 0)) & 0x3); 680 return (((n >> 12)) & 0x3f);
813}
814
815static __inline unsigned int
816get_UnOpcodeExtension_X0(tile_bundle_bits num)
817{
818 const unsigned int n = (unsigned int)num;
819 return (((n >> 12)) & 0x1f);
820}
821
822static __inline unsigned int
823get_UnOpcodeExtension_X1(tile_bundle_bits n)
824{
825 return (((unsigned int)(n >> 43)) & 0x1f);
826}
827
828static __inline unsigned int
829get_UnOpcodeExtension_Y0(tile_bundle_bits num)
830{
831 const unsigned int n = (unsigned int)num;
832 return (((n >> 12)) & 0x1f);
833} 681}
834 682
835static __inline unsigned int 683static __inline unsigned int
836get_UnOpcodeExtension_Y1(tile_bundle_bits n) 684get_SrcB_Y1(tilegx_bundle_bits n)
837{ 685{
838 return (((unsigned int)(n >> 43)) & 0x1f); 686 return (((unsigned int)(n >> 43)) & 0x3f);
839} 687}
840 688
841static __inline unsigned int 689static __inline unsigned int
842get_UnShOpcodeExtension_X0(tile_bundle_bits num) 690get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
843{ 691{
844 const unsigned int n = (unsigned int)num; 692 const unsigned int n = (unsigned int)num;
845 return (((n >> 17)) & 0x3ff); 693 return (((n >> 12)) & 0x3f);
846} 694}
847 695
848static __inline unsigned int 696static __inline unsigned int
849get_UnShOpcodeExtension_X1(tile_bundle_bits n) 697get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
850{ 698{
851 return (((unsigned int)(n >> 48)) & 0x3ff); 699 return (((unsigned int)(n >> 43)) & 0x3f);
852} 700}
853 701
854static __inline unsigned int 702static __inline unsigned int
855get_UnShOpcodeExtension_Y0(tile_bundle_bits num) 703get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
856{ 704{
857 const unsigned int n = (unsigned int)num; 705 const unsigned int n = (unsigned int)num;
858 return (((n >> 17)) & 0x7); 706 return (((n >> 12)) & 0x3f);
859} 707}
860 708
861static __inline unsigned int 709static __inline unsigned int
862get_UnShOpcodeExtension_Y1(tile_bundle_bits n) 710get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
863{ 711{
864 return (((unsigned int)(n >> 48)) & 0x7); 712 return (((unsigned int)(n >> 43)) & 0x3f);
865} 713}
866 714
867 715
@@ -874,546 +722,441 @@ sign_extend(int n, int num_bits)
874 722
875 723
876 724
877static __inline tile_bundle_bits 725static __inline tilegx_bundle_bits
878create_BrOff_SN(int num) 726create_BFEnd_X0(int num)
879{ 727{
880 const unsigned int n = (unsigned int)num; 728 const unsigned int n = (unsigned int)num;
881 return ((n & 0x3ff) << 0); 729 return ((n & 0x3f) << 12);
882} 730}
883 731
884static __inline tile_bundle_bits 732static __inline tilegx_bundle_bits
885create_BrOff_X1(int num) 733create_BFOpcodeExtension_X0(int num)
886{ 734{
887 const unsigned int n = (unsigned int)num; 735 const unsigned int n = (unsigned int)num;
888 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) | 736 return ((n & 0xf) << 24);
889 (((tile_bundle_bits)(n & 0x00018000)) << 20);
890} 737}
891 738
892static __inline tile_bundle_bits 739static __inline tilegx_bundle_bits
893create_BrType_X1(int num) 740create_BFStart_X0(int num)
894{ 741{
895 const unsigned int n = (unsigned int)num; 742 const unsigned int n = (unsigned int)num;
896 return (((tile_bundle_bits)(n & 0xf)) << 31); 743 return ((n & 0x3f) << 18);
897} 744}
898 745
899static __inline tile_bundle_bits 746static __inline tilegx_bundle_bits
900create_Dest_Imm8_X1(int num) 747create_BrOff_X1(int num)
901{ 748{
902 const unsigned int n = (unsigned int)num; 749 const unsigned int n = (unsigned int)num;
903 return (((tile_bundle_bits)(n & 0x0000003f)) << 31) | 750 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
904 (((tile_bundle_bits)(n & 0x000000c0)) << 43); 751 (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
905} 752}
906 753
907static __inline tile_bundle_bits 754static __inline tilegx_bundle_bits
908create_Dest_SN(int num) 755create_BrType_X1(int num)
756{
757 const unsigned int n = (unsigned int)num;
758 return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
759}
760
761static __inline tilegx_bundle_bits
762create_Dest_Imm8_X1(int num)
909{ 763{
910 const unsigned int n = (unsigned int)num; 764 const unsigned int n = (unsigned int)num;
911 return ((n & 0x3) << 2); 765 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
766 (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
912} 767}
913 768
914static __inline tile_bundle_bits 769static __inline tilegx_bundle_bits
915create_Dest_X0(int num) 770create_Dest_X0(int num)
916{ 771{
917 const unsigned int n = (unsigned int)num; 772 const unsigned int n = (unsigned int)num;
918 return ((n & 0x3f) << 0); 773 return ((n & 0x3f) << 0);
919} 774}
920 775
921static __inline tile_bundle_bits 776static __inline tilegx_bundle_bits
922create_Dest_X1(int num) 777create_Dest_X1(int num)
923{ 778{
924 const unsigned int n = (unsigned int)num; 779 const unsigned int n = (unsigned int)num;
925 return (((tile_bundle_bits)(n & 0x3f)) << 31); 780 return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
926} 781}
927 782
928static __inline tile_bundle_bits 783static __inline tilegx_bundle_bits
929create_Dest_Y0(int num) 784create_Dest_Y0(int num)
930{ 785{
931 const unsigned int n = (unsigned int)num; 786 const unsigned int n = (unsigned int)num;
932 return ((n & 0x3f) << 0); 787 return ((n & 0x3f) << 0);
933} 788}
934 789
935static __inline tile_bundle_bits 790static __inline tilegx_bundle_bits
936create_Dest_Y1(int num) 791create_Dest_Y1(int num)
937{ 792{
938 const unsigned int n = (unsigned int)num; 793 const unsigned int n = (unsigned int)num;
939 return (((tile_bundle_bits)(n & 0x3f)) << 31); 794 return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
940} 795}
941 796
942static __inline tile_bundle_bits 797static __inline tilegx_bundle_bits
943create_Imm16_X0(int num) 798create_Imm16_X0(int num)
944{ 799{
945 const unsigned int n = (unsigned int)num; 800 const unsigned int n = (unsigned int)num;
946 return ((n & 0xffff) << 12); 801 return ((n & 0xffff) << 12);
947} 802}
948 803
949static __inline tile_bundle_bits 804static __inline tilegx_bundle_bits
950create_Imm16_X1(int num) 805create_Imm16_X1(int num)
951{ 806{
952 const unsigned int n = (unsigned int)num; 807 const unsigned int n = (unsigned int)num;
953 return (((tile_bundle_bits)(n & 0xffff)) << 43); 808 return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
954} 809}
955 810
956static __inline tile_bundle_bits 811static __inline tilegx_bundle_bits
957create_Imm8_SN(int num) 812create_Imm8OpcodeExtension_X0(int num)
958{ 813{
959 const unsigned int n = (unsigned int)num; 814 const unsigned int n = (unsigned int)num;
960 return ((n & 0xff) << 0); 815 return ((n & 0xff) << 20);
961} 816}
962 817
963static __inline tile_bundle_bits 818static __inline tilegx_bundle_bits
819create_Imm8OpcodeExtension_X1(int num)
820{
821 const unsigned int n = (unsigned int)num;
822 return (((tilegx_bundle_bits)(n & 0xff)) << 51);
823}
824
825static __inline tilegx_bundle_bits
964create_Imm8_X0(int num) 826create_Imm8_X0(int num)
965{ 827{
966 const unsigned int n = (unsigned int)num; 828 const unsigned int n = (unsigned int)num;
967 return ((n & 0xff) << 12); 829 return ((n & 0xff) << 12);
968} 830}
969 831
970static __inline tile_bundle_bits 832static __inline tilegx_bundle_bits
971create_Imm8_X1(int num) 833create_Imm8_X1(int num)
972{ 834{
973 const unsigned int n = (unsigned int)num; 835 const unsigned int n = (unsigned int)num;
974 return (((tile_bundle_bits)(n & 0xff)) << 43); 836 return (((tilegx_bundle_bits)(n & 0xff)) << 43);
975} 837}
976 838
977static __inline tile_bundle_bits 839static __inline tilegx_bundle_bits
978create_Imm8_Y0(int num) 840create_Imm8_Y0(int num)
979{ 841{
980 const unsigned int n = (unsigned int)num; 842 const unsigned int n = (unsigned int)num;
981 return ((n & 0xff) << 12); 843 return ((n & 0xff) << 12);
982} 844}
983 845
984static __inline tile_bundle_bits 846static __inline tilegx_bundle_bits
985create_Imm8_Y1(int num) 847create_Imm8_Y1(int num)
986{ 848{
987 const unsigned int n = (unsigned int)num; 849 const unsigned int n = (unsigned int)num;
988 return (((tile_bundle_bits)(n & 0xff)) << 43); 850 return (((tilegx_bundle_bits)(n & 0xff)) << 43);
989}
990
991static __inline tile_bundle_bits
992create_ImmOpcodeExtension_X0(int num)
993{
994 const unsigned int n = (unsigned int)num;
995 return ((n & 0x7f) << 20);
996}
997
998static __inline tile_bundle_bits
999create_ImmOpcodeExtension_X1(int num)
1000{
1001 const unsigned int n = (unsigned int)num;
1002 return (((tile_bundle_bits)(n & 0x7f)) << 51);
1003}
1004
1005static __inline tile_bundle_bits
1006create_ImmRROpcodeExtension_SN(int num)
1007{
1008 const unsigned int n = (unsigned int)num;
1009 return ((n & 0x3) << 8);
1010}
1011
1012static __inline tile_bundle_bits
1013create_JOffLong_X1(int num)
1014{
1015 const unsigned int n = (unsigned int)num;
1016 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
1017 (((tile_bundle_bits)(n & 0x00018000)) << 20) |
1018 (((tile_bundle_bits)(n & 0x001e0000)) << 14) |
1019 (((tile_bundle_bits)(n & 0x07e00000)) << 16) |
1020 (((tile_bundle_bits)(n & 0x18000000)) << 31);
1021}
1022
1023static __inline tile_bundle_bits
1024create_JOff_X1(int num)
1025{
1026 const unsigned int n = (unsigned int)num;
1027 return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
1028 (((tile_bundle_bits)(n & 0x00018000)) << 20) |
1029 (((tile_bundle_bits)(n & 0x001e0000)) << 14) |
1030 (((tile_bundle_bits)(n & 0x07e00000)) << 16) |
1031 (((tile_bundle_bits)(n & 0x08000000)) << 31);
1032}
1033
1034static __inline tile_bundle_bits
1035create_MF_Imm15_X1(int num)
1036{
1037 const unsigned int n = (unsigned int)num;
1038 return (((tile_bundle_bits)(n & 0x00003fff)) << 37) |
1039 (((tile_bundle_bits)(n & 0x00004000)) << 44);
1040} 851}
1041 852
1042static __inline tile_bundle_bits 853static __inline tilegx_bundle_bits
1043create_MMEnd_X0(int num) 854create_JumpOff_X1(int num)
1044{ 855{
1045 const unsigned int n = (unsigned int)num; 856 const unsigned int n = (unsigned int)num;
1046 return ((n & 0x1f) << 18); 857 return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
1047} 858}
1048 859
1049static __inline tile_bundle_bits 860static __inline tilegx_bundle_bits
1050create_MMEnd_X1(int num) 861create_JumpOpcodeExtension_X1(int num)
1051{ 862{
1052 const unsigned int n = (unsigned int)num; 863 const unsigned int n = (unsigned int)num;
1053 return (((tile_bundle_bits)(n & 0x1f)) << 49); 864 return (((tilegx_bundle_bits)(n & 0x1)) << 58);
1054} 865}
1055 866
1056static __inline tile_bundle_bits 867static __inline tilegx_bundle_bits
1057create_MMStart_X0(int num) 868create_MF_Imm14_X1(int num)
1058{ 869{
1059 const unsigned int n = (unsigned int)num; 870 const unsigned int n = (unsigned int)num;
1060 return ((n & 0x1f) << 23); 871 return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
1061} 872}
1062 873
1063static __inline tile_bundle_bits 874static __inline tilegx_bundle_bits
1064create_MMStart_X1(int num) 875create_MT_Imm14_X1(int num)
1065{ 876{
1066 const unsigned int n = (unsigned int)num; 877 const unsigned int n = (unsigned int)num;
1067 return (((tile_bundle_bits)(n & 0x1f)) << 54); 878 return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
879 (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
1068} 880}
1069 881
1070static __inline tile_bundle_bits 882static __inline tilegx_bundle_bits
1071create_MT_Imm15_X1(int num)
1072{
1073 const unsigned int n = (unsigned int)num;
1074 return (((tile_bundle_bits)(n & 0x0000003f)) << 31) |
1075 (((tile_bundle_bits)(n & 0x00003fc0)) << 37) |
1076 (((tile_bundle_bits)(n & 0x00004000)) << 44);
1077}
1078
1079static __inline tile_bundle_bits
1080create_Mode(int num) 883create_Mode(int num)
1081{ 884{
1082 const unsigned int n = (unsigned int)num; 885 const unsigned int n = (unsigned int)num;
1083 return (((tile_bundle_bits)(n & 0x1)) << 63); 886 return (((tilegx_bundle_bits)(n & 0x3)) << 62);
1084} 887}
1085 888
1086static __inline tile_bundle_bits 889static __inline tilegx_bundle_bits
1087create_NoRegOpcodeExtension_SN(int num)
1088{
1089 const unsigned int n = (unsigned int)num;
1090 return ((n & 0xf) << 0);
1091}
1092
1093static __inline tile_bundle_bits
1094create_Opcode_SN(int num)
1095{
1096 const unsigned int n = (unsigned int)num;
1097 return ((n & 0x3f) << 10);
1098}
1099
1100static __inline tile_bundle_bits
1101create_Opcode_X0(int num) 890create_Opcode_X0(int num)
1102{ 891{
1103 const unsigned int n = (unsigned int)num; 892 const unsigned int n = (unsigned int)num;
1104 return ((n & 0x7) << 28); 893 return ((n & 0x7) << 28);
1105} 894}
1106 895
1107static __inline tile_bundle_bits 896static __inline tilegx_bundle_bits
1108create_Opcode_X1(int num) 897create_Opcode_X1(int num)
1109{ 898{
1110 const unsigned int n = (unsigned int)num; 899 const unsigned int n = (unsigned int)num;
1111 return (((tile_bundle_bits)(n & 0xf)) << 59); 900 return (((tilegx_bundle_bits)(n & 0x7)) << 59);
1112} 901}
1113 902
1114static __inline tile_bundle_bits 903static __inline tilegx_bundle_bits
1115create_Opcode_Y0(int num) 904create_Opcode_Y0(int num)
1116{ 905{
1117 const unsigned int n = (unsigned int)num; 906 const unsigned int n = (unsigned int)num;
1118 return ((n & 0xf) << 27); 907 return ((n & 0xf) << 27);
1119} 908}
1120 909
1121static __inline tile_bundle_bits 910static __inline tilegx_bundle_bits
1122create_Opcode_Y1(int num) 911create_Opcode_Y1(int num)
1123{ 912{
1124 const unsigned int n = (unsigned int)num; 913 const unsigned int n = (unsigned int)num;
1125 return (((tile_bundle_bits)(n & 0xf)) << 59); 914 return (((tilegx_bundle_bits)(n & 0xf)) << 58);
1126} 915}
1127 916
1128static __inline tile_bundle_bits 917static __inline tilegx_bundle_bits
1129create_Opcode_Y2(int num) 918create_Opcode_Y2(int num)
1130{ 919{
1131 const unsigned int n = (unsigned int)num; 920 const unsigned int n = (unsigned int)num;
1132 return (((tile_bundle_bits)(n & 0x7)) << 56); 921 return ((n & 0x00000001) << 26) |
1133} 922 (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
1134
1135static __inline tile_bundle_bits
1136create_RROpcodeExtension_SN(int num)
1137{
1138 const unsigned int n = (unsigned int)num;
1139 return ((n & 0xf) << 4);
1140} 923}
1141 924
1142static __inline tile_bundle_bits 925static __inline tilegx_bundle_bits
1143create_RRROpcodeExtension_X0(int num) 926create_RRROpcodeExtension_X0(int num)
1144{ 927{
1145 const unsigned int n = (unsigned int)num; 928 const unsigned int n = (unsigned int)num;
1146 return ((n & 0x1ff) << 18); 929 return ((n & 0x3ff) << 18);
1147} 930}
1148 931
1149static __inline tile_bundle_bits 932static __inline tilegx_bundle_bits
1150create_RRROpcodeExtension_X1(int num) 933create_RRROpcodeExtension_X1(int num)
1151{ 934{
1152 const unsigned int n = (unsigned int)num; 935 const unsigned int n = (unsigned int)num;
1153 return (((tile_bundle_bits)(n & 0x1ff)) << 49); 936 return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
1154} 937}
1155 938
1156static __inline tile_bundle_bits 939static __inline tilegx_bundle_bits
1157create_RRROpcodeExtension_Y0(int num) 940create_RRROpcodeExtension_Y0(int num)
1158{ 941{
1159 const unsigned int n = (unsigned int)num; 942 const unsigned int n = (unsigned int)num;
1160 return ((n & 0x3) << 18); 943 return ((n & 0x3) << 18);
1161} 944}
1162 945
1163static __inline tile_bundle_bits 946static __inline tilegx_bundle_bits
1164create_RRROpcodeExtension_Y1(int num) 947create_RRROpcodeExtension_Y1(int num)
1165{ 948{
1166 const unsigned int n = (unsigned int)num; 949 const unsigned int n = (unsigned int)num;
1167 return (((tile_bundle_bits)(n & 0x3)) << 49); 950 return (((tilegx_bundle_bits)(n & 0x3)) << 49);
1168} 951}
1169 952
1170static __inline tile_bundle_bits 953static __inline tilegx_bundle_bits
1171create_RouteOpcodeExtension_SN(int num) 954create_ShAmt_X0(int num)
1172{ 955{
1173 const unsigned int n = (unsigned int)num; 956 const unsigned int n = (unsigned int)num;
1174 return ((n & 0x3ff) << 0); 957 return ((n & 0x3f) << 12);
1175} 958}
1176 959
1177static __inline tile_bundle_bits 960static __inline tilegx_bundle_bits
1178create_S_X0(int num) 961create_ShAmt_X1(int num)
1179{ 962{
1180 const unsigned int n = (unsigned int)num; 963 const unsigned int n = (unsigned int)num;
1181 return ((n & 0x1) << 27); 964 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1182} 965}
1183 966
1184static __inline tile_bundle_bits 967static __inline tilegx_bundle_bits
1185create_S_X1(int num) 968create_ShAmt_Y0(int num)
1186{ 969{
1187 const unsigned int n = (unsigned int)num; 970 const unsigned int n = (unsigned int)num;
1188 return (((tile_bundle_bits)(n & 0x1)) << 58); 971 return ((n & 0x3f) << 12);
1189} 972}
1190 973
1191static __inline tile_bundle_bits 974static __inline tilegx_bundle_bits
1192create_ShAmt_X0(int num) 975create_ShAmt_Y1(int num)
1193{ 976{
1194 const unsigned int n = (unsigned int)num; 977 const unsigned int n = (unsigned int)num;
1195 return ((n & 0x1f) << 12); 978 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1196} 979}
1197 980
1198static __inline tile_bundle_bits 981static __inline tilegx_bundle_bits
1199create_ShAmt_X1(int num) 982create_ShiftOpcodeExtension_X0(int num)
1200{ 983{
1201 const unsigned int n = (unsigned int)num; 984 const unsigned int n = (unsigned int)num;
1202 return (((tile_bundle_bits)(n & 0x1f)) << 43); 985 return ((n & 0x3ff) << 18);
1203} 986}
1204 987
1205static __inline tile_bundle_bits 988static __inline tilegx_bundle_bits
1206create_ShAmt_Y0(int num) 989create_ShiftOpcodeExtension_X1(int num)
1207{ 990{
1208 const unsigned int n = (unsigned int)num; 991 const unsigned int n = (unsigned int)num;
1209 return ((n & 0x1f) << 12); 992 return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
1210} 993}
1211 994
1212static __inline tile_bundle_bits 995static __inline tilegx_bundle_bits
1213create_ShAmt_Y1(int num) 996create_ShiftOpcodeExtension_Y0(int num)
1214{ 997{
1215 const unsigned int n = (unsigned int)num; 998 const unsigned int n = (unsigned int)num;
1216 return (((tile_bundle_bits)(n & 0x1f)) << 43); 999 return ((n & 0x3) << 18);
1217} 1000}
1218 1001
1219static __inline tile_bundle_bits 1002static __inline tilegx_bundle_bits
1003create_ShiftOpcodeExtension_Y1(int num)
1004{
1005 const unsigned int n = (unsigned int)num;
1006 return (((tilegx_bundle_bits)(n & 0x3)) << 49);
1007}
1008
1009static __inline tilegx_bundle_bits
1220create_SrcA_X0(int num) 1010create_SrcA_X0(int num)
1221{ 1011{
1222 const unsigned int n = (unsigned int)num; 1012 const unsigned int n = (unsigned int)num;
1223 return ((n & 0x3f) << 6); 1013 return ((n & 0x3f) << 6);
1224} 1014}
1225 1015
1226static __inline tile_bundle_bits 1016static __inline tilegx_bundle_bits
1227create_SrcA_X1(int num) 1017create_SrcA_X1(int num)
1228{ 1018{
1229 const unsigned int n = (unsigned int)num; 1019 const unsigned int n = (unsigned int)num;
1230 return (((tile_bundle_bits)(n & 0x3f)) << 37); 1020 return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
1231} 1021}
1232 1022
1233static __inline tile_bundle_bits 1023static __inline tilegx_bundle_bits
1234create_SrcA_Y0(int num) 1024create_SrcA_Y0(int num)
1235{ 1025{
1236 const unsigned int n = (unsigned int)num; 1026 const unsigned int n = (unsigned int)num;
1237 return ((n & 0x3f) << 6); 1027 return ((n & 0x3f) << 6);
1238} 1028}
1239 1029
1240static __inline tile_bundle_bits 1030static __inline tilegx_bundle_bits
1241create_SrcA_Y1(int num) 1031create_SrcA_Y1(int num)
1242{ 1032{
1243 const unsigned int n = (unsigned int)num; 1033 const unsigned int n = (unsigned int)num;
1244 return (((tile_bundle_bits)(n & 0x3f)) << 37); 1034 return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
1245} 1035}
1246 1036
1247static __inline tile_bundle_bits 1037static __inline tilegx_bundle_bits
1248create_SrcA_Y2(int num) 1038create_SrcA_Y2(int num)
1249{ 1039{
1250 const unsigned int n = (unsigned int)num; 1040 const unsigned int n = (unsigned int)num;
1251 return ((n & 0x00000001) << 26) | 1041 return ((n & 0x3f) << 20);
1252 (((tile_bundle_bits)(n & 0x0000003e)) << 50);
1253} 1042}
1254 1043
1255static __inline tile_bundle_bits 1044static __inline tilegx_bundle_bits
1256create_SrcBDest_Y2(int num) 1045create_SrcBDest_Y2(int num)
1257{ 1046{
1258 const unsigned int n = (unsigned int)num; 1047 const unsigned int n = (unsigned int)num;
1259 return ((n & 0x3f) << 20); 1048 return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
1260} 1049}
1261 1050
1262static __inline tile_bundle_bits 1051static __inline tilegx_bundle_bits
1263create_SrcB_X0(int num) 1052create_SrcB_X0(int num)
1264{ 1053{
1265 const unsigned int n = (unsigned int)num; 1054 const unsigned int n = (unsigned int)num;
1266 return ((n & 0x3f) << 12); 1055 return ((n & 0x3f) << 12);
1267} 1056}
1268 1057
1269static __inline tile_bundle_bits 1058static __inline tilegx_bundle_bits
1270create_SrcB_X1(int num) 1059create_SrcB_X1(int num)
1271{ 1060{
1272 const unsigned int n = (unsigned int)num; 1061 const unsigned int n = (unsigned int)num;
1273 return (((tile_bundle_bits)(n & 0x3f)) << 43); 1062 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1274} 1063}
1275 1064
1276static __inline tile_bundle_bits 1065static __inline tilegx_bundle_bits
1277create_SrcB_Y0(int num) 1066create_SrcB_Y0(int num)
1278{ 1067{
1279 const unsigned int n = (unsigned int)num; 1068 const unsigned int n = (unsigned int)num;
1280 return ((n & 0x3f) << 12); 1069 return ((n & 0x3f) << 12);
1281} 1070}
1282 1071
1283static __inline tile_bundle_bits 1072static __inline tilegx_bundle_bits
1284create_SrcB_Y1(int num) 1073create_SrcB_Y1(int num)
1285{ 1074{
1286 const unsigned int n = (unsigned int)num; 1075 const unsigned int n = (unsigned int)num;
1287 return (((tile_bundle_bits)(n & 0x3f)) << 43); 1076 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1288} 1077}
1289 1078
1290static __inline tile_bundle_bits 1079static __inline tilegx_bundle_bits
1291create_Src_SN(int num) 1080create_UnaryOpcodeExtension_X0(int num)
1292{ 1081{
1293 const unsigned int n = (unsigned int)num; 1082 const unsigned int n = (unsigned int)num;
1294 return ((n & 0x3) << 0); 1083 return ((n & 0x3f) << 12);
1295}
1296
1297static __inline tile_bundle_bits
1298create_UnOpcodeExtension_X0(int num)
1299{
1300 const unsigned int n = (unsigned int)num;
1301 return ((n & 0x1f) << 12);
1302}
1303
1304static __inline tile_bundle_bits
1305create_UnOpcodeExtension_X1(int num)
1306{
1307 const unsigned int n = (unsigned int)num;
1308 return (((tile_bundle_bits)(n & 0x1f)) << 43);
1309}
1310
1311static __inline tile_bundle_bits
1312create_UnOpcodeExtension_Y0(int num)
1313{
1314 const unsigned int n = (unsigned int)num;
1315 return ((n & 0x1f) << 12);
1316}
1317
1318static __inline tile_bundle_bits
1319create_UnOpcodeExtension_Y1(int num)
1320{
1321 const unsigned int n = (unsigned int)num;
1322 return (((tile_bundle_bits)(n & 0x1f)) << 43);
1323}
1324
1325static __inline tile_bundle_bits
1326create_UnShOpcodeExtension_X0(int num)
1327{
1328 const unsigned int n = (unsigned int)num;
1329 return ((n & 0x3ff) << 17);
1330} 1084}
1331 1085
1332static __inline tile_bundle_bits 1086static __inline tilegx_bundle_bits
1333create_UnShOpcodeExtension_X1(int num) 1087create_UnaryOpcodeExtension_X1(int num)
1334{ 1088{
1335 const unsigned int n = (unsigned int)num; 1089 const unsigned int n = (unsigned int)num;
1336 return (((tile_bundle_bits)(n & 0x3ff)) << 48); 1090 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1337} 1091}
1338 1092
1339static __inline tile_bundle_bits 1093static __inline tilegx_bundle_bits
1340create_UnShOpcodeExtension_Y0(int num) 1094create_UnaryOpcodeExtension_Y0(int num)
1341{ 1095{
1342 const unsigned int n = (unsigned int)num; 1096 const unsigned int n = (unsigned int)num;
1343 return ((n & 0x7) << 17); 1097 return ((n & 0x3f) << 12);
1344} 1098}
1345 1099
1346static __inline tile_bundle_bits 1100static __inline tilegx_bundle_bits
1347create_UnShOpcodeExtension_Y1(int num) 1101create_UnaryOpcodeExtension_Y1(int num)
1348{ 1102{
1349 const unsigned int n = (unsigned int)num; 1103 const unsigned int n = (unsigned int)num;
1350 return (((tile_bundle_bits)(n & 0x7)) << 48); 1104 return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
1351} 1105}
1352 1106
1353 1107
1354
1355typedef enum 1108typedef enum
1356{ 1109{
1357 TILE_PIPELINE_X0, 1110 TILEGX_PIPELINE_X0,
1358 TILE_PIPELINE_X1, 1111 TILEGX_PIPELINE_X1,
1359 TILE_PIPELINE_Y0, 1112 TILEGX_PIPELINE_Y0,
1360 TILE_PIPELINE_Y1, 1113 TILEGX_PIPELINE_Y1,
1361 TILE_PIPELINE_Y2, 1114 TILEGX_PIPELINE_Y2,
1362} tile_pipeline; 1115} tilegx_pipeline;
1363 1116
1364#define tile_is_x_pipeline(p) ((int)(p) <= (int)TILE_PIPELINE_X1) 1117#define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1)
1365 1118
1366typedef enum 1119typedef enum
1367{ 1120{
1368 TILE_OP_TYPE_REGISTER, 1121 TILEGX_OP_TYPE_REGISTER,
1369 TILE_OP_TYPE_IMMEDIATE, 1122 TILEGX_OP_TYPE_IMMEDIATE,
1370 TILE_OP_TYPE_ADDRESS, 1123 TILEGX_OP_TYPE_ADDRESS,
1371 TILE_OP_TYPE_SPR 1124 TILEGX_OP_TYPE_SPR
1372} tile_operand_type; 1125} tilegx_operand_type;
1373 1126
1374/* This is the bit that determines if a bundle is in the Y encoding. */ 1127/* These are the bits that determine if a bundle is in the X encoding. */
1375#define TILE_BUNDLE_Y_ENCODING_MASK ((tile_bundle_bits)1 << 63) 1128#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
1376 1129
1377enum 1130enum
1378{ 1131{
1379 /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ 1132 /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
1380 TILE_MAX_INSTRUCTIONS_PER_BUNDLE = 3, 1133 TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
1381 1134
1382 /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ 1135 /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
1383 TILE_NUM_PIPELINE_ENCODINGS = 5, 1136 TILEGX_NUM_PIPELINE_ENCODINGS = 5,
1384 1137
1385 /* Log base 2 of TILE_BUNDLE_SIZE_IN_BYTES. */ 1138 /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
1386 TILE_LOG2_BUNDLE_SIZE_IN_BYTES = 3, 1139 TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
1387 1140
1388 /* Instructions take this many bytes. */ 1141 /* Instructions take this many bytes. */
1389 TILE_BUNDLE_SIZE_IN_BYTES = 1 << TILE_LOG2_BUNDLE_SIZE_IN_BYTES, 1142 TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
1390 1143
1391 /* Log base 2 of TILE_BUNDLE_ALIGNMENT_IN_BYTES. */ 1144 /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
1392 TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, 1145 TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
1393 1146
1394 /* Bundles should be aligned modulo this number of bytes. */ 1147 /* Bundles should be aligned modulo this number of bytes. */
1395 TILE_BUNDLE_ALIGNMENT_IN_BYTES = 1148 TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
1396 (1 << TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), 1149 (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
1397
1398 /* Log base 2 of TILE_SN_INSTRUCTION_SIZE_IN_BYTES. */
1399 TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1,
1400
1401 /* Static network instructions take this many bytes. */
1402 TILE_SN_INSTRUCTION_SIZE_IN_BYTES =
1403 (1 << TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES),
1404 1150
1405 /* Number of registers (some are magic, such as network I/O). */ 1151 /* Number of registers (some are magic, such as network I/O). */
1406 TILE_NUM_REGISTERS = 64, 1152 TILEGX_NUM_REGISTERS = 64,
1407
1408 /* Number of static network registers. */
1409 TILE_NUM_SN_REGISTERS = 4
1410}; 1153};
1411 1154
1412 1155
1413struct tile_operand 1156struct tilegx_operand
1414{ 1157{
1415 /* Is this operand a register, immediate or address? */ 1158 /* Is this operand a register, immediate or address? */
1416 tile_operand_type type; 1159 tilegx_operand_type type;
1417 1160
1418 /* The default relocation type for this operand. */ 1161 /* The default relocation type for this operand. */
1419 signed int default_reloc : 16; 1162 signed int default_reloc : 16;
@@ -1437,27 +1180,27 @@ struct tile_operand
1437 unsigned int rightshift : 2; 1180 unsigned int rightshift : 2;
1438 1181
1439 /* Return the bits for this operand to be ORed into an existing bundle. */ 1182 /* Return the bits for this operand to be ORed into an existing bundle. */
1440 tile_bundle_bits (*insert) (int op); 1183 tilegx_bundle_bits (*insert) (int op);
1441 1184
1442 /* Extract this operand and return it. */ 1185 /* Extract this operand and return it. */
1443 unsigned int (*extract) (tile_bundle_bits bundle); 1186 unsigned int (*extract) (tilegx_bundle_bits bundle);
1444}; 1187};
1445 1188
1446 1189
1447extern const struct tile_operand tile_operands[]; 1190extern const struct tilegx_operand tilegx_operands[];
1448 1191
1449/* One finite-state machine per pipe for rapid instruction decoding. */ 1192/* One finite-state machine per pipe for rapid instruction decoding. */
1450extern const unsigned short * const 1193extern const unsigned short * const
1451tile_bundle_decoder_fsms[TILE_NUM_PIPELINE_ENCODINGS]; 1194tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS];
1452 1195
1453 1196
1454struct tile_opcode 1197struct tilegx_opcode
1455{ 1198{
1456 /* The opcode mnemonic, e.g. "add" */ 1199 /* The opcode mnemonic, e.g. "add" */
1457 const char *name; 1200 const char *name;
1458 1201
1459 /* The enum value for this mnemonic. */ 1202 /* The enum value for this mnemonic. */
1460 tile_mnemonic mnemonic; 1203 tilegx_mnemonic mnemonic;
1461 1204
1462 /* A bit mask of which of the five pipes this instruction 1205 /* A bit mask of which of the five pipes this instruction
1463 is compatible with: 1206 is compatible with:
@@ -1478,29 +1221,28 @@ struct tile_opcode
1478 unsigned char can_bundle; 1221 unsigned char can_bundle;
1479 1222
1480 /* The description of the operands. Each of these is an 1223 /* The description of the operands. Each of these is an
1481 * index into the tile_operands[] table. */ 1224 * index into the tilegx_operands[] table. */
1482 unsigned char operands[TILE_NUM_PIPELINE_ENCODINGS][TILE_MAX_OPERANDS]; 1225 unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS];
1483 1226
1484}; 1227};
1485 1228
1486extern const struct tile_opcode tile_opcodes[]; 1229extern const struct tilegx_opcode tilegx_opcodes[];
1487
1488 1230
1489/* Used for non-textual disassembly into structs. */ 1231/* Used for non-textual disassembly into structs. */
1490struct tile_decoded_instruction 1232struct tilegx_decoded_instruction
1491{ 1233{
1492 const struct tile_opcode *opcode; 1234 const struct tilegx_opcode *opcode;
1493 const struct tile_operand *operands[TILE_MAX_OPERANDS]; 1235 const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS];
1494 int operand_values[TILE_MAX_OPERANDS]; 1236 long long operand_values[TILEGX_MAX_OPERANDS];
1495}; 1237};
1496 1238
1497 1239
1498/* Disassemble a bundle into a struct for machine processing. */ 1240/* Disassemble a bundle into a struct for machine processing. */
1499extern int parse_insn_tile(tile_bundle_bits bits, 1241extern int parse_insn_tilegx(tilegx_bundle_bits bits,
1500 unsigned int pc, 1242 unsigned long long pc,
1501 struct tile_decoded_instruction 1243 struct tilegx_decoded_instruction
1502 decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]); 1244 decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]);
1503 1245
1504 1246
1505 1247
1506#endif /* opcode_tile_h */ 1248#endif /* opcode_tilegx_h */
diff --git a/arch/tile/include/asm/opcode_constants_64.h b/arch/tile/include/asm/opcode_constants_64.h
index 227d033b180c..710192869476 100644
--- a/arch/tile/include/asm/opcode_constants_64.h
+++ b/arch/tile/include/asm/opcode_constants_64.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved. 2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
@@ -19,462 +19,591 @@
19#define _TILE_OPCODE_CONSTANTS_H 19#define _TILE_OPCODE_CONSTANTS_H
20enum 20enum
21{ 21{
22 ADDBS_U_SPECIAL_0_OPCODE_X0 = 98, 22 ADDI_IMM8_OPCODE_X0 = 1,
23 ADDBS_U_SPECIAL_0_OPCODE_X1 = 68, 23 ADDI_IMM8_OPCODE_X1 = 1,
24 ADDB_SPECIAL_0_OPCODE_X0 = 1, 24 ADDI_OPCODE_Y0 = 0,
25 ADDB_SPECIAL_0_OPCODE_X1 = 1, 25 ADDI_OPCODE_Y1 = 1,
26 ADDHS_SPECIAL_0_OPCODE_X0 = 99, 26 ADDLI_OPCODE_X0 = 1,
27 ADDHS_SPECIAL_0_OPCODE_X1 = 69, 27 ADDLI_OPCODE_X1 = 0,
28 ADDH_SPECIAL_0_OPCODE_X0 = 2, 28 ADDXI_IMM8_OPCODE_X0 = 2,
29 ADDH_SPECIAL_0_OPCODE_X1 = 2, 29 ADDXI_IMM8_OPCODE_X1 = 2,
30 ADDIB_IMM_0_OPCODE_X0 = 1, 30 ADDXI_OPCODE_Y0 = 1,
31 ADDIB_IMM_0_OPCODE_X1 = 1, 31 ADDXI_OPCODE_Y1 = 2,
32 ADDIH_IMM_0_OPCODE_X0 = 2, 32 ADDXLI_OPCODE_X0 = 2,
33 ADDIH_IMM_0_OPCODE_X1 = 2, 33 ADDXLI_OPCODE_X1 = 1,
34 ADDI_IMM_0_OPCODE_X0 = 3, 34 ADDXSC_RRR_0_OPCODE_X0 = 1,
35 ADDI_IMM_0_OPCODE_X1 = 3, 35 ADDXSC_RRR_0_OPCODE_X1 = 1,
36 ADDI_IMM_1_OPCODE_SN = 1, 36 ADDX_RRR_0_OPCODE_X0 = 2,
37 ADDI_OPCODE_Y0 = 9, 37 ADDX_RRR_0_OPCODE_X1 = 2,
38 ADDI_OPCODE_Y1 = 7, 38 ADDX_RRR_0_OPCODE_Y0 = 0,
39 ADDLIS_OPCODE_X0 = 1, 39 ADDX_SPECIAL_0_OPCODE_Y1 = 0,
40 ADDLIS_OPCODE_X1 = 2, 40 ADD_RRR_0_OPCODE_X0 = 3,
41 ADDLI_OPCODE_X0 = 2, 41 ADD_RRR_0_OPCODE_X1 = 3,
42 ADDLI_OPCODE_X1 = 3, 42 ADD_RRR_0_OPCODE_Y0 = 1,
43 ADDS_SPECIAL_0_OPCODE_X0 = 96, 43 ADD_SPECIAL_0_OPCODE_Y1 = 1,
44 ADDS_SPECIAL_0_OPCODE_X1 = 66, 44 ANDI_IMM8_OPCODE_X0 = 3,
45 ADD_SPECIAL_0_OPCODE_X0 = 3, 45 ANDI_IMM8_OPCODE_X1 = 3,
46 ADD_SPECIAL_0_OPCODE_X1 = 3, 46 ANDI_OPCODE_Y0 = 2,
47 ADD_SPECIAL_0_OPCODE_Y0 = 0, 47 ANDI_OPCODE_Y1 = 3,
48 ADD_SPECIAL_0_OPCODE_Y1 = 0, 48 AND_RRR_0_OPCODE_X0 = 4,
49 ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4, 49 AND_RRR_0_OPCODE_X1 = 4,
50 ADIFFH_SPECIAL_0_OPCODE_X0 = 5, 50 AND_RRR_5_OPCODE_Y0 = 0,
51 ANDI_IMM_0_OPCODE_X0 = 1, 51 AND_RRR_5_OPCODE_Y1 = 0,
52 ANDI_IMM_0_OPCODE_X1 = 4, 52 BEQZT_BRANCH_OPCODE_X1 = 16,
53 ANDI_OPCODE_Y0 = 10, 53 BEQZ_BRANCH_OPCODE_X1 = 17,
54 ANDI_OPCODE_Y1 = 8, 54 BFEXTS_BF_OPCODE_X0 = 4,
55 AND_SPECIAL_0_OPCODE_X0 = 6, 55 BFEXTU_BF_OPCODE_X0 = 5,
56 AND_SPECIAL_0_OPCODE_X1 = 4, 56 BFINS_BF_OPCODE_X0 = 6,
57 AND_SPECIAL_2_OPCODE_Y0 = 0, 57 BF_OPCODE_X0 = 3,
58 AND_SPECIAL_2_OPCODE_Y1 = 0, 58 BGEZT_BRANCH_OPCODE_X1 = 18,
59 AULI_OPCODE_X0 = 3, 59 BGEZ_BRANCH_OPCODE_X1 = 19,
60 AULI_OPCODE_X1 = 4, 60 BGTZT_BRANCH_OPCODE_X1 = 20,
61 AVGB_U_SPECIAL_0_OPCODE_X0 = 7, 61 BGTZ_BRANCH_OPCODE_X1 = 21,
62 AVGH_SPECIAL_0_OPCODE_X0 = 8, 62 BLBCT_BRANCH_OPCODE_X1 = 22,
63 BBNST_BRANCH_OPCODE_X1 = 15, 63 BLBC_BRANCH_OPCODE_X1 = 23,
64 BBNS_BRANCH_OPCODE_X1 = 14, 64 BLBST_BRANCH_OPCODE_X1 = 24,
65 BBNS_OPCODE_SN = 63, 65 BLBS_BRANCH_OPCODE_X1 = 25,
66 BBST_BRANCH_OPCODE_X1 = 13, 66 BLEZT_BRANCH_OPCODE_X1 = 26,
67 BBS_BRANCH_OPCODE_X1 = 12, 67 BLEZ_BRANCH_OPCODE_X1 = 27,
68 BBS_OPCODE_SN = 62, 68 BLTZT_BRANCH_OPCODE_X1 = 28,
69 BGEZT_BRANCH_OPCODE_X1 = 7, 69 BLTZ_BRANCH_OPCODE_X1 = 29,
70 BGEZ_BRANCH_OPCODE_X1 = 6, 70 BNEZT_BRANCH_OPCODE_X1 = 30,
71 BGEZ_OPCODE_SN = 61, 71 BNEZ_BRANCH_OPCODE_X1 = 31,
72 BGZT_BRANCH_OPCODE_X1 = 5, 72 BRANCH_OPCODE_X1 = 2,
73 BGZ_BRANCH_OPCODE_X1 = 4, 73 CMOVEQZ_RRR_0_OPCODE_X0 = 5,
74 BGZ_OPCODE_SN = 58, 74 CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
75 BITX_UN_0_SHUN_0_OPCODE_X0 = 1, 75 CMOVNEZ_RRR_0_OPCODE_X0 = 6,
76 BITX_UN_0_SHUN_0_OPCODE_Y0 = 1, 76 CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
77 BLEZT_BRANCH_OPCODE_X1 = 11, 77 CMPEQI_IMM8_OPCODE_X0 = 4,
78 BLEZ_BRANCH_OPCODE_X1 = 10, 78 CMPEQI_IMM8_OPCODE_X1 = 4,
79 BLEZ_OPCODE_SN = 59, 79 CMPEQI_OPCODE_Y0 = 3,
80 BLZT_BRANCH_OPCODE_X1 = 9, 80 CMPEQI_OPCODE_Y1 = 4,
81 BLZ_BRANCH_OPCODE_X1 = 8, 81 CMPEQ_RRR_0_OPCODE_X0 = 7,
82 BLZ_OPCODE_SN = 60, 82 CMPEQ_RRR_0_OPCODE_X1 = 5,
83 BNZT_BRANCH_OPCODE_X1 = 3, 83 CMPEQ_RRR_3_OPCODE_Y0 = 0,
84 BNZ_BRANCH_OPCODE_X1 = 2, 84 CMPEQ_RRR_3_OPCODE_Y1 = 2,
85 BNZ_OPCODE_SN = 57, 85 CMPEXCH4_RRR_0_OPCODE_X1 = 6,
86 BPT_NOREG_RR_IMM_0_OPCODE_SN = 1, 86 CMPEXCH_RRR_0_OPCODE_X1 = 7,
87 BRANCH_OPCODE_X1 = 5, 87 CMPLES_RRR_0_OPCODE_X0 = 8,
88 BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2, 88 CMPLES_RRR_0_OPCODE_X1 = 8,
89 BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2, 89 CMPLES_RRR_2_OPCODE_Y0 = 0,
90 BZT_BRANCH_OPCODE_X1 = 1, 90 CMPLES_RRR_2_OPCODE_Y1 = 0,
91 BZ_BRANCH_OPCODE_X1 = 0, 91 CMPLEU_RRR_0_OPCODE_X0 = 9,
92 BZ_OPCODE_SN = 56, 92 CMPLEU_RRR_0_OPCODE_X1 = 9,
93 CLZ_UN_0_SHUN_0_OPCODE_X0 = 3, 93 CMPLEU_RRR_2_OPCODE_Y0 = 1,
94 CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3, 94 CMPLEU_RRR_2_OPCODE_Y1 = 1,
95 CRC32_32_SPECIAL_0_OPCODE_X0 = 9, 95 CMPLTSI_IMM8_OPCODE_X0 = 5,
96 CRC32_8_SPECIAL_0_OPCODE_X0 = 10, 96 CMPLTSI_IMM8_OPCODE_X1 = 5,
97 CTZ_UN_0_SHUN_0_OPCODE_X0 = 4, 97 CMPLTSI_OPCODE_Y0 = 4,
98 CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4, 98 CMPLTSI_OPCODE_Y1 = 5,
99 DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1, 99 CMPLTS_RRR_0_OPCODE_X0 = 10,
100 DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2, 100 CMPLTS_RRR_0_OPCODE_X1 = 10,
101 DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95, 101 CMPLTS_RRR_2_OPCODE_Y0 = 2,
102 FINV_UN_0_SHUN_0_OPCODE_X1 = 3, 102 CMPLTS_RRR_2_OPCODE_Y1 = 2,
103 FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4, 103 CMPLTUI_IMM8_OPCODE_X0 = 6,
104 FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3, 104 CMPLTUI_IMM8_OPCODE_X1 = 6,
105 FNOP_UN_0_SHUN_0_OPCODE_X0 = 5, 105 CMPLTU_RRR_0_OPCODE_X0 = 11,
106 FNOP_UN_0_SHUN_0_OPCODE_X1 = 5, 106 CMPLTU_RRR_0_OPCODE_X1 = 11,
107 FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5, 107 CMPLTU_RRR_2_OPCODE_Y0 = 3,
108 FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1, 108 CMPLTU_RRR_2_OPCODE_Y1 = 3,
109 HALT_NOREG_RR_IMM_0_OPCODE_SN = 0, 109 CMPNE_RRR_0_OPCODE_X0 = 12,
110 ICOH_UN_0_SHUN_0_OPCODE_X1 = 6, 110 CMPNE_RRR_0_OPCODE_X1 = 12,
111 ILL_UN_0_SHUN_0_OPCODE_X1 = 7, 111 CMPNE_RRR_3_OPCODE_Y0 = 1,
112 ILL_UN_0_SHUN_0_OPCODE_Y1 = 2, 112 CMPNE_RRR_3_OPCODE_Y1 = 3,
113 IMM_0_OPCODE_SN = 0, 113 CMULAF_RRR_0_OPCODE_X0 = 13,
114 IMM_0_OPCODE_X0 = 4, 114 CMULA_RRR_0_OPCODE_X0 = 14,
115 IMM_0_OPCODE_X1 = 6, 115 CMULFR_RRR_0_OPCODE_X0 = 15,
116 IMM_1_OPCODE_SN = 1, 116 CMULF_RRR_0_OPCODE_X0 = 16,
117 IMM_OPCODE_0_X0 = 5, 117 CMULHR_RRR_0_OPCODE_X0 = 17,
118 INTHB_SPECIAL_0_OPCODE_X0 = 11, 118 CMULH_RRR_0_OPCODE_X0 = 18,
119 INTHB_SPECIAL_0_OPCODE_X1 = 5, 119 CMUL_RRR_0_OPCODE_X0 = 19,
120 INTHH_SPECIAL_0_OPCODE_X0 = 12, 120 CNTLZ_UNARY_OPCODE_X0 = 1,
121 INTHH_SPECIAL_0_OPCODE_X1 = 6, 121 CNTLZ_UNARY_OPCODE_Y0 = 1,
122 INTLB_SPECIAL_0_OPCODE_X0 = 13, 122 CNTTZ_UNARY_OPCODE_X0 = 2,
123 INTLB_SPECIAL_0_OPCODE_X1 = 7, 123 CNTTZ_UNARY_OPCODE_Y0 = 2,
124 INTLH_SPECIAL_0_OPCODE_X0 = 14, 124 CRC32_32_RRR_0_OPCODE_X0 = 20,
125 INTLH_SPECIAL_0_OPCODE_X1 = 8, 125 CRC32_8_RRR_0_OPCODE_X0 = 21,
126 INV_UN_0_SHUN_0_OPCODE_X1 = 8, 126 DBLALIGN2_RRR_0_OPCODE_X0 = 22,
127 IRET_UN_0_SHUN_0_OPCODE_X1 = 9, 127 DBLALIGN2_RRR_0_OPCODE_X1 = 13,
128 JALB_OPCODE_X1 = 13, 128 DBLALIGN4_RRR_0_OPCODE_X0 = 23,
129 JALF_OPCODE_X1 = 12, 129 DBLALIGN4_RRR_0_OPCODE_X1 = 14,
130 JALRP_SPECIAL_0_OPCODE_X1 = 9, 130 DBLALIGN6_RRR_0_OPCODE_X0 = 24,
131 JALRR_IMM_1_OPCODE_SN = 3, 131 DBLALIGN6_RRR_0_OPCODE_X1 = 15,
132 JALR_RR_IMM_0_OPCODE_SN = 5, 132 DBLALIGN_RRR_0_OPCODE_X0 = 25,
133 JALR_SPECIAL_0_OPCODE_X1 = 10, 133 DRAIN_UNARY_OPCODE_X1 = 1,
134 JB_OPCODE_X1 = 11, 134 DTLBPR_UNARY_OPCODE_X1 = 2,
135 JF_OPCODE_X1 = 10, 135 EXCH4_RRR_0_OPCODE_X1 = 16,
136 JRP_SPECIAL_0_OPCODE_X1 = 11, 136 EXCH_RRR_0_OPCODE_X1 = 17,
137 JRR_IMM_1_OPCODE_SN = 2, 137 FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
138 JR_RR_IMM_0_OPCODE_SN = 4, 138 FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
139 JR_SPECIAL_0_OPCODE_X1 = 12, 139 FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
140 LBADD_IMM_0_OPCODE_X1 = 22, 140 FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
141 LBADD_U_IMM_0_OPCODE_X1 = 23, 141 FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
142 LB_OPCODE_Y2 = 0, 142 FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
143 LB_UN_0_SHUN_0_OPCODE_X1 = 10, 143 FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
144 LB_U_OPCODE_Y2 = 1, 144 FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
145 LB_U_UN_0_SHUN_0_OPCODE_X1 = 11, 145 FETCHADD4_RRR_0_OPCODE_X1 = 18,
146 LHADD_IMM_0_OPCODE_X1 = 24, 146 FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
147 LHADD_U_IMM_0_OPCODE_X1 = 25, 147 FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
148 LH_OPCODE_Y2 = 2, 148 FETCHADD_RRR_0_OPCODE_X1 = 21,
149 LH_UN_0_SHUN_0_OPCODE_X1 = 12, 149 FETCHAND4_RRR_0_OPCODE_X1 = 22,
150 LH_U_OPCODE_Y2 = 3, 150 FETCHAND_RRR_0_OPCODE_X1 = 23,
151 LH_U_UN_0_SHUN_0_OPCODE_X1 = 13, 151 FETCHOR4_RRR_0_OPCODE_X1 = 24,
152 LNK_SPECIAL_0_OPCODE_X1 = 13, 152 FETCHOR_RRR_0_OPCODE_X1 = 25,
153 LWADD_IMM_0_OPCODE_X1 = 26, 153 FINV_UNARY_OPCODE_X1 = 3,
154 LWADD_NA_IMM_0_OPCODE_X1 = 27, 154 FLUSHWB_UNARY_OPCODE_X1 = 4,
155 LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24, 155 FLUSH_UNARY_OPCODE_X1 = 5,
156 LW_OPCODE_Y2 = 4, 156 FNOP_UNARY_OPCODE_X0 = 3,
157 LW_UN_0_SHUN_0_OPCODE_X1 = 14, 157 FNOP_UNARY_OPCODE_X1 = 6,
158 MAXB_U_SPECIAL_0_OPCODE_X0 = 15, 158 FNOP_UNARY_OPCODE_Y0 = 3,
159 MAXB_U_SPECIAL_0_OPCODE_X1 = 14, 159 FNOP_UNARY_OPCODE_Y1 = 8,
160 MAXH_SPECIAL_0_OPCODE_X0 = 16, 160 FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
161 MAXH_SPECIAL_0_OPCODE_X1 = 15, 161 FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
162 MAXIB_U_IMM_0_OPCODE_X0 = 4, 162 FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
163 MAXIB_U_IMM_0_OPCODE_X1 = 5, 163 FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
164 MAXIH_IMM_0_OPCODE_X0 = 5, 164 FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
165 MAXIH_IMM_0_OPCODE_X1 = 6, 165 FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
166 MFSPR_IMM_0_OPCODE_X1 = 7, 166 FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
167 MF_UN_0_SHUN_0_OPCODE_X1 = 15, 167 FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
168 MINB_U_SPECIAL_0_OPCODE_X0 = 17, 168 ICOH_UNARY_OPCODE_X1 = 7,
169 MINB_U_SPECIAL_0_OPCODE_X1 = 16, 169 ILL_UNARY_OPCODE_X1 = 8,
170 MINH_SPECIAL_0_OPCODE_X0 = 18, 170 ILL_UNARY_OPCODE_Y1 = 9,
171 MINH_SPECIAL_0_OPCODE_X1 = 17, 171 IMM8_OPCODE_X0 = 4,
172 MINIB_U_IMM_0_OPCODE_X0 = 6, 172 IMM8_OPCODE_X1 = 3,
173 MINIB_U_IMM_0_OPCODE_X1 = 8, 173 INV_UNARY_OPCODE_X1 = 9,
174 MINIH_IMM_0_OPCODE_X0 = 7, 174 IRET_UNARY_OPCODE_X1 = 10,
175 MINIH_IMM_0_OPCODE_X1 = 9, 175 JALRP_UNARY_OPCODE_X1 = 11,
176 MM_OPCODE_X0 = 6, 176 JALRP_UNARY_OPCODE_Y1 = 10,
177 MM_OPCODE_X1 = 7, 177 JALR_UNARY_OPCODE_X1 = 12,
178 MNZB_SPECIAL_0_OPCODE_X0 = 19, 178 JALR_UNARY_OPCODE_Y1 = 11,
179 MNZB_SPECIAL_0_OPCODE_X1 = 18, 179 JAL_JUMP_OPCODE_X1 = 0,
180 MNZH_SPECIAL_0_OPCODE_X0 = 20, 180 JRP_UNARY_OPCODE_X1 = 13,
181 MNZH_SPECIAL_0_OPCODE_X1 = 19, 181 JRP_UNARY_OPCODE_Y1 = 12,
182 MNZ_SPECIAL_0_OPCODE_X0 = 21, 182 JR_UNARY_OPCODE_X1 = 14,
183 MNZ_SPECIAL_0_OPCODE_X1 = 20, 183 JR_UNARY_OPCODE_Y1 = 13,
184 MNZ_SPECIAL_1_OPCODE_Y0 = 0, 184 JUMP_OPCODE_X1 = 4,
185 MNZ_SPECIAL_1_OPCODE_Y1 = 1, 185 J_JUMP_OPCODE_X1 = 1,
186 MOVEI_IMM_1_OPCODE_SN = 0, 186 LD1S_ADD_IMM8_OPCODE_X1 = 7,
187 MOVE_RR_IMM_0_OPCODE_SN = 8, 187 LD1S_OPCODE_Y2 = 0,
188 MTSPR_IMM_0_OPCODE_X1 = 10, 188 LD1S_UNARY_OPCODE_X1 = 15,
189 MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22, 189 LD1U_ADD_IMM8_OPCODE_X1 = 8,
190 MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0, 190 LD1U_OPCODE_Y2 = 1,
191 MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23, 191 LD1U_UNARY_OPCODE_X1 = 16,
192 MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24, 192 LD2S_ADD_IMM8_OPCODE_X1 = 9,
193 MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1, 193 LD2S_OPCODE_Y2 = 2,
194 MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25, 194 LD2S_UNARY_OPCODE_X1 = 17,
195 MULHH_SS_SPECIAL_0_OPCODE_X0 = 26, 195 LD2U_ADD_IMM8_OPCODE_X1 = 10,
196 MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0, 196 LD2U_OPCODE_Y2 = 3,
197 MULHH_SU_SPECIAL_0_OPCODE_X0 = 27, 197 LD2U_UNARY_OPCODE_X1 = 18,
198 MULHH_UU_SPECIAL_0_OPCODE_X0 = 28, 198 LD4S_ADD_IMM8_OPCODE_X1 = 11,
199 MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1, 199 LD4S_OPCODE_Y2 = 1,
200 MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29, 200 LD4S_UNARY_OPCODE_X1 = 19,
201 MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30, 201 LD4U_ADD_IMM8_OPCODE_X1 = 12,
202 MULHLA_US_SPECIAL_0_OPCODE_X0 = 31, 202 LD4U_OPCODE_Y2 = 2,
203 MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32, 203 LD4U_UNARY_OPCODE_X1 = 20,
204 MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33, 204 LDNA_UNARY_OPCODE_X1 = 21,
205 MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0, 205 LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
206 MULHL_SS_SPECIAL_0_OPCODE_X0 = 34, 206 LDNT1S_UNARY_OPCODE_X1 = 22,
207 MULHL_SU_SPECIAL_0_OPCODE_X0 = 35, 207 LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
208 MULHL_US_SPECIAL_0_OPCODE_X0 = 36, 208 LDNT1U_UNARY_OPCODE_X1 = 23,
209 MULHL_UU_SPECIAL_0_OPCODE_X0 = 37, 209 LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
210 MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38, 210 LDNT2S_UNARY_OPCODE_X1 = 24,
211 MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2, 211 LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
212 MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39, 212 LDNT2U_UNARY_OPCODE_X1 = 25,
213 MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40, 213 LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
214 MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3, 214 LDNT4S_UNARY_OPCODE_X1 = 26,
215 MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41, 215 LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
216 MULLL_SS_SPECIAL_0_OPCODE_X0 = 42, 216 LDNT4U_UNARY_OPCODE_X1 = 27,
217 MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2, 217 LDNT_ADD_IMM8_OPCODE_X1 = 19,
218 MULLL_SU_SPECIAL_0_OPCODE_X0 = 43, 218 LDNT_UNARY_OPCODE_X1 = 28,
219 MULLL_UU_SPECIAL_0_OPCODE_X0 = 44, 219 LD_ADD_IMM8_OPCODE_X1 = 20,
220 MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3, 220 LD_OPCODE_Y2 = 3,
221 MVNZ_SPECIAL_0_OPCODE_X0 = 45, 221 LD_UNARY_OPCODE_X1 = 29,
222 MVNZ_SPECIAL_1_OPCODE_Y0 = 1, 222 LNK_UNARY_OPCODE_X1 = 30,
223 MVZ_SPECIAL_0_OPCODE_X0 = 46, 223 LNK_UNARY_OPCODE_Y1 = 14,
224 MVZ_SPECIAL_1_OPCODE_Y0 = 2, 224 LWNA_ADD_IMM8_OPCODE_X1 = 21,
225 MZB_SPECIAL_0_OPCODE_X0 = 47, 225 MFSPR_IMM8_OPCODE_X1 = 22,
226 MZB_SPECIAL_0_OPCODE_X1 = 21, 226 MF_UNARY_OPCODE_X1 = 31,
227 MZH_SPECIAL_0_OPCODE_X0 = 48, 227 MM_BF_OPCODE_X0 = 7,
228 MZH_SPECIAL_0_OPCODE_X1 = 22, 228 MNZ_RRR_0_OPCODE_X0 = 40,
229 MZ_SPECIAL_0_OPCODE_X0 = 49, 229 MNZ_RRR_0_OPCODE_X1 = 26,
230 MZ_SPECIAL_0_OPCODE_X1 = 23, 230 MNZ_RRR_4_OPCODE_Y0 = 2,
231 MZ_SPECIAL_1_OPCODE_Y0 = 3, 231 MNZ_RRR_4_OPCODE_Y1 = 2,
232 MZ_SPECIAL_1_OPCODE_Y1 = 2, 232 MODE_OPCODE_YA2 = 1,
233 NAP_UN_0_SHUN_0_OPCODE_X1 = 16, 233 MODE_OPCODE_YB2 = 2,
234 NOP_NOREG_RR_IMM_0_OPCODE_SN = 2, 234 MODE_OPCODE_YC2 = 3,
235 NOP_UN_0_SHUN_0_OPCODE_X0 = 6, 235 MTSPR_IMM8_OPCODE_X1 = 23,
236 NOP_UN_0_SHUN_0_OPCODE_X1 = 17, 236 MULAX_RRR_0_OPCODE_X0 = 41,
237 NOP_UN_0_SHUN_0_OPCODE_Y0 = 6, 237 MULAX_RRR_3_OPCODE_Y0 = 2,
238 NOP_UN_0_SHUN_0_OPCODE_Y1 = 3, 238 MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
239 NOREG_RR_IMM_0_OPCODE_SN = 0, 239 MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
240 NOR_SPECIAL_0_OPCODE_X0 = 50, 240 MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
241 NOR_SPECIAL_0_OPCODE_X1 = 24, 241 MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
242 NOR_SPECIAL_2_OPCODE_Y0 = 1, 242 MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
243 NOR_SPECIAL_2_OPCODE_Y1 = 1, 243 MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
244 ORI_IMM_0_OPCODE_X0 = 8, 244 MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
245 ORI_IMM_0_OPCODE_X1 = 11, 245 MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
246 ORI_OPCODE_Y0 = 11, 246 MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
247 ORI_OPCODE_Y1 = 9, 247 MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
248 OR_SPECIAL_0_OPCODE_X0 = 51, 248 MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
249 OR_SPECIAL_0_OPCODE_X1 = 25, 249 MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
250 OR_SPECIAL_2_OPCODE_Y0 = 2, 250 MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
251 OR_SPECIAL_2_OPCODE_Y1 = 2, 251 MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
252 PACKBS_U_SPECIAL_0_OPCODE_X0 = 103, 252 MULX_RRR_0_OPCODE_X0 = 52,
253 PACKBS_U_SPECIAL_0_OPCODE_X1 = 73, 253 MULX_RRR_3_OPCODE_Y0 = 3,
254 PACKHB_SPECIAL_0_OPCODE_X0 = 52, 254 MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
255 PACKHB_SPECIAL_0_OPCODE_X1 = 26, 255 MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
256 PACKHS_SPECIAL_0_OPCODE_X0 = 102, 256 MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
257 PACKHS_SPECIAL_0_OPCODE_X1 = 72, 257 MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
258 PACKLB_SPECIAL_0_OPCODE_X0 = 53, 258 MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
259 PACKLB_SPECIAL_0_OPCODE_X1 = 27, 259 MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
260 PCNT_UN_0_SHUN_0_OPCODE_X0 = 7, 260 MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
261 PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7, 261 MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
262 RLI_SHUN_0_OPCODE_X0 = 1, 262 MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
263 RLI_SHUN_0_OPCODE_X1 = 1, 263 MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
264 RLI_SHUN_0_OPCODE_Y0 = 1, 264 MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
265 RLI_SHUN_0_OPCODE_Y1 = 1, 265 MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
266 RL_SPECIAL_0_OPCODE_X0 = 54, 266 MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
267 RL_SPECIAL_0_OPCODE_X1 = 28, 267 MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
268 RL_SPECIAL_3_OPCODE_Y0 = 0, 268 MZ_RRR_0_OPCODE_X0 = 63,
269 RL_SPECIAL_3_OPCODE_Y1 = 0, 269 MZ_RRR_0_OPCODE_X1 = 27,
270 RR_IMM_0_OPCODE_SN = 0, 270 MZ_RRR_4_OPCODE_Y0 = 3,
271 S1A_SPECIAL_0_OPCODE_X0 = 55, 271 MZ_RRR_4_OPCODE_Y1 = 3,
272 S1A_SPECIAL_0_OPCODE_X1 = 29, 272 NAP_UNARY_OPCODE_X1 = 32,
273 S1A_SPECIAL_0_OPCODE_Y0 = 1, 273 NOP_UNARY_OPCODE_X0 = 5,
274 S1A_SPECIAL_0_OPCODE_Y1 = 1, 274 NOP_UNARY_OPCODE_X1 = 33,
275 S2A_SPECIAL_0_OPCODE_X0 = 56, 275 NOP_UNARY_OPCODE_Y0 = 5,
276 S2A_SPECIAL_0_OPCODE_X1 = 30, 276 NOP_UNARY_OPCODE_Y1 = 15,
277 S2A_SPECIAL_0_OPCODE_Y0 = 2, 277 NOR_RRR_0_OPCODE_X0 = 64,
278 S2A_SPECIAL_0_OPCODE_Y1 = 2, 278 NOR_RRR_0_OPCODE_X1 = 28,
279 S3A_SPECIAL_0_OPCODE_X0 = 57, 279 NOR_RRR_5_OPCODE_Y0 = 1,
280 S3A_SPECIAL_0_OPCODE_X1 = 31, 280 NOR_RRR_5_OPCODE_Y1 = 1,
281 S3A_SPECIAL_5_OPCODE_Y0 = 1, 281 ORI_IMM8_OPCODE_X0 = 7,
282 S3A_SPECIAL_5_OPCODE_Y1 = 1, 282 ORI_IMM8_OPCODE_X1 = 24,
283 SADAB_U_SPECIAL_0_OPCODE_X0 = 58, 283 OR_RRR_0_OPCODE_X0 = 65,
284 SADAH_SPECIAL_0_OPCODE_X0 = 59, 284 OR_RRR_0_OPCODE_X1 = 29,
285 SADAH_U_SPECIAL_0_OPCODE_X0 = 60, 285 OR_RRR_5_OPCODE_Y0 = 2,
286 SADB_U_SPECIAL_0_OPCODE_X0 = 61, 286 OR_RRR_5_OPCODE_Y1 = 2,
287 SADH_SPECIAL_0_OPCODE_X0 = 62, 287 PCNT_UNARY_OPCODE_X0 = 6,
288 SADH_U_SPECIAL_0_OPCODE_X0 = 63, 288 PCNT_UNARY_OPCODE_Y0 = 6,
289 SBADD_IMM_0_OPCODE_X1 = 28, 289 REVBITS_UNARY_OPCODE_X0 = 7,
290 SB_OPCODE_Y2 = 5, 290 REVBITS_UNARY_OPCODE_Y0 = 7,
291 SB_SPECIAL_0_OPCODE_X1 = 32, 291 REVBYTES_UNARY_OPCODE_X0 = 8,
292 SEQB_SPECIAL_0_OPCODE_X0 = 64, 292 REVBYTES_UNARY_OPCODE_Y0 = 8,
293 SEQB_SPECIAL_0_OPCODE_X1 = 33, 293 ROTLI_SHIFT_OPCODE_X0 = 1,
294 SEQH_SPECIAL_0_OPCODE_X0 = 65, 294 ROTLI_SHIFT_OPCODE_X1 = 1,
295 SEQH_SPECIAL_0_OPCODE_X1 = 34, 295 ROTLI_SHIFT_OPCODE_Y0 = 0,
296 SEQIB_IMM_0_OPCODE_X0 = 9, 296 ROTLI_SHIFT_OPCODE_Y1 = 0,
297 SEQIB_IMM_0_OPCODE_X1 = 12, 297 ROTL_RRR_0_OPCODE_X0 = 66,
298 SEQIH_IMM_0_OPCODE_X0 = 10, 298 ROTL_RRR_0_OPCODE_X1 = 30,
299 SEQIH_IMM_0_OPCODE_X1 = 13, 299 ROTL_RRR_6_OPCODE_Y0 = 0,
300 SEQI_IMM_0_OPCODE_X0 = 11, 300 ROTL_RRR_6_OPCODE_Y1 = 0,
301 SEQI_IMM_0_OPCODE_X1 = 14, 301 RRR_0_OPCODE_X0 = 5,
302 SEQI_OPCODE_Y0 = 12, 302 RRR_0_OPCODE_X1 = 5,
303 SEQI_OPCODE_Y1 = 10, 303 RRR_0_OPCODE_Y0 = 5,
304 SEQ_SPECIAL_0_OPCODE_X0 = 66, 304 RRR_0_OPCODE_Y1 = 6,
305 SEQ_SPECIAL_0_OPCODE_X1 = 35, 305 RRR_1_OPCODE_Y0 = 6,
306 SEQ_SPECIAL_5_OPCODE_Y0 = 2, 306 RRR_1_OPCODE_Y1 = 7,
307 SEQ_SPECIAL_5_OPCODE_Y1 = 2, 307 RRR_2_OPCODE_Y0 = 7,
308 SHADD_IMM_0_OPCODE_X1 = 29, 308 RRR_2_OPCODE_Y1 = 8,
309 SHL8II_IMM_0_OPCODE_SN = 3, 309 RRR_3_OPCODE_Y0 = 8,
310 SHLB_SPECIAL_0_OPCODE_X0 = 67, 310 RRR_3_OPCODE_Y1 = 9,
311 SHLB_SPECIAL_0_OPCODE_X1 = 36, 311 RRR_4_OPCODE_Y0 = 9,
312 SHLH_SPECIAL_0_OPCODE_X0 = 68, 312 RRR_4_OPCODE_Y1 = 10,
313 SHLH_SPECIAL_0_OPCODE_X1 = 37, 313 RRR_5_OPCODE_Y0 = 10,
314 SHLIB_SHUN_0_OPCODE_X0 = 2, 314 RRR_5_OPCODE_Y1 = 11,
315 SHLIB_SHUN_0_OPCODE_X1 = 2, 315 RRR_6_OPCODE_Y0 = 11,
316 SHLIH_SHUN_0_OPCODE_X0 = 3, 316 RRR_6_OPCODE_Y1 = 12,
317 SHLIH_SHUN_0_OPCODE_X1 = 3, 317 RRR_7_OPCODE_Y0 = 12,
318 SHLI_SHUN_0_OPCODE_X0 = 4, 318 RRR_7_OPCODE_Y1 = 13,
319 SHLI_SHUN_0_OPCODE_X1 = 4, 319 RRR_8_OPCODE_Y0 = 13,
320 SHLI_SHUN_0_OPCODE_Y0 = 2, 320 RRR_9_OPCODE_Y0 = 14,
321 SHLI_SHUN_0_OPCODE_Y1 = 2, 321 SHIFT_OPCODE_X0 = 6,
322 SHL_SPECIAL_0_OPCODE_X0 = 69, 322 SHIFT_OPCODE_X1 = 6,
323 SHL_SPECIAL_0_OPCODE_X1 = 38, 323 SHIFT_OPCODE_Y0 = 15,
324 SHL_SPECIAL_3_OPCODE_Y0 = 1, 324 SHIFT_OPCODE_Y1 = 14,
325 SHL_SPECIAL_3_OPCODE_Y1 = 1, 325 SHL16INSLI_OPCODE_X0 = 7,
326 SHR1_RR_IMM_0_OPCODE_SN = 9, 326 SHL16INSLI_OPCODE_X1 = 7,
327 SHRB_SPECIAL_0_OPCODE_X0 = 70, 327 SHL1ADDX_RRR_0_OPCODE_X0 = 67,
328 SHRB_SPECIAL_0_OPCODE_X1 = 39, 328 SHL1ADDX_RRR_0_OPCODE_X1 = 31,
329 SHRH_SPECIAL_0_OPCODE_X0 = 71, 329 SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
330 SHRH_SPECIAL_0_OPCODE_X1 = 40, 330 SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
331 SHRIB_SHUN_0_OPCODE_X0 = 5, 331 SHL1ADD_RRR_0_OPCODE_X0 = 68,
332 SHRIB_SHUN_0_OPCODE_X1 = 5, 332 SHL1ADD_RRR_0_OPCODE_X1 = 32,
333 SHRIH_SHUN_0_OPCODE_X0 = 6, 333 SHL1ADD_RRR_1_OPCODE_Y0 = 0,
334 SHRIH_SHUN_0_OPCODE_X1 = 6, 334 SHL1ADD_RRR_1_OPCODE_Y1 = 0,
335 SHRI_SHUN_0_OPCODE_X0 = 7, 335 SHL2ADDX_RRR_0_OPCODE_X0 = 69,
336 SHRI_SHUN_0_OPCODE_X1 = 7, 336 SHL2ADDX_RRR_0_OPCODE_X1 = 33,
337 SHRI_SHUN_0_OPCODE_Y0 = 3, 337 SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
338 SHRI_SHUN_0_OPCODE_Y1 = 3, 338 SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
339 SHR_SPECIAL_0_OPCODE_X0 = 72, 339 SHL2ADD_RRR_0_OPCODE_X0 = 70,
340 SHR_SPECIAL_0_OPCODE_X1 = 41, 340 SHL2ADD_RRR_0_OPCODE_X1 = 34,
341 SHR_SPECIAL_3_OPCODE_Y0 = 2, 341 SHL2ADD_RRR_1_OPCODE_Y0 = 1,
342 SHR_SPECIAL_3_OPCODE_Y1 = 2, 342 SHL2ADD_RRR_1_OPCODE_Y1 = 1,
343 SHUN_0_OPCODE_X0 = 7, 343 SHL3ADDX_RRR_0_OPCODE_X0 = 71,
344 SHUN_0_OPCODE_X1 = 8, 344 SHL3ADDX_RRR_0_OPCODE_X1 = 35,
345 SHUN_0_OPCODE_Y0 = 13, 345 SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
346 SHUN_0_OPCODE_Y1 = 11, 346 SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
347 SH_OPCODE_Y2 = 6, 347 SHL3ADD_RRR_0_OPCODE_X0 = 72,
348 SH_SPECIAL_0_OPCODE_X1 = 42, 348 SHL3ADD_RRR_0_OPCODE_X1 = 36,
349 SLTB_SPECIAL_0_OPCODE_X0 = 73, 349 SHL3ADD_RRR_1_OPCODE_Y0 = 2,
350 SLTB_SPECIAL_0_OPCODE_X1 = 43, 350 SHL3ADD_RRR_1_OPCODE_Y1 = 2,
351 SLTB_U_SPECIAL_0_OPCODE_X0 = 74, 351 SHLI_SHIFT_OPCODE_X0 = 2,
352 SLTB_U_SPECIAL_0_OPCODE_X1 = 44, 352 SHLI_SHIFT_OPCODE_X1 = 2,
353 SLTEB_SPECIAL_0_OPCODE_X0 = 75, 353 SHLI_SHIFT_OPCODE_Y0 = 1,
354 SLTEB_SPECIAL_0_OPCODE_X1 = 45, 354 SHLI_SHIFT_OPCODE_Y1 = 1,
355 SLTEB_U_SPECIAL_0_OPCODE_X0 = 76, 355 SHLXI_SHIFT_OPCODE_X0 = 3,
356 SLTEB_U_SPECIAL_0_OPCODE_X1 = 46, 356 SHLXI_SHIFT_OPCODE_X1 = 3,
357 SLTEH_SPECIAL_0_OPCODE_X0 = 77, 357 SHLX_RRR_0_OPCODE_X0 = 73,
358 SLTEH_SPECIAL_0_OPCODE_X1 = 47, 358 SHLX_RRR_0_OPCODE_X1 = 37,
359 SLTEH_U_SPECIAL_0_OPCODE_X0 = 78, 359 SHL_RRR_0_OPCODE_X0 = 74,
360 SLTEH_U_SPECIAL_0_OPCODE_X1 = 48, 360 SHL_RRR_0_OPCODE_X1 = 38,
361 SLTE_SPECIAL_0_OPCODE_X0 = 79, 361 SHL_RRR_6_OPCODE_Y0 = 1,
362 SLTE_SPECIAL_0_OPCODE_X1 = 49, 362 SHL_RRR_6_OPCODE_Y1 = 1,
363 SLTE_SPECIAL_4_OPCODE_Y0 = 0, 363 SHRSI_SHIFT_OPCODE_X0 = 4,
364 SLTE_SPECIAL_4_OPCODE_Y1 = 0, 364 SHRSI_SHIFT_OPCODE_X1 = 4,
365 SLTE_U_SPECIAL_0_OPCODE_X0 = 80, 365 SHRSI_SHIFT_OPCODE_Y0 = 2,
366 SLTE_U_SPECIAL_0_OPCODE_X1 = 50, 366 SHRSI_SHIFT_OPCODE_Y1 = 2,
367 SLTE_U_SPECIAL_4_OPCODE_Y0 = 1, 367 SHRS_RRR_0_OPCODE_X0 = 75,
368 SLTE_U_SPECIAL_4_OPCODE_Y1 = 1, 368 SHRS_RRR_0_OPCODE_X1 = 39,
369 SLTH_SPECIAL_0_OPCODE_X0 = 81, 369 SHRS_RRR_6_OPCODE_Y0 = 2,
370 SLTH_SPECIAL_0_OPCODE_X1 = 51, 370 SHRS_RRR_6_OPCODE_Y1 = 2,
371 SLTH_U_SPECIAL_0_OPCODE_X0 = 82, 371 SHRUI_SHIFT_OPCODE_X0 = 5,
372 SLTH_U_SPECIAL_0_OPCODE_X1 = 52, 372 SHRUI_SHIFT_OPCODE_X1 = 5,
373 SLTIB_IMM_0_OPCODE_X0 = 12, 373 SHRUI_SHIFT_OPCODE_Y0 = 3,
374 SLTIB_IMM_0_OPCODE_X1 = 15, 374 SHRUI_SHIFT_OPCODE_Y1 = 3,
375 SLTIB_U_IMM_0_OPCODE_X0 = 13, 375 SHRUXI_SHIFT_OPCODE_X0 = 6,
376 SLTIB_U_IMM_0_OPCODE_X1 = 16, 376 SHRUXI_SHIFT_OPCODE_X1 = 6,
377 SLTIH_IMM_0_OPCODE_X0 = 14, 377 SHRUX_RRR_0_OPCODE_X0 = 76,
378 SLTIH_IMM_0_OPCODE_X1 = 17, 378 SHRUX_RRR_0_OPCODE_X1 = 40,
379 SLTIH_U_IMM_0_OPCODE_X0 = 15, 379 SHRU_RRR_0_OPCODE_X0 = 77,
380 SLTIH_U_IMM_0_OPCODE_X1 = 18, 380 SHRU_RRR_0_OPCODE_X1 = 41,
381 SLTI_IMM_0_OPCODE_X0 = 16, 381 SHRU_RRR_6_OPCODE_Y0 = 3,
382 SLTI_IMM_0_OPCODE_X1 = 19, 382 SHRU_RRR_6_OPCODE_Y1 = 3,
383 SLTI_OPCODE_Y0 = 14, 383 SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
384 SLTI_OPCODE_Y1 = 12, 384 ST1_ADD_IMM8_OPCODE_X1 = 25,
385 SLTI_U_IMM_0_OPCODE_X0 = 17, 385 ST1_OPCODE_Y2 = 0,
386 SLTI_U_IMM_0_OPCODE_X1 = 20, 386 ST1_RRR_0_OPCODE_X1 = 42,
387 SLTI_U_OPCODE_Y0 = 15, 387 ST2_ADD_IMM8_OPCODE_X1 = 26,
388 SLTI_U_OPCODE_Y1 = 13, 388 ST2_OPCODE_Y2 = 1,
389 SLT_SPECIAL_0_OPCODE_X0 = 83, 389 ST2_RRR_0_OPCODE_X1 = 43,
390 SLT_SPECIAL_0_OPCODE_X1 = 53, 390 ST4_ADD_IMM8_OPCODE_X1 = 27,
391 SLT_SPECIAL_4_OPCODE_Y0 = 2, 391 ST4_OPCODE_Y2 = 2,
392 SLT_SPECIAL_4_OPCODE_Y1 = 2, 392 ST4_RRR_0_OPCODE_X1 = 44,
393 SLT_U_SPECIAL_0_OPCODE_X0 = 84, 393 STNT1_ADD_IMM8_OPCODE_X1 = 28,
394 SLT_U_SPECIAL_0_OPCODE_X1 = 54, 394 STNT1_RRR_0_OPCODE_X1 = 45,
395 SLT_U_SPECIAL_4_OPCODE_Y0 = 3, 395 STNT2_ADD_IMM8_OPCODE_X1 = 29,
396 SLT_U_SPECIAL_4_OPCODE_Y1 = 3, 396 STNT2_RRR_0_OPCODE_X1 = 46,
397 SNEB_SPECIAL_0_OPCODE_X0 = 85, 397 STNT4_ADD_IMM8_OPCODE_X1 = 30,
398 SNEB_SPECIAL_0_OPCODE_X1 = 55, 398 STNT4_RRR_0_OPCODE_X1 = 47,
399 SNEH_SPECIAL_0_OPCODE_X0 = 86, 399 STNT_ADD_IMM8_OPCODE_X1 = 31,
400 SNEH_SPECIAL_0_OPCODE_X1 = 56, 400 STNT_RRR_0_OPCODE_X1 = 48,
401 SNE_SPECIAL_0_OPCODE_X0 = 87, 401 ST_ADD_IMM8_OPCODE_X1 = 32,
402 SNE_SPECIAL_0_OPCODE_X1 = 57, 402 ST_OPCODE_Y2 = 3,
403 SNE_SPECIAL_5_OPCODE_Y0 = 3, 403 ST_RRR_0_OPCODE_X1 = 49,
404 SNE_SPECIAL_5_OPCODE_Y1 = 3, 404 SUBXSC_RRR_0_OPCODE_X0 = 79,
405 SPECIAL_0_OPCODE_X0 = 0, 405 SUBXSC_RRR_0_OPCODE_X1 = 50,
406 SPECIAL_0_OPCODE_X1 = 1, 406 SUBX_RRR_0_OPCODE_X0 = 80,
407 SPECIAL_0_OPCODE_Y0 = 1, 407 SUBX_RRR_0_OPCODE_X1 = 51,
408 SPECIAL_0_OPCODE_Y1 = 1, 408 SUBX_RRR_0_OPCODE_Y0 = 2,
409 SPECIAL_1_OPCODE_Y0 = 2, 409 SUBX_RRR_0_OPCODE_Y1 = 2,
410 SPECIAL_1_OPCODE_Y1 = 2, 410 SUB_RRR_0_OPCODE_X0 = 81,
411 SPECIAL_2_OPCODE_Y0 = 3, 411 SUB_RRR_0_OPCODE_X1 = 52,
412 SPECIAL_2_OPCODE_Y1 = 3, 412 SUB_RRR_0_OPCODE_Y0 = 3,
413 SPECIAL_3_OPCODE_Y0 = 4, 413 SUB_RRR_0_OPCODE_Y1 = 3,
414 SPECIAL_3_OPCODE_Y1 = 4, 414 SWINT0_UNARY_OPCODE_X1 = 34,
415 SPECIAL_4_OPCODE_Y0 = 5, 415 SWINT1_UNARY_OPCODE_X1 = 35,
416 SPECIAL_4_OPCODE_Y1 = 5, 416 SWINT2_UNARY_OPCODE_X1 = 36,
417 SPECIAL_5_OPCODE_Y0 = 6, 417 SWINT3_UNARY_OPCODE_X1 = 37,
418 SPECIAL_5_OPCODE_Y1 = 6, 418 TBLIDXB0_UNARY_OPCODE_X0 = 9,
419 SPECIAL_6_OPCODE_Y0 = 7, 419 TBLIDXB0_UNARY_OPCODE_Y0 = 9,
420 SPECIAL_7_OPCODE_Y0 = 8, 420 TBLIDXB1_UNARY_OPCODE_X0 = 10,
421 SRAB_SPECIAL_0_OPCODE_X0 = 88, 421 TBLIDXB1_UNARY_OPCODE_Y0 = 10,
422 SRAB_SPECIAL_0_OPCODE_X1 = 58, 422 TBLIDXB2_UNARY_OPCODE_X0 = 11,
423 SRAH_SPECIAL_0_OPCODE_X0 = 89, 423 TBLIDXB2_UNARY_OPCODE_Y0 = 11,
424 SRAH_SPECIAL_0_OPCODE_X1 = 59, 424 TBLIDXB3_UNARY_OPCODE_X0 = 12,
425 SRAIB_SHUN_0_OPCODE_X0 = 8, 425 TBLIDXB3_UNARY_OPCODE_Y0 = 12,
426 SRAIB_SHUN_0_OPCODE_X1 = 8, 426 UNARY_RRR_0_OPCODE_X0 = 82,
427 SRAIH_SHUN_0_OPCODE_X0 = 9, 427 UNARY_RRR_0_OPCODE_X1 = 53,
428 SRAIH_SHUN_0_OPCODE_X1 = 9, 428 UNARY_RRR_1_OPCODE_Y0 = 3,
429 SRAI_SHUN_0_OPCODE_X0 = 10, 429 UNARY_RRR_1_OPCODE_Y1 = 3,
430 SRAI_SHUN_0_OPCODE_X1 = 10, 430 V1ADDI_IMM8_OPCODE_X0 = 8,
431 SRAI_SHUN_0_OPCODE_Y0 = 4, 431 V1ADDI_IMM8_OPCODE_X1 = 33,
432 SRAI_SHUN_0_OPCODE_Y1 = 4, 432 V1ADDUC_RRR_0_OPCODE_X0 = 83,
433 SRA_SPECIAL_0_OPCODE_X0 = 90, 433 V1ADDUC_RRR_0_OPCODE_X1 = 54,
434 SRA_SPECIAL_0_OPCODE_X1 = 60, 434 V1ADD_RRR_0_OPCODE_X0 = 84,
435 SRA_SPECIAL_3_OPCODE_Y0 = 3, 435 V1ADD_RRR_0_OPCODE_X1 = 55,
436 SRA_SPECIAL_3_OPCODE_Y1 = 3, 436 V1ADIFFU_RRR_0_OPCODE_X0 = 85,
437 SUBBS_U_SPECIAL_0_OPCODE_X0 = 100, 437 V1AVGU_RRR_0_OPCODE_X0 = 86,
438 SUBBS_U_SPECIAL_0_OPCODE_X1 = 70, 438 V1CMPEQI_IMM8_OPCODE_X0 = 9,
439 SUBB_SPECIAL_0_OPCODE_X0 = 91, 439 V1CMPEQI_IMM8_OPCODE_X1 = 34,
440 SUBB_SPECIAL_0_OPCODE_X1 = 61, 440 V1CMPEQ_RRR_0_OPCODE_X0 = 87,
441 SUBHS_SPECIAL_0_OPCODE_X0 = 101, 441 V1CMPEQ_RRR_0_OPCODE_X1 = 56,
442 SUBHS_SPECIAL_0_OPCODE_X1 = 71, 442 V1CMPLES_RRR_0_OPCODE_X0 = 88,
443 SUBH_SPECIAL_0_OPCODE_X0 = 92, 443 V1CMPLES_RRR_0_OPCODE_X1 = 57,
444 SUBH_SPECIAL_0_OPCODE_X1 = 62, 444 V1CMPLEU_RRR_0_OPCODE_X0 = 89,
445 SUBS_SPECIAL_0_OPCODE_X0 = 97, 445 V1CMPLEU_RRR_0_OPCODE_X1 = 58,
446 SUBS_SPECIAL_0_OPCODE_X1 = 67, 446 V1CMPLTSI_IMM8_OPCODE_X0 = 10,
447 SUB_SPECIAL_0_OPCODE_X0 = 93, 447 V1CMPLTSI_IMM8_OPCODE_X1 = 35,
448 SUB_SPECIAL_0_OPCODE_X1 = 63, 448 V1CMPLTS_RRR_0_OPCODE_X0 = 90,
449 SUB_SPECIAL_0_OPCODE_Y0 = 3, 449 V1CMPLTS_RRR_0_OPCODE_X1 = 59,
450 SUB_SPECIAL_0_OPCODE_Y1 = 3, 450 V1CMPLTUI_IMM8_OPCODE_X0 = 11,
451 SWADD_IMM_0_OPCODE_X1 = 30, 451 V1CMPLTUI_IMM8_OPCODE_X1 = 36,
452 SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18, 452 V1CMPLTU_RRR_0_OPCODE_X0 = 91,
453 SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19, 453 V1CMPLTU_RRR_0_OPCODE_X1 = 60,
454 SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20, 454 V1CMPNE_RRR_0_OPCODE_X0 = 92,
455 SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21, 455 V1CMPNE_RRR_0_OPCODE_X1 = 61,
456 SW_OPCODE_Y2 = 7, 456 V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
457 SW_SPECIAL_0_OPCODE_X1 = 64, 457 V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
458 TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8, 458 V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
459 TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8, 459 V1DDOTPU_RRR_0_OPCODE_X0 = 162,
460 TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9, 460 V1DOTPA_RRR_0_OPCODE_X0 = 95,
461 TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9, 461 V1DOTPUA_RRR_0_OPCODE_X0 = 163,
462 TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10, 462 V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
463 TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10, 463 V1DOTPUS_RRR_0_OPCODE_X0 = 97,
464 TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11, 464 V1DOTPU_RRR_0_OPCODE_X0 = 164,
465 TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11, 465 V1DOTP_RRR_0_OPCODE_X0 = 98,
466 TNS_UN_0_SHUN_0_OPCODE_X1 = 22, 466 V1INT_H_RRR_0_OPCODE_X0 = 99,
467 UN_0_SHUN_0_OPCODE_X0 = 11, 467 V1INT_H_RRR_0_OPCODE_X1 = 62,
468 UN_0_SHUN_0_OPCODE_X1 = 11, 468 V1INT_L_RRR_0_OPCODE_X0 = 100,
469 UN_0_SHUN_0_OPCODE_Y0 = 5, 469 V1INT_L_RRR_0_OPCODE_X1 = 63,
470 UN_0_SHUN_0_OPCODE_Y1 = 5, 470 V1MAXUI_IMM8_OPCODE_X0 = 12,
471 WH64_UN_0_SHUN_0_OPCODE_X1 = 23, 471 V1MAXUI_IMM8_OPCODE_X1 = 37,
472 XORI_IMM_0_OPCODE_X0 = 2, 472 V1MAXU_RRR_0_OPCODE_X0 = 101,
473 XORI_IMM_0_OPCODE_X1 = 21, 473 V1MAXU_RRR_0_OPCODE_X1 = 64,
474 XOR_SPECIAL_0_OPCODE_X0 = 94, 474 V1MINUI_IMM8_OPCODE_X0 = 13,
475 XOR_SPECIAL_0_OPCODE_X1 = 65, 475 V1MINUI_IMM8_OPCODE_X1 = 38,
476 XOR_SPECIAL_2_OPCODE_Y0 = 3, 476 V1MINU_RRR_0_OPCODE_X0 = 102,
477 XOR_SPECIAL_2_OPCODE_Y1 = 3 477 V1MINU_RRR_0_OPCODE_X1 = 65,
478 V1MNZ_RRR_0_OPCODE_X0 = 103,
479 V1MNZ_RRR_0_OPCODE_X1 = 66,
480 V1MULTU_RRR_0_OPCODE_X0 = 104,
481 V1MULUS_RRR_0_OPCODE_X0 = 105,
482 V1MULU_RRR_0_OPCODE_X0 = 106,
483 V1MZ_RRR_0_OPCODE_X0 = 107,
484 V1MZ_RRR_0_OPCODE_X1 = 67,
485 V1SADAU_RRR_0_OPCODE_X0 = 108,
486 V1SADU_RRR_0_OPCODE_X0 = 109,
487 V1SHLI_SHIFT_OPCODE_X0 = 7,
488 V1SHLI_SHIFT_OPCODE_X1 = 7,
489 V1SHL_RRR_0_OPCODE_X0 = 110,
490 V1SHL_RRR_0_OPCODE_X1 = 68,
491 V1SHRSI_SHIFT_OPCODE_X0 = 8,
492 V1SHRSI_SHIFT_OPCODE_X1 = 8,
493 V1SHRS_RRR_0_OPCODE_X0 = 111,
494 V1SHRS_RRR_0_OPCODE_X1 = 69,
495 V1SHRUI_SHIFT_OPCODE_X0 = 9,
496 V1SHRUI_SHIFT_OPCODE_X1 = 9,
497 V1SHRU_RRR_0_OPCODE_X0 = 112,
498 V1SHRU_RRR_0_OPCODE_X1 = 70,
499 V1SUBUC_RRR_0_OPCODE_X0 = 113,
500 V1SUBUC_RRR_0_OPCODE_X1 = 71,
501 V1SUB_RRR_0_OPCODE_X0 = 114,
502 V1SUB_RRR_0_OPCODE_X1 = 72,
503 V2ADDI_IMM8_OPCODE_X0 = 14,
504 V2ADDI_IMM8_OPCODE_X1 = 39,
505 V2ADDSC_RRR_0_OPCODE_X0 = 115,
506 V2ADDSC_RRR_0_OPCODE_X1 = 73,
507 V2ADD_RRR_0_OPCODE_X0 = 116,
508 V2ADD_RRR_0_OPCODE_X1 = 74,
509 V2ADIFFS_RRR_0_OPCODE_X0 = 117,
510 V2AVGS_RRR_0_OPCODE_X0 = 118,
511 V2CMPEQI_IMM8_OPCODE_X0 = 15,
512 V2CMPEQI_IMM8_OPCODE_X1 = 40,
513 V2CMPEQ_RRR_0_OPCODE_X0 = 119,
514 V2CMPEQ_RRR_0_OPCODE_X1 = 75,
515 V2CMPLES_RRR_0_OPCODE_X0 = 120,
516 V2CMPLES_RRR_0_OPCODE_X1 = 76,
517 V2CMPLEU_RRR_0_OPCODE_X0 = 121,
518 V2CMPLEU_RRR_0_OPCODE_X1 = 77,
519 V2CMPLTSI_IMM8_OPCODE_X0 = 16,
520 V2CMPLTSI_IMM8_OPCODE_X1 = 41,
521 V2CMPLTS_RRR_0_OPCODE_X0 = 122,
522 V2CMPLTS_RRR_0_OPCODE_X1 = 78,
523 V2CMPLTUI_IMM8_OPCODE_X0 = 17,
524 V2CMPLTUI_IMM8_OPCODE_X1 = 42,
525 V2CMPLTU_RRR_0_OPCODE_X0 = 123,
526 V2CMPLTU_RRR_0_OPCODE_X1 = 79,
527 V2CMPNE_RRR_0_OPCODE_X0 = 124,
528 V2CMPNE_RRR_0_OPCODE_X1 = 80,
529 V2DOTPA_RRR_0_OPCODE_X0 = 125,
530 V2DOTP_RRR_0_OPCODE_X0 = 126,
531 V2INT_H_RRR_0_OPCODE_X0 = 127,
532 V2INT_H_RRR_0_OPCODE_X1 = 81,
533 V2INT_L_RRR_0_OPCODE_X0 = 128,
534 V2INT_L_RRR_0_OPCODE_X1 = 82,
535 V2MAXSI_IMM8_OPCODE_X0 = 18,
536 V2MAXSI_IMM8_OPCODE_X1 = 43,
537 V2MAXS_RRR_0_OPCODE_X0 = 129,
538 V2MAXS_RRR_0_OPCODE_X1 = 83,
539 V2MINSI_IMM8_OPCODE_X0 = 19,
540 V2MINSI_IMM8_OPCODE_X1 = 44,
541 V2MINS_RRR_0_OPCODE_X0 = 130,
542 V2MINS_RRR_0_OPCODE_X1 = 84,
543 V2MNZ_RRR_0_OPCODE_X0 = 131,
544 V2MNZ_RRR_0_OPCODE_X1 = 85,
545 V2MULFSC_RRR_0_OPCODE_X0 = 132,
546 V2MULS_RRR_0_OPCODE_X0 = 133,
547 V2MULTS_RRR_0_OPCODE_X0 = 134,
548 V2MZ_RRR_0_OPCODE_X0 = 135,
549 V2MZ_RRR_0_OPCODE_X1 = 86,
550 V2PACKH_RRR_0_OPCODE_X0 = 136,
551 V2PACKH_RRR_0_OPCODE_X1 = 87,
552 V2PACKL_RRR_0_OPCODE_X0 = 137,
553 V2PACKL_RRR_0_OPCODE_X1 = 88,
554 V2PACKUC_RRR_0_OPCODE_X0 = 138,
555 V2PACKUC_RRR_0_OPCODE_X1 = 89,
556 V2SADAS_RRR_0_OPCODE_X0 = 139,
557 V2SADAU_RRR_0_OPCODE_X0 = 140,
558 V2SADS_RRR_0_OPCODE_X0 = 141,
559 V2SADU_RRR_0_OPCODE_X0 = 142,
560 V2SHLI_SHIFT_OPCODE_X0 = 10,
561 V2SHLI_SHIFT_OPCODE_X1 = 10,
562 V2SHLSC_RRR_0_OPCODE_X0 = 143,
563 V2SHLSC_RRR_0_OPCODE_X1 = 90,
564 V2SHL_RRR_0_OPCODE_X0 = 144,
565 V2SHL_RRR_0_OPCODE_X1 = 91,
566 V2SHRSI_SHIFT_OPCODE_X0 = 11,
567 V2SHRSI_SHIFT_OPCODE_X1 = 11,
568 V2SHRS_RRR_0_OPCODE_X0 = 145,
569 V2SHRS_RRR_0_OPCODE_X1 = 92,
570 V2SHRUI_SHIFT_OPCODE_X0 = 12,
571 V2SHRUI_SHIFT_OPCODE_X1 = 12,
572 V2SHRU_RRR_0_OPCODE_X0 = 146,
573 V2SHRU_RRR_0_OPCODE_X1 = 93,
574 V2SUBSC_RRR_0_OPCODE_X0 = 147,
575 V2SUBSC_RRR_0_OPCODE_X1 = 94,
576 V2SUB_RRR_0_OPCODE_X0 = 148,
577 V2SUB_RRR_0_OPCODE_X1 = 95,
578 V4ADDSC_RRR_0_OPCODE_X0 = 149,
579 V4ADDSC_RRR_0_OPCODE_X1 = 96,
580 V4ADD_RRR_0_OPCODE_X0 = 150,
581 V4ADD_RRR_0_OPCODE_X1 = 97,
582 V4INT_H_RRR_0_OPCODE_X0 = 151,
583 V4INT_H_RRR_0_OPCODE_X1 = 98,
584 V4INT_L_RRR_0_OPCODE_X0 = 152,
585 V4INT_L_RRR_0_OPCODE_X1 = 99,
586 V4PACKSC_RRR_0_OPCODE_X0 = 153,
587 V4PACKSC_RRR_0_OPCODE_X1 = 100,
588 V4SHLSC_RRR_0_OPCODE_X0 = 154,
589 V4SHLSC_RRR_0_OPCODE_X1 = 101,
590 V4SHL_RRR_0_OPCODE_X0 = 155,
591 V4SHL_RRR_0_OPCODE_X1 = 102,
592 V4SHRS_RRR_0_OPCODE_X0 = 156,
593 V4SHRS_RRR_0_OPCODE_X1 = 103,
594 V4SHRU_RRR_0_OPCODE_X0 = 157,
595 V4SHRU_RRR_0_OPCODE_X1 = 104,
596 V4SUBSC_RRR_0_OPCODE_X0 = 158,
597 V4SUBSC_RRR_0_OPCODE_X1 = 105,
598 V4SUB_RRR_0_OPCODE_X0 = 159,
599 V4SUB_RRR_0_OPCODE_X1 = 106,
600 WH64_UNARY_OPCODE_X1 = 38,
601 XORI_IMM8_OPCODE_X0 = 20,
602 XORI_IMM8_OPCODE_X1 = 45,
603 XOR_RRR_0_OPCODE_X0 = 160,
604 XOR_RRR_0_OPCODE_X1 = 107,
605 XOR_RRR_5_OPCODE_Y0 = 3,
606 XOR_RRR_5_OPCODE_Y1 = 3
478}; 607};
479 608
480#endif /* !_TILE_OPCODE_CONSTANTS_H */ 609#endif /* !_TILE_OPCODE_CONSTANTS_H */
diff --git a/arch/tile/include/asm/page.h b/arch/tile/include/asm/page.h
index 7d90641cf18d..db93518fac03 100644
--- a/arch/tile/include/asm/page.h
+++ b/arch/tile/include/asm/page.h
@@ -16,10 +16,12 @@
16#define _ASM_TILE_PAGE_H 16#define _ASM_TILE_PAGE_H
17 17
18#include <linux/const.h> 18#include <linux/const.h>
19#include <hv/hypervisor.h>
20#include <arch/chip.h>
19 21
20/* PAGE_SHIFT and HPAGE_SHIFT determine the page sizes. */ 22/* PAGE_SHIFT and HPAGE_SHIFT determine the page sizes. */
21#define PAGE_SHIFT 16 23#define PAGE_SHIFT HV_LOG2_PAGE_SIZE_SMALL
22#define HPAGE_SHIFT 24 24#define HPAGE_SHIFT HV_LOG2_PAGE_SIZE_LARGE
23 25
24#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) 26#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
25#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 27#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
@@ -27,25 +29,13 @@
27#define PAGE_MASK (~(PAGE_SIZE - 1)) 29#define PAGE_MASK (~(PAGE_SIZE - 1))
28#define HPAGE_MASK (~(HPAGE_SIZE - 1)) 30#define HPAGE_MASK (~(HPAGE_SIZE - 1))
29 31
30#ifdef __KERNEL__
31
32#include <hv/hypervisor.h>
33#include <arch/chip.h>
34
35/* 32/*
36 * The {,H}PAGE_SHIFT values must match the HV_LOG2_PAGE_SIZE_xxx 33 * If the Kconfig doesn't specify, set a maximum zone order that
37 * definitions in <hv/hypervisor.h>. We validate this at build time 34 * is enough so that we can create huge pages from small pages given
38 * here, and again at runtime during early boot. We provide a 35 * the respective sizes of the two page types. See <linux/mmzone.h>.
39 * separate definition since userspace doesn't have <hv/hypervisor.h>.
40 *
41 * Be careful to distinguish PAGE_SHIFT from HV_PTE_INDEX_PFN, since
42 * they are the same on i386 but not TILE.
43 */ 36 */
44#if HV_LOG2_PAGE_SIZE_SMALL != PAGE_SHIFT 37#ifndef CONFIG_FORCE_MAX_ZONEORDER
45# error Small page size mismatch in Linux 38#define CONFIG_FORCE_MAX_ZONEORDER (HPAGE_SHIFT - PAGE_SHIFT + 1)
46#endif
47#if HV_LOG2_PAGE_SIZE_LARGE != HPAGE_SHIFT
48# error Huge page size mismatch in Linux
49#endif 39#endif
50 40
51#ifndef __ASSEMBLY__ 41#ifndef __ASSEMBLY__
@@ -81,12 +71,6 @@ static inline void copy_user_page(void *to, void *from, unsigned long vaddr,
81 * Hypervisor page tables are made of the same basic structure. 71 * Hypervisor page tables are made of the same basic structure.
82 */ 72 */
83 73
84typedef __u64 pteval_t;
85typedef __u64 pmdval_t;
86typedef __u64 pudval_t;
87typedef __u64 pgdval_t;
88typedef __u64 pgprotval_t;
89
90typedef HV_PTE pte_t; 74typedef HV_PTE pte_t;
91typedef HV_PTE pgd_t; 75typedef HV_PTE pgd_t;
92typedef HV_PTE pgprot_t; 76typedef HV_PTE pgprot_t;
@@ -103,6 +87,10 @@ typedef struct page *pgtable_t;
103/* Must be a macro since it is used to create constants. */ 87/* Must be a macro since it is used to create constants. */
104#define __pgprot(val) hv_pte(val) 88#define __pgprot(val) hv_pte(val)
105 89
90/* Rarely-used initializers, typically with a "zero" value. */
91#define __pte(x) hv_pte(x)
92#define __pgd(x) hv_pte(x)
93
106static inline u64 pgprot_val(pgprot_t pgprot) 94static inline u64 pgprot_val(pgprot_t pgprot)
107{ 95{
108 return hv_pte_val(pgprot); 96 return hv_pte_val(pgprot);
@@ -122,6 +110,8 @@ static inline u64 pgd_val(pgd_t pgd)
122 110
123typedef HV_PTE pmd_t; 111typedef HV_PTE pmd_t;
124 112
113#define __pmd(x) hv_pte(x)
114
125static inline u64 pmd_val(pmd_t pmd) 115static inline u64 pmd_val(pmd_t pmd)
126{ 116{
127 return hv_pte_val(pmd); 117 return hv_pte_val(pmd);
@@ -199,17 +189,17 @@ static inline __attribute_const__ int get_order(unsigned long size)
199 * If you want more physical memory than this then see the CONFIG_HIGHMEM 189 * If you want more physical memory than this then see the CONFIG_HIGHMEM
200 * option in the kernel configuration. 190 * option in the kernel configuration.
201 * 191 *
202 * The top two 16MB chunks in the table below (VIRT and HV) are 192 * The top 16MB chunk in the table below is unavailable to Linux. Since
203 * unavailable to Linux. Since the kernel interrupt vectors must live 193 * the kernel interrupt vectors must live at ether 0xfe000000 or 0xfd000000
204 * at 0xfd000000, we map all of the bottom of RAM at this address with 194 * (depending on whether the kernel is at PL2 or Pl1), we map all of the
205 * a huge page table entry to minimize its ITLB footprint (as well as 195 * bottom of RAM at this address with a huge page table entry to minimize
206 * at PAGE_OFFSET). The last architected requirement is that user 196 * its ITLB footprint (as well as at PAGE_OFFSET). The last architected
207 * interrupt vectors live at 0xfc000000, so we make that range of 197 * requirement is that user interrupt vectors live at 0xfc000000, so we
208 * memory available to user processes. The remaining regions are sized 198 * make that range of memory available to user processes. The remaining
209 * as shown; after the first four addresses, we show "typical" values, 199 * regions are sized as shown; the first four addresses use the PL 1
210 * since the actual addresses depend on kernel #defines. 200 * values, and after that, we show "typical" values, since the actual
201 * addresses depend on kernel #defines.
211 * 202 *
212 * MEM_VIRT_INTRPT 0xff000000
213 * MEM_HV_INTRPT 0xfe000000 203 * MEM_HV_INTRPT 0xfe000000
214 * MEM_SV_INTRPT (kernel code) 0xfd000000 204 * MEM_SV_INTRPT (kernel code) 0xfd000000
215 * MEM_USER_INTRPT (user vector) 0xfc000000 205 * MEM_USER_INTRPT (user vector) 0xfc000000
@@ -221,9 +211,14 @@ static inline __attribute_const__ int get_order(unsigned long size)
221 */ 211 */
222 212
223#define MEM_USER_INTRPT _AC(0xfc000000, UL) 213#define MEM_USER_INTRPT _AC(0xfc000000, UL)
214#if CONFIG_KERNEL_PL == 1
224#define MEM_SV_INTRPT _AC(0xfd000000, UL) 215#define MEM_SV_INTRPT _AC(0xfd000000, UL)
225#define MEM_HV_INTRPT _AC(0xfe000000, UL) 216#define MEM_HV_INTRPT _AC(0xfe000000, UL)
226#define MEM_VIRT_INTRPT _AC(0xff000000, UL) 217#else
218#define MEM_GUEST_INTRPT _AC(0xfd000000, UL)
219#define MEM_SV_INTRPT _AC(0xfe000000, UL)
220#define MEM_HV_INTRPT _AC(0xff000000, UL)
221#endif
227 222
228#define INTRPT_SIZE 0x4000 223#define INTRPT_SIZE 0x4000
229 224
@@ -325,7 +320,7 @@ static inline int pfn_valid(unsigned long pfn)
325 320
326/* Provide as macros since these require some other headers included. */ 321/* Provide as macros since these require some other headers included. */
327#define page_to_pa(page) ((phys_addr_t)(page_to_pfn(page)) << PAGE_SHIFT) 322#define page_to_pa(page) ((phys_addr_t)(page_to_pfn(page)) << PAGE_SHIFT)
328#define virt_to_page(kaddr) pfn_to_page(kaddr_to_pfn(kaddr)) 323#define virt_to_page(kaddr) pfn_to_page(kaddr_to_pfn((void *)(kaddr)))
329#define page_to_virt(page) pfn_to_kaddr(page_to_pfn(page)) 324#define page_to_virt(page) pfn_to_kaddr(page_to_pfn(page))
330 325
331struct mm_struct; 326struct mm_struct;
@@ -338,6 +333,4 @@ extern pte_t *virt_to_pte(struct mm_struct *mm, unsigned long addr);
338 333
339#include <asm-generic/memory_model.h> 334#include <asm-generic/memory_model.h>
340 335
341#endif /* __KERNEL__ */
342
343#endif /* _ASM_TILE_PAGE_H */ 336#endif /* _ASM_TILE_PAGE_H */
diff --git a/arch/tile/include/asm/parport.h b/arch/tile/include/asm/parport.h
new file mode 100644
index 000000000000..cf252af64590
--- /dev/null
+++ b/arch/tile/include/asm/parport.h
@@ -0,0 +1 @@
#include <asm-generic/parport.h>
diff --git a/arch/tile/include/asm/pci-bridge.h b/arch/tile/include/asm/pci-bridge.h
deleted file mode 100644
index e853b0e2793b..000000000000
--- a/arch/tile/include/asm/pci-bridge.h
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#ifndef _ASM_TILE_PCI_BRIDGE_H
16#define _ASM_TILE_PCI_BRIDGE_H
17
18#include <linux/ioport.h>
19#include <linux/pci.h>
20
21struct device_node;
22struct pci_controller;
23
24/*
25 * pci_io_base returns the memory address at which you can access
26 * the I/O space for PCI bus number `bus' (or NULL on error).
27 */
28extern void __iomem *pci_bus_io_base(unsigned int bus);
29extern unsigned long pci_bus_io_base_phys(unsigned int bus);
30extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
31
32/* Allocate a new PCI host bridge structure */
33extern struct pci_controller *pcibios_alloc_controller(void);
34
35/* Helper function for setting up resources */
36extern void pci_init_resource(struct resource *res, unsigned long start,
37 unsigned long end, int flags, char *name);
38
39/* Get the PCI host controller for a bus */
40extern struct pci_controller *pci_bus_to_hose(int bus);
41
42/*
43 * Structure of a PCI controller (host bridge)
44 */
45struct pci_controller {
46 int index; /* PCI domain number */
47 struct pci_bus *root_bus;
48
49 int first_busno;
50 int last_busno;
51
52 int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */
53 int hv_mem_fd; /* fd to Hypervisor for MMIO operations */
54
55 struct pci_ops *ops;
56
57 int irq_base; /* Base IRQ from the Hypervisor */
58 int plx_gen1; /* flag for PLX Gen 1 configuration */
59
60 /* Address ranges that are routed to this controller/bridge. */
61 struct resource mem_resources[3];
62};
63
64static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
65{
66 return bus->sysdata;
67}
68
69extern void setup_indirect_pci_nomap(struct pci_controller *hose,
70 void __iomem *cfg_addr, void __iomem *cfg_data);
71extern void setup_indirect_pci(struct pci_controller *hose,
72 u32 cfg_addr, u32 cfg_data);
73extern void setup_grackle(struct pci_controller *hose);
74
75extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
76
77/*
78 * The following code swizzles for exactly one bridge. The routine
79 * common_swizzle below handles multiple bridges. But there are a
80 * some boards that don't follow the PCI spec's suggestion so we
81 * break this piece out separately.
82 */
83static inline unsigned char bridge_swizzle(unsigned char pin,
84 unsigned char idsel)
85{
86 return (((pin-1) + idsel) % 4) + 1;
87}
88
89/*
90 * The following macro is used to lookup irqs in a standard table
91 * format for those PPC systems that do not already have PCI
92 * interrupts properly routed.
93 */
94/* FIXME - double check this */
95#define PCI_IRQ_TABLE_LOOKUP ({ \
96 long _ctl_ = -1; \
97 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
98 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
99 _ctl_; \
100})
101
102/*
103 * Scan the buses below a given PCI host bridge and assign suitable
104 * resources to all devices found.
105 */
106extern int pciauto_bus_scan(struct pci_controller *, int);
107
108#ifdef CONFIG_PCI
109extern unsigned long pci_address_to_pio(phys_addr_t address);
110#else
111static inline unsigned long pci_address_to_pio(phys_addr_t address)
112{
113 return (unsigned long)-1;
114}
115#endif
116
117#endif /* _ASM_TILE_PCI_BRIDGE_H */
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
index b0c15da2d5d5..7f03cefed1b9 100644
--- a/arch/tile/include/asm/pci.h
+++ b/arch/tile/include/asm/pci.h
@@ -15,7 +15,29 @@
15#ifndef _ASM_TILE_PCI_H 15#ifndef _ASM_TILE_PCI_H
16#define _ASM_TILE_PCI_H 16#define _ASM_TILE_PCI_H
17 17
18#include <asm/pci-bridge.h> 18#include <linux/pci.h>
19
20/*
21 * Structure of a PCI controller (host bridge)
22 */
23struct pci_controller {
24 int index; /* PCI domain number */
25 struct pci_bus *root_bus;
26
27 int first_busno;
28 int last_busno;
29
30 int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */
31 int hv_mem_fd; /* fd to Hypervisor for MMIO operations */
32
33 struct pci_ops *ops;
34
35 int irq_base; /* Base IRQ from the Hypervisor */
36 int plx_gen1; /* flag for PLX Gen 1 configuration */
37
38 /* Address ranges that are routed to this controller/bridge. */
39 struct resource mem_resources[3];
40};
19 41
20/* 42/*
21 * The hypervisor maps the entirety of CPA-space as bus addresses, so 43 * The hypervisor maps the entirety of CPA-space as bus addresses, so
@@ -24,56 +46,13 @@
24 */ 46 */
25#define PCI_DMA_BUS_IS_PHYS 1 47#define PCI_DMA_BUS_IS_PHYS 1
26 48
27struct pci_controller *pci_bus_to_hose(int bus); 49int __devinit tile_pci_init(void);
28unsigned char __init common_swizzle(struct pci_dev *dev, unsigned char *pinp); 50int __devinit pcibios_init(void);
29int __init tile_pci_init(void);
30void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
31void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
32void __devinit pcibios_fixup_bus(struct pci_bus *bus);
33 51
34int __devinit _tile_cfg_read(struct pci_controller *hose, 52void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
35 int bus, 53static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
36 int slot,
37 int function,
38 int offset,
39 int size,
40 u32 *val);
41int __devinit _tile_cfg_write(struct pci_controller *hose,
42 int bus,
43 int slot,
44 int function,
45 int offset,
46 int size,
47 u32 val);
48 54
49/* 55void __devinit pcibios_fixup_bus(struct pci_bus *bus);
50 * These are used to to config reads and writes in the early stages of
51 * setup before the driver infrastructure has been set up enough to be
52 * able to do config reads and writes.
53 */
54#define early_cfg_read(where, size, value) \
55 _tile_cfg_read(controller, \
56 current_bus, \
57 pci_slot, \
58 pci_fn, \
59 where, \
60 size, \
61 value)
62
63#define early_cfg_write(where, size, value) \
64 _tile_cfg_write(controller, \
65 current_bus, \
66 pci_slot, \
67 pci_fn, \
68 where, \
69 size, \
70 value)
71
72
73
74#define PCICFG_BYTE 1
75#define PCICFG_WORD 2
76#define PCICFG_DWORD 4
77 56
78#define TILE_NUM_PCIE 2 57#define TILE_NUM_PCIE 2
79 58
@@ -88,33 +67,33 @@ static inline int pci_proc_domain(struct pci_bus *bus)
88} 67}
89 68
90/* 69/*
91 * I/O space is currently not supported. 70 * pcibios_assign_all_busses() tells whether or not the bus numbers
71 * should be reassigned, in case the BIOS didn't do it correctly, or
72 * in case we don't have a BIOS and we want to let Linux do it.
92 */ 73 */
74static inline int pcibios_assign_all_busses(void)
75{
76 return 1;
77}
93 78
94#define TILE_PCIE_LOWER_IO 0x0 79/*
95#define TILE_PCIE_UPPER_IO 0x10000 80 * No special bus mastering setup handling.
96#define TILE_PCIE_PCIE_IO_SIZE 0x0000FFFF 81 */
97
98#define _PAGE_NO_CACHE 0
99#define _PAGE_GUARDED 0
100
101
102#define pcibios_assign_all_busses() pci_assign_all_buses
103extern int pci_assign_all_buses;
104
105static inline void pcibios_set_master(struct pci_dev *dev) 82static inline void pcibios_set_master(struct pci_dev *dev)
106{ 83{
107 /* No special bus mastering setup handling */
108} 84}
109 85
110#define PCIBIOS_MIN_MEM 0 86#define PCIBIOS_MIN_MEM 0
111#define PCIBIOS_MIN_IO TILE_PCIE_LOWER_IO 87#define PCIBIOS_MIN_IO 0
112 88
113/* 89/*
114 * This flag tells if the platform is TILEmpower that needs 90 * This flag tells if the platform is TILEmpower that needs
115 * special configuration for the PLX switch chip. 91 * special configuration for the PLX switch chip.
116 */ 92 */
117extern int blade_pci; 93extern int tile_plx_gen1;
94
95/* Use any cpu for PCI. */
96#define cpumask_of_pcibus(bus) cpu_online_mask
118 97
119/* implement the pci_ DMA API in terms of the generic device dma_ one */ 98/* implement the pci_ DMA API in terms of the generic device dma_ one */
120#include <asm-generic/pci-dma-compat.h> 99#include <asm-generic/pci-dma-compat.h>
@@ -122,7 +101,4 @@ extern int blade_pci;
122/* generic pci stuff */ 101/* generic pci stuff */
123#include <asm-generic/pci.h> 102#include <asm-generic/pci.h>
124 103
125/* Use any cpu for PCI. */
126#define cpumask_of_pcibus(bus) cpu_online_mask
127
128#endif /* _ASM_TILE_PCI_H */ 104#endif /* _ASM_TILE_PCI_H */
diff --git a/arch/tile/include/asm/pgalloc.h b/arch/tile/include/asm/pgalloc.h
index cf52791a5501..e919c0bdc22d 100644
--- a/arch/tile/include/asm/pgalloc.h
+++ b/arch/tile/include/asm/pgalloc.h
@@ -41,9 +41,9 @@
41static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) 41static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
42{ 42{
43#ifdef CONFIG_64BIT 43#ifdef CONFIG_64BIT
44 set_pte_order(pmdp, pmd, L2_USER_PGTABLE_ORDER); 44 set_pte(pmdp, pmd);
45#else 45#else
46 set_pte_order(&pmdp->pud.pgd, pmd.pud.pgd, L2_USER_PGTABLE_ORDER); 46 set_pte(&pmdp->pud.pgd, pmd.pud.pgd);
47#endif 47#endif
48} 48}
49 49
@@ -100,6 +100,9 @@ pte_t *get_prealloc_pte(unsigned long pfn);
100/* During init, we can shatter kernel huge pages if needed. */ 100/* During init, we can shatter kernel huge pages if needed. */
101void shatter_pmd(pmd_t *pmd); 101void shatter_pmd(pmd_t *pmd);
102 102
103/* After init, a more complex technique is required. */
104void shatter_huge_page(unsigned long addr);
105
103#ifdef __tilegx__ 106#ifdef __tilegx__
104/* We share a single page allocator for both L1 and L2 page tables. */ 107/* We share a single page allocator for both L1 and L2 page tables. */
105#if HV_L1_SIZE != HV_L2_SIZE 108#if HV_L1_SIZE != HV_L2_SIZE
diff --git a/arch/tile/include/asm/pgtable.h b/arch/tile/include/asm/pgtable.h
index b3367379d537..1a20b7ef8ea2 100644
--- a/arch/tile/include/asm/pgtable.h
+++ b/arch/tile/include/asm/pgtable.h
@@ -233,15 +233,23 @@ static inline void __pte_clear(pte_t *ptep)
233#define pgd_ERROR(e) \ 233#define pgd_ERROR(e) \
234 pr_err("%s:%d: bad pgd 0x%016llx.\n", __FILE__, __LINE__, pgd_val(e)) 234 pr_err("%s:%d: bad pgd 0x%016llx.\n", __FILE__, __LINE__, pgd_val(e))
235 235
236/* Return PA and protection info for a given kernel VA. */
237int va_to_cpa_and_pte(void *va, phys_addr_t *cpa, pte_t *pte);
238
239/*
240 * __set_pte() ensures we write the 64-bit PTE with 32-bit words in
241 * the right order on 32-bit platforms and also allows us to write
242 * hooks to check valid PTEs, etc., if we want.
243 */
244void __set_pte(pte_t *ptep, pte_t pte);
245
236/* 246/*
237 * set_pte_order() sets the given PTE and also sanity-checks the 247 * set_pte() sets the given PTE and also sanity-checks the
238 * requested PTE against the page homecaching. Unspecified parts 248 * requested PTE against the page homecaching. Unspecified parts
239 * of the PTE are filled in when it is written to memory, i.e. all 249 * of the PTE are filled in when it is written to memory, i.e. all
240 * caching attributes if "!forcecache", or the home cpu if "anyhome". 250 * caching attributes if "!forcecache", or the home cpu if "anyhome".
241 */ 251 */
242extern void set_pte_order(pte_t *ptep, pte_t pte, int order); 252extern void set_pte(pte_t *ptep, pte_t pte);
243
244#define set_pte(ptep, pteval) set_pte_order(ptep, pteval, 0)
245#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) 253#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
246#define set_pte_atomic(pteptr, pteval) set_pte(pteptr, pteval) 254#define set_pte_atomic(pteptr, pteval) set_pte(pteptr, pteval)
247 255
@@ -293,21 +301,6 @@ extern void check_mm_caching(struct mm_struct *prev, struct mm_struct *next);
293#define __swp_entry_to_pte(swp) ((pte_t) { (((long long) ((swp).val)) << 32) }) 301#define __swp_entry_to_pte(swp) ((pte_t) { (((long long) ((swp).val)) << 32) })
294 302
295/* 303/*
296 * clone_pgd_range(pgd_t *dst, pgd_t *src, int count);
297 *
298 * dst - pointer to pgd range anwhere on a pgd page
299 * src - ""
300 * count - the number of pgds to copy.
301 *
302 * dst and src can be on the same page, but the range must not overlap,
303 * and must not cross a page boundary.
304 */
305static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count)
306{
307 memcpy(dst, src, count * sizeof(pgd_t));
308}
309
310/*
311 * Conversion functions: convert a page and protection to a page entry, 304 * Conversion functions: convert a page and protection to a page entry,
312 * and a page entry and page directory to the page they refer to. 305 * and a page entry and page directory to the page they refer to.
313 */ 306 */
@@ -344,18 +337,11 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
344#define pgd_offset_k(address) pgd_offset(&init_mm, address) 337#define pgd_offset_k(address) pgd_offset(&init_mm, address)
345 338
346#if defined(CONFIG_HIGHPTE) 339#if defined(CONFIG_HIGHPTE)
347extern pte_t *_pte_offset_map(pmd_t *, unsigned long address, enum km_type); 340extern pte_t *pte_offset_map(pmd_t *, unsigned long address);
348#define pte_offset_map(dir, address) \ 341#define pte_unmap(pte) kunmap_atomic(pte)
349 _pte_offset_map(dir, address, KM_PTE0)
350#define pte_offset_map_nested(dir, address) \
351 _pte_offset_map(dir, address, KM_PTE1)
352#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
353#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
354#else 342#else
355#define pte_offset_map(dir, address) pte_offset_kernel(dir, address) 343#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
356#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
357#define pte_unmap(pte) do { } while (0) 344#define pte_unmap(pte) do { } while (0)
358#define pte_unmap_nested(pte) do { } while (0)
359#endif 345#endif
360 346
361/* Clear a non-executable kernel PTE and flush it from the TLB. */ 347/* Clear a non-executable kernel PTE and flush it from the TLB. */
diff --git a/arch/tile/include/asm/pgtable_32.h b/arch/tile/include/asm/pgtable_32.h
index 53ec34884744..9f98529761fd 100644
--- a/arch/tile/include/asm/pgtable_32.h
+++ b/arch/tile/include/asm/pgtable_32.h
@@ -24,6 +24,7 @@
24#define PGDIR_SIZE HV_PAGE_SIZE_LARGE 24#define PGDIR_SIZE HV_PAGE_SIZE_LARGE
25#define PGDIR_MASK (~(PGDIR_SIZE-1)) 25#define PGDIR_MASK (~(PGDIR_SIZE-1))
26#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT)) 26#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
27#define SIZEOF_PGD (PTRS_PER_PGD * sizeof(pgd_t))
27 28
28/* 29/*
29 * The level-2 index is defined by the difference between the huge 30 * The level-2 index is defined by the difference between the huge
@@ -33,6 +34,7 @@
33 * this nomenclature is somewhat confusing. 34 * this nomenclature is somewhat confusing.
34 */ 35 */
35#define PTRS_PER_PTE (1 << (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL)) 36#define PTRS_PER_PTE (1 << (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL))
37#define SIZEOF_PTE (PTRS_PER_PTE * sizeof(pte_t))
36 38
37#ifndef __ASSEMBLY__ 39#ifndef __ASSEMBLY__
38 40
@@ -94,7 +96,6 @@ static inline int pgd_addr_invalid(unsigned long addr)
94 */ 96 */
95#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 97#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
96#define __HAVE_ARCH_PTEP_SET_WRPROTECT 98#define __HAVE_ARCH_PTEP_SET_WRPROTECT
97#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
98 99
99extern int ptep_test_and_clear_young(struct vm_area_struct *, 100extern int ptep_test_and_clear_young(struct vm_area_struct *,
100 unsigned long addr, pte_t *); 101 unsigned long addr, pte_t *);
@@ -110,6 +111,11 @@ static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
110 return pte; 111 return pte;
111} 112}
112 113
114static inline void __set_pmd(pmd_t *pmdp, pmd_t pmdval)
115{
116 set_pte(&pmdp->pud.pgd, pmdval.pud.pgd);
117}
118
113/* Create a pmd from a PTFN. */ 119/* Create a pmd from a PTFN. */
114static inline pmd_t ptfn_pmd(unsigned long ptfn, pgprot_t prot) 120static inline pmd_t ptfn_pmd(unsigned long ptfn, pgprot_t prot)
115{ 121{
diff --git a/arch/tile/include/asm/pgtable_64.h b/arch/tile/include/asm/pgtable_64.h
new file mode 100644
index 000000000000..fd80328523b4
--- /dev/null
+++ b/arch/tile/include/asm/pgtable_64.h
@@ -0,0 +1,175 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16#ifndef _ASM_TILE_PGTABLE_64_H
17#define _ASM_TILE_PGTABLE_64_H
18
19/* The level-0 page table breaks the address space into 32-bit chunks. */
20#define PGDIR_SHIFT HV_LOG2_L1_SPAN
21#define PGDIR_SIZE HV_L1_SPAN
22#define PGDIR_MASK (~(PGDIR_SIZE-1))
23#define PTRS_PER_PGD HV_L0_ENTRIES
24#define SIZEOF_PGD (PTRS_PER_PGD * sizeof(pgd_t))
25
26/*
27 * The level-1 index is defined by the huge page size. A PMD is composed
28 * of PTRS_PER_PMD pgd_t's and is the middle level of the page table.
29 */
30#define PMD_SHIFT HV_LOG2_PAGE_SIZE_LARGE
31#define PMD_SIZE HV_PAGE_SIZE_LARGE
32#define PMD_MASK (~(PMD_SIZE-1))
33#define PTRS_PER_PMD (1 << (PGDIR_SHIFT - PMD_SHIFT))
34#define SIZEOF_PMD (PTRS_PER_PMD * sizeof(pmd_t))
35
36/*
37 * The level-2 index is defined by the difference between the huge
38 * page size and the normal page size. A PTE is composed of
39 * PTRS_PER_PTE pte_t's and is the bottom level of the page table.
40 * Note that the hypervisor docs use PTE for what we call pte_t, so
41 * this nomenclature is somewhat confusing.
42 */
43#define PTRS_PER_PTE (1 << (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL))
44#define SIZEOF_PTE (PTRS_PER_PTE * sizeof(pte_t))
45
46/*
47 * Align the vmalloc area to an L2 page table, and leave a guard page
48 * at the beginning and end. The vmalloc code also puts in an internal
49 * guard page between each allocation.
50 */
51#define _VMALLOC_END HUGE_VMAP_BASE
52#define VMALLOC_END (_VMALLOC_END - PAGE_SIZE)
53#define VMALLOC_START (_VMALLOC_START + PAGE_SIZE)
54
55#define HUGE_VMAP_END (HUGE_VMAP_BASE + PGDIR_SIZE)
56
57#ifndef __ASSEMBLY__
58
59/* We have no pud since we are a three-level page table. */
60#include <asm-generic/pgtable-nopud.h>
61
62static inline int pud_none(pud_t pud)
63{
64 return pud_val(pud) == 0;
65}
66
67static inline int pud_present(pud_t pud)
68{
69 return pud_val(pud) & _PAGE_PRESENT;
70}
71
72#define pmd_ERROR(e) \
73 pr_err("%s:%d: bad pmd 0x%016llx.\n", __FILE__, __LINE__, pmd_val(e))
74
75static inline void pud_clear(pud_t *pudp)
76{
77 __pte_clear(&pudp->pgd);
78}
79
80static inline int pud_bad(pud_t pud)
81{
82 return ((pud_val(pud) & _PAGE_ALL) != _PAGE_TABLE);
83}
84
85/* Return the page-table frame number (ptfn) that a pud_t points at. */
86#define pud_ptfn(pud) hv_pte_get_ptfn((pud).pgd)
87
88/*
89 * A given kernel pud_t maps to a kernel pmd_t table at a specific
90 * virtual address. Since kernel pmd_t tables can be aligned at
91 * sub-page granularity, this macro can return non-page-aligned
92 * pointers, despite its name.
93 */
94#define pud_page_vaddr(pud) \
95 (__va((phys_addr_t)pud_ptfn(pud) << HV_LOG2_PAGE_TABLE_ALIGN))
96
97/*
98 * A pud_t points to a pmd_t array. Since we can have multiple per
99 * page, we don't have a one-to-one mapping of pud_t's to pages.
100 */
101#define pud_page(pud) pfn_to_page(HV_PTFN_TO_PFN(pud_ptfn(pud)))
102
103static inline unsigned long pud_index(unsigned long address)
104{
105 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
106}
107
108#define pmd_offset(pud, address) \
109 ((pmd_t *)pud_page_vaddr(*(pud)) + pmd_index(address))
110
111static inline void __set_pmd(pmd_t *pmdp, pmd_t pmdval)
112{
113 set_pte(pmdp, pmdval);
114}
115
116/* Create a pmd from a PTFN and pgprot. */
117static inline pmd_t ptfn_pmd(unsigned long ptfn, pgprot_t prot)
118{
119 return hv_pte_set_ptfn(prot, ptfn);
120}
121
122/* Return the page-table frame number (ptfn) that a pmd_t points at. */
123static inline unsigned long pmd_ptfn(pmd_t pmd)
124{
125 return hv_pte_get_ptfn(pmd);
126}
127
128static inline void pmd_clear(pmd_t *pmdp)
129{
130 __pte_clear(pmdp);
131}
132
133/* Normalize an address to having the correct high bits set. */
134#define pgd_addr_normalize pgd_addr_normalize
135static inline unsigned long pgd_addr_normalize(unsigned long addr)
136{
137 return ((long)addr << (CHIP_WORD_SIZE() - CHIP_VA_WIDTH())) >>
138 (CHIP_WORD_SIZE() - CHIP_VA_WIDTH());
139}
140
141/* We don't define any pgds for these addresses. */
142static inline int pgd_addr_invalid(unsigned long addr)
143{
144 return addr >= MEM_HV_START ||
145 (addr > MEM_LOW_END && addr < MEM_HIGH_START);
146}
147
148/*
149 * Use atomic instructions to provide atomicity against the hypervisor.
150 */
151#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
152static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
153 unsigned long addr, pte_t *ptep)
154{
155 return (__insn_fetchand(&ptep->val, ~HV_PTE_ACCESSED) >>
156 HV_PTE_INDEX_ACCESSED) & 0x1;
157}
158
159#define __HAVE_ARCH_PTEP_SET_WRPROTECT
160static inline void ptep_set_wrprotect(struct mm_struct *mm,
161 unsigned long addr, pte_t *ptep)
162{
163 __insn_fetchand(&ptep->val, ~HV_PTE_WRITABLE);
164}
165
166#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
167static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
168 unsigned long addr, pte_t *ptep)
169{
170 return hv_pte(__insn_exch(&ptep->val, 0UL));
171}
172
173#endif /* __ASSEMBLY__ */
174
175#endif /* _ASM_TILE_PGTABLE_64_H */
diff --git a/arch/tile/include/asm/processor.h b/arch/tile/include/asm/processor.h
index ccd5f8425688..34c1e01ffb5e 100644
--- a/arch/tile/include/asm/processor.h
+++ b/arch/tile/include/asm/processor.h
@@ -215,6 +215,8 @@ static inline void release_thread(struct task_struct *dead_task)
215 215
216extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); 216extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
217 217
218extern int do_work_pending(struct pt_regs *regs, u32 flags);
219
218 220
219/* 221/*
220 * Return saved (kernel) PC of a blocked thread. 222 * Return saved (kernel) PC of a blocked thread.
@@ -255,10 +257,6 @@ static inline void cpu_relax(void)
255 barrier(); 257 barrier();
256} 258}
257 259
258struct siginfo;
259extern void arch_coredump_signal(struct siginfo *, struct pt_regs *);
260#define arch_coredump_signal arch_coredump_signal
261
262/* Info on this processor (see fs/proc/cpuinfo.c) */ 260/* Info on this processor (see fs/proc/cpuinfo.c) */
263struct seq_operations; 261struct seq_operations;
264extern const struct seq_operations cpuinfo_op; 262extern const struct seq_operations cpuinfo_op;
@@ -269,10 +267,6 @@ extern char chip_model[64];
269/* Data on which physical memory controller corresponds to which NUMA node. */ 267/* Data on which physical memory controller corresponds to which NUMA node. */
270extern int node_controller[]; 268extern int node_controller[];
271 269
272
273/* Do we dump information to the console when a user application crashes? */
274extern int show_crashinfo;
275
276#if CHIP_HAS_CBOX_HOME_MAP() 270#if CHIP_HAS_CBOX_HOME_MAP()
277/* Does the heap allocator return hash-for-home pages by default? */ 271/* Does the heap allocator return hash-for-home pages by default? */
278extern int hash_default; 272extern int hash_default;
@@ -292,8 +286,18 @@ extern int kstack_hash;
292/* Are we using huge pages in the TLB for kernel data? */ 286/* Are we using huge pages in the TLB for kernel data? */
293extern int kdata_huge; 287extern int kdata_huge;
294 288
289/* Support standard Linux prefetching. */
290#define ARCH_HAS_PREFETCH
291#define prefetch(x) __builtin_prefetch(x)
295#define PREFETCH_STRIDE CHIP_L2_LINE_SIZE() 292#define PREFETCH_STRIDE CHIP_L2_LINE_SIZE()
296 293
294/* Bring a value into the L1D, faulting the TLB if necessary. */
295#ifdef __tilegx__
296#define prefetch_L1(x) __insn_prefetch_l1_fault((void *)(x))
297#else
298#define prefetch_L1(x) __insn_prefetch_L1((void *)(x))
299#endif
300
297#else /* __ASSEMBLY__ */ 301#else /* __ASSEMBLY__ */
298 302
299/* Do some slow action (e.g. read a slow SPR). */ 303/* Do some slow action (e.g. read a slow SPR). */
@@ -328,18 +332,21 @@ extern int kdata_huge;
328 * Note that assembly code assumes that USER_PL is zero. 332 * Note that assembly code assumes that USER_PL is zero.
329 */ 333 */
330#define USER_PL 0 334#define USER_PL 0
331#define KERNEL_PL 1 335#if CONFIG_KERNEL_PL == 2
336#define GUEST_PL 1
337#endif
338#define KERNEL_PL CONFIG_KERNEL_PL
332 339
333/* SYSTEM_SAVE_1_0 holds the current cpu number ORed with ksp0. */ 340/* SYSTEM_SAVE_K_0 holds the current cpu number ORed with ksp0. */
334#define CPU_LOG_MASK_VALUE 12 341#define CPU_LOG_MASK_VALUE 12
335#define CPU_MASK_VALUE ((1 << CPU_LOG_MASK_VALUE) - 1) 342#define CPU_MASK_VALUE ((1 << CPU_LOG_MASK_VALUE) - 1)
336#if CONFIG_NR_CPUS > CPU_MASK_VALUE 343#if CONFIG_NR_CPUS > CPU_MASK_VALUE
337# error Too many cpus! 344# error Too many cpus!
338#endif 345#endif
339#define raw_smp_processor_id() \ 346#define raw_smp_processor_id() \
340 ((int)__insn_mfspr(SPR_SYSTEM_SAVE_1_0) & CPU_MASK_VALUE) 347 ((int)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & CPU_MASK_VALUE)
341#define get_current_ksp0() \ 348#define get_current_ksp0() \
342 (__insn_mfspr(SPR_SYSTEM_SAVE_1_0) & ~CPU_MASK_VALUE) 349 (__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & ~CPU_MASK_VALUE)
343#define next_current_ksp0(task) ({ \ 350#define next_current_ksp0(task) ({ \
344 unsigned long __ksp0 = task_ksp0(task); \ 351 unsigned long __ksp0 = task_ksp0(task); \
345 int __cpu = raw_smp_processor_id(); \ 352 int __cpu = raw_smp_processor_id(); \
diff --git a/arch/tile/include/asm/ptrace.h b/arch/tile/include/asm/ptrace.h
index 4a02bb073979..6be2246e015c 100644
--- a/arch/tile/include/asm/ptrace.h
+++ b/arch/tile/include/asm/ptrace.h
@@ -62,8 +62,8 @@ struct pt_regs {
62 pt_reg_t lr; /* aliases regs[TREG_LR] */ 62 pt_reg_t lr; /* aliases regs[TREG_LR] */
63 63
64 /* Saved special registers. */ 64 /* Saved special registers. */
65 pt_reg_t pc; /* stored in EX_CONTEXT_1_0 */ 65 pt_reg_t pc; /* stored in EX_CONTEXT_K_0 */
66 pt_reg_t ex1; /* stored in EX_CONTEXT_1_1 (PL and ICS bit) */ 66 pt_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */
67 pt_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */ 67 pt_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */
68 pt_reg_t orig_r0; /* r0 at syscall entry, else zero */ 68 pt_reg_t orig_r0; /* r0 at syscall entry, else zero */
69 pt_reg_t flags; /* flags (see below) */ 69 pt_reg_t flags; /* flags (see below) */
@@ -141,6 +141,9 @@ struct single_step_state {
141/* Single-step the instruction at regs->pc */ 141/* Single-step the instruction at regs->pc */
142extern void single_step_once(struct pt_regs *regs); 142extern void single_step_once(struct pt_regs *regs);
143 143
144/* Clean up after execve(). */
145extern void single_step_execve(void);
146
144struct task_struct; 147struct task_struct;
145 148
146extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs, 149extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
diff --git a/arch/tile/include/asm/serial.h b/arch/tile/include/asm/serial.h
new file mode 100644
index 000000000000..a0cb0caff152
--- /dev/null
+++ b/arch/tile/include/asm/serial.h
@@ -0,0 +1 @@
#include <asm-generic/serial.h>
diff --git a/arch/tile/include/asm/signal.h b/arch/tile/include/asm/signal.h
index c1ee1d61d44c..1e1e616783eb 100644
--- a/arch/tile/include/asm/signal.h
+++ b/arch/tile/include/asm/signal.h
@@ -25,9 +25,13 @@
25 25
26#if defined(__KERNEL__) && !defined(__ASSEMBLY__) 26#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
27struct pt_regs; 27struct pt_regs;
28int restore_sigcontext(struct pt_regs *, struct sigcontext __user *, long *); 28int restore_sigcontext(struct pt_regs *, struct sigcontext __user *);
29int setup_sigcontext(struct sigcontext __user *, struct pt_regs *); 29int setup_sigcontext(struct sigcontext __user *, struct pt_regs *);
30void do_signal(struct pt_regs *regs); 30void do_signal(struct pt_regs *regs);
31void signal_fault(const char *type, struct pt_regs *,
32 void __user *frame, int sig);
33void trace_unhandled_signal(const char *type, struct pt_regs *regs,
34 unsigned long address, int signo);
31#endif 35#endif
32 36
33#endif /* _ASM_TILE_SIGNAL_H */ 37#endif /* _ASM_TILE_SIGNAL_H */
diff --git a/arch/tile/include/asm/spinlock_32.h b/arch/tile/include/asm/spinlock_32.h
index 88efdde8dd2b..a8f2c6e31a87 100644
--- a/arch/tile/include/asm/spinlock_32.h
+++ b/arch/tile/include/asm/spinlock_32.h
@@ -78,13 +78,6 @@ void arch_spin_unlock_wait(arch_spinlock_t *lock);
78#define _RD_COUNT_SHIFT 24 78#define _RD_COUNT_SHIFT 24
79#define _RD_COUNT_WIDTH 8 79#define _RD_COUNT_WIDTH 8
80 80
81/* Internal functions; do not use. */
82void arch_read_lock_slow(arch_rwlock_t *, u32);
83int arch_read_trylock_slow(arch_rwlock_t *);
84void arch_read_unlock_slow(arch_rwlock_t *);
85void arch_write_lock_slow(arch_rwlock_t *, u32);
86void arch_write_unlock_slow(arch_rwlock_t *, u32);
87
88/** 81/**
89 * arch_read_can_lock() - would read_trylock() succeed? 82 * arch_read_can_lock() - would read_trylock() succeed?
90 */ 83 */
@@ -104,94 +97,32 @@ static inline int arch_write_can_lock(arch_rwlock_t *rwlock)
104/** 97/**
105 * arch_read_lock() - acquire a read lock. 98 * arch_read_lock() - acquire a read lock.
106 */ 99 */
107static inline void arch_read_lock(arch_rwlock_t *rwlock) 100void arch_read_lock(arch_rwlock_t *rwlock);
108{
109 u32 val = __insn_tns((int *)&rwlock->lock);
110 if (unlikely(val << _RD_COUNT_WIDTH)) {
111 arch_read_lock_slow(rwlock, val);
112 return;
113 }
114 rwlock->lock = val + (1 << _RD_COUNT_SHIFT);
115}
116 101
117/** 102/**
118 * arch_read_lock() - acquire a write lock. 103 * arch_write_lock() - acquire a write lock.
119 */ 104 */
120static inline void arch_write_lock(arch_rwlock_t *rwlock) 105void arch_write_lock(arch_rwlock_t *rwlock);
121{
122 u32 val = __insn_tns((int *)&rwlock->lock);
123 if (unlikely(val != 0)) {
124 arch_write_lock_slow(rwlock, val);
125 return;
126 }
127 rwlock->lock = 1 << _WR_NEXT_SHIFT;
128}
129 106
130/** 107/**
131 * arch_read_trylock() - try to acquire a read lock. 108 * arch_read_trylock() - try to acquire a read lock.
132 */ 109 */
133static inline int arch_read_trylock(arch_rwlock_t *rwlock) 110int arch_read_trylock(arch_rwlock_t *rwlock);
134{
135 int locked;
136 u32 val = __insn_tns((int *)&rwlock->lock);
137 if (unlikely(val & 1))
138 return arch_read_trylock_slow(rwlock);
139 locked = (val << _RD_COUNT_WIDTH) == 0;
140 rwlock->lock = val + (locked << _RD_COUNT_SHIFT);
141 return locked;
142}
143 111
144/** 112/**
145 * arch_write_trylock() - try to acquire a write lock. 113 * arch_write_trylock() - try to acquire a write lock.
146 */ 114 */
147static inline int arch_write_trylock(arch_rwlock_t *rwlock) 115int arch_write_trylock(arch_rwlock_t *rwlock);
148{
149 u32 val = __insn_tns((int *)&rwlock->lock);
150
151 /*
152 * If a tns is in progress, or there's a waiting or active locker,
153 * or active readers, we can't take the lock, so give up.
154 */
155 if (unlikely(val != 0)) {
156 if (!(val & 1))
157 rwlock->lock = val;
158 return 0;
159 }
160
161 /* Set the "next" field to mark it locked. */
162 rwlock->lock = 1 << _WR_NEXT_SHIFT;
163 return 1;
164}
165 116
166/** 117/**
167 * arch_read_unlock() - release a read lock. 118 * arch_read_unlock() - release a read lock.
168 */ 119 */
169static inline void arch_read_unlock(arch_rwlock_t *rwlock) 120void arch_read_unlock(arch_rwlock_t *rwlock);
170{
171 u32 val;
172 mb(); /* guarantee anything modified under the lock is visible */
173 val = __insn_tns((int *)&rwlock->lock);
174 if (unlikely(val & 1)) {
175 arch_read_unlock_slow(rwlock);
176 return;
177 }
178 rwlock->lock = val - (1 << _RD_COUNT_SHIFT);
179}
180 121
181/** 122/**
182 * arch_write_unlock() - release a write lock. 123 * arch_write_unlock() - release a write lock.
183 */ 124 */
184static inline void arch_write_unlock(arch_rwlock_t *rwlock) 125void arch_write_unlock(arch_rwlock_t *rwlock);
185{
186 u32 val;
187 mb(); /* guarantee anything modified under the lock is visible */
188 val = __insn_tns((int *)&rwlock->lock);
189 if (unlikely(val != (1 << _WR_NEXT_SHIFT))) {
190 arch_write_unlock_slow(rwlock, val);
191 return;
192 }
193 rwlock->lock = 0;
194}
195 126
196#define arch_read_lock_flags(lock, flags) arch_read_lock(lock) 127#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
197#define arch_write_lock_flags(lock, flags) arch_write_lock(lock) 128#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
diff --git a/arch/tile/include/asm/spinlock_64.h b/arch/tile/include/asm/spinlock_64.h
new file mode 100644
index 000000000000..72be5904e020
--- /dev/null
+++ b/arch/tile/include/asm/spinlock_64.h
@@ -0,0 +1,161 @@
1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * 64-bit SMP ticket spinlocks, allowing only a single CPU anywhere
15 * (the type definitions are in asm/spinlock_types.h)
16 */
17
18#ifndef _ASM_TILE_SPINLOCK_64_H
19#define _ASM_TILE_SPINLOCK_64_H
20
21/* Shifts and masks for the various fields in "lock". */
22#define __ARCH_SPIN_CURRENT_SHIFT 17
23#define __ARCH_SPIN_NEXT_MASK 0x7fff
24#define __ARCH_SPIN_NEXT_OVERFLOW 0x8000
25
26/*
27 * Return the "current" portion of a ticket lock value,
28 * i.e. the number that currently owns the lock.
29 */
30static inline int arch_spin_current(u32 val)
31{
32 return val >> __ARCH_SPIN_CURRENT_SHIFT;
33}
34
35/*
36 * Return the "next" portion of a ticket lock value,
37 * i.e. the number that the next task to try to acquire the lock will get.
38 */
39static inline int arch_spin_next(u32 val)
40{
41 return val & __ARCH_SPIN_NEXT_MASK;
42}
43
44/* The lock is locked if a task would have to wait to get it. */
45static inline int arch_spin_is_locked(arch_spinlock_t *lock)
46{
47 u32 val = lock->lock;
48 return arch_spin_current(val) != arch_spin_next(val);
49}
50
51/* Bump the current ticket so the next task owns the lock. */
52static inline void arch_spin_unlock(arch_spinlock_t *lock)
53{
54 wmb(); /* guarantee anything modified under the lock is visible */
55 __insn_fetchadd4(&lock->lock, 1U << __ARCH_SPIN_CURRENT_SHIFT);
56}
57
58void arch_spin_unlock_wait(arch_spinlock_t *lock);
59
60void arch_spin_lock_slow(arch_spinlock_t *lock, u32 val);
61
62/* Grab the "next" ticket number and bump it atomically.
63 * If the current ticket is not ours, go to the slow path.
64 * We also take the slow path if the "next" value overflows.
65 */
66static inline void arch_spin_lock(arch_spinlock_t *lock)
67{
68 u32 val = __insn_fetchadd4(&lock->lock, 1);
69 u32 ticket = val & (__ARCH_SPIN_NEXT_MASK | __ARCH_SPIN_NEXT_OVERFLOW);
70 if (unlikely(arch_spin_current(val) != ticket))
71 arch_spin_lock_slow(lock, ticket);
72}
73
74/* Try to get the lock, and return whether we succeeded. */
75int arch_spin_trylock(arch_spinlock_t *lock);
76
77/* We cannot take an interrupt after getting a ticket, so don't enable them. */
78#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
79
80/*
81 * Read-write spinlocks, allowing multiple readers
82 * but only one writer.
83 *
84 * We use fetchadd() for readers, and fetchor() with the sign bit
85 * for writers.
86 */
87
88#define __WRITE_LOCK_BIT (1 << 31)
89
90static inline int arch_write_val_locked(int val)
91{
92 return val < 0; /* Optimize "val & __WRITE_LOCK_BIT". */
93}
94
95/**
96 * read_can_lock - would read_trylock() succeed?
97 * @lock: the rwlock in question.
98 */
99static inline int arch_read_can_lock(arch_rwlock_t *rw)
100{
101 return !arch_write_val_locked(rw->lock);
102}
103
104/**
105 * write_can_lock - would write_trylock() succeed?
106 * @lock: the rwlock in question.
107 */
108static inline int arch_write_can_lock(arch_rwlock_t *rw)
109{
110 return rw->lock == 0;
111}
112
113extern void __read_lock_failed(arch_rwlock_t *rw);
114
115static inline void arch_read_lock(arch_rwlock_t *rw)
116{
117 u32 val = __insn_fetchaddgez4(&rw->lock, 1);
118 if (unlikely(arch_write_val_locked(val)))
119 __read_lock_failed(rw);
120}
121
122extern void __write_lock_failed(arch_rwlock_t *rw, u32 val);
123
124static inline void arch_write_lock(arch_rwlock_t *rw)
125{
126 u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
127 if (unlikely(val != 0))
128 __write_lock_failed(rw, val);
129}
130
131static inline void arch_read_unlock(arch_rwlock_t *rw)
132{
133 __insn_mf();
134 __insn_fetchadd4(&rw->lock, -1);
135}
136
137static inline void arch_write_unlock(arch_rwlock_t *rw)
138{
139 __insn_mf();
140 rw->lock = 0;
141}
142
143static inline int arch_read_trylock(arch_rwlock_t *rw)
144{
145 return !arch_write_val_locked(__insn_fetchaddgez4(&rw->lock, 1));
146}
147
148static inline int arch_write_trylock(arch_rwlock_t *rw)
149{
150 u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
151 if (likely(val == 0))
152 return 1;
153 if (!arch_write_val_locked(val))
154 __insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT);
155 return 0;
156}
157
158#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
159#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
160
161#endif /* _ASM_TILE_SPINLOCK_64_H */
diff --git a/arch/tile/include/asm/stack.h b/arch/tile/include/asm/stack.h
index f908473c322d..4d97a2db932e 100644
--- a/arch/tile/include/asm/stack.h
+++ b/arch/tile/include/asm/stack.h
@@ -18,13 +18,14 @@
18#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/sched.h> 19#include <linux/sched.h>
20#include <asm/backtrace.h> 20#include <asm/backtrace.h>
21#include <asm/page.h>
21#include <hv/hypervisor.h> 22#include <hv/hypervisor.h>
22 23
23/* Everything we need to keep track of a backtrace iteration */ 24/* Everything we need to keep track of a backtrace iteration */
24struct KBacktraceIterator { 25struct KBacktraceIterator {
25 BacktraceIterator it; 26 BacktraceIterator it;
26 struct task_struct *task; /* task we are backtracing */ 27 struct task_struct *task; /* task we are backtracing */
27 HV_PTE *pgtable; /* page table for user space access */ 28 pte_t *pgtable; /* page table for user space access */
28 int end; /* iteration complete. */ 29 int end; /* iteration complete. */
29 int new_context; /* new context is starting */ 30 int new_context; /* new context is starting */
30 int profile; /* profiling, so stop on async intrpt */ 31 int profile; /* profiling, so stop on async intrpt */
diff --git a/arch/tile/include/asm/stat.h b/arch/tile/include/asm/stat.h
index 3dc90fa92c70..c0db34d56be3 100644
--- a/arch/tile/include/asm/stat.h
+++ b/arch/tile/include/asm/stat.h
@@ -1 +1,4 @@
1#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
2#define __ARCH_WANT_STAT64 /* Used for compat_sys_stat64() etc. */
3#endif
1#include <asm-generic/stat.h> 4#include <asm-generic/stat.h>
diff --git a/arch/tile/include/asm/swab.h b/arch/tile/include/asm/swab.h
index 25c686a00f1d..7c37b38f6c8d 100644
--- a/arch/tile/include/asm/swab.h
+++ b/arch/tile/include/asm/swab.h
@@ -18,12 +18,6 @@
18/* Tile gcc is always >= 4.3.0, so we use __builtin_bswap. */ 18/* Tile gcc is always >= 4.3.0, so we use __builtin_bswap. */
19#define __arch_swab32(x) __builtin_bswap32(x) 19#define __arch_swab32(x) __builtin_bswap32(x)
20#define __arch_swab64(x) __builtin_bswap64(x) 20#define __arch_swab64(x) __builtin_bswap64(x)
21
22/* Use the variant that is natural for the wordsize. */
23#ifdef CONFIG_64BIT
24#define __arch_swab16(x) (__builtin_bswap64(x) >> 48)
25#else
26#define __arch_swab16(x) (__builtin_bswap32(x) >> 16) 21#define __arch_swab16(x) (__builtin_bswap32(x) >> 16)
27#endif
28 22
29#endif /* _ASM_TILE_SWAB_H */ 23#endif /* _ASM_TILE_SWAB_H */
diff --git a/arch/tile/include/asm/syscalls.h b/arch/tile/include/asm/syscalls.h
index ce99ffefeacf..3b5507c31eae 100644
--- a/arch/tile/include/asm/syscalls.h
+++ b/arch/tile/include/asm/syscalls.h
@@ -32,8 +32,9 @@ extern void *compat_sys_call_table[];
32 32
33/* 33/*
34 * Note that by convention, any syscall which requires the current 34 * Note that by convention, any syscall which requires the current
35 * register set takes an additional "struct pt_regs *" pointer; the 35 * register set takes an additional "struct pt_regs *" pointer; a
36 * sys_xxx() function just adds the pointer and tail-calls to _sys_xxx(). 36 * _sys_xxx() trampoline in intvec*.S just sets up the pointer and
37 * jumps to sys_xxx().
37 */ 38 */
38 39
39/* kernel/sys.c */ 40/* kernel/sys.c */
@@ -43,66 +44,17 @@ long sys32_fadvise64(int fd, u32 offset_lo, u32 offset_hi,
43int sys32_fadvise64_64(int fd, u32 offset_lo, u32 offset_hi, 44int sys32_fadvise64_64(int fd, u32 offset_lo, u32 offset_hi,
44 u32 len_lo, u32 len_hi, int advice); 45 u32 len_lo, u32 len_hi, int advice);
45long sys_flush_cache(void); 46long sys_flush_cache(void);
46long sys_mmap2(unsigned long addr, unsigned long len, 47#ifndef __tilegx__ /* No mmap() in the 32-bit kernel. */
47 unsigned long prot, unsigned long flags, 48#define sys_mmap sys_mmap
48 unsigned long fd, unsigned long pgoff);
49#ifdef __tilegx__
50long sys_mmap(unsigned long addr, unsigned long len,
51 unsigned long prot, unsigned long flags,
52 unsigned long fd, off_t pgoff);
53#endif 49#endif
54 50
55/* kernel/process.c */
56long sys_clone(unsigned long clone_flags, unsigned long newsp,
57 void __user *parent_tid, void __user *child_tid);
58long _sys_clone(unsigned long clone_flags, unsigned long newsp,
59 void __user *parent_tid, void __user *child_tid,
60 struct pt_regs *regs);
61long sys_fork(void);
62long _sys_fork(struct pt_regs *regs);
63long sys_vfork(void);
64long _sys_vfork(struct pt_regs *regs);
65long sys_execve(const char __user *filename,
66 const char __user *const __user *argv,
67 const char __user *const __user *envp);
68long _sys_execve(const char __user *filename,
69 const char __user *const __user *argv,
70 const char __user *const __user *envp, struct pt_regs *regs);
71
72/* kernel/signal.c */
73long sys_sigaltstack(const stack_t __user *, stack_t __user *);
74long _sys_sigaltstack(const stack_t __user *, stack_t __user *,
75 struct pt_regs *);
76long sys_rt_sigreturn(void);
77long _sys_rt_sigreturn(struct pt_regs *regs);
78
79/* platform-independent functions */
80long sys_rt_sigsuspend(sigset_t __user *unewset, size_t sigsetsize);
81long sys_rt_sigaction(int sig, const struct sigaction __user *act,
82 struct sigaction __user *oact, size_t sigsetsize);
83
84#ifndef __tilegx__ 51#ifndef __tilegx__
85/* mm/fault.c */ 52/* mm/fault.c */
86int sys_cmpxchg_badaddr(unsigned long address); 53long sys_cmpxchg_badaddr(unsigned long address, struct pt_regs *);
87int _sys_cmpxchg_badaddr(unsigned long address, struct pt_regs *); 54long _sys_cmpxchg_badaddr(unsigned long address);
88#endif 55#endif
89 56
90#ifdef CONFIG_COMPAT 57#ifdef CONFIG_COMPAT
91long compat_sys_execve(const char __user *path,
92 const compat_uptr_t __user *argv,
93 const compat_uptr_t __user *envp);
94long _compat_sys_execve(const char __user *path,
95 const compat_uptr_t __user *argv,
96 const compat_uptr_t __user *envp,
97 struct pt_regs *regs);
98long compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr,
99 struct compat_sigaltstack __user *uoss_ptr);
100long _compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr,
101 struct compat_sigaltstack __user *uoss_ptr,
102 struct pt_regs *regs);
103long compat_sys_rt_sigreturn(void);
104long _compat_sys_rt_sigreturn(struct pt_regs *regs);
105
106/* These four are not defined for 64-bit, but serve as "compat" syscalls. */ 58/* These four are not defined for 64-bit, but serve as "compat" syscalls. */
107long sys_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg); 59long sys_fcntl64(unsigned int fd, unsigned int cmd, unsigned long arg);
108long sys_fstat64(unsigned long fd, struct stat64 __user *statbuf); 60long sys_fstat64(unsigned long fd, struct stat64 __user *statbuf);
@@ -110,4 +62,15 @@ long sys_truncate64(const char __user *path, loff_t length);
110long sys_ftruncate64(unsigned int fd, loff_t length); 62long sys_ftruncate64(unsigned int fd, loff_t length);
111#endif 63#endif
112 64
65/* These are the intvec*.S trampolines. */
66long _sys_sigaltstack(const stack_t __user *, stack_t __user *);
67long _sys_rt_sigreturn(void);
68long _sys_clone(unsigned long clone_flags, unsigned long newsp,
69 void __user *parent_tid, void __user *child_tid);
70long _sys_execve(const char __user *filename,
71 const char __user *const __user *argv,
72 const char __user *const __user *envp);
73
74#include <asm-generic/syscalls.h>
75
113#endif /* _ASM_TILE_SYSCALLS_H */ 76#endif /* _ASM_TILE_SYSCALLS_H */
diff --git a/arch/tile/include/asm/system.h b/arch/tile/include/asm/system.h
index f749be327ce0..23d1842f4839 100644
--- a/arch/tile/include/asm/system.h
+++ b/arch/tile/include/asm/system.h
@@ -89,6 +89,27 @@
89#define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */ 89#define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */
90#endif 90#endif
91 91
92#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
93#include <hv/syscall_public.h>
94/*
95 * Issue an uncacheable load to each memory controller, then
96 * wait until those loads have completed.
97 */
98static inline void __mb_incoherent(void)
99{
100 long clobber_r10;
101 asm volatile("swint2"
102 : "=R10" (clobber_r10)
103 : "R10" (HV_SYS_fence_incoherent)
104 : "r0", "r1", "r2", "r3", "r4",
105 "r5", "r6", "r7", "r8", "r9",
106 "r11", "r12", "r13", "r14",
107 "r15", "r16", "r17", "r18", "r19",
108 "r20", "r21", "r22", "r23", "r24",
109 "r25", "r26", "r27", "r28", "r29");
110}
111#endif
112
92/* Fence to guarantee visibility of stores to incoherent memory. */ 113/* Fence to guarantee visibility of stores to incoherent memory. */
93static inline void 114static inline void
94mb_incoherent(void) 115mb_incoherent(void)
@@ -97,7 +118,6 @@ mb_incoherent(void)
97 118
98#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS() 119#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
99 { 120 {
100 int __mb_incoherent(void);
101#if CHIP_HAS_TILE_WRITE_PENDING() 121#if CHIP_HAS_TILE_WRITE_PENDING()
102 const unsigned long WRITE_TIMEOUT_CYCLES = 400; 122 const unsigned long WRITE_TIMEOUT_CYCLES = 400;
103 unsigned long start = get_cycles_low(); 123 unsigned long start = get_cycles_low();
@@ -161,7 +181,7 @@ extern struct task_struct *_switch_to(struct task_struct *prev,
161/* Helper function for _switch_to(). */ 181/* Helper function for _switch_to(). */
162extern struct task_struct *__switch_to(struct task_struct *prev, 182extern struct task_struct *__switch_to(struct task_struct *prev,
163 struct task_struct *next, 183 struct task_struct *next,
164 unsigned long new_system_save_1_0); 184 unsigned long new_system_save_k_0);
165 185
166/* Address that switched-away from tasks are at. */ 186/* Address that switched-away from tasks are at. */
167extern unsigned long get_switch_to_pc(void); 187extern unsigned long get_switch_to_pc(void);
@@ -214,13 +234,6 @@ int hardwall_deactivate(struct task_struct *task);
214} while (0) 234} while (0)
215#endif 235#endif
216 236
217/* Invoke the simulator "syscall" mechanism (see arch/tile/kernel/entry.S). */
218extern int _sim_syscall(int syscall_num, ...);
219#define sim_syscall(syscall_num, ...) \
220 _sim_syscall(SIM_CONTROL_SYSCALL + \
221 ((syscall_num) << _SIM_CONTROL_OPERATOR_BITS), \
222 ## __VA_ARGS__)
223
224/* 237/*
225 * Kernel threads can check to see if they need to migrate their 238 * Kernel threads can check to see if they need to migrate their
226 * stack whenever they return from a context switch; for user 239 * stack whenever they return from a context switch; for user
diff --git a/arch/tile/include/asm/thread_info.h b/arch/tile/include/asm/thread_info.h
index 3872f2b345d2..bc4f562bd459 100644
--- a/arch/tile/include/asm/thread_info.h
+++ b/arch/tile/include/asm/thread_info.h
@@ -68,6 +68,7 @@ struct thread_info {
68#else 68#else
69#define THREAD_SIZE_ORDER (0) 69#define THREAD_SIZE_ORDER (0)
70#endif 70#endif
71#define THREAD_SIZE_PAGES (1 << THREAD_SIZE_ORDER)
71 72
72#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) 73#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
73#define LOG2_THREAD_SIZE (PAGE_SHIFT + THREAD_SIZE_ORDER) 74#define LOG2_THREAD_SIZE (PAGE_SHIFT + THREAD_SIZE_ORDER)
@@ -83,7 +84,7 @@ register unsigned long stack_pointer __asm__("sp");
83 ((struct thread_info *)(stack_pointer & -THREAD_SIZE)) 84 ((struct thread_info *)(stack_pointer & -THREAD_SIZE))
84 85
85#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR 86#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
86extern struct thread_info *alloc_thread_info(struct task_struct *task); 87extern struct thread_info *alloc_thread_info_node(struct task_struct *task, int node);
87extern void free_thread_info(struct thread_info *info); 88extern void free_thread_info(struct thread_info *info);
88 89
89/* Sit on a nap instruction until interrupted. */ 90/* Sit on a nap instruction until interrupted. */
@@ -124,6 +125,7 @@ extern void cpu_idle_on_new_stack(struct thread_info *old_ti,
124#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */ 125#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */
125#define TIF_SECCOMP 6 /* secure computing */ 126#define TIF_SECCOMP 6 /* secure computing */
126#define TIF_MEMDIE 7 /* OOM killer at work */ 127#define TIF_MEMDIE 7 /* OOM killer at work */
128#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */
127 129
128#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) 130#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
129#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) 131#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
@@ -133,10 +135,12 @@ extern void cpu_idle_on_new_stack(struct thread_info *old_ti,
133#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) 135#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
134#define _TIF_SECCOMP (1<<TIF_SECCOMP) 136#define _TIF_SECCOMP (1<<TIF_SECCOMP)
135#define _TIF_MEMDIE (1<<TIF_MEMDIE) 137#define _TIF_MEMDIE (1<<TIF_MEMDIE)
138#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
136 139
137/* Work to do on any return to user space. */ 140/* Work to do on any return to user space. */
138#define _TIF_ALLWORK_MASK \ 141#define _TIF_ALLWORK_MASK \
139 (_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_SINGLESTEP|_TIF_ASYNC_TLB) 142 (_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_SINGLESTEP|\
143 _TIF_ASYNC_TLB|_TIF_NOTIFY_RESUME)
140 144
141/* 145/*
142 * Thread-synchronous status. 146 * Thread-synchronous status.
diff --git a/arch/tile/include/asm/timex.h b/arch/tile/include/asm/timex.h
index 3baf5fc4c0a1..29921f0b86da 100644
--- a/arch/tile/include/asm/timex.h
+++ b/arch/tile/include/asm/timex.h
@@ -38,6 +38,9 @@ static inline cycles_t get_cycles(void)
38 38
39cycles_t get_clock_rate(void); 39cycles_t get_clock_rate(void);
40 40
41/* Convert nanoseconds to core clock cycles. */
42cycles_t ns2cycles(unsigned long nsecs);
43
41/* Called at cpu initialization to set some low-level constants. */ 44/* Called at cpu initialization to set some low-level constants. */
42void setup_clock(void); 45void setup_clock(void);
43 46
diff --git a/arch/tile/include/asm/topology.h b/arch/tile/include/asm/topology.h
index 343172d422a9..6fdd0c860193 100644
--- a/arch/tile/include/asm/topology.h
+++ b/arch/tile/include/asm/topology.h
@@ -44,25 +44,64 @@ static inline const struct cpumask *cpumask_of_node(int node)
44/* For now, use numa node -1 for global allocation. */ 44/* For now, use numa node -1 for global allocation. */
45#define pcibus_to_node(bus) ((void)(bus), -1) 45#define pcibus_to_node(bus) ((void)(bus), -1)
46 46
47/*
48 * TILE architecture has many cores integrated in one processor, so we need
49 * setup bigger balance_interval for both CPU/NODE scheduling domains to
50 * reduce process scheduling costs.
51 */
52
53/* sched_domains SD_CPU_INIT for TILE architecture */
54#define SD_CPU_INIT (struct sched_domain) { \
55 .min_interval = 4, \
56 .max_interval = 128, \
57 .busy_factor = 64, \
58 .imbalance_pct = 125, \
59 .cache_nice_tries = 1, \
60 .busy_idx = 2, \
61 .idle_idx = 1, \
62 .newidle_idx = 0, \
63 .wake_idx = 0, \
64 .forkexec_idx = 0, \
65 \
66 .flags = 1*SD_LOAD_BALANCE \
67 | 1*SD_BALANCE_NEWIDLE \
68 | 1*SD_BALANCE_EXEC \
69 | 1*SD_BALANCE_FORK \
70 | 0*SD_BALANCE_WAKE \
71 | 0*SD_WAKE_AFFINE \
72 | 0*SD_PREFER_LOCAL \
73 | 0*SD_SHARE_CPUPOWER \
74 | 0*SD_SHARE_PKG_RESOURCES \
75 | 0*SD_SERIALIZE \
76 , \
77 .last_balance = jiffies, \
78 .balance_interval = 32, \
79}
80
47/* sched_domains SD_NODE_INIT for TILE architecture */ 81/* sched_domains SD_NODE_INIT for TILE architecture */
48#define SD_NODE_INIT (struct sched_domain) { \ 82#define SD_NODE_INIT (struct sched_domain) { \
49 .min_interval = 8, \ 83 .min_interval = 16, \
50 .max_interval = 32, \ 84 .max_interval = 512, \
51 .busy_factor = 32, \ 85 .busy_factor = 32, \
52 .imbalance_pct = 125, \ 86 .imbalance_pct = 125, \
53 .cache_nice_tries = 1, \ 87 .cache_nice_tries = 1, \
54 .busy_idx = 3, \ 88 .busy_idx = 3, \
55 .idle_idx = 1, \ 89 .idle_idx = 1, \
56 .newidle_idx = 2, \ 90 .newidle_idx = 2, \
57 .wake_idx = 1, \ 91 .wake_idx = 1, \
58 .flags = SD_LOAD_BALANCE \ 92 .flags = 1*SD_LOAD_BALANCE \
59 | SD_BALANCE_NEWIDLE \ 93 | 1*SD_BALANCE_NEWIDLE \
60 | SD_BALANCE_EXEC \ 94 | 1*SD_BALANCE_EXEC \
61 | SD_BALANCE_FORK \ 95 | 1*SD_BALANCE_FORK \
62 | SD_WAKE_AFFINE \ 96 | 0*SD_BALANCE_WAKE \
63 | SD_SERIALIZE, \ 97 | 0*SD_WAKE_AFFINE \
64 .last_balance = jiffies, \ 98 | 0*SD_PREFER_LOCAL \
65 .balance_interval = 1, \ 99 | 0*SD_SHARE_CPUPOWER \
100 | 0*SD_SHARE_PKG_RESOURCES \
101 | 1*SD_SERIALIZE \
102 , \
103 .last_balance = jiffies, \
104 .balance_interval = 128, \
66} 105}
67 106
68/* By definition, we create nodes based on online memory. */ 107/* By definition, we create nodes based on online memory. */
diff --git a/arch/tile/include/asm/traps.h b/arch/tile/include/asm/traps.h
index 432a9c15c8a2..5f20f920f932 100644
--- a/arch/tile/include/asm/traps.h
+++ b/arch/tile/include/asm/traps.h
@@ -15,10 +15,14 @@
15#ifndef _ASM_TILE_TRAPS_H 15#ifndef _ASM_TILE_TRAPS_H
16#define _ASM_TILE_TRAPS_H 16#define _ASM_TILE_TRAPS_H
17 17
18#include <arch/chip.h>
19
18/* mm/fault.c */ 20/* mm/fault.c */
19void do_page_fault(struct pt_regs *, int fault_num, 21void do_page_fault(struct pt_regs *, int fault_num,
20 unsigned long address, unsigned long write); 22 unsigned long address, unsigned long write);
23#if CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC()
21void do_async_page_fault(struct pt_regs *); 24void do_async_page_fault(struct pt_regs *);
25#endif
22 26
23#ifndef __tilegx__ 27#ifndef __tilegx__
24/* 28/*
@@ -59,4 +63,8 @@ void do_hardwall_trap(struct pt_regs *, int fault_num);
59void do_breakpoint(struct pt_regs *, int fault_num); 63void do_breakpoint(struct pt_regs *, int fault_num);
60 64
61 65
66#ifdef __tilegx__
67void gx_singlestep_handle(struct pt_regs *, int fault_num);
68#endif
69
62#endif /* _ASM_TILE_SYSCALLS_H */ 70#endif /* _ASM_TILE_SYSCALLS_H */
diff --git a/arch/tile/include/asm/unistd.h b/arch/tile/include/asm/unistd.h
index f2e3ff485333..f70bf1c541f1 100644
--- a/arch/tile/include/asm/unistd.h
+++ b/arch/tile/include/asm/unistd.h
@@ -15,7 +15,7 @@
15#if !defined(_ASM_TILE_UNISTD_H) || defined(__SYSCALL) 15#if !defined(_ASM_TILE_UNISTD_H) || defined(__SYSCALL)
16#define _ASM_TILE_UNISTD_H 16#define _ASM_TILE_UNISTD_H
17 17
18#ifndef __LP64__ 18#if !defined(__LP64__) || defined(__SYSCALL_COMPAT)
19/* Use the flavor of this syscall that matches the 32-bit API better. */ 19/* Use the flavor of this syscall that matches the 32-bit API better. */
20#define __ARCH_WANT_SYNC_FILE_RANGE2 20#define __ARCH_WANT_SYNC_FILE_RANGE2
21#endif 21#endif
@@ -41,6 +41,7 @@ __SYSCALL(__NR_cmpxchg_badaddr, sys_cmpxchg_badaddr)
41#ifdef CONFIG_COMPAT 41#ifdef CONFIG_COMPAT
42#define __ARCH_WANT_SYS_LLSEEK 42#define __ARCH_WANT_SYS_LLSEEK
43#endif 43#endif
44#define __ARCH_WANT_SYS_NEWFSTATAT
44#endif 45#endif
45 46
46#endif /* _ASM_TILE_UNISTD_H */ 47#endif /* _ASM_TILE_UNISTD_H */
diff --git a/arch/tile/include/asm/vga.h b/arch/tile/include/asm/vga.h
new file mode 100644
index 000000000000..7b46e754d611
--- /dev/null
+++ b/arch/tile/include/asm/vga.h
@@ -0,0 +1,39 @@
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * Access to VGA videoram.
15 */
16
17#ifndef _ASM_TILE_VGA_H
18#define _ASM_TILE_VGA_H
19
20#include <asm/io.h>
21
22#define VT_BUF_HAVE_RW
23
24static inline void scr_writew(u16 val, volatile u16 *addr)
25{
26 __raw_writew(val, (volatile u16 __iomem *) addr);
27}
28
29static inline u16 scr_readw(volatile const u16 *addr)
30{
31 return __raw_readw((volatile const u16 __iomem *) addr);
32}
33
34#define vga_readb(a) readb((u8 __iomem *)(a))
35#define vga_writeb(v,a) writeb(v, (u8 __iomem *)(a))
36
37#define VGA_MAP_MEM(x,s) ((unsigned long) ioremap(x, s))
38
39#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-17 06:14:36 -0400