[SPARC64]: Fix bogus flush instruction usage.

Some of the trap code was still assuming that alternate
global %g6 was hard coded with current_thread_info().
Let's just consistently flush at KERNBASE when we need
a pipeline synchronization.  That's locked into the TLB
and will always work.

Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 3 insertions, 1 deletions

diff --git a/arch/sparc64/lib/clear_page.S b/arch/sparc64/lib/clear_page.S
index b59884ef051d..cdc634bceba0 100644
--- a/arch/sparc64/lib/clear_page.S
+++ b/arch/sparc64/lib/clear_page.S
@@ -9,6 +9,7 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/spitfire.h>
+#include <asm/head.h>
 
         /* What we used to do was lock a TLB entry into a specific
          * TLB slot, clear the page with interrupts disabled, then
@@ -66,7 +67,8 @@ clear_user_page:	/* %o0=dest, %o1=vaddr */
         wrpr            %o4, PSTATE_IE, %pstate
         stxa            %o0, [%g3] ASI_DMMU
         stxa            %g1, [%g0] ASI_DTLB_DATA_IN
-        flush           %g6
+        sethi           %hi(KERNBASE), %g1
+        flush           %g1
         wrpr            %o4, 0x0, %pstate
 
         mov             1, %o4