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authorDavid S. Miller <davem@davemloft.net>2005-05-20 14:40:32 -0400
committerDavid S. Miller <davem@davemloft.net>2005-05-20 14:40:32 -0400
commita228dfd5dc4b92288ea22d427b2bfc48ba5bb8b0 (patch)
treebd3c9a5892a5e3823427c9d614fd6c9aee96c1fb /arch/sparc64/kernel
parent37e0915b701281182cea9fc90e894d10addf134a (diff)
[SPARC64]: Fix bad performance side effect of strbuf timeout changes.
The recent change to add a timeout to strbuf flushing had a negative performance impact. The udelay()'s are too long, and they were done in the wrong order wrt. the register read checks. Fix both, and things are happy again. There are more possible improvements in this area. In fact, PCI streaming buffer flushing seems to be part of the bottleneck in network receive performance on my SunBlade1000 box. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel')
-rw-r--r--arch/sparc64/kernel/pci_iommu.c16
-rw-r--r--arch/sparc64/kernel/sbus.c4
2 files changed, 11 insertions, 9 deletions
diff --git a/arch/sparc64/kernel/pci_iommu.c b/arch/sparc64/kernel/pci_iommu.c
index f009b1b45501..33ca56c90da2 100644
--- a/arch/sparc64/kernel/pci_iommu.c
+++ b/arch/sparc64/kernel/pci_iommu.c
@@ -392,14 +392,16 @@ static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu *iommu,
392 flushreg = strbuf->strbuf_ctxflush; 392 flushreg = strbuf->strbuf_ctxflush;
393 matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx); 393 matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
394 394
395 limit = 10000; 395 limit = 100000;
396 do { 396 pci_iommu_write(flushreg, ctx);
397 pci_iommu_write(flushreg, ctx); 397 for(;;) {
398 udelay(10); 398 if (((long)pci_iommu_read(matchreg)) >= 0L)
399 break;
399 limit--; 400 limit--;
400 if (!limit) 401 if (!limit)
401 break; 402 break;
402 } while(((long)pci_iommu_read(matchreg)) < 0L); 403 udelay(1);
404 }
403 if (!limit) 405 if (!limit)
404 printk(KERN_WARNING "pci_strbuf_flush: ctx flush " 406 printk(KERN_WARNING "pci_strbuf_flush: ctx flush "
405 "timeout vaddr[%08x] ctx[%lx]\n", 407 "timeout vaddr[%08x] ctx[%lx]\n",
@@ -414,12 +416,12 @@ static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu *iommu,
414 pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa); 416 pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
415 (void) pci_iommu_read(iommu->write_complete_reg); 417 (void) pci_iommu_read(iommu->write_complete_reg);
416 418
417 limit = 10000; 419 limit = 100000;
418 while (!PCI_STC_FLUSHFLAG_SET(strbuf)) { 420 while (!PCI_STC_FLUSHFLAG_SET(strbuf)) {
419 limit--; 421 limit--;
420 if (!limit) 422 if (!limit)
421 break; 423 break;
422 udelay(10); 424 udelay(1);
423 membar("#LoadLoad"); 425 membar("#LoadLoad");
424 } 426 }
425 if (!limit) 427 if (!limit)
diff --git a/arch/sparc64/kernel/sbus.c b/arch/sparc64/kernel/sbus.c
index d3eca98e1fe7..76ea6455433f 100644
--- a/arch/sparc64/kernel/sbus.c
+++ b/arch/sparc64/kernel/sbus.c
@@ -133,12 +133,12 @@ static void sbus_strbuf_flush(struct sbus_iommu *iommu, u32 base, unsigned long
133 iommu->strbuf_regs + STRBUF_FSYNC); 133 iommu->strbuf_regs + STRBUF_FSYNC);
134 upa_readq(iommu->sbus_control_reg); 134 upa_readq(iommu->sbus_control_reg);
135 135
136 limit = 10000; 136 limit = 100000;
137 while (iommu->strbuf_flushflag == 0UL) { 137 while (iommu->strbuf_flushflag == 0UL) {
138 limit--; 138 limit--;
139 if (!limit) 139 if (!limit)
140 break; 140 break;
141 udelay(10); 141 udelay(1);
142 membar("#LoadLoad"); 142 membar("#LoadLoad");
143 } 143 }
144 if (!limit) 144 if (!limit)