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authorDavid S. Miller <davem@sunset.davemloft.net>2007-03-09 01:46:02 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2007-04-26 04:55:15 -0400
commit8d3aee937596d2ca6676c2c27789751445bf0bc9 (patch)
treeb22a333a9947ab94d8c35c13b4989cde53630ac9 /arch/sparc64/kernel/pci_sun4v.c
parent0bae5f81b6f8130f5197e59b0e2ad6820c766b2b (diff)
[SPARC64]: Kill pci_controller->base_address_update().
Implemented but never actually used. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/pci_sun4v.c')
-rw-r--r--arch/sparc64/kernel/pci_sun4v.c46
1 files changed, 0 insertions, 46 deletions
diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c
index ce0417e776a1..f9cd9f620d4e 100644
--- a/arch/sparc64/kernel/pci_sun4v.c
+++ b/arch/sparc64/kernel/pci_sun4v.c
@@ -698,51 +698,6 @@ static void pci_sun4v_scan_bus(struct pci_controller_info *p)
698 /* XXX register error interrupt handlers XXX */ 698 /* XXX register error interrupt handlers XXX */
699} 699}
700 700
701static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
702{
703 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
704 struct resource *res, *root;
705 u32 reg;
706 int where, size, is_64bit;
707
708 res = &pdev->resource[resource];
709 if (resource < 6) {
710 where = PCI_BASE_ADDRESS_0 + (resource * 4);
711 } else if (resource == PCI_ROM_RESOURCE) {
712 where = pdev->rom_base_reg;
713 } else {
714 /* Somebody might have asked allocation of a non-standard resource */
715 return;
716 }
717
718 /* XXX 64-bit MEM handling is not %100 correct... XXX */
719 is_64bit = 0;
720 if (res->flags & IORESOURCE_IO)
721 root = &pbm->io_space;
722 else {
723 root = &pbm->mem_space;
724 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
725 == PCI_BASE_ADDRESS_MEM_TYPE_64)
726 is_64bit = 1;
727 }
728
729 size = res->end - res->start;
730 pci_read_config_dword(pdev, where, &reg);
731 reg = ((reg & size) |
732 (((u32)(res->start - root->start)) & ~size));
733 if (resource == PCI_ROM_RESOURCE) {
734 reg |= PCI_ROM_ADDRESS_ENABLE;
735 res->flags |= IORESOURCE_ROM_ENABLE;
736 }
737 pci_write_config_dword(pdev, where, reg);
738
739 /* This knows that the upper 32-bits of the address
740 * must be zero. Our PCI common layer enforces this.
741 */
742 if (is_64bit)
743 pci_write_config_dword(pdev, where + 4, 0);
744}
745
746static unsigned long probe_existing_entries(struct pci_pbm_info *pbm, 701static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
747 struct pci_iommu *iommu) 702 struct pci_iommu *iommu)
748{ 703{
@@ -1378,7 +1333,6 @@ void sun4v_pci_init(struct device_node *dp, char *model_name)
1378 p->pbms_same_domain = 0; 1333 p->pbms_same_domain = 0;
1379 1334
1380 p->scan_bus = pci_sun4v_scan_bus; 1335 p->scan_bus = pci_sun4v_scan_bus;
1381 p->base_address_update = pci_sun4v_base_address_update;
1382#ifdef CONFIG_PCI_MSI 1336#ifdef CONFIG_PCI_MSI
1383 p->setup_msi_irq = pci_sun4v_setup_msi_irq; 1337 p->setup_msi_irq = pci_sun4v_setup_msi_irq;
1384 p->teardown_msi_irq = pci_sun4v_teardown_msi_irq; 1338 p->teardown_msi_irq = pci_sun4v_teardown_msi_irq;