sparc64: Make PAGE_OFFSET variable.

Choose PAGE_OFFSET dynamically based upon cpu type.

Original UltraSPARC-I (spitfire) chips only supported a 44-bit
virtual address space.

Newer chips (T4 and later) support 52-bit virtual addresses
and up to 47-bits of physical memory space.

Therefore we have to adjust PAGE_SIZE dynamically based upon
the capabilities of the chip.

Note that this change alone does not allow us to support > 43-bit
physical memory, to do that we need to re-arrange our page table
support.  The current encodings of the pmd_t and pgd_t pointers
restricts us to "32 + 11" == 43 bits.

This change can waste quite a bit of memory for the various tables.
In particular, a future change should work to size and allocate
kern_linear_bitmap[] and sparc64_valid_addr_bitmap[] dynamically.
This isn't easy as we really cannot take a TLB miss when accessing
kern_linear_bitmap[].  We'd have to lock it into the TLB or similar.

Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Bob Picco <bob.picco@oracle.com>

1 files changed, 92 insertions, 0 deletions

diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index e295a5b30ac9..7a97b5a28b4b 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -1557,6 +1557,96 @@ unsigned long __init find_ecache_flush_span(unsigned long size)
         return ~0UL;
 }
 
+unsigned long PAGE_OFFSET;
+EXPORT_SYMBOL(PAGE_OFFSET);
+
+static void __init page_offset_shift_patch_one(unsigned int *insn, unsigned long phys_bits)
+{
+        unsigned long final_shift;
+        unsigned int val = *insn;
+        unsigned int cnt;
+
+        /* We are patching in ilog2(max_supported_phys_address), and
+         * we are doing so in a manner similar to a relocation addend.
+         * That is, we are adding the shift value to whatever value
+         * is in the shift instruction count field already.
+         */
+        cnt = (val & 0x3f);
+        val &= ~0x3f;
+
+        /* If we are trying to shift >= 64 bits, clear the destination
+         * register.  This can happen when phys_bits ends up being equal
+         * to MAX_PHYS_ADDRESS_BITS.
+         */
+        final_shift = (cnt + (64 - phys_bits));
+        if (final_shift >= 64) {
+                unsigned int rd = (val >> 25) & 0x1f;
+
+                val = 0x80100000 | (rd << 25);
+        } else {
+                val |= final_shift;
+        }
+        *insn = val;
+
+        __asm__ __volatile__("flush     %0"
+                             : /* no outputs */
+                             : "r" (insn));
+}
+
+static void __init page_offset_shift_patch(unsigned long phys_bits)
+{
+        extern unsigned int __page_offset_shift_patch;
+        extern unsigned int __page_offset_shift_patch_end;
+        unsigned int *p;
+
+        p = &__page_offset_shift_patch;
+        while (p < &__page_offset_shift_patch_end) {
+                unsigned int *insn = (unsigned int *)(unsigned long)*p;
+
+                page_offset_shift_patch_one(insn, phys_bits);
+
+                p++;
+        }
+}
+
+static void __init setup_page_offset(void)
+{
+        unsigned long max_phys_bits = 40;
+
+        if (tlb_type == cheetah || tlb_type == cheetah_plus) {
+                max_phys_bits = 42;
+        } else if (tlb_type == hypervisor) {
+                switch (sun4v_chip_type) {
+                case SUN4V_CHIP_NIAGARA1:
+                case SUN4V_CHIP_NIAGARA2:
+                        max_phys_bits = 39;
+                        break;
+                case SUN4V_CHIP_NIAGARA3:
+                        max_phys_bits = 43;
+                        break;
+                case SUN4V_CHIP_NIAGARA4:
+                case SUN4V_CHIP_NIAGARA5:
+                case SUN4V_CHIP_SPARC64X:
+                default:
+                        max_phys_bits = 47;
+                        break;
+                }
+        }
+
+        if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
+                prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
+                            max_phys_bits);
+                prom_halt();
+        }
+
+        PAGE_OFFSET = PAGE_OFFSET_BY_BITS(max_phys_bits);
+
+        pr_info("PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
+                PAGE_OFFSET, max_phys_bits);
+
+        page_offset_shift_patch(max_phys_bits);
+}
+
 static void __init tsb_phys_patch(void)
 {
         struct tsb_ldquad_phys_patch_entry *pquad;
@@ -1763,6 +1853,8 @@ void __init paging_init(void)
         unsigned long real_end, i;
         int node;
 
+        setup_page_offset();
+
         /* These build time checkes make sure that the dcache_dirty_cpu()
          * page->flags usage will work.
          *