sparc64: Make PAGE_OFFSET variable.

Choose PAGE_OFFSET dynamically based upon cpu type.

Original UltraSPARC-I (spitfire) chips only supported a 44-bit
virtual address space.

Newer chips (T4 and later) support 52-bit virtual addresses
and up to 47-bits of physical memory space.

Therefore we have to adjust PAGE_SIZE dynamically based upon
the capabilities of the chip.

Note that this change alone does not allow us to support > 43-bit
physical memory, to do that we need to re-arrange our page table
support.  The current encodings of the pmd_t and pgd_t pointers
restricts us to "32 + 11" == 43 bits.

This change can waste quite a bit of memory for the various tables.
In particular, a future change should work to size and allocate
kern_linear_bitmap[] and sparc64_valid_addr_bitmap[] dynamically.
This isn't easy as we really cannot take a TLB miss when accessing
kern_linear_bitmap[].  We'd have to lock it into the TLB or similar.

Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Bob Picco <bob.picco@oracle.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/sparc/lib/clear_page.S b/arch/sparc/lib/clear_page.S
index 77e531f6c2a7..46272dfc26e8 100644
--- a/arch/sparc/lib/clear_page.S
+++ b/arch/sparc/lib/clear_page.S
@@ -37,10 +37,10 @@ _clear_page:		/* %o0=dest */
         .globl          clear_user_page
 clear_user_page:        /* %o0=dest, %o1=vaddr */
         lduw            [%g6 + TI_PRE_COUNT], %o2
-        sethi           %uhi(PAGE_OFFSET), %g2
+        sethi           %hi(PAGE_OFFSET), %g2
         sethi           %hi(PAGE_SIZE), %o4
 
-        sllx            %g2, 32, %g2
+        ldx             [%g2 + %lo(PAGE_OFFSET)], %g2
         sethi           %hi(PAGE_KERNEL_LOCKED), %g3
 
         ldx             [%g3 + %lo(PAGE_KERNEL_LOCKED)], %g3