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authorAllen Pais <allen.pais@oracle.com>2013-07-23 07:20:38 -0400
committerDavid S. Miller <davem@davemloft.net>2013-07-31 22:10:03 -0400
commit4e96377983d2e060dd89703f1846ad920af9e17f (patch)
tree469c869ddb876fa9138c63805fe830035afbf60c /arch/sparc/kernel
parent64ccccf8525fee499625b517c0faadf784c79e93 (diff)
cpu hw caps support for sparc64x
Signed-off-by: Allen Pais <allen.pais@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/kernel')
-rw-r--r--arch/sparc/kernel/setup_64.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c
index 13785547e435..3fdb455e3318 100644
--- a/arch/sparc/kernel/setup_64.c
+++ b/arch/sparc/kernel/setup_64.c
@@ -499,12 +499,14 @@ static void __init init_sparc64_elf_hwcap(void)
499 sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || 499 sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
500 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || 500 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
501 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || 501 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
502 sun4v_chip_type == SUN4V_CHIP_NIAGARA5) 502 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
503 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
503 cap |= HWCAP_SPARC_BLKINIT; 504 cap |= HWCAP_SPARC_BLKINIT;
504 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || 505 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
505 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || 506 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
506 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || 507 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
507 sun4v_chip_type == SUN4V_CHIP_NIAGARA5) 508 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
509 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
508 cap |= HWCAP_SPARC_N2; 510 cap |= HWCAP_SPARC_N2;
509 } 511 }
510 512
@@ -530,13 +532,15 @@ static void __init init_sparc64_elf_hwcap(void)
530 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || 532 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
531 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || 533 sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
532 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || 534 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
533 sun4v_chip_type == SUN4V_CHIP_NIAGARA5) 535 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
536 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
534 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 | 537 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
535 AV_SPARC_ASI_BLK_INIT | 538 AV_SPARC_ASI_BLK_INIT |
536 AV_SPARC_POPC); 539 AV_SPARC_POPC);
537 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || 540 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
538 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || 541 sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
539 sun4v_chip_type == SUN4V_CHIP_NIAGARA5) 542 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
543 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
540 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC | 544 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
541 AV_SPARC_FMAF); 545 AV_SPARC_FMAF);
542 } 546 }