aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sparc/kernel/head_64.S
diff options
context:
space:
mode:
authorDavid S. Miller <davem@davemloft.net>2011-09-11 13:42:20 -0400
committerDavid S. Miller <davem@davemloft.net>2011-09-16 17:21:33 -0400
commit08cefa9fa7e5b3ddaefb8b7bfa408d148429c08d (patch)
tree07a33d960d2ce5d72733dd21cf8d179fd06d145a /arch/sparc/kernel/head_64.S
parent1a8e0da5937a6c87807083baa318cf8f98dac9aa (diff)
sparc64: Future proof Niagara cpu detection.
Recognize T4 and T5 chips. Treating them both as "T2 plus other stuff" should be extremely safe and make sure distributions will work when those chips actually ship to customers. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/kernel/head_64.S')
-rw-r--r--arch/sparc/kernel/head_64.S25
1 files changed, 22 insertions, 3 deletions
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index 0eac1b2fc53d..0d810c2f1d00 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -133,7 +133,7 @@ prom_sun4v_name:
133prom_niagara_prefix: 133prom_niagara_prefix:
134 .asciz "SUNW,UltraSPARC-T" 134 .asciz "SUNW,UltraSPARC-T"
135prom_sparc_prefix: 135prom_sparc_prefix:
136 .asciz "SPARC-T" 136 .asciz "SPARC-"
137 .align 4 137 .align 4
138prom_root_compatible: 138prom_root_compatible:
139 .skip 64 139 .skip 64
@@ -396,7 +396,7 @@ sun4v_chip_type:
396 or %g1, %lo(prom_cpu_compatible), %g1 396 or %g1, %lo(prom_cpu_compatible), %g1
397 sethi %hi(prom_sparc_prefix), %g7 397 sethi %hi(prom_sparc_prefix), %g7
398 or %g7, %lo(prom_sparc_prefix), %g7 398 or %g7, %lo(prom_sparc_prefix), %g7
399 mov 7, %g3 399 mov 6, %g3
40090: ldub [%g7], %g2 40090: ldub [%g7], %g2
401 ldub [%g1], %g4 401 ldub [%g1], %g4
402 cmp %g2, %g4 402 cmp %g2, %g4
@@ -408,10 +408,23 @@ sun4v_chip_type:
408 408
409 sethi %hi(prom_cpu_compatible), %g1 409 sethi %hi(prom_cpu_compatible), %g1
410 or %g1, %lo(prom_cpu_compatible), %g1 410 or %g1, %lo(prom_cpu_compatible), %g1
411 ldub [%g1 + 7], %g2 411 ldub [%g1 + 6], %g2
412 cmp %g2, 'T'
413 be,pt %xcc, 70f
414 cmp %g2, 'M'
415 bne,pn %xcc, 4f
416 nop
417
41870: ldub [%g1 + 7], %g2
412 cmp %g2, '3' 419 cmp %g2, '3'
413 be,pt %xcc, 5f 420 be,pt %xcc, 5f
414 mov SUN4V_CHIP_NIAGARA3, %g4 421 mov SUN4V_CHIP_NIAGARA3, %g4
422 cmp %g2, '4'
423 be,pt %xcc, 5f
424 mov SUN4V_CHIP_NIAGARA4, %g4
425 cmp %g2, '5'
426 be,pt %xcc, 5f
427 mov SUN4V_CHIP_NIAGARA5, %g4
415 ba,pt %xcc, 4f 428 ba,pt %xcc, 4f
416 nop 429 nop
417 430
@@ -545,6 +558,12 @@ niagara_tlb_fixup:
545 cmp %g1, SUN4V_CHIP_NIAGARA3 558 cmp %g1, SUN4V_CHIP_NIAGARA3
546 be,pt %xcc, niagara2_patch 559 be,pt %xcc, niagara2_patch
547 nop 560 nop
561 cmp %g1, SUN4V_CHIP_NIAGARA4
562 be,pt %xcc, niagara2_patch
563 nop
564 cmp %g1, SUN4V_CHIP_NIAGARA5
565 be,pt %xcc, niagara2_patch
566 nop
548 567
549 call generic_patch_copyops 568 call generic_patch_copyops
550 nop 569 nop