aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sparc/kernel/cpu.c
diff options
context:
space:
mode:
authorDavid S. Miller <davem@davemloft.net>2011-09-11 13:42:20 -0400
committerDavid S. Miller <davem@davemloft.net>2011-09-16 17:21:33 -0400
commit08cefa9fa7e5b3ddaefb8b7bfa408d148429c08d (patch)
tree07a33d960d2ce5d72733dd21cf8d179fd06d145a /arch/sparc/kernel/cpu.c
parent1a8e0da5937a6c87807083baa318cf8f98dac9aa (diff)
sparc64: Future proof Niagara cpu detection.
Recognize T4 and T5 chips. Treating them both as "T2 plus other stuff" should be extremely safe and make sure distributions will work when those chips actually ship to customers. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/kernel/cpu.c')
-rw-r--r--arch/sparc/kernel/cpu.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c
index 9810fd881058..ba9b1cec4e6b 100644
--- a/arch/sparc/kernel/cpu.c
+++ b/arch/sparc/kernel/cpu.c
@@ -481,6 +481,18 @@ static void __init sun4v_cpu_probe(void)
481 sparc_pmu_type = "niagara3"; 481 sparc_pmu_type = "niagara3";
482 break; 482 break;
483 483
484 case SUN4V_CHIP_NIAGARA4:
485 sparc_cpu_type = "UltraSparc T4 (Niagara4)";
486 sparc_fpu_type = "UltraSparc T4 integrated FPU";
487 sparc_pmu_type = "niagara4";
488 break;
489
490 case SUN4V_CHIP_NIAGARA5:
491 sparc_cpu_type = "UltraSparc T5 (Niagara5)";
492 sparc_fpu_type = "UltraSparc T5 integrated FPU";
493 sparc_pmu_type = "niagara5";
494 break;
495
484 default: 496 default:
485 printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n", 497 printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
486 prom_cpu_compatible); 498 prom_cpu_compatible);