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authorPaul Mundt <lethal@linux-sh.org>2008-07-02 00:58:38 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-07-28 05:10:32 -0400
commitef9247ef89be79ffbd9faaf722e05b7bed14fc1e (patch)
tree6d8afba92435f2df0290d198b5a742c6a75d048d /arch/sh
parentd88a3ea6fa4c98d482240a6a85945ed448b7671d (diff)
sh: Tidy up the SH-3 exception vector table.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/kernel/cpu/sh3/ex.S38
1 files changed, 19 insertions, 19 deletions
diff --git a/arch/sh/kernel/cpu/sh3/ex.S b/arch/sh/kernel/cpu/sh3/ex.S
index 11b6d9c6edae..dac429726899 100644
--- a/arch/sh/kernel/cpu/sh3/ex.S
+++ b/arch/sh/kernel/cpu/sh3/ex.S
@@ -4,7 +4,7 @@
4 * The SH-3 and SH-4 exception vector table. 4 * The SH-3 and SH-4 exception vector table.
5 5
6 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka 6 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
7 * Copyright (C) 2003 - 2006 Paul Mundt 7 * Copyright (C) 2003 - 2008 Paul Mundt
8 * 8 *
9 * This file is subject to the terms and conditions of the GNU General Public 9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive 10 * License. See the file "COPYING" in the main directory of this archive
@@ -12,13 +12,30 @@
12 */ 12 */
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14 14
15#if !defined(CONFIG_MMU)
16#define tlb_miss_load exception_error
17#define tlb_miss_store exception_error
18#define initial_page_write exception_error
19#define tlb_protection_violation_load exception_error
20#define tlb_protection_violation_store exception_error
21#define address_error_load exception_error
22#define address_error_store exception_error
23#endif
24
25#if !defined(CONFIG_SH_FPU)
26#define fpu_error_trap_handler exception_error
27#endif
28
29#if !defined(CONFIG_KGDB_NMI)
30#define kgdb_handle_exception exception_error
31#endif
32
15 .align 2 33 .align 2
16 .data 34 .data
17 35
18ENTRY(exception_handling_table) 36ENTRY(exception_handling_table)
19 .long exception_error /* 000 */ 37 .long exception_error /* 000 */
20 .long exception_error 38 .long exception_error
21#if defined(CONFIG_MMU)
22 .long tlb_miss_load /* 040 */ 39 .long tlb_miss_load /* 040 */
23 .long tlb_miss_store 40 .long tlb_miss_store
24 .long initial_page_write 41 .long initial_page_write
@@ -26,30 +43,13 @@ ENTRY(exception_handling_table)
26 .long tlb_protection_violation_store 43 .long tlb_protection_violation_store
27 .long address_error_load 44 .long address_error_load
28 .long address_error_store /* 100 */ 45 .long address_error_store /* 100 */
29#else
30 .long exception_error ! tlb miss load /* 040 */
31 .long exception_error ! tlb miss store
32 .long exception_error ! initial page write
33 .long exception_error ! tlb prot violation load
34 .long exception_error ! tlb prot violation store
35 .long exception_error ! address error load
36 .long exception_error ! address error store /* 100 */
37#endif
38#if defined(CONFIG_SH_FPU)
39 .long fpu_error_trap_handler /* 120 */ 46 .long fpu_error_trap_handler /* 120 */
40#else
41 .long exception_error /* 120 */
42#endif
43 .long exception_error /* 140 */ 47 .long exception_error /* 140 */
44 .long system_call ! Unconditional Trap /* 160 */ 48 .long system_call ! Unconditional Trap /* 160 */
45 .long exception_error ! reserved_instruction (filled by trap_init) /* 180 */ 49 .long exception_error ! reserved_instruction (filled by trap_init) /* 180 */
46 .long exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/ 50 .long exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/
47ENTRY(nmi_slot) 51ENTRY(nmi_slot)
48#if defined (CONFIG_KGDB_NMI)
49 .long kgdb_handle_exception /* 1C0 */ ! Allow trap to debugger 52 .long kgdb_handle_exception /* 1C0 */ ! Allow trap to debugger
50#else
51 .long exception_none /* 1C0 */ ! Not implemented yet
52#endif
53ENTRY(user_break_point_trap) 53ENTRY(user_break_point_trap)
54 .long break_point_trap /* 1E0 */ 54 .long break_point_trap /* 1E0 */
55 55