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authorPaul Mundt <lethal@linux-sh.org>2009-03-06 05:20:32 -0500
committerPaul Mundt <lethal@linux-sh.org>2009-03-06 05:20:32 -0500
commit0caedb02c4a02b6fd0f1a62dfeb917353d3c6162 (patch)
treef10ff7b7421a7cc3a2f484d5f8578462041dd305 /arch/sh
parent592acbda89f40a93f7d71564cdf1da83229d226e (diff)
sh: multiple vectors per irq - sh7705.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c61
1 files changed, 19 insertions, 42 deletions
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 6468ae86b944..63b67badd67e 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7705 Setup 2 * SH7705 Setup
3 * 3 *
4 * Copyright (C) 2006, 2007 Paul Mundt 4 * Copyright (C) 2006 - 2009 Paul Mundt
5 * Copyright (C) 2007 Nobuhiro Iwamatsu 5 * Copyright (C) 2007 Nobuhiro Iwamatsu
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
@@ -21,51 +21,36 @@ enum {
21 /* interrupt sources */ 21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, 22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
23 PINT07, PINT815, 23 PINT07, PINT815,
24 DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3, 24
25 SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, 25 DMAC, SCIF0, SCIF2, ADC_ADI, USB,
26 SCIF2_ERI, SCIF2_RXI, SCIF2_TXI, 26
27 ADC_ADI,
28 USB_USI0, USB_USI1,
29 TPU0, TPU1, TPU2, TPU3, 27 TPU0, TPU1, TPU2, TPU3,
30 TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 28 TMU0, TMU1, TMU2,
31 RTC_ATI, RTC_PRI, RTC_CUI,
32 WDT,
33 REF_RCMI,
34 29
35 /* interrupt groups */ 30 RTC, WDT, REF_RCMI,
36 RTC, TMU2, DMAC, USB, SCIF2, SCIF0,
37}; 31};
38 32
39static struct intc_vect vectors[] __initdata = { 33static struct intc_vect vectors[] __initdata = {
40 /* IRQ0->5 are handled in setup-sh3.c */ 34 /* IRQ0->5 are handled in setup-sh3.c */
41 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), 35 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
42 INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), 36 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
43 INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), 37 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
44 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), 38 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
45 INTC_VECT(SCIF0_TXI, 0x8e0), 39 INTC_VECT(SCIF0, 0x8e0),
46 INTC_VECT(SCIF2_ERI, 0x900), INTC_VECT(SCIF2_RXI, 0x920), 40 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
47 INTC_VECT(SCIF2_TXI, 0x960), 41 INTC_VECT(SCIF2, 0x960),
48 INTC_VECT(ADC_ADI, 0x980), 42 INTC_VECT(ADC_ADI, 0x980),
49 INTC_VECT(USB_USI0, 0xa20), INTC_VECT(USB_USI1, 0xa40), 43 INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40),
50 INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20), 44 INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20),
51 INTC_VECT(TPU2, 0xc80), INTC_VECT(TPU3, 0xca0), 45 INTC_VECT(TPU2, 0xc80), INTC_VECT(TPU3, 0xca0),
52 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 46 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
53 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 47 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
54 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 48 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
55 INTC_VECT(RTC_CUI, 0x4c0), 49 INTC_VECT(RTC, 0x4c0),
56 INTC_VECT(WDT, 0x560), 50 INTC_VECT(WDT, 0x560),
57 INTC_VECT(REF_RCMI, 0x580), 51 INTC_VECT(REF_RCMI, 0x580),
58}; 52};
59 53
60static struct intc_group groups[] __initdata = {
61 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
62 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
63 INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
64 INTC_GROUP(USB, USB_USI0, USB_USI1),
65 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
66 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
67};
68
69static struct intc_prio_reg prio_registers[] __initdata = { 54static struct intc_prio_reg prio_registers[] __initdata = {
70 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 55 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
71 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } }, 56 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
@@ -78,7 +63,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
78 63
79}; 64};
80 65
81static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, groups, 66static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
82 NULL, prio_registers, NULL); 67 NULL, prio_registers, NULL);
83 68
84static struct plat_sci_port sci_platform_data[] = { 69static struct plat_sci_port sci_platform_data[] = {
@@ -86,12 +71,12 @@ static struct plat_sci_port sci_platform_data[] = {
86 .mapbase = 0xa4410000, 71 .mapbase = 0xa4410000,
87 .flags = UPF_BOOT_AUTOCONF, 72 .flags = UPF_BOOT_AUTOCONF,
88 .type = PORT_SCIF, 73 .type = PORT_SCIF,
89 .irqs = { 56, 57, 59 }, 74 .irqs = { 56, 56, 56 },
90 }, { 75 }, {
91 .mapbase = 0xa4400000, 76 .mapbase = 0xa4400000,
92 .flags = UPF_BOOT_AUTOCONF, 77 .flags = UPF_BOOT_AUTOCONF,
93 .type = PORT_SCIF, 78 .type = PORT_SCIF,
94 .irqs = { 52, 53, 55 }, 79 .irqs = { 52, 52, 52 },
95 }, { 80 }, {
96 .flags = 0, 81 .flags = 0,
97 } 82 }
@@ -115,14 +100,6 @@ static struct resource rtc_resources[] = {
115 .start = 20, 100 .start = 20,
116 .flags = IORESOURCE_IRQ, 101 .flags = IORESOURCE_IRQ,
117 }, 102 },
118 [2] = {
119 .start = 21,
120 .flags = IORESOURCE_IRQ,
121 },
122 [3] = {
123 .start = 22,
124 .flags = IORESOURCE_IRQ,
125 },
126}; 103};
127 104
128static struct sh_rtc_platform_info rtc_info = { 105static struct sh_rtc_platform_info rtc_info = {