Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp

Conflicts:
	litmus/sched_cedf.c

334 files changed, 9063 insertions, 5371 deletions

diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 33990fa95af0..bbdeb48bbf8e 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -1,14 +1,7 @@
-#
-# For a description of the syntax of this configuration file,
-# see Documentation/kbuild/kconfig-language.txt.
-#
-
-mainmenu "Linux/SuperH Kernel Configuration"
-
 config SUPERH
         def_bool y
-        select EMBEDDED
-        select HAVE_CLK
+        select EXPERT
+        select CLKDEV_LOOKUP
         select HAVE_IDE if HAS_IOPORT
         select HAVE_MEMBLOCK
         select HAVE_OPROFILE
@@ -16,15 +9,22 @@ config SUPERH
         select HAVE_ARCH_TRACEHOOK
         select HAVE_DMA_API_DEBUG
         select HAVE_DMA_ATTRS
+        select HAVE_IRQ_WORK
         select HAVE_PERF_EVENTS
         select PERF_USE_VMALLOC
         select HAVE_KERNEL_GZIP
         select HAVE_KERNEL_BZIP2
         select HAVE_KERNEL_LZMA
+        select HAVE_KERNEL_XZ
         select HAVE_KERNEL_LZO
         select HAVE_SYSCALL_TRACEPOINTS
+        select HAVE_REGS_AND_STACK_ACCESS_API
+        select HAVE_GENERIC_HARDIRQS
+        select HAVE_SPARSE_IRQ
+        select IRQ_FORCED_THREADING
         select RTC_LIB
         select GENERIC_ATOMIC64
+        select GENERIC_IRQ_SHOW
         help
           The SuperH is a RISC processor targeted for use in embedded systems
           and consumer electronics; it was also used in the Sega Dreamcast
@@ -45,8 +45,9 @@ config SUPERH32
         select HAVE_ARCH_KGDB
         select HAVE_HW_BREAKPOINT
         select HAVE_MIXED_BREAKPOINTS_REGS
-        select PERF_EVENTS if HAVE_HW_BREAKPOINT
+        select PERF_EVENTS
         select ARCH_HIBERNATION_POSSIBLE if MMU
+        select SPARSE_IRQ
 
 config SUPERH64
         def_bool ARCH = "sh64"
@@ -70,25 +71,12 @@ config GENERIC_CSUM
         def_bool y
         depends on SUPERH64
 
-config GENERIC_FIND_NEXT_BIT
-        def_bool y
-
 config GENERIC_HWEIGHT
         def_bool y
 
-config GENERIC_HARDIRQS
-        def_bool y
-
-config GENERIC_HARDIRQS_NO__DO_IRQ
-        def_bool y
-
 config IRQ_PER_CPU
         def_bool y
 
-config SPARSE_IRQ
-        def_bool y
-        depends on SUPERH32
-
 config GENERIC_GPIO
         def_bool n
 
@@ -172,7 +160,8 @@ config ARCH_HAS_CPU_IDLE_WAIT
         def_bool y
 
 config NO_IOPORT
-        bool
+        def_bool !PCI
+        depends on !SH_CAYMAN && !SH_SH4202_MICRODEV && !SH_SHMIN
 
 config IO_TRAPPED
         bool
@@ -204,6 +193,7 @@ config CPU_SH2
 config CPU_SH2A
         bool
         select CPU_SH2
+        select UNCACHED_MAPPING
 
 config CPU_SH3
         bool
@@ -249,6 +239,11 @@ config ARCH_SHMOBILE
         select PM
         select PM_RUNTIME
 
+config CPU_HAS_PMU
+       depends on CPU_SH4 || CPU_SH4A
+       default y
+       bool
+
 if SUPERH32
 
 choice
@@ -279,6 +274,7 @@ config CPU_SUBTYPE_SH7203
         select CPU_HAS_FPU
         select SYS_SUPPORTS_CMT
         select SYS_SUPPORTS_MTU2
+        select ARCH_WANT_OPTIONAL_GPIOLIB
 
 config CPU_SUBTYPE_SH7206
         bool "Support SH7206 processor"
@@ -350,6 +346,9 @@ config CPU_SUBTYPE_SH7720
         select CPU_SH3
         select CPU_HAS_DSP
         select SYS_SUPPORTS_CMT
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select USB_ARCH_HAS_OHCI
+        select USB_OHCI_SH if USB_OHCI_HCD
         help
           Select SH7720 if you have a SH3-DSP SH7720 CPU.
 
@@ -358,6 +357,8 @@ config CPU_SUBTYPE_SH7721
         select CPU_SH3
         select CPU_HAS_DSP
         select SYS_SUPPORTS_CMT
+        select USB_ARCH_HAS_OHCI
+        select USB_OHCI_SH if USB_OHCI_HCD
         help
           Select SH7721 if you have a SH3-DSP SH7721 CPU.
 
@@ -412,6 +413,7 @@ config CPU_SUBTYPE_SH7723
         select ARCH_SHMOBILE
         select ARCH_SPARSEMEM_ENABLE
         select SYS_SUPPORTS_CMT
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         help
           Select SH7723 if you have an SH-MobileR2 CPU.
 
@@ -422,6 +424,7 @@ config CPU_SUBTYPE_SH7724
         select ARCH_SHMOBILE
         select ARCH_SPARSEMEM_ENABLE
         select SYS_SUPPORTS_CMT
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         help
           Select SH7724 if you have an SH-MobileR2R CPU.
 
@@ -429,12 +432,17 @@ config CPU_SUBTYPE_SH7757
         bool "Support SH7757 processor"
         select CPU_SH4A
         select CPU_SHX2
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select USB_ARCH_HAS_OHCI
+        select USB_ARCH_HAS_EHCI
         help
           Select SH7757 if you have a SH4A SH7757 CPU.
 
 config CPU_SUBTYPE_SH7763
         bool "Support SH7763 processor"
         select CPU_SH4A
+        select USB_ARCH_HAS_OHCI
+        select USB_OHCI_SH if USB_OHCI_HCD
         help
           Select SH7763 if you have a SH4A SH7763(R5S77631) CPU.
 
@@ -452,6 +460,7 @@ config CPU_SUBTYPE_SH7785
         select CPU_SHX2
         select ARCH_SPARSEMEM_ENABLE
         select SYS_SUPPORTS_NUMA
+        select ARCH_WANT_OPTIONAL_GPIOLIB
 
 config CPU_SUBTYPE_SH7786
         bool "Support SH7786 processor"
@@ -459,12 +468,18 @@ config CPU_SUBTYPE_SH7786
         select CPU_SHX3
         select CPU_HAS_PTEAEX
         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select USB_ARCH_HAS_OHCI
+        select USB_OHCI_SH if USB_OHCI_HCD
+        select USB_ARCH_HAS_EHCI
+        select USB_EHCI_SH if USB_EHCI_HCD
 
 config CPU_SUBTYPE_SHX3
         bool "Support SH-X3 processor"
         select CPU_SH4A
         select CPU_SHX3
         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
+        select ARCH_REQUIRE_GPIOLIB
 
 # SH4AL-DSP Processor Support
 
@@ -482,6 +497,7 @@ config CPU_SUBTYPE_SH7722
         select ARCH_SPARSEMEM_ENABLE
         select SYS_SUPPORTS_NUMA
         select SYS_SUPPORTS_CMT
+        select ARCH_WANT_OPTIONAL_GPIOLIB
 
 config CPU_SUBTYPE_SH7366
         bool "Support SH7366 processor"
@@ -569,16 +585,7 @@ config SH_CLK_CPG
 config SH_CLK_CPG_LEGACY
         depends on SH_CLK_CPG
         def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
-                      !CPU_SUBTYPE_SH7786
-
-config SH_CLK_MD
-        int "CPU Mode Pin Setting"
-        depends on CPU_SH2
-        default 6 if CPU_SUBTYPE_SH7206
-        default 5 if CPU_SUBTYPE_SH7619
-        default 0
-        help
-          MD2 - MD0 pin setting.
+                      !CPU_SHX3 && !CPU_SUBTYPE_SH7757
 
 source "kernel/time/Kconfig"
 
@@ -738,6 +745,14 @@ config GUSA_RB
           LLSC, this should be more efficient than the other alternative of
           disabling interrupts around the atomic sequence.
 
+config HW_PERF_EVENTS
+        bool "Enable hardware performance counter support for perf events"
+        depends on PERF_EVENTS && CPU_HAS_PMU
+        default y
+        help
+          Enable hardware performance counter support for perf events. If
+          disabled, perf events will use software events only.
+
 source "drivers/sh/Kconfig"
 
 endmenu
diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug
index 12fec72fec5f..c1d5a820b1aa 100644
--- a/arch/sh/Kconfig.debug
+++ b/arch/sh/Kconfig.debug
@@ -28,15 +28,6 @@ config STACK_DEBUG
           every function call and will therefore incur a major
           performance hit. Most users should say N.
 
-config DEBUG_STACK_USAGE
-        bool "Stack utilization instrumentation"
-        depends on DEBUG_KERNEL
-        help
-          Enables the display of the minimum amount of free stack which each
-          task has ever had available in the sysrq-T and sysrq-P debug output.
-
-          This option will slow down process creation somewhat.
-
 config 4KSTACKS
         bool "Use 4Kb for kernel stacks instead of 8Kb"
         depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB
@@ -82,7 +73,7 @@ config SH_NO_BSS_INIT
         help
           If running in painfully slow environments, such as an RTL
           simulation or from remote memory via SHdebug, where the memory
-          can already be gauranteed to ber zeroed on boot, say Y.
+          can already be guaranteed to ber zeroed on boot, say Y.
 
           For all other cases, say N. If this option seems perplexing, or
           you aren't sure, say N.
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index 307b3a4a790b..e3d8170ad00b 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -133,10 +133,7 @@ machdir-$(CONFIG_SOLUTION_ENGINE)		+= mach-se
 machdir-$(CONFIG_SH_HP6XX)                      += mach-hp6xx
 machdir-$(CONFIG_SH_DREAMCAST)                  += mach-dreamcast
 machdir-$(CONFIG_SH_SH03)                       += mach-sh03
-machdir-$(CONFIG_SH_SECUREEDGE5410)             += mach-snapgear
 machdir-$(CONFIG_SH_RTS7751R2D)                 += mach-r2d
-machdir-$(CONFIG_SH_7751_SYSTEMH)               += mach-systemh
-machdir-$(CONFIG_SH_EDOSK7705)                  += mach-edosk7705
 machdir-$(CONFIG_SH_HIGHLANDER)                 += mach-highlander
 machdir-$(CONFIG_SH_MIGOR)                      += mach-migor
 machdir-$(CONFIG_SH_AP325RXA)                   += mach-ap325rxa
@@ -203,7 +200,7 @@ endif
 libs-$(CONFIG_SUPERH32)         := arch/sh/lib/ $(libs-y)
 libs-$(CONFIG_SUPERH64)         := arch/sh/lib64/ $(libs-y)
 
-BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.lzo \
+BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.xz uImage.lzo \
                uImage.srec uImage.bin zImage vmlinux.bin vmlinux.srec \
                romImage
 PHONY += $(BOOT_TARGETS)
@@ -233,5 +230,6 @@ define archhelp
         @echo '* uImage.gz                 - Kernel-only image for U-Boot (gzip)'
         @echo '  uImage.bz2                - Kernel-only image for U-Boot (bzip2)'
         @echo '  uImage.lzma               - Kernel-only image for U-Boot (lzma)'
+        @echo '  uImage.xz                 - Kernel-only image for U-Boot (xz)'
         @echo '  uImage.lzo                - Kernel-only image for U-Boot (lzo)'
 endef
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index 07b35ca2f644..d893411022d5 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -3,6 +3,9 @@ menu "Board support"
 config SOLUTION_ENGINE
         bool
 
+config SH_ALPHA_BOARD
+        bool
+
 config SH_SOLUTION_ENGINE
         bool "SolutionEngine"
         select SOLUTION_ENGINE
@@ -81,13 +84,6 @@ config SH_7343_SOLUTION_ENGINE
           Select 7343 SolutionEngine if configuring for a Hitachi
           SH7343 (SH-Mobile 3AS) evaluation board.
 
-config SH_7751_SYSTEMH
-        bool "SystemH7751R"
-        depends on CPU_SUBTYPE_SH7751R
-        help
-          Select SystemH if you are configuring for a Renesas SystemH
-          7751R evaluation board.
-
 config SH_HP6XX
         bool "HP6XX"
         select SYS_SUPPORTS_APM_EMULATION
@@ -155,6 +151,8 @@ config SH_SDK7786
         depends on CPU_SUBTYPE_SH7786
         select SYS_SUPPORTS_PCI
         select NO_IOPORT if !PCI
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select HAVE_SRAM_POOL
         help
           Select SDK7786 if configuring for a Renesas Technology Europe
           SH7786-65nm board.
@@ -165,6 +163,11 @@ config SH_HIGHLANDER
         select SYS_SUPPORTS_PCI
         select IO_TRAPPED if MMU
 
+config SH_SH7757LCR
+        bool "SH7757LCR"
+        depends on CPU_SUBTYPE_SH7757
+        select ARCH_REQUIRE_GPIOLIB
+
 config SH_SH7785LCR
         bool "SH7785LCR"
         depends on CPU_SUBTYPE_SH7785
@@ -309,6 +312,32 @@ config SH_POLARIS
         help
           Select if configuring for an SMSC Polaris development board
 
+config SH_SH2007
+        bool "SH-2007 board"
+        select NO_IOPORT
+        depends on CPU_SUBTYPE_SH7780
+        help
+          SH-2007 is a single-board computer based around SH7780 chip
+          intended for embedded applications.
+          It has an Ethernet interface (SMC9118), direct connected
+          Compact Flash socket, two serial ports and PC-104 bus.
+          More information at <http://sh2000.sh-linux.org>.
+
+config SH_APSH4A3A
+        bool "AP-SH4A-3A"
+        select SH_ALPHA_BOARD
+        depends on CPU_SUBTYPE_SH7785
+        help
+          Select AP-SH4A-3A if configuring for an ALPHAPROJECT AP-SH4A-3A.
+
+config SH_APSH4AD0A
+        bool "AP-SH4AD-0A"
+        select SH_ALPHA_BOARD
+        select SYS_SUPPORTS_PCI
+        depends on CPU_SUBTYPE_SH7786
+        help
+          Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A.
+
 endmenu
 
 source "arch/sh/boards/mach-r2d/Kconfig"
diff --git a/arch/sh/boards/Makefile b/arch/sh/boards/Makefile
index 4f90f9b7a922..975a0f64ff20 100644
--- a/arch/sh/boards/Makefile
+++ b/arch/sh/boards/Makefile
@@ -2,10 +2,16 @@
 # Specific board support, not covered by a mach group.
 #
 obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o
+obj-$(CONFIG_SH_SECUREEDGE5410) += board-secureedge5410.o
+obj-$(CONFIG_SH_SH2007)         += board-sh2007.o
 obj-$(CONFIG_SH_SH7785LCR)      += board-sh7785lcr.o
 obj-$(CONFIG_SH_URQUELL)        += board-urquell.o
 obj-$(CONFIG_SH_SHMIN)          += board-shmin.o
+obj-$(CONFIG_SH_EDOSK7705)      += board-edosk7705.o
 obj-$(CONFIG_SH_EDOSK7760)      += board-edosk7760.o
 obj-$(CONFIG_SH_ESPT)           += board-espt.o
 obj-$(CONFIG_SH_POLARIS)        += board-polaris.o
 obj-$(CONFIG_SH_TITAN)          += board-titan.o
+obj-$(CONFIG_SH_SH7757LCR)      += board-sh7757lcr.o
+obj-$(CONFIG_SH_APSH4A3A)       += board-apsh4a3a.o
+obj-$(CONFIG_SH_APSH4AD0A)      += board-apsh4ad0a.o
diff --git a/arch/sh/boards/board-apsh4a3a.c b/arch/sh/boards/board-apsh4a3a.c
new file mode 100644
index 000000000000..8e2a27057bc9
--- /dev/null
+++ b/arch/sh/boards/board-apsh4a3a.c
@@ -0,0 +1,175 @@
+/*
+ * ALPHAPROJECT AP-SH4A-3A Support.
+ *
+ * Copyright (C) 2010 ALPHAPROJECT Co.,Ltd.
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ * Copyright (C) 2009  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/mtd/physmap.h>
+#include <linux/smsc911x.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <asm/machvec.h>
+#include <asm/sizes.h>
+#include <asm/clock.h>
+
+static struct mtd_partition nor_flash_partitions[] = {
+        {
+                .name           = "loader",
+                .offset         = 0x00000000,
+                .size           = 512 * 1024,
+        },
+        {
+                .name           = "bootenv",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 512 * 1024,
+        },
+        {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 4 * 1024 * 1024,
+        },
+        {
+                .name           = "data",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data nor_flash_data = {
+        .width          = 4,
+        .parts          = nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
+};
+
+static struct resource nor_flash_resources[] = {
+        [0]     = {
+                .start  = 0x00000000,
+                .end    = 0x01000000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device nor_flash_device = {
+        .name           = "physmap-flash",
+        .dev            = {
+                .platform_data  = &nor_flash_data,
+        },
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+        .resource       = nor_flash_resources,
+};
+
+static struct resource smsc911x_resources[] = {
+        [0] = {
+                .name           = "smsc911x-memory",
+                .start          = 0xA4000000,
+                .end            = 0xA4000000 + SZ_256 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name           = "smsc911x-irq",
+                .start          = evt2irq(0x200),
+                .end            = evt2irq(0x200),
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct smsc911x_platform_config smsc911x_config = {
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+        .flags          = SMSC911X_USE_16BIT,
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+};
+
+static struct platform_device smsc911x_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smsc911x_resources),
+        .resource       = smsc911x_resources,
+        .dev = {
+                .platform_data = &smsc911x_config,
+        },
+};
+
+static struct platform_device *apsh4a3a_devices[] __initdata = {
+        &nor_flash_device,
+        &smsc911x_device,
+};
+
+static int __init apsh4a3a_devices_setup(void)
+{
+        return platform_add_devices(apsh4a3a_devices,
+                                    ARRAY_SIZE(apsh4a3a_devices));
+}
+device_initcall(apsh4a3a_devices_setup);
+
+static int apsh4a3a_clk_init(void)
+{
+        struct clk *clk;
+        int ret;
+
+        clk = clk_get(NULL, "extal");
+        if (!clk || IS_ERR(clk))
+                return PTR_ERR(clk);
+        ret = clk_set_rate(clk, 33333000);
+        clk_put(clk);
+
+        return ret;
+}
+
+/* Initialize the board */
+static void __init apsh4a3a_setup(char **cmdline_p)
+{
+        printk(KERN_INFO "Alpha Project AP-SH4A-3A support:\n");
+}
+
+static void __init apsh4a3a_init_irq(void)
+{
+        plat_irq_setup_pins(IRQ_MODE_IRQ7654);
+}
+
+/* Return the board specific boot mode pin configuration */
+static int apsh4a3a_mode_pins(void)
+{
+        int value = 0;
+
+        /* These are the factory default settings of SW1 and SW2.
+         * If you change these dip switches then you will need to
+         * adjust the values below as well.
+         */
+        value &= ~MODE_PIN0;  /* Clock Mode 16 */
+        value &= ~MODE_PIN1;
+        value &= ~MODE_PIN2;
+        value &= ~MODE_PIN3;
+        value |=  MODE_PIN4;
+        value &= ~MODE_PIN5;  /* 16-bit Area0 bus width */
+        value |=  MODE_PIN6;  /* Area 0 SRAM interface */
+        value |=  MODE_PIN7;
+        value |=  MODE_PIN8;  /* Little Endian */
+        value |=  MODE_PIN9;  /* Master Mode */
+        value |=  MODE_PIN10; /* Crystal resonator */
+        value |=  MODE_PIN11; /* Display Unit */
+        value |=  MODE_PIN12;
+        value &= ~MODE_PIN13; /* 29-bit address mode */
+        value |=  MODE_PIN14; /* No PLL step-up */
+
+        return value;
+}
+
+/*
+ * The Machine Vector
+ */
+static struct sh_machine_vector mv_apsh4a3a __initmv = {
+        .mv_name                = "AP-SH4A-3A",
+        .mv_setup               = apsh4a3a_setup,
+        .mv_clk_init            = apsh4a3a_clk_init,
+        .mv_init_irq            = apsh4a3a_init_irq,
+        .mv_mode_pins           = apsh4a3a_mode_pins,
+};
diff --git a/arch/sh/boards/board-apsh4ad0a.c b/arch/sh/boards/board-apsh4ad0a.c
new file mode 100644
index 000000000000..e2bd218a054e
--- /dev/null
+++ b/arch/sh/boards/board-apsh4ad0a.c
@@ -0,0 +1,125 @@
+/*
+ * ALPHAPROJECT AP-SH4AD-0A Support.
+ *
+ * Copyright (C) 2010 ALPHAPROJECT Co.,Ltd.
+ * Copyright (C) 2010  Matt Fleming
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/smsc911x.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <asm/machvec.h>
+#include <asm/sizes.h>
+
+static struct resource smsc911x_resources[] = {
+        [0] = {
+                .name           = "smsc911x-memory",
+                .start          = 0xA4000000,
+                .end            = 0xA4000000 + SZ_256 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name           = "smsc911x-irq",
+                .start          = evt2irq(0x200),
+                .end            = evt2irq(0x200),
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct smsc911x_platform_config smsc911x_config = {
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+        .flags          = SMSC911X_USE_16BIT,
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+};
+
+static struct platform_device smsc911x_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smsc911x_resources),
+        .resource       = smsc911x_resources,
+        .dev = {
+                .platform_data = &smsc911x_config,
+        },
+};
+
+static struct platform_device *apsh4ad0a_devices[] __initdata = {
+        &smsc911x_device,
+};
+
+static int __init apsh4ad0a_devices_setup(void)
+{
+        return platform_add_devices(apsh4ad0a_devices,
+                                    ARRAY_SIZE(apsh4ad0a_devices));
+}
+device_initcall(apsh4ad0a_devices_setup);
+
+static int apsh4ad0a_mode_pins(void)
+{
+        int value = 0;
+
+        /* These are the factory default settings of SW1 and SW2.
+         * If you change these dip switches then you will need to
+         * adjust the values below as well.
+         */
+        value |=  MODE_PIN0;  /* Clock Mode 3 */
+        value |=  MODE_PIN1;
+        value &= ~MODE_PIN2;
+        value &= ~MODE_PIN3;
+        value &= ~MODE_PIN4;  /* 16-bit Area0 bus width  */
+        value |=  MODE_PIN5;
+        value |=  MODE_PIN6;
+        value |=  MODE_PIN7;  /* Normal mode */
+        value |=  MODE_PIN8;  /* Little Endian */
+        value |=  MODE_PIN9;  /* Crystal resonator */
+        value &= ~MODE_PIN10; /* 29-bit address mode */
+        value &= ~MODE_PIN11; /* PCI-E Root port */
+        value &= ~MODE_PIN12; /* 4 lane + 1 lane */
+        value |=  MODE_PIN13; /* AUD Enable */
+        value &= ~MODE_PIN14; /* Normal Operation */
+
+        return value;
+}
+
+static int apsh4ad0a_clk_init(void)
+{
+        struct clk *clk;
+        int ret;
+
+        clk = clk_get(NULL, "extal");
+        if (!clk || IS_ERR(clk))
+                return PTR_ERR(clk);
+        ret = clk_set_rate(clk, 33333000);
+        clk_put(clk);
+
+        return ret;
+}
+
+/* Initialize the board */
+static void __init apsh4ad0a_setup(char **cmdline_p)
+{
+        pr_info("Alpha Project AP-SH4AD-0A support:\n");
+}
+
+static void __init apsh4ad0a_init_irq(void)
+{
+        plat_irq_setup_pins(IRQ_MODE_IRQ3210);
+}
+
+/*
+ * The Machine Vector
+ */
+static struct sh_machine_vector mv_apsh4ad0a __initmv = {
+        .mv_name                = "AP-SH4AD-0A",
+        .mv_setup               = apsh4ad0a_setup,
+        .mv_mode_pins           = apsh4ad0a_mode_pins,
+        .mv_clk_init            = apsh4ad0a_clk_init,
+        .mv_init_irq            = apsh4ad0a_init_irq,
+};
diff --git a/arch/sh/boards/board-edosk7705.c b/arch/sh/boards/board-edosk7705.c
new file mode 100644
index 000000000000..541d8a281035
--- /dev/null
+++ b/arch/sh/boards/board-edosk7705.c
@@ -0,0 +1,78 @@
+/*
+ * arch/sh/boards/renesas/edosk7705/setup.c
+ *
+ * Copyright (C) 2000  Kazumoto Kojima
+ *
+ * Hitachi SolutionEngine Support.
+ *
+ * Modified for edosk7705 development
+ * board by S. Dunn, 2003.
+ */
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/smc91x.h>
+#include <asm/machvec.h>
+#include <asm/sizes.h>
+
+#define SMC_IOBASE      0xA2000000
+#define SMC_IO_OFFSET   0x300
+#define SMC_IOADDR      (SMC_IOBASE + SMC_IO_OFFSET)
+
+#define ETHERNET_IRQ    0x09
+
+static void __init sh_edosk7705_init_irq(void)
+{
+        make_imask_irq(ETHERNET_IRQ);
+}
+
+/* eth initialization functions */
+static struct smc91x_platdata smc91x_info = {
+        .flags = SMC91X_USE_16BIT | SMC91X_IO_SHIFT_1 | IORESOURCE_IRQ_LOWLEVEL,
+};
+
+static struct resource smc91x_res[] = {
+        [0] = {
+                .start  = SMC_IOADDR,
+                .end    = SMC_IOADDR + SZ_32 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = ETHERNET_IRQ,
+                .end    = ETHERNET_IRQ,
+                .flags  = IORESOURCE_IRQ ,
+        }
+};
+
+static struct platform_device smc91x_dev = {
+        .name           = "smc91x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smc91x_res),
+        .resource       = smc91x_res,
+
+        .dev    = {
+                .platform_data  = &smc91x_info,
+        },
+};
+
+/* platform init code */
+static struct platform_device *edosk7705_devices[] __initdata = {
+        &smc91x_dev,
+};
+
+static int __init init_edosk7705_devices(void)
+{
+        return platform_add_devices(edosk7705_devices,
+                                    ARRAY_SIZE(edosk7705_devices));
+}
+device_initcall(init_edosk7705_devices);
+
+/*
+ * The Machine Vector
+ */
+static struct sh_machine_vector mv_edosk7705 __initmv = {
+        .mv_name                = "EDOSK7705",
+        .mv_nr_irqs             = 80,
+        .mv_init_irq            = sh_edosk7705_init_irq,
+};
diff --git a/arch/sh/boards/board-edosk7760.c b/arch/sh/boards/board-edosk7760.c
index 35dc0994875d..e9656a2cc4cc 100644
--- a/arch/sh/boards/board-edosk7760.c
+++ b/arch/sh/boards/board-edosk7760.c
@@ -56,7 +56,7 @@ static struct mtd_partition edosk7760_nor_flash_partitions[] = {
         }, {
                 .name = "fs",
                 .offset = MTDPART_OFS_APPEND,
-                .size = SZ_26M,
+                .size = (26 << 20),
         }, {
                 .name = "other",
                 .offset = MTDPART_OFS_APPEND,
@@ -182,7 +182,7 @@ static int __init init_edosk7760_devices(void)
         return platform_add_devices(edosk7760_devices,
                                     ARRAY_SIZE(edosk7760_devices));
 }
-__initcall(init_edosk7760_devices);
+device_initcall(init_edosk7760_devices);
 
 /*
  * The Machine Vector
diff --git a/arch/sh/boards/board-espt.c b/arch/sh/boards/board-espt.c
index d5ce5e18eb37..9da92ac36533 100644
--- a/arch/sh/boards/board-espt.c
+++ b/arch/sh/boards/board-espt.c
@@ -66,6 +66,11 @@ static struct resource sh_eth_resources[] = {
                 .end    = 0xFEE00F7C - 1,
                 .flags  = IORESOURCE_MEM,
         }, {
+                .start  = 0xFEE01800,   /* TSU */
+                .end    = 0xFEE01FFF,
+                .flags  = IORESOURCE_MEM,
+        }, {
+
                 .start  = 57,   /* irq number */
                 .flags  = IORESOURCE_IRQ,
         },
@@ -74,6 +79,8 @@ static struct resource sh_eth_resources[] = {
 static struct sh_eth_plat_data sh7763_eth_pdata = {
         .phy = 0,
         .edmac_endian = EDMAC_LITTLE_ENDIAN,
+        .register_type = SH_ETH_REG_GIGABIT,
+        .phy_interface = PHY_INTERFACE_MODE_MII,
 };
 
 static struct platform_device espt_eth_device = {
diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c
index efba450a0518..93f5039099b7 100644
--- a/arch/sh/boards/board-magicpanelr2.c
+++ b/arch/sh/boards/board-magicpanelr2.c
@@ -388,12 +388,12 @@ static void __init init_mpr2_IRQ(void)
 {
         plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */
 
-        set_irq_type(32, IRQ_TYPE_LEVEL_LOW);    /* IRQ0 CAN1 */
-        set_irq_type(33, IRQ_TYPE_LEVEL_LOW);    /* IRQ1 CAN2 */
-        set_irq_type(34, IRQ_TYPE_LEVEL_LOW);    /* IRQ2 CAN3 */
-        set_irq_type(35, IRQ_TYPE_LEVEL_LOW);    /* IRQ3 SMSC9115 */
-        set_irq_type(36, IRQ_TYPE_EDGE_RISING);  /* IRQ4 touchscreen */
-        set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */
+        irq_set_irq_type(32, IRQ_TYPE_LEVEL_LOW);    /* IRQ0 CAN1 */
+        irq_set_irq_type(33, IRQ_TYPE_LEVEL_LOW);    /* IRQ1 CAN2 */
+        irq_set_irq_type(34, IRQ_TYPE_LEVEL_LOW);    /* IRQ2 CAN3 */
+        irq_set_irq_type(35, IRQ_TYPE_LEVEL_LOW);    /* IRQ3 SMSC9115 */
+        irq_set_irq_type(36, IRQ_TYPE_EDGE_RISING);  /* IRQ4 touchscreen */
+        irq_set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */
 
         intc_set_priority(32, 13);              /* IRQ0 CAN1 */
         intc_set_priority(33, 13);              /* IRQ0 CAN2 */
diff --git a/arch/sh/boards/mach-snapgear/setup.c b/arch/sh/boards/board-secureedge5410.c
index 331745dee379..f968f17891a4 100644
--- a/arch/sh/boards/mach-snapgear/setup.c
+++ b/arch/sh/boards/board-secureedge5410.c
@@ -1,6 +1,4 @@
 /*
- * linux/arch/sh/boards/snapgear/setup.c
- *
  * Copyright (C) 2002  David McCullough <davidm@snapgear.com>
  * Copyright (C) 2003  Paul Mundt <lethal@linux-sh.org>
  *
@@ -19,19 +17,18 @@
 #include <linux/module.h>
 #include <linux/sched.h>
 #include <asm/machvec.h>
-#include <mach/snapgear.h>
+#include <mach/secureedge5410.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 #include <cpu/timer.h>
 
+unsigned short secureedge5410_ioport;
+
 /*
  * EraseConfig handling functions
  */
-
 static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
 {
-        (void)__raw_readb(0xb8000000);  /* dummy read */
-
         printk("SnapGear: erase switch interrupt!\n");
 
         return IRQ_HANDLED;
@@ -39,21 +36,22 @@ static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
 
 static int __init eraseconfig_init(void)
 {
+        unsigned int irq = evt2irq(0x240);
+
         printk("SnapGear: EraseConfig init\n");
+
         /* Setup "EraseConfig" switch on external IRQ 0 */
-        if (request_irq(IRL0_IRQ, eraseconfig_interrupt, IRQF_DISABLED,
+        if (request_irq(irq, eraseconfig_interrupt, IRQF_DISABLED,
                                 "Erase Config", NULL))
                 printk("SnapGear: failed to register IRQ%d for Reset witch\n",
-                                IRL0_IRQ);
+                                irq);
         else
                 printk("SnapGear: registered EraseConfig switch on IRQ%d\n",
-                                IRL0_IRQ);
-        return(0);
+                                irq);
+        return 0;
 }
-
 module_init(eraseconfig_init);
 
-/****************************************************************************/
 /*
  * Initialize IRQ setting
  *
@@ -62,7 +60,6 @@ module_init(eraseconfig_init);
  * IRL2 = eth1
  * IRL3 = crypto
  */
-
 static void __init init_snapgear_IRQ(void)
 {
         printk("Setup SnapGear IRQ/IPR ...\n");
@@ -76,20 +73,5 @@ static void __init init_snapgear_IRQ(void)
 static struct sh_machine_vector mv_snapgear __initmv = {
         .mv_name                = "SnapGear SecureEdge5410",
         .mv_nr_irqs             = 72,
-
-        .mv_inb                 = snapgear_inb,
-        .mv_inw                 = snapgear_inw,
-        .mv_inl                 = snapgear_inl,
-        .mv_outb                = snapgear_outb,
-        .mv_outw                = snapgear_outw,
-        .mv_outl                = snapgear_outl,
-
-        .mv_inb_p               = snapgear_inb_p,
-        .mv_inw_p               = snapgear_inw,
-        .mv_inl_p               = snapgear_inl,
-        .mv_outb_p              = snapgear_outb_p,
-        .mv_outw_p              = snapgear_outw,
-        .mv_outl_p              = snapgear_outl,
-
         .mv_init_irq            = init_snapgear_IRQ,
 };
diff --git a/arch/sh/boards/board-sh2007.c b/arch/sh/boards/board-sh2007.c
new file mode 100644
index 000000000000..b90b78f6a829
--- /dev/null
+++ b/arch/sh/boards/board-sh2007.c
@@ -0,0 +1,133 @@
+/*
+ * SH-2007 board support.
+ *
+ * Copyright (C) 2003, 2004  SUGIOKA Toshinobu
+ * Copyright (C) 2010  Hitoshi Mitake <mitake@dcl.info.waseda.ac.jp>
+ */
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/smsc911x.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/io.h>
+#include <asm/machvec.h>
+#include <mach/sh2007.h>
+
+struct smsc911x_platform_config smc911x_info = {
+        .flags          = SMSC911X_USE_32BIT,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+
+static struct resource smsc9118_0_resources[] = {
+        [0] = {
+                .start  = SMC0_BASE,
+                .end    = SMC0_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x240),
+                .end    = evt2irq(0x240),
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct resource smsc9118_1_resources[] = {
+        [0] = {
+                .start  = SMC1_BASE,
+                .end    = SMC1_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x280),
+                .end    = evt2irq(0x280),
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device smsc9118_0_device = {
+        .name           = "smsc911x",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(smsc9118_0_resources),
+        .resource       = smsc9118_0_resources,
+        .dev = {
+                .platform_data = &smc911x_info,
+        },
+};
+
+static struct platform_device smsc9118_1_device = {
+        .name           = "smsc911x",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(smsc9118_1_resources),
+        .resource       = smsc9118_1_resources,
+        .dev = {
+                .platform_data = &smc911x_info,
+        },
+};
+
+static struct resource cf_resources[] = {
+        [0] = {
+                .start  = CF_BASE + CF_OFFSET,
+                .end    = CF_BASE + CF_OFFSET + 0x0f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = CF_BASE + CF_OFFSET + 0x206,
+                .end    = CF_BASE + CF_OFFSET + 0x20f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = evt2irq(0x2c0),
+                .end    = evt2irq(0x2c0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cf_device  = {
+        .name           = "pata_platform",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(cf_resources),
+        .resource       = cf_resources,
+};
+
+static struct platform_device *sh2007_devices[] __initdata = {
+        &smsc9118_0_device,
+        &smsc9118_1_device,
+        &cf_device,
+};
+
+static int __init sh2007_io_init(void)
+{
+        platform_add_devices(sh2007_devices, ARRAY_SIZE(sh2007_devices));
+        return 0;
+}
+subsys_initcall(sh2007_io_init);
+
+static void __init sh2007_init_irq(void)
+{
+        plat_irq_setup_pins(IRQ_MODE_IRQ);
+}
+
+/*
+ * Initialize the board
+ */
+static void __init sh2007_setup(char **cmdline_p)
+{
+        printk(KERN_INFO "SH-2007 Setup...");
+
+        /* setup wait control registers for area 5 */
+        __raw_writel(CS5BCR_D, CS5BCR);
+        __raw_writel(CS5WCR_D, CS5WCR);
+        __raw_writel(CS5PCR_D, CS5PCR);
+
+        printk(KERN_INFO " done.\n");
+}
+
+/*
+ * The Machine Vector
+ */
+struct sh_machine_vector mv_sh2007 __initmv = {
+        .mv_setup               = sh2007_setup,
+        .mv_name                = "sh2007",
+        .mv_init_irq            = sh2007_init_irq,
+};
diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c
new file mode 100644
index 000000000000..fa2a208ec6cb
--- /dev/null
+++ b/arch/sh/boards/board-sh7757lcr.c
@@ -0,0 +1,559 @@
+/*
+ * Renesas R0P7757LC0012RL Support.
+ *
+ * Copyright (C) 2009 - 2010  Renesas Solutions Corp.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/io.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
+#include <cpu/sh7757.h>
+#include <asm/sh_eth.h>
+#include <asm/heartbeat.h>
+
+static struct resource heartbeat_resource = {
+        .start  = 0xffec005c,   /* PUDR */
+        .end    = 0xffec005c,
+        .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
+};
+
+static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
+
+static struct heartbeat_data heartbeat_data = {
+        .bit_pos        = heartbeat_bit_pos,
+        .nr_bits        = ARRAY_SIZE(heartbeat_bit_pos),
+        .flags          = HEARTBEAT_INVERTED,
+};
+
+static struct platform_device heartbeat_device = {
+        .name           = "heartbeat",
+        .id             = -1,
+        .dev    = {
+                .platform_data  = &heartbeat_data,
+        },
+        .num_resources  = 1,
+        .resource       = &heartbeat_resource,
+};
+
+/* Fast Ethernet */
+#define GBECONT         0xffc10100
+#define GBECONT_RMII1   BIT(17)
+#define GBECONT_RMII0   BIT(16)
+static void sh7757_eth_set_mdio_gate(unsigned long addr)
+{
+        if ((addr & 0x00000fff) < 0x0800)
+                writel(readl(GBECONT) | GBECONT_RMII0, GBECONT);
+        else
+                writel(readl(GBECONT) | GBECONT_RMII1, GBECONT);
+}
+
+static struct resource sh_eth0_resources[] = {
+        {
+                .start  = 0xfef00000,
+                .end    = 0xfef001ff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = 84,
+                .end    = 84,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct sh_eth_plat_data sh7757_eth0_pdata = {
+        .phy = 1,
+        .edmac_endian = EDMAC_LITTLE_ENDIAN,
+        .register_type = SH_ETH_REG_FAST_SH4,
+        .set_mdio_gate = sh7757_eth_set_mdio_gate,
+};
+
+static struct platform_device sh7757_eth0_device = {
+        .name           = "sh-eth",
+        .resource       = sh_eth0_resources,
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(sh_eth0_resources),
+        .dev            = {
+                .platform_data = &sh7757_eth0_pdata,
+        },
+};
+
+static struct resource sh_eth1_resources[] = {
+        {
+                .start  = 0xfef00800,
+                .end    = 0xfef009ff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = 84,
+                .end    = 84,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct sh_eth_plat_data sh7757_eth1_pdata = {
+        .phy = 1,
+        .edmac_endian = EDMAC_LITTLE_ENDIAN,
+        .register_type = SH_ETH_REG_FAST_SH4,
+        .set_mdio_gate = sh7757_eth_set_mdio_gate,
+};
+
+static struct platform_device sh7757_eth1_device = {
+        .name           = "sh-eth",
+        .resource       = sh_eth1_resources,
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(sh_eth1_resources),
+        .dev            = {
+                .platform_data = &sh7757_eth1_pdata,
+        },
+};
+
+static void sh7757_eth_giga_set_mdio_gate(unsigned long addr)
+{
+        if ((addr & 0x00000fff) < 0x0800) {
+                gpio_set_value(GPIO_PTT4, 1);
+                writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT);
+        } else {
+                gpio_set_value(GPIO_PTT4, 0);
+                writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT);
+        }
+}
+
+static struct resource sh_eth_giga0_resources[] = {
+        {
+                .start  = 0xfee00000,
+                .end    = 0xfee007ff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                /* TSU */
+                .start  = 0xfee01800,
+                .end    = 0xfee01fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = 315,
+                .end    = 315,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct sh_eth_plat_data sh7757_eth_giga0_pdata = {
+        .phy = 18,
+        .edmac_endian = EDMAC_LITTLE_ENDIAN,
+        .register_type = SH_ETH_REG_GIGABIT,
+        .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
+        .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
+};
+
+static struct platform_device sh7757_eth_giga0_device = {
+        .name           = "sh-eth",
+        .resource       = sh_eth_giga0_resources,
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(sh_eth_giga0_resources),
+        .dev            = {
+                .platform_data = &sh7757_eth_giga0_pdata,
+        },
+};
+
+static struct resource sh_eth_giga1_resources[] = {
+        {
+                .start  = 0xfee00800,
+                .end    = 0xfee00fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = 316,
+                .end    = 316,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct sh_eth_plat_data sh7757_eth_giga1_pdata = {
+        .phy = 19,
+        .edmac_endian = EDMAC_LITTLE_ENDIAN,
+        .register_type = SH_ETH_REG_GIGABIT,
+        .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
+        .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
+};
+
+static struct platform_device sh7757_eth_giga1_device = {
+        .name           = "sh-eth",
+        .resource       = sh_eth_giga1_resources,
+        .id             = 3,
+        .num_resources  = ARRAY_SIZE(sh_eth_giga1_resources),
+        .dev            = {
+                .platform_data = &sh7757_eth_giga1_pdata,
+        },
+};
+
+/* SH_MMCIF */
+static struct resource sh_mmcif_resources[] = {
+        [0] = {
+                .start  = 0xffcb0000,
+                .end    = 0xffcb00ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 211,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = 212,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct sh_mmcif_dma sh7757lcr_mmcif_dma = {
+        .chan_priv_tx   = SHDMA_SLAVE_MMCIF_TX,
+        .chan_priv_rx   = SHDMA_SLAVE_MMCIF_RX,
+};
+
+static struct sh_mmcif_plat_data sh_mmcif_plat = {
+        .dma            = &sh7757lcr_mmcif_dma,
+        .sup_pclk       = 0x0f,
+        .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+        .ocr            = MMC_VDD_32_33 | MMC_VDD_33_34,
+};
+
+static struct platform_device sh_mmcif_device = {
+        .name           = "sh_mmcif",
+        .id             = 0,
+        .dev            = {
+                .platform_data          = &sh_mmcif_plat,
+        },
+        .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
+        .resource       = sh_mmcif_resources,
+};
+
+/* SDHI0 */
+static struct sh_mobile_sdhi_info sdhi_info = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI_RX,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
+};
+
+static struct resource sdhi_resources[] = {
+        [0] = {
+                .start  = 0xffe50000,
+                .end    = 0xffe501ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 20,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sdhi_device = {
+        .name           = "sh_mobile_sdhi",
+        .num_resources  = ARRAY_SIZE(sdhi_resources),
+        .resource       = sdhi_resources,
+        .id             = 0,
+        .dev    = {
+                .platform_data  = &sdhi_info,
+        },
+};
+
+static struct platform_device *sh7757lcr_devices[] __initdata = {
+        &heartbeat_device,
+        &sh7757_eth0_device,
+        &sh7757_eth1_device,
+        &sh7757_eth_giga0_device,
+        &sh7757_eth_giga1_device,
+        &sh_mmcif_device,
+        &sdhi_device,
+};
+
+static struct flash_platform_data spi_flash_data = {
+        .name = "m25p80",
+        .type = "m25px64",
+};
+
+static struct spi_board_info spi_board_info[] = {
+        {
+                .modalias = "m25p80",
+                .max_speed_hz = 25000000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .platform_data = &spi_flash_data,
+        },
+};
+
+static int __init sh7757lcr_devices_setup(void)
+{
+        /* RGMII (PTA) */
+        gpio_request(GPIO_FN_ET0_MDC, NULL);
+        gpio_request(GPIO_FN_ET0_MDIO, NULL);
+        gpio_request(GPIO_FN_ET1_MDC, NULL);
+        gpio_request(GPIO_FN_ET1_MDIO, NULL);
+
+        /* ONFI (PTB, PTZ) */
+        gpio_request(GPIO_FN_ON_NRE, NULL);
+        gpio_request(GPIO_FN_ON_NWE, NULL);
+        gpio_request(GPIO_FN_ON_NWP, NULL);
+        gpio_request(GPIO_FN_ON_NCE0, NULL);
+        gpio_request(GPIO_FN_ON_R_B0, NULL);
+        gpio_request(GPIO_FN_ON_ALE, NULL);
+        gpio_request(GPIO_FN_ON_CLE, NULL);
+
+        gpio_request(GPIO_FN_ON_DQ7, NULL);
+        gpio_request(GPIO_FN_ON_DQ6, NULL);
+        gpio_request(GPIO_FN_ON_DQ5, NULL);
+        gpio_request(GPIO_FN_ON_DQ4, NULL);
+        gpio_request(GPIO_FN_ON_DQ3, NULL);
+        gpio_request(GPIO_FN_ON_DQ2, NULL);
+        gpio_request(GPIO_FN_ON_DQ1, NULL);
+        gpio_request(GPIO_FN_ON_DQ0, NULL);
+
+        /* IRQ8 to 0 (PTB, PTC) */
+        gpio_request(GPIO_FN_IRQ8, NULL);
+        gpio_request(GPIO_FN_IRQ7, NULL);
+        gpio_request(GPIO_FN_IRQ6, NULL);
+        gpio_request(GPIO_FN_IRQ5, NULL);
+        gpio_request(GPIO_FN_IRQ4, NULL);
+        gpio_request(GPIO_FN_IRQ3, NULL);
+        gpio_request(GPIO_FN_IRQ2, NULL);
+        gpio_request(GPIO_FN_IRQ1, NULL);
+        gpio_request(GPIO_FN_IRQ0, NULL);
+
+        /* SPI0 (PTD) */
+        gpio_request(GPIO_FN_SP0_MOSI, NULL);
+        gpio_request(GPIO_FN_SP0_MISO, NULL);
+        gpio_request(GPIO_FN_SP0_SCK, NULL);
+        gpio_request(GPIO_FN_SP0_SCK_FB, NULL);
+        gpio_request(GPIO_FN_SP0_SS0, NULL);
+        gpio_request(GPIO_FN_SP0_SS1, NULL);
+        gpio_request(GPIO_FN_SP0_SS2, NULL);
+        gpio_request(GPIO_FN_SP0_SS3, NULL);
+
+        /* RMII 0/1 (PTE, PTF) */
+        gpio_request(GPIO_FN_RMII0_CRS_DV, NULL);
+        gpio_request(GPIO_FN_RMII0_TXD1, NULL);
+        gpio_request(GPIO_FN_RMII0_TXD0, NULL);
+        gpio_request(GPIO_FN_RMII0_TXEN, NULL);
+        gpio_request(GPIO_FN_RMII0_REFCLK, NULL);
+        gpio_request(GPIO_FN_RMII0_RXD1, NULL);
+        gpio_request(GPIO_FN_RMII0_RXD0, NULL);
+        gpio_request(GPIO_FN_RMII0_RX_ER, NULL);
+        gpio_request(GPIO_FN_RMII1_CRS_DV, NULL);
+        gpio_request(GPIO_FN_RMII1_TXD1, NULL);
+        gpio_request(GPIO_FN_RMII1_TXD0, NULL);
+        gpio_request(GPIO_FN_RMII1_TXEN, NULL);
+        gpio_request(GPIO_FN_RMII1_REFCLK, NULL);
+        gpio_request(GPIO_FN_RMII1_RXD1, NULL);
+        gpio_request(GPIO_FN_RMII1_RXD0, NULL);
+        gpio_request(GPIO_FN_RMII1_RX_ER, NULL);
+
+        /* eMMC (PTG) */
+        gpio_request(GPIO_FN_MMCCLK, NULL);
+        gpio_request(GPIO_FN_MMCCMD, NULL);
+        gpio_request(GPIO_FN_MMCDAT7, NULL);
+        gpio_request(GPIO_FN_MMCDAT6, NULL);
+        gpio_request(GPIO_FN_MMCDAT5, NULL);
+        gpio_request(GPIO_FN_MMCDAT4, NULL);
+        gpio_request(GPIO_FN_MMCDAT3, NULL);
+        gpio_request(GPIO_FN_MMCDAT2, NULL);
+        gpio_request(GPIO_FN_MMCDAT1, NULL);
+        gpio_request(GPIO_FN_MMCDAT0, NULL);
+
+        /* LPC (PTG, PTH, PTQ, PTU) */
+        gpio_request(GPIO_FN_SERIRQ, NULL);
+        gpio_request(GPIO_FN_LPCPD, NULL);
+        gpio_request(GPIO_FN_LDRQ, NULL);
+        gpio_request(GPIO_FN_WP, NULL);
+        gpio_request(GPIO_FN_FMS0, NULL);
+        gpio_request(GPIO_FN_LAD3, NULL);
+        gpio_request(GPIO_FN_LAD2, NULL);
+        gpio_request(GPIO_FN_LAD1, NULL);
+        gpio_request(GPIO_FN_LAD0, NULL);
+        gpio_request(GPIO_FN_LFRAME, NULL);
+        gpio_request(GPIO_FN_LRESET, NULL);
+        gpio_request(GPIO_FN_LCLK, NULL);
+        gpio_request(GPIO_FN_LGPIO7, NULL);
+        gpio_request(GPIO_FN_LGPIO6, NULL);
+        gpio_request(GPIO_FN_LGPIO5, NULL);
+        gpio_request(GPIO_FN_LGPIO4, NULL);
+
+        /* SPI1 (PTH) */
+        gpio_request(GPIO_FN_SP1_MOSI, NULL);
+        gpio_request(GPIO_FN_SP1_MISO, NULL);
+        gpio_request(GPIO_FN_SP1_SCK, NULL);
+        gpio_request(GPIO_FN_SP1_SCK_FB, NULL);
+        gpio_request(GPIO_FN_SP1_SS0, NULL);
+        gpio_request(GPIO_FN_SP1_SS1, NULL);
+
+        /* SDHI (PTI) */
+        gpio_request(GPIO_FN_SD_WP, NULL);
+        gpio_request(GPIO_FN_SD_CD, NULL);
+        gpio_request(GPIO_FN_SD_CLK, NULL);
+        gpio_request(GPIO_FN_SD_CMD, NULL);
+        gpio_request(GPIO_FN_SD_D3, NULL);
+        gpio_request(GPIO_FN_SD_D2, NULL);
+        gpio_request(GPIO_FN_SD_D1, NULL);
+        gpio_request(GPIO_FN_SD_D0, NULL);
+
+        /* SCIF3/4 (PTJ, PTW) */
+        gpio_request(GPIO_FN_RTS3, NULL);
+        gpio_request(GPIO_FN_CTS3, NULL);
+        gpio_request(GPIO_FN_TXD3, NULL);
+        gpio_request(GPIO_FN_RXD3, NULL);
+        gpio_request(GPIO_FN_RTS4, NULL);
+        gpio_request(GPIO_FN_RXD4, NULL);
+        gpio_request(GPIO_FN_TXD4, NULL);
+        gpio_request(GPIO_FN_CTS4, NULL);
+
+        /* SERMUX (PTK, PTL, PTO, PTV) */
+        gpio_request(GPIO_FN_COM2_TXD, NULL);
+        gpio_request(GPIO_FN_COM2_RXD, NULL);
+        gpio_request(GPIO_FN_COM2_RTS, NULL);
+        gpio_request(GPIO_FN_COM2_CTS, NULL);
+        gpio_request(GPIO_FN_COM2_DTR, NULL);
+        gpio_request(GPIO_FN_COM2_DSR, NULL);
+        gpio_request(GPIO_FN_COM2_DCD, NULL);
+        gpio_request(GPIO_FN_COM2_RI, NULL);
+        gpio_request(GPIO_FN_RAC_RXD, NULL);
+        gpio_request(GPIO_FN_RAC_RTS, NULL);
+        gpio_request(GPIO_FN_RAC_CTS, NULL);
+        gpio_request(GPIO_FN_RAC_DTR, NULL);
+        gpio_request(GPIO_FN_RAC_DSR, NULL);
+        gpio_request(GPIO_FN_RAC_DCD, NULL);
+        gpio_request(GPIO_FN_RAC_TXD, NULL);
+        gpio_request(GPIO_FN_COM1_TXD, NULL);
+        gpio_request(GPIO_FN_COM1_RXD, NULL);
+        gpio_request(GPIO_FN_COM1_RTS, NULL);
+        gpio_request(GPIO_FN_COM1_CTS, NULL);
+
+        writeb(0x10, 0xfe470000);       /* SMR0: SerMux mode 0 */
+
+        /* IIC (PTM, PTR, PTS) */
+        gpio_request(GPIO_FN_SDA7, NULL);
+        gpio_request(GPIO_FN_SCL7, NULL);
+        gpio_request(GPIO_FN_SDA6, NULL);
+        gpio_request(GPIO_FN_SCL6, NULL);
+        gpio_request(GPIO_FN_SDA5, NULL);
+        gpio_request(GPIO_FN_SCL5, NULL);
+        gpio_request(GPIO_FN_SDA4, NULL);
+        gpio_request(GPIO_FN_SCL4, NULL);
+        gpio_request(GPIO_FN_SDA3, NULL);
+        gpio_request(GPIO_FN_SCL3, NULL);
+        gpio_request(GPIO_FN_SDA2, NULL);
+        gpio_request(GPIO_FN_SCL2, NULL);
+        gpio_request(GPIO_FN_SDA1, NULL);
+        gpio_request(GPIO_FN_SCL1, NULL);
+        gpio_request(GPIO_FN_SDA0, NULL);
+        gpio_request(GPIO_FN_SCL0, NULL);
+
+        /* USB (PTN) */
+        gpio_request(GPIO_FN_VBUS_EN, NULL);
+        gpio_request(GPIO_FN_VBUS_OC, NULL);
+
+        /* SGPIO1/0 (PTN, PTO) */
+        gpio_request(GPIO_FN_SGPIO1_CLK, NULL);
+        gpio_request(GPIO_FN_SGPIO1_LOAD, NULL);
+        gpio_request(GPIO_FN_SGPIO1_DI, NULL);
+        gpio_request(GPIO_FN_SGPIO1_DO, NULL);
+        gpio_request(GPIO_FN_SGPIO0_CLK, NULL);
+        gpio_request(GPIO_FN_SGPIO0_LOAD, NULL);
+        gpio_request(GPIO_FN_SGPIO0_DI, NULL);
+        gpio_request(GPIO_FN_SGPIO0_DO, NULL);
+
+        /* WDT (PTN) */
+        gpio_request(GPIO_FN_SUB_CLKIN, NULL);
+
+        /* System (PTT) */
+        gpio_request(GPIO_FN_STATUS1, NULL);
+        gpio_request(GPIO_FN_STATUS0, NULL);
+
+        /* PWMX (PTT) */
+        gpio_request(GPIO_FN_PWMX1, NULL);
+        gpio_request(GPIO_FN_PWMX0, NULL);
+
+        /* R-SPI (PTV) */
+        gpio_request(GPIO_FN_R_SPI_MOSI, NULL);
+        gpio_request(GPIO_FN_R_SPI_MISO, NULL);
+        gpio_request(GPIO_FN_R_SPI_RSPCK, NULL);
+        gpio_request(GPIO_FN_R_SPI_SSL0, NULL);
+        gpio_request(GPIO_FN_R_SPI_SSL1, NULL);
+
+        /* EVC (PTV, PTW) */
+        gpio_request(GPIO_FN_EVENT7, NULL);
+        gpio_request(GPIO_FN_EVENT6, NULL);
+        gpio_request(GPIO_FN_EVENT5, NULL);
+        gpio_request(GPIO_FN_EVENT4, NULL);
+        gpio_request(GPIO_FN_EVENT3, NULL);
+        gpio_request(GPIO_FN_EVENT2, NULL);
+        gpio_request(GPIO_FN_EVENT1, NULL);
+        gpio_request(GPIO_FN_EVENT0, NULL);
+
+        /* LED for heartbeat */
+        gpio_request(GPIO_PTU3, NULL);
+        gpio_direction_output(GPIO_PTU3, 1);
+        gpio_request(GPIO_PTU2, NULL);
+        gpio_direction_output(GPIO_PTU2, 1);
+        gpio_request(GPIO_PTU1, NULL);
+        gpio_direction_output(GPIO_PTU1, 1);
+        gpio_request(GPIO_PTU0, NULL);
+        gpio_direction_output(GPIO_PTU0, 1);
+
+        /* control for MDIO of Gigabit Ethernet */
+        gpio_request(GPIO_PTT4, NULL);
+        gpio_direction_output(GPIO_PTT4, 1);
+
+        /* control for eMMC */
+        gpio_request(GPIO_PTT7, NULL);          /* eMMC_RST# */
+        gpio_direction_output(GPIO_PTT7, 0);
+        gpio_request(GPIO_PTT6, NULL);          /* eMMC_INDEX# */
+        gpio_direction_output(GPIO_PTT6, 0);
+        gpio_request(GPIO_PTT5, NULL);          /* eMMC_PRST# */
+        gpio_direction_output(GPIO_PTT5, 1);
+
+        /* register SPI device information */
+        spi_register_board_info(spi_board_info,
+                                ARRAY_SIZE(spi_board_info));
+
+        /* General platform */
+        return platform_add_devices(sh7757lcr_devices,
+                                    ARRAY_SIZE(sh7757lcr_devices));
+}
+arch_initcall(sh7757lcr_devices_setup);
+
+/* Initialize IRQ setting */
+void __init init_sh7757lcr_IRQ(void)
+{
+        plat_irq_setup_pins(IRQ_MODE_IRQ7654);
+        plat_irq_setup_pins(IRQ_MODE_IRQ3210);
+}
+
+/* Initialize the board */
+static void __init sh7757lcr_setup(char **cmdline_p)
+{
+        printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n");
+}
+
+static int sh7757lcr_mode_pins(void)
+{
+        int value = 0;
+
+        /* These are the factory default settings of S3 (Low active).
+         * If you change these dip switches then you will need to
+         * adjust the values below as well.
+         */
+        value |= MODE_PIN0;     /* Clock Mode: 1 */
+
+        return value;
+}
+
+/* The Machine Vector */
+static struct sh_machine_vector mv_sh7757lcr __initmv = {
+        .mv_name                = "SH7757LCR",
+        .mv_setup               = sh7757lcr_setup,
+        .mv_init_irq            = init_sh7757lcr_IRQ,
+        .mv_mode_pins           = sh7757lcr_mode_pins,
+};
+
diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c
index fe7e686c94ac..ee65ff05c558 100644
--- a/arch/sh/boards/board-sh7785lcr.c
+++ b/arch/sh/boards/board-sh7785lcr.c
@@ -284,7 +284,7 @@ static int __init sh7785lcr_devices_setup(void)
         return platform_add_devices(sh7785lcr_devices,
                                     ARRAY_SIZE(sh7785lcr_devices));
 }
-__initcall(sh7785lcr_devices_setup);
+device_initcall(sh7785lcr_devices_setup);
 
 /* Initialize IRQ setting */
 void __init init_sh7785lcr_IRQ(void)
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c
index 3da116f47f01..969421f64a15 100644
--- a/arch/sh/boards/mach-ap325rxa/setup.c
+++ b/arch/sh/boards/mach-ap325rxa/setup.c
@@ -14,6 +14,8 @@
 #include <linux/device.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/sh_flctl.h>
 #include <linux/delay.h>
@@ -154,28 +156,53 @@ static struct platform_device nand_flash_device = {
 #define PORT_DRVCRA     0xA405018A
 #define PORT_DRVCRB     0xA405018C
 
+static int ap320_wvga_set_brightness(void *board_data, int brightness)
+{
+        if (brightness) {
+                gpio_set_value(GPIO_PTS3, 0);
+                __raw_writew(0x100, FPGA_BKLREG);
+        } else {
+                __raw_writew(0, FPGA_BKLREG);
+                gpio_set_value(GPIO_PTS3, 1);
+        }
+        
+        return 0;
+}
+
+static int ap320_wvga_get_brightness(void *board_data)
+{
+        return gpio_get_value(GPIO_PTS3);
+}
+
 static void ap320_wvga_power_on(void *board_data, struct fb_info *info)
 {
         msleep(100);
 
         /* ASD AP-320/325 LCD ON */
         __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
-
-        /* backlight */
-        gpio_set_value(GPIO_PTS3, 0);
-        __raw_writew(0x100, FPGA_BKLREG);
 }
 
 static void ap320_wvga_power_off(void *board_data)
 {
-        /* backlight */
-        __raw_writew(0, FPGA_BKLREG);
-        gpio_set_value(GPIO_PTS3, 1);
-
         /* ASD AP-320/325 LCD OFF */
         __raw_writew(0, FPGA_LCDREG);
 }
 
+const static struct fb_videomode ap325rxa_lcdc_modes[] = {
+        {
+                .name = "LB070WV1",
+                .xres = 800,
+                .yres = 480,
+                .left_margin = 32,
+                .right_margin = 160,
+                .hsync_len = 8,
+                .upper_margin = 63,
+                .lower_margin = 80,
+                .vsync_len = 1,
+                .sync = 0, /* hsync and vsync are active low */
+        },
+};
+
 static struct sh_mobile_lcdc_info lcdc_info = {
         .clock_source = LCDC_CLK_EXTERNAL,
         .ch[0] = {
@@ -183,18 +210,8 @@ static struct sh_mobile_lcdc_info lcdc_info = {
                 .bpp = 16,
                 .interface_type = RGB18,
                 .clock_divider = 1,
-                .lcd_cfg = {
-                        .name = "LB070WV1",
-                        .xres = 800,
-                        .yres = 480,
-                        .left_margin = 32,
-                        .right_margin = 160,
-                        .hsync_len = 8,
-                        .upper_margin = 63,
-                        .lower_margin = 80,
-                        .vsync_len = 1,
-                        .sync = 0, /* hsync and vsync are active low */
-                },
+                .lcd_cfg = ap325rxa_lcdc_modes,
+                .num_cfg = ARRAY_SIZE(ap325rxa_lcdc_modes),
                 .lcd_size_cfg = { /* 7.0 inch */
                         .width = 152,
                         .height = 91,
@@ -202,6 +219,12 @@ static struct sh_mobile_lcdc_info lcdc_info = {
                 .board_cfg = {
                         .display_on = ap320_wvga_power_on,
                         .display_off = ap320_wvga_power_off,
+                        .set_brightness = ap320_wvga_set_brightness,
+                        .get_brightness = ap320_wvga_get_brightness,
+                },
+                .bl_info = {
+                        .name = "sh_mobile_lcdc_bl",
+                        .max_brightness = 1,
                 },
         }
 };
@@ -336,37 +359,31 @@ static struct soc_camera_link camera_link = {
         .priv           = &camera_info,
 };
 
-static void dummy_release(struct device *dev)
+static struct platform_device *camera_device;
+
+static void ap325rxa_camera_release(struct device *dev)
 {
+        soc_camera_platform_release(&camera_device);
 }
 
-static struct platform_device camera_device = {
-        .name           = "soc_camera_platform",
-        .dev            = {
-                .platform_data  = &camera_info,
-                .release        = dummy_release,
-        },
-};
-
 static int ap325rxa_camera_add(struct soc_camera_link *icl,
                                struct device *dev)
 {
-        if (icl != &camera_link || camera_probe() <= 0)
-                return -ENODEV;
+        int ret = soc_camera_platform_add(icl, dev, &camera_device, &camera_link,
+                                          ap325rxa_camera_release, 0);
+        if (ret < 0)
+                return ret;
 
-        camera_info.dev = dev;
+        ret = camera_probe();
+        if (ret < 0)
+                soc_camera_platform_del(icl, camera_device, &camera_link);
 
-        return platform_device_register(&camera_device);
+        return ret;
 }
 
 static void ap325rxa_camera_del(struct soc_camera_link *icl)
 {
-        if (icl != &camera_link)
-                return;
-
-        platform_device_unregister(&camera_device);
-        memset(&camera_device.dev.kobj, 0,
-               sizeof(camera_device.dev.kobj));
+        soc_camera_platform_del(icl, camera_device, &camera_link);
 }
 #endif /* CONFIG_I2C */
 
@@ -416,7 +433,7 @@ static struct resource sdhi0_cn3_resources[] = {
         [0] = {
                 .name   = "SDHI0",
                 .start  = 0x04ce0000,
-                .end    = 0x04ce01ff,
+                .end    = 0x04ce00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -425,11 +442,18 @@ static struct resource sdhi0_cn3_resources[] = {
         },
 };
 
+static struct sh_mobile_sdhi_info sdhi0_cn3_data = {
+        .tmio_caps      = MMC_CAP_SDIO_IRQ,
+};
+
 static struct platform_device sdhi0_cn3_device = {
         .name           = "sh_mobile_sdhi",
         .id             = 0, /* "sdhi0" clock */
         .num_resources  = ARRAY_SIZE(sdhi0_cn3_resources),
         .resource       = sdhi0_cn3_resources,
+        .dev = {
+                .platform_data = &sdhi0_cn3_data,
+        },
         .archdata = {
                 .hwblk_id = HWBLK_SDHI0,
         },
@@ -439,7 +463,7 @@ static struct resource sdhi1_cn7_resources[] = {
         [0] = {
                 .name   = "SDHI1",
                 .start  = 0x04cf0000,
-                .end    = 0x04cf01ff,
+                .end    = 0x04cf00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -448,11 +472,18 @@ static struct resource sdhi1_cn7_resources[] = {
         },
 };
 
+static struct sh_mobile_sdhi_info sdhi1_cn7_data = {
+        .tmio_caps      = MMC_CAP_SDIO_IRQ,
+};
+
 static struct platform_device sdhi1_cn7_device = {
         .name           = "sh_mobile_sdhi",
         .id             = 1, /* "sdhi1" clock */
         .num_resources  = ARRAY_SIZE(sdhi1_cn7_resources),
         .resource       = sdhi1_cn7_resources,
+        .dev = {
+                .platform_data = &sdhi1_cn7_data,
+        },
         .archdata = {
                 .hwblk_id = HWBLK_SDHI1,
         },
@@ -481,7 +512,6 @@ static struct soc_camera_link ov7725_link = {
         .power          = ov7725_power,
         .board_info     = &ap325rxa_i2c_camera[0],
         .i2c_adapter_id = 0,
-        .module_name    = "ov772x",
         .priv           = &ov7725_info,
 };
 
diff --git a/arch/sh/boards/mach-cayman/irq.c b/arch/sh/boards/mach-cayman/irq.c
index 1394b078db36..311bcebdbd07 100644
--- a/arch/sh/boards/mach-cayman/irq.c
+++ b/arch/sh/boards/mach-cayman/irq.c
@@ -55,8 +55,9 @@ static struct irqaction cayman_action_pci2 = {
         .flags          = IRQF_DISABLED,
 };
 
-static void enable_cayman_irq(unsigned int irq)
+static void enable_cayman_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned long flags;
         unsigned long mask;
         unsigned int reg;
@@ -72,8 +73,9 @@ static void enable_cayman_irq(unsigned int irq)
         local_irq_restore(flags);
 }
 
-void disable_cayman_irq(unsigned int irq)
+static void disable_cayman_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned long flags;
         unsigned long mask;
         unsigned int reg;
@@ -89,16 +91,10 @@ void disable_cayman_irq(unsigned int irq)
         local_irq_restore(flags);
 }
 
-static void ack_cayman_irq(unsigned int irq)
-{
-        disable_cayman_irq(irq);
-}
-
 struct irq_chip cayman_irq_type = {
         .name           = "Cayman-IRQ",
-        .unmask         = enable_cayman_irq,
-        .mask           = disable_cayman_irq,
-        .mask_ack       = ack_cayman_irq,
+        .irq_unmask     = enable_cayman_irq,
+        .irq_mask       = disable_cayman_irq,
 };
 
 int cayman_irq_demux(int evt)
@@ -153,8 +149,8 @@ void init_cayman_irq(void)
         }
 
         for (i = 0; i < NR_EXT_IRQS; i++) {
-                set_irq_chip_and_handler(START_EXT_IRQS + i, &cayman_irq_type,
-                                         handle_level_irq);
+                irq_set_chip_and_handler(START_EXT_IRQS + i,
+                                         &cayman_irq_type, handle_level_irq);
         }
 
         /* Setup the SMSC interrupt */
diff --git a/arch/sh/boards/mach-cayman/setup.c b/arch/sh/boards/mach-cayman/setup.c
index 7e8216ac31bd..e89e8e122a26 100644
--- a/arch/sh/boards/mach-cayman/setup.c
+++ b/arch/sh/boards/mach-cayman/setup.c
@@ -165,7 +165,7 @@ static int __init smsc_superio_setup(void)
 
         return 0;
 }
-__initcall(smsc_superio_setup);
+device_initcall(smsc_superio_setup);
 
 static void __iomem *cayman_ioport_map(unsigned long port, unsigned int len)
 {
diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c
index d932667410ab..f63d323f411f 100644
--- a/arch/sh/boards/mach-dreamcast/irq.c
+++ b/arch/sh/boards/mach-dreamcast/irq.c
@@ -51,7 +51,7 @@
  */
 #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)
 
-/* Return the hardware event's bit positon within the EMR/ESR */
+/* Return the hardware event's bit position within the EMR/ESR */
 #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)
 
 /*
@@ -60,8 +60,9 @@
  */
 
 /* Disable the hardware event by masking its bit in its EMR */
-static inline void disable_systemasic_irq(unsigned int irq)
+static inline void disable_systemasic_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
         __u32 mask;
 
@@ -71,8 +72,9 @@ static inline void disable_systemasic_irq(unsigned int irq)
 }
 
 /* Enable the hardware event by setting its bit in its EMR */
-static inline void enable_systemasic_irq(unsigned int irq)
+static inline void enable_systemasic_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         __u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
         __u32 mask;
 
@@ -82,18 +84,19 @@ static inline void enable_systemasic_irq(unsigned int irq)
 }
 
 /* Acknowledge a hardware event by writing its bit back to its ESR */
-static void mask_ack_systemasic_irq(unsigned int irq)
+static void mask_ack_systemasic_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         __u32 esr = ESR_BASE + (LEVEL(irq) << 2);
-        disable_systemasic_irq(irq);
+        disable_systemasic_irq(data);
         outl((1 << EVENT_BIT(irq)), esr);
 }
 
 struct irq_chip systemasic_int = {
         .name           = "System ASIC",
-        .mask           = disable_systemasic_irq,
-        .mask_ack       = mask_ack_systemasic_irq,
-        .unmask         = enable_systemasic_irq,
+        .irq_mask       = disable_systemasic_irq,
+        .irq_mask_ack   = mask_ack_systemasic_irq,
+        .irq_unmask     = enable_systemasic_irq,
 };
 
 /*
@@ -158,7 +161,6 @@ void systemasic_irq_init(void)
                         return;
                 }
 
-                set_irq_chip_and_handler(i, &systemasic_int,
-                                         handle_level_irq);
+                irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq);
         }
 }
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 1d7b495a7db4..513cb1a2e6c8 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -11,15 +11,16 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
-#include <linux/mfd/sh_mobile_sdhi.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/usb/r8a66597.h>
+#include <linux/usb/renesas_usbhs.h>
 #include <linux/i2c.h>
 #include <linux/i2c/tsc2007.h>
 #include <linux/spi/spi.h>
@@ -142,6 +143,8 @@ static struct resource sh_eth_resources[] = {
 static struct sh_eth_plat_data sh_eth_plat = {
         .phy = 0x1f, /* SMSC LAN8700 */
         .edmac_endian = EDMAC_LITTLE_ENDIAN,
+        .register_type = SH_ETH_REG_FAST_SH4,
+        .phy_interface = PHY_INTERFACE_MODE_MII,
         .ether_link_active_low = 1
 };
 
@@ -230,20 +233,111 @@ static struct platform_device usb1_common_device = {
         .resource       = usb1_common_resources,
 };
 
+/*
+ * USBHS
+ */
+static int usbhs_get_id(struct platform_device *pdev)
+{
+        return gpio_get_value(GPIO_PTB3);
+}
+
+static struct renesas_usbhs_platform_info usbhs_info = {
+        .platform_callback = {
+                .get_id         = usbhs_get_id,
+        },
+        .driver_param = {
+                .buswait_bwait          = 4,
+                .detection_delay        = 5,
+        },
+};
+
+static struct resource usbhs_resources[] = {
+        [0] = {
+                .start  = 0xa4d90000,
+                .end    = 0xa4d90124 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 66,
+                .end    = 66,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device usbhs_device = {
+        .name   = "renesas_usbhs",
+        .id     = 1,
+        .dev = {
+                .dma_mask               = NULL,         /*  not use dma */
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &usbhs_info,
+        },
+        .num_resources  = ARRAY_SIZE(usbhs_resources),
+        .resource       = usbhs_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_USB1,
+        },
+};
+
 /* LCDC */
+const static struct fb_videomode ecovec_lcd_modes[] = {
+        {
+                .name           = "Panel",
+                .xres           = 800,
+                .yres           = 480,
+                .left_margin    = 220,
+                .right_margin   = 110,
+                .hsync_len      = 70,
+                .upper_margin   = 20,
+                .lower_margin   = 5,
+                .vsync_len      = 5,
+                .sync           = 0, /* hsync and vsync are active low */
+        },
+};
+
+const static struct fb_videomode ecovec_dvi_modes[] = {
+        {
+                .name           = "DVI",
+                .xres           = 1280,
+                .yres           = 720,
+                .left_margin    = 220,
+                .right_margin   = 110,
+                .hsync_len      = 40,
+                .upper_margin   = 20,
+                .lower_margin   = 5,
+                .vsync_len      = 5,
+                .sync = 0, /* hsync and vsync are active low */
+        },
+};
+
+static int ecovec24_set_brightness(void *board_data, int brightness)
+{
+        gpio_set_value(GPIO_PTR1, brightness);
+
+        return 0;
+}
+
+static int ecovec24_get_brightness(void *board_data)
+{
+        return gpio_get_value(GPIO_PTR1);
+}
+
 static struct sh_mobile_lcdc_info lcdc_info = {
         .ch[0] = {
                 .interface_type = RGB18,
                 .chan = LCDC_CHAN_MAINLCD,
                 .bpp = 16,
-                .lcd_cfg = {
-                        .sync = 0, /* hsync and vsync are active low */
-                },
                 .lcd_size_cfg = { /* 7.0 inch */
                         .width = 152,
                         .height = 91,
                 },
                 .board_cfg = {
+                        .set_brightness = ecovec24_set_brightness,
+                        .get_brightness = ecovec24_get_brightness,
+                },
+                .bl_info = {
+                        .name = "sh_mobile_lcdc_bl",
+                        .max_brightness = 1,
                 },
         }
 };
@@ -435,7 +529,7 @@ static struct i2c_board_info ts_i2c_clients = {
         .irq            = IRQ0,
 };
 
-#ifdef CONFIG_MFD_SH_MOBILE_SDHI
+#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
 /* SDHI0 */
 static void sdhi0_set_pwr(struct platform_device *pdev, int state)
 {
@@ -446,13 +540,14 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
         .set_pwr        = sdhi0_set_pwr,
+        .tmio_caps      = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD,
 };
 
 static struct resource sdhi0_resources[] = {
         [0] = {
                 .name   = "SDHI0",
                 .start  = 0x04ce0000,
-                .end    = 0x04ce01ff,
+                .end    = 0x04ce00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -474,7 +569,7 @@ static struct platform_device sdhi0_device = {
         },
 };
 
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
 /* SDHI1 */
 static void sdhi1_set_pwr(struct platform_device *pdev, int state)
 {
@@ -484,6 +579,7 @@ static void sdhi1_set_pwr(struct platform_device *pdev, int state)
 static struct sh_mobile_sdhi_info sdhi1_info = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
+        .tmio_caps      = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD,
         .set_pwr        = sdhi1_set_pwr,
 };
 
@@ -491,7 +587,7 @@ static struct resource sdhi1_resources[] = {
         [0] = {
                 .name   = "SDHI1",
                 .start  = 0x04cf0000,
-                .end    = 0x04cf01ff,
+                .end    = 0x04cf00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -620,7 +716,6 @@ static struct soc_camera_link tw9910_link = {
         .bus_id         = 1,
         .power          = tw9910_power,
         .board_info     = &i2c_camera[0],
-        .module_name    = "tw9910",
         .priv           = &tw9910_info,
 };
 
@@ -644,7 +739,6 @@ static struct soc_camera_link mt9t112_link1 = {
         .power          = mt9t112_power1,
         .bus_id         = 0,
         .board_info     = &i2c_camera[1],
-        .module_name    = "mt9t112",
         .priv           = &mt9t112_info1,
 };
 
@@ -667,7 +761,6 @@ static struct soc_camera_link mt9t112_link2 = {
         .power          = mt9t112_power2,
         .bus_id         = 1,
         .board_info     = &i2c_camera[2],
-        .module_name    = "mt9t112",
         .priv           = &mt9t112_info2,
 };
 
@@ -696,38 +789,8 @@ static struct platform_device camera_devices[] = {
 };
 
 /* FSI */
-/*
- * FSI-B use external clock which came from da7210.
- * So, we should change parent of fsi
- */
-#define FCLKBCR         0xa415000c
-static void fsimck_init(struct clk *clk)
-{
-        u32 status = __raw_readl(clk->enable_reg);
-
-        /* use external clock */
-        status &= ~0x000000ff;
-        status |= 0x00000080;
-
-        __raw_writel(status, clk->enable_reg);
-}
-
-static struct clk_ops fsimck_clk_ops = {
-        .init = fsimck_init,
-};
-
-static struct clk fsimckb_clk = {
-        .ops            = &fsimck_clk_ops,
-        .enable_reg     = (void __iomem *)FCLKBCR,
-        .rate           = 0, /* unknown */
-};
-
 static struct sh_fsi_platform_info fsi_info = {
-        .portb_flags = SH_FSI_BRS_INV |
-                       SH_FSI_OUT_SLAVE_MODE |
-                       SH_FSI_IN_SLAVE_MODE |
-                       SH_FSI_OFMT(I2S) |
-                       SH_FSI_IFMT(I2S),
+        .portb_flags = SH_FSI_BRS_INV,
 };
 
 static struct resource fsi_resources[] = {
@@ -793,7 +856,6 @@ static struct sh_vou_pdata sh_vou_pdata = {
         .flags          = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
         .board_info     = &ak8813,
         .i2c_adap       = 0,
-        .module_name    = "ak881x",
 };
 
 static struct resource sh_vou_resources[] = {
@@ -821,7 +883,7 @@ static struct platform_device vou_device = {
         },
 };
 
-#if defined(CONFIG_MMC_SH_MMCIF)
+#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
 /* SH_MMCIF */
 static void mmcif_set_pwr(struct platform_device *pdev, int state)
 {
@@ -870,6 +932,9 @@ static struct platform_device sh_mmcif_device = {
         },
         .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
         .resource       = sh_mmcif_resources,
+        .archdata = {
+                .hwblk_id = HWBLK_MMC,
+        },
 };
 #endif
 
@@ -879,13 +944,14 @@ static struct platform_device *ecovec_devices[] __initdata = {
         &sh_eth_device,
         &usb0_host_device,
         &usb1_common_device,
+        &usbhs_device,
         &lcdc_device,
         &ceu0_device,
         &ceu1_device,
         &keysc_device,
-#ifdef CONFIG_MFD_SH_MOBILE_SDHI
+#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
         &sdhi0_device,
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
         &sdhi1_device,
 #endif
 #else
@@ -897,7 +963,7 @@ static struct platform_device *ecovec_devices[] __initdata = {
         &fsi_device,
         &irda_device,
         &vou_device,
-#if defined(CONFIG_MMC_SH_MMCIF)
+#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
         &sh_mmcif_device,
 #endif
 };
@@ -939,7 +1005,7 @@ static void __init sh_eth_init(struct sh_eth_plat_data *pd)
                 return;
         }
 
-        /* read MAC address frome EEPROM */
+        /* read MAC address from EEPROM */
         for (i = 0; i < sizeof(pd->mac_addr); i++) {
                 pd->mac_addr[i] = mac_read(a, 0x10 + i);
                 msleep(10);
@@ -1079,33 +1145,18 @@ static int __init arch_setup(void)
         if (gpio_get_value(GPIO_PTE6)) {
                 /* DVI */
                 lcdc_info.clock_source                  = LCDC_CLK_EXTERNAL;
-                lcdc_info.ch[0].clock_divider           = 1,
-                lcdc_info.ch[0].lcd_cfg.name            = "DVI";
-                lcdc_info.ch[0].lcd_cfg.xres            = 1280;
-                lcdc_info.ch[0].lcd_cfg.yres            = 720;
-                lcdc_info.ch[0].lcd_cfg.left_margin     = 220;
-                lcdc_info.ch[0].lcd_cfg.right_margin    = 110;
-                lcdc_info.ch[0].lcd_cfg.hsync_len       = 40;
-                lcdc_info.ch[0].lcd_cfg.upper_margin    = 20;
-                lcdc_info.ch[0].lcd_cfg.lower_margin    = 5;
-                lcdc_info.ch[0].lcd_cfg.vsync_len       = 5;
+                lcdc_info.ch[0].clock_divider           = 1;
+                lcdc_info.ch[0].lcd_cfg                 = ecovec_dvi_modes;
+                lcdc_info.ch[0].num_cfg                 = ARRAY_SIZE(ecovec_dvi_modes);
 
                 gpio_set_value(GPIO_PTA2, 1);
                 gpio_set_value(GPIO_PTU1, 1);
         } else {
                 /* Panel */
-
                 lcdc_info.clock_source                  = LCDC_CLK_PERIPHERAL;
-                lcdc_info.ch[0].clock_divider           = 2,
-                lcdc_info.ch[0].lcd_cfg.name            = "Panel";
-                lcdc_info.ch[0].lcd_cfg.xres            = 800;
-                lcdc_info.ch[0].lcd_cfg.yres            = 480;
-                lcdc_info.ch[0].lcd_cfg.left_margin     = 220;
-                lcdc_info.ch[0].lcd_cfg.right_margin    = 110;
-                lcdc_info.ch[0].lcd_cfg.hsync_len       = 70;
-                lcdc_info.ch[0].lcd_cfg.upper_margin    = 20;
-                lcdc_info.ch[0].lcd_cfg.lower_margin    = 5;
-                lcdc_info.ch[0].lcd_cfg.vsync_len       = 5;
+                lcdc_info.ch[0].clock_divider           = 2;
+                lcdc_info.ch[0].lcd_cfg                 = ecovec_lcd_modes;
+                lcdc_info.ch[0].num_cfg                 = ARRAY_SIZE(ecovec_lcd_modes);
 
                 gpio_set_value(GPIO_PTR1, 1);
 
@@ -1120,7 +1171,7 @@ static int __init arch_setup(void)
 
                 /* enable TouchScreen */
                 i2c_register_board_info(0, &ts_i2c_clients, 1);
-                set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW);
+                irq_set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW);
         }
 
         /* enable CEU0 */
@@ -1180,7 +1231,7 @@ static int __init arch_setup(void)
         gpio_direction_input(GPIO_PTR5);
         gpio_direction_input(GPIO_PTR6);
 
-#ifdef CONFIG_MFD_SH_MOBILE_SDHI
+#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
         /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */
         gpio_request(GPIO_FN_SDHI0CD,  NULL);
         gpio_request(GPIO_FN_SDHI0WP,  NULL);
@@ -1193,7 +1244,7 @@ static int __init arch_setup(void)
         gpio_request(GPIO_PTB6, NULL);
         gpio_direction_output(GPIO_PTB6, 0);
 
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
         /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
         gpio_request(GPIO_FN_SDHI1CD,  NULL);
         gpio_request(GPIO_FN_SDHI1WP,  NULL);
@@ -1248,18 +1299,18 @@ static int __init arch_setup(void)
 
         /* set SPU2 clock to 83.4 MHz */
         clk = clk_get(NULL, "spu_clk");
-        if (clk) {
+        if (!IS_ERR(clk)) {
                 clk_set_rate(clk, clk_round_rate(clk, 83333333));
                 clk_put(clk);
         }
 
         /* change parent of FSI B */
         clk = clk_get(NULL, "fsib_clk");
-        if (clk) {
-                clk_register(&fsimckb_clk);
-                clk_set_parent(clk, &fsimckb_clk);
-                clk_set_rate(clk, 11000);
-                clk_set_rate(&fsimckb_clk, 11000);
+        if (!IS_ERR(clk)) {
+                /* 48kHz dummy clock was used to make sure 1/1 divide */
+                clk_set_rate(&sh7724_fsimckb_clk, 48000);
+                clk_set_parent(clk, &sh7724_fsimckb_clk);
+                clk_set_rate(clk, 48000);
                 clk_put(clk);
         }
 
@@ -1273,7 +1324,7 @@ static int __init arch_setup(void)
 
         /* set VPU clock to 166 MHz */
         clk = clk_get(NULL, "vpu_clk");
-        if (clk) {
+        if (!IS_ERR(clk)) {
                 clk_set_rate(clk, clk_round_rate(clk, 166000000));
                 clk_put(clk);
         }
@@ -1284,7 +1335,7 @@ static int __init arch_setup(void)
         gpio_request(GPIO_PTU5, NULL);
         gpio_direction_output(GPIO_PTU5, 0);
 
-#if defined(CONFIG_MMC_SH_MMCIF)
+#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
         /* enable MMCIF (needs DS2.6,7 set to OFF,ON) */
         gpio_request(GPIO_FN_MMC_D7, NULL);
         gpio_request(GPIO_FN_MMC_D6, NULL);
@@ -1310,6 +1361,7 @@ static int __init arch_setup(void)
         i2c_register_board_info(1, i2c1_devices,
                                 ARRAY_SIZE(i2c1_devices));
 
+#if defined(CONFIG_VIDEO_SH_VOU) || defined(CONFIG_VIDEO_SH_VOU_MODULE)
         /* VOU */
         gpio_request(GPIO_FN_DV_D15, NULL);
         gpio_request(GPIO_FN_DV_D14, NULL);
@@ -1341,6 +1393,7 @@ static int __init arch_setup(void)
 
         /* Remove reset */
         gpio_set_value(GPIO_PTG4, 1);
+#endif
 
         return platform_add_devices(ecovec_devices,
                                     ARRAY_SIZE(ecovec_devices));
diff --git a/arch/sh/boards/mach-edosk7705/Makefile b/arch/sh/boards/mach-edosk7705/Makefile
deleted file mode 100644
index cd54acb51499..000000000000
--- a/arch/sh/boards/mach-edosk7705/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the EDOSK7705 specific parts of the kernel
-#
-
-obj-y    := setup.o io.o
diff --git a/arch/sh/boards/mach-edosk7705/io.c b/arch/sh/boards/mach-edosk7705/io.c
deleted file mode 100644
index 5b9c57c43241..000000000000
--- a/arch/sh/boards/mach-edosk7705/io.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * arch/sh/boards/renesas/edosk7705/io.c
- *
- * Copyright (C) 2001  Ian da Silva, Jeremy Siegel
- * Based largely on io_se.c.
- *
- * I/O routines for Hitachi EDOSK7705 board.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/io.h>
-#include <mach/edosk7705.h>
-#include <asm/addrspace.h>
-
-#define SMC_IOADDR      0xA2000000
-
-/* Map the Ethernet addresses as if it is at 0x300 - 0x320 */
-static unsigned long sh_edosk7705_isa_port2addr(unsigned long port)
-{
-        /*
-         * SMC91C96 registers are 4 byte aligned rather than the
-         * usual 2 byte!
-         */
-        if (port >= 0x300 && port < 0x320)
-                return SMC_IOADDR + ((port - 0x300) * 2);
-
-        maybebadio(port);
-        return port;
-}
-
-/* Trying to read / write bytes on odd-byte boundaries to the Ethernet
- * registers causes problems. So we bit-shift the value and read / write
- * in 2 byte chunks. Setting the low byte to 0 does not cause problems
- * now as odd byte writes are only made on the bit mask / interrupt
- * register. This may not be the case in future Mar-2003 SJD
- */
-unsigned char sh_edosk7705_inb(unsigned long port)
-{
-        if (port >= 0x300 && port < 0x320 && port & 0x01)
-                return __raw_readw(port - 1) >> 8;
-
-        return __raw_readb(sh_edosk7705_isa_port2addr(port));
-}
-
-void sh_edosk7705_outb(unsigned char value, unsigned long port)
-{
-        if (port >= 0x300 && port < 0x320 && port & 0x01) {
-                __raw_writew(((unsigned short)value << 8), port - 1);
-                return;
-        }
-
-        __raw_writeb(value, sh_edosk7705_isa_port2addr(port));
-}
-
-void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count)
-{
-        unsigned char *p = addr;
-
-        while (count--)
-                *p++ = sh_edosk7705_inb(port);
-}
-
-void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count)
-{
-        unsigned char *p = (unsigned char *)addr;
-
-        while (count--)
-                sh_edosk7705_outb(*p++, port);
-}
diff --git a/arch/sh/boards/mach-edosk7705/setup.c b/arch/sh/boards/mach-edosk7705/setup.c
deleted file mode 100644
index d59225e26fb9..000000000000
--- a/arch/sh/boards/mach-edosk7705/setup.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * arch/sh/boards/renesas/edosk7705/setup.c
- *
- * Copyright (C) 2000  Kazumoto Kojima
- *
- * Hitachi SolutionEngine Support.
- *
- * Modified for edosk7705 development
- * board by S. Dunn, 2003.
- */
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <asm/machvec.h>
-#include <mach/edosk7705.h>
-
-static void __init sh_edosk7705_init_irq(void)
-{
-        /* This is the Ethernet interrupt */
-        make_imask_irq(0x09);
-}
-
-/*
- * The Machine Vector
- */
-static struct sh_machine_vector mv_edosk7705 __initmv = {
-        .mv_name                = "EDOSK7705",
-        .mv_nr_irqs             = 80,
-
-        .mv_inb                 = sh_edosk7705_inb,
-        .mv_outb                = sh_edosk7705_outb,
-
-        .mv_insb                = sh_edosk7705_insb,
-        .mv_outsb               = sh_edosk7705_outsb,
-
-        .mv_init_irq            = sh_edosk7705_init_irq,
-};
diff --git a/arch/sh/boards/mach-highlander/setup.c b/arch/sh/boards/mach-highlander/setup.c
index a5ecfbacaf36..87618c91d178 100644
--- a/arch/sh/boards/mach-highlander/setup.c
+++ b/arch/sh/boards/mach-highlander/setup.c
@@ -24,10 +24,10 @@
 #include <linux/interrupt.h>
 #include <linux/usb/r8a66597.h>
 #include <linux/usb/m66592.h>
+#include <linux/clkdev.h>
 #include <net/ax88796.h>
 #include <asm/machvec.h>
 #include <mach/highlander.h>
-#include <asm/clkdev.h>
 #include <asm/clock.h>
 #include <asm/heartbeat.h>
 #include <asm/io.h>
diff --git a/arch/sh/boards/mach-hp6xx/pm.c b/arch/sh/boards/mach-hp6xx/pm.c
index 4499a3749d40..adc9b4bba828 100644
--- a/arch/sh/boards/mach-hp6xx/pm.c
+++ b/arch/sh/boards/mach-hp6xx/pm.c
@@ -143,7 +143,7 @@ static int hp6x0_pm_enter(suspend_state_t state)
         return 0;
 }
 
-static struct platform_suspend_ops hp6x0_pm_ops = {
+static const struct platform_suspend_ops hp6x0_pm_ops = {
         .enter          = hp6x0_pm_enter,
         .valid          = suspend_valid_only_mem,
 };
diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c
index 68994a163f6c..8b4abbbd1477 100644
--- a/arch/sh/boards/mach-kfr2r09/setup.c
+++ b/arch/sh/boards/mach-kfr2r09/setup.c
@@ -10,7 +10,8 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
-#include <linux/mfd/sh_mobile_sdhi.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/onenand.h>
@@ -126,6 +127,21 @@ static struct platform_device kfr2r09_sh_keysc_device = {
         },
 };
 
+const static struct fb_videomode kfr2r09_lcdc_modes[] = {
+        {
+                .name = "TX07D34VM0AAA",
+                .xres = 240,
+                .yres = 400,
+                .left_margin = 0,
+                .right_margin = 16,
+                .hsync_len = 8,
+                .upper_margin = 0,
+                .lower_margin = 1,
+                .vsync_len = 1,
+                .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+        },
+};
+
 static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
         .clock_source = LCDC_CLK_BUS,
         .ch[0] = {
@@ -134,18 +150,8 @@ static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
                 .interface_type = SYS18,
                 .clock_divider = 6,
                 .flags = LCDC_FLAGS_DWPOL,
-                .lcd_cfg = {
-                        .name = "TX07D34VM0AAA",
-                        .xres = 240,
-                        .yres = 400,
-                        .left_margin = 0,
-                        .right_margin = 16,
-                        .hsync_len = 8,
-                        .upper_margin = 0,
-                        .lower_margin = 1,
-                        .vsync_len = 1,
-                        .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-                },
+                .lcd_cfg = kfr2r09_lcdc_modes,
+                .num_cfg = ARRAY_SIZE(kfr2r09_lcdc_modes),
                 .lcd_size_cfg = {
                         .width = 35,
                         .height = 58,
@@ -333,7 +339,6 @@ static struct soc_camera_link rj54n1_link = {
         .power          = camera_power,
         .board_info     = &kfr2r09_i2c_camera,
         .i2c_adapter_id = 1,
-        .module_name    = "rj54n1cb0c",
         .priv           = &rj54n1_priv,
 };
 
@@ -349,7 +354,7 @@ static struct resource kfr2r09_sh_sdhi0_resources[] = {
         [0] = {
                 .name   = "SDHI0",
                 .start  = 0x04ce0000,
-                .end    = 0x04ce01ff,
+                .end    = 0x04ce00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -362,6 +367,7 @@ static struct sh_mobile_sdhi_info sh7724_sdhi0_data = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
         .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
+        .tmio_caps      = MMC_CAP_SDIO_IRQ,
 };
 
 static struct platform_device kfr2r09_sh_sdhi0_device = {
diff --git a/arch/sh/boards/mach-landisk/gio.c b/arch/sh/boards/mach-landisk/gio.c
index 01e6abb769b9..8132dff078fb 100644
--- a/arch/sh/boards/mach-landisk/gio.c
+++ b/arch/sh/boards/mach-landisk/gio.c
@@ -128,6 +128,7 @@ static const struct file_operations gio_fops = {
         .open = gio_open,       /* open */
         .release = gio_close,   /* release */
         .unlocked_ioctl = gio_ioctl,
+        .llseek = noop_llseek,
 };
 
 static int __init gio_init(void)
diff --git a/arch/sh/boards/mach-landisk/irq.c b/arch/sh/boards/mach-landisk/irq.c
index 96f38a4187d0..c00ace38db3f 100644
--- a/arch/sh/boards/mach-landisk/irq.c
+++ b/arch/sh/boards/mach-landisk/irq.c
@@ -1,9 +1,10 @@
 /*
- * arch/sh/boards/landisk/irq.c
+ * arch/sh/boards/mach-landisk/irq.c
  *
  * I-O DATA Device, Inc. LANDISK Support
  *
  * Copyright (C) 2005-2007 kogiidena
+ * Copyright (C) 2011 Nobuhiro Iwamatsu
  *
  * Copyright (C) 2001  Ian da Silva, Jeremy Siegel
  * Based largely on io_se.c.
@@ -12,45 +13,54 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  */
+
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <mach-landisk/mach/iodata_landisk.h>
 
-static void disable_landisk_irq(unsigned int irq)
-{
-        unsigned char mask = 0xff ^ (0x01 << (irq - 5));
+enum {
+        UNUSED = 0,
 
-        __raw_writeb(__raw_readb(PA_IMASK) & mask, PA_IMASK);
-}
-
-static void enable_landisk_irq(unsigned int irq)
-{
-        unsigned char value = (0x01 << (irq - 5));
+        PCI_INTA, /* PCI int A */
+        PCI_INTB, /* PCI int B */
+        PCI_INTC, /* PCI int C */
+        PCI_INTD, /* PCI int D */
+        ATA,      /* ATA */
+        FATA,     /* CF */
+        POWER,    /* Power swtich */
+        BUTTON,   /* Button swtich */
+};
 
-        __raw_writeb(__raw_readb(PA_IMASK) | value, PA_IMASK);
-}
+/* Vectors for LANDISK */
+static struct intc_vect vectors_landisk[] __initdata = {
+        INTC_IRQ(PCI_INTA, IRQ_PCIINTA),
+        INTC_IRQ(PCI_INTB, IRQ_PCIINTB),
+        INTC_IRQ(PCI_INTC, IRQ_PCIINTC),
+        INTC_IRQ(PCI_INTD, IRQ_PCIINTD),
+        INTC_IRQ(ATA, IRQ_ATA),
+        INTC_IRQ(FATA, IRQ_FATA),
+        INTC_IRQ(POWER, IRQ_POWER),
+        INTC_IRQ(BUTTON, IRQ_BUTTON),
+};
 
-static struct irq_chip landisk_irq_chip __read_mostly = {
-        .name           = "LANDISK",
-        .mask           = disable_landisk_irq,
-        .unmask         = enable_landisk_irq,
-        .mask_ack       = disable_landisk_irq,
+/* IRLMSK mask register layout for LANDISK */
+static struct intc_mask_reg mask_registers_landisk[] __initdata = {
+        { PA_IMASK, 0, 8, /* IRLMSK */
+          {  BUTTON, POWER, FATA, ATA,
+             PCI_INTD, PCI_INTC, PCI_INTB, PCI_INTA,
+          }
+        },
 };
 
+static DECLARE_INTC_DESC(intc_desc_landisk, "landisk", vectors_landisk, NULL,
+                        mask_registers_landisk, NULL, NULL);
 /*
  * Initialize IRQ setting
  */
 void __init init_landisk_IRQ(void)
 {
-        int i;
-
-        for (i = 5; i < 14; i++) {
-                disable_irq_nosync(i);
-                set_irq_chip_and_handler_name(i, &landisk_irq_chip,
-                                              handle_level_irq, "level");
-                enable_landisk_irq(i);
-        }
+        register_intc_controller(&intc_desc_landisk);
         __raw_writeb(0x00, PA_PWRINT_CLR);
 }
diff --git a/arch/sh/boards/mach-landisk/setup.c b/arch/sh/boards/mach-landisk/setup.c
index 50337acc18c5..f1147caebacf 100644
--- a/arch/sh/boards/mach-landisk/setup.c
+++ b/arch/sh/boards/mach-landisk/setup.c
@@ -21,11 +21,9 @@
 #include <mach-landisk/mach/iodata_landisk.h>
 #include <asm/io.h>
 
-void init_landisk_IRQ(void);
-
 static void landisk_power_off(void)
 {
-        __raw_writeb(0x01, PA_SHUTDOWN);
+        __raw_writeb(0x01, PA_SHUTDOWN);
 }
 
 static struct resource cf_ide_resources[3];
@@ -83,11 +81,11 @@ static int __init landisk_devices_setup(void)
                                     ARRAY_SIZE(landisk_devices));
 }
 
-__initcall(landisk_devices_setup);
+device_initcall(landisk_devices_setup);
 
 static void __init landisk_setup(char **cmdline_p)
 {
-        /* LED ON */
+        /* LED ON */
         __raw_writeb(__raw_readb(PA_LED) | 0x03, PA_LED);
 
         printk(KERN_INFO "I-O DATA DEVICE, INC. \"LANDISK Series\" support.\n");
@@ -99,7 +97,6 @@ static void __init landisk_setup(char **cmdline_p)
  */
 static struct sh_machine_vector mv_landisk __initmv = {
         .mv_name = "LANDISK",
-        .mv_nr_irqs = 72,
         .mv_setup = landisk_setup,
         .mv_init_irq = init_landisk_IRQ,
 };
diff --git a/arch/sh/boards/mach-microdev/io.c b/arch/sh/boards/mach-microdev/io.c
index 2960c659020e..acdafb0c6404 100644
--- a/arch/sh/boards/mach-microdev/io.c
+++ b/arch/sh/boards/mach-microdev/io.c
@@ -54,7 +54,7 @@
 /*
  * map I/O ports to memory-mapped addresses
  */
-static unsigned long microdev_isa_port2addr(unsigned long offset)
+void __iomem *microdev_ioport_map(unsigned long offset, unsigned int len)
 {
         unsigned long result;
 
@@ -72,16 +72,6 @@ static unsigned long microdev_isa_port2addr(unsigned long offset)
                          *      Configuration Registers
                          */
                 result = IO_SUPERIO_PHYS + (offset << 1);
-#if 0
-        } else if (offset == KBD_DATA_REG || offset == KBD_CNTL_REG ||
-                   offset == KBD_STATUS_REG) {
-                        /*
-                         *      SMSC FDC37C93xAPM SuperIO chip
-                         *
-                         *      PS/2 Keyboard + Mouse (ports 0x60 and 0x64).
-                         */
-                result = IO_SUPERIO_PHYS + (offset << 1);
-#endif
         } else if (((offset >= IO_IDE1_BASE) &&
                     (offset <  IO_IDE1_BASE + IO_IDE_EXTENT)) ||
                     (offset == IO_IDE1_MISC)) {
@@ -131,237 +121,5 @@ static unsigned long microdev_isa_port2addr(unsigned long offset)
                 result = PVR;
         }
 
-        return result;
-}
-
-#define PORT2ADDR(x) (microdev_isa_port2addr(x))
-
-static inline void delay(void)
-{
-#if defined(CONFIG_PCI)
-        /* System board present, just make a dummy SRAM access.  (CS0 will be
-           mapped to PCI memory, probably good to avoid it.) */
-        __raw_readw(0xa6800000);
-#else
-        /* CS0 will be mapped to flash, ROM etc so safe to access it. */
-        __raw_readw(0xa0000000);
-#endif
-}
-
-unsigned char microdev_inb(unsigned long port)
-{
-#ifdef CONFIG_PCI
-        if (port >= PCIBIOS_MIN_IO)
-                return microdev_pci_inb(port);
-#endif
-        return *(volatile unsigned char*)PORT2ADDR(port);
-}
-
-unsigned short microdev_inw(unsigned long port)
-{
-#ifdef CONFIG_PCI
-        if (port >= PCIBIOS_MIN_IO)
-                return microdev_pci_inw(port);
-#endif
-        return *(volatile unsigned short*)PORT2ADDR(port);
-}
-
-unsigned int microdev_inl(unsigned long port)
-{
-#ifdef CONFIG_PCI
-        if (port >= PCIBIOS_MIN_IO)
-                return microdev_pci_inl(port);
-#endif
-        return *(volatile unsigned int*)PORT2ADDR(port);
-}
-
-void microdev_outw(unsigned short b, unsigned long port)
-{
-#ifdef CONFIG_PCI
-        if (port >= PCIBIOS_MIN_IO) {
-                microdev_pci_outw(b, port);
-                return;
-        }
-#endif
-        *(volatile unsigned short*)PORT2ADDR(port) = b;
-}
-
-void microdev_outb(unsigned char b, unsigned long port)
-{
-#ifdef CONFIG_PCI
-        if (port >= PCIBIOS_MIN_IO) {
-                microdev_pci_outb(b, port);
-                return;
-        }
-#endif
-
-        /*
-         *      There is a board feature with the current SH4-202 MicroDev in
-         *      that the 2 byte enables (nBE0 and nBE1) are tied together (and
-         *      to the Chip Select Line (Ethernet_CS)). Due to this connectivity,
-         *      it is not possible to safely perform 8-bit writes to the
-         *      Ethernet registers, as 16-bits will be consumed from the Data
-         *      lines (corrupting the other byte).  Hence, this function is
-         *      written to implement 16-bit read/modify/write for all byte-wide
-         *      accesses.
-         *
-         *      Note: there is no problem with byte READS (even or odd).
-         *
-         *                      Sean McGoogan - 16th June 2003.
-         */
-        if ((port >= IO_LAN91C111_BASE) &&
-            (port <  IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) {
-                        /*
-                         * Then are trying to perform a byte-write to the
-                         * LAN91C111.  This needs special care.
-                         */
-                if (port % 2 == 1) {    /* is the port odd ? */
-                        /* unset bit-0, i.e. make even */
-                        const unsigned long evenPort = port-1;
-                        unsigned short word;
-
-                        /*
-                         * do a 16-bit read/write to write to 'port',
-                         * preserving even byte.
-                         *
-                         *      Even addresses are bits 0-7
-                         *      Odd  addresses are bits 8-15
-                         */
-                        word = microdev_inw(evenPort);
-                        word = (word & 0xffu) | (b << 8);
-                        microdev_outw(word, evenPort);
-                } else {
-                        /* else, we are trying to do an even byte write */
-                        unsigned short word;
-
-                        /*
-                         * do a 16-bit read/write to write to 'port',
-                         * preserving odd byte.
-                         *
-                         *      Even addresses are bits 0-7
-                         *      Odd  addresses are bits 8-15
-                         */
-                        word = microdev_inw(port);
-                        word = (word & 0xff00u) | (b);
-                        microdev_outw(word, port);
-                }
-        } else {
-                *(volatile unsigned char*)PORT2ADDR(port) = b;
-        }
-}
-
-void microdev_outl(unsigned int b, unsigned long port)
-{
-#ifdef CONFIG_PCI
-        if (port >= PCIBIOS_MIN_IO) {
-                microdev_pci_outl(b, port);
-                return;
-        }
-#endif
-        *(volatile unsigned int*)PORT2ADDR(port) = b;
-}
-
-unsigned char microdev_inb_p(unsigned long port)
-{
-        unsigned char v = microdev_inb(port);
-        delay();
-        return v;
-}
-
-unsigned short microdev_inw_p(unsigned long port)
-{
-        unsigned short v = microdev_inw(port);
-        delay();
-        return v;
-}
-
-unsigned int microdev_inl_p(unsigned long port)
-{
-        unsigned int v = microdev_inl(port);
-        delay();
-        return v;
-}
-
-void microdev_outb_p(unsigned char b, unsigned long port)
-{
-        microdev_outb(b, port);
-        delay();
-}
-
-void microdev_outw_p(unsigned short b, unsigned long port)
-{
-        microdev_outw(b, port);
-        delay();
-}
-
-void microdev_outl_p(unsigned int b, unsigned long port)
-{
-        microdev_outl(b, port);
-        delay();
-}
-
-void microdev_insb(unsigned long port, void *buffer, unsigned long count)
-{
-        volatile unsigned char *port_addr;
-        unsigned char *buf = buffer;
-
-        port_addr = (volatile unsigned char *)PORT2ADDR(port);
-
-        while (count--)
-                *buf++ = *port_addr;
-}
-
-void microdev_insw(unsigned long port, void *buffer, unsigned long count)
-{
-        volatile unsigned short *port_addr;
-        unsigned short *buf = buffer;
-
-        port_addr = (volatile unsigned short *)PORT2ADDR(port);
-
-        while (count--)
-                *buf++ = *port_addr;
-}
-
-void microdev_insl(unsigned long port, void *buffer, unsigned long count)
-{
-        volatile unsigned long *port_addr;
-        unsigned int *buf = buffer;
-
-        port_addr = (volatile unsigned long *)PORT2ADDR(port);
-
-        while (count--)
-                *buf++ = *port_addr;
-}
-
-void microdev_outsb(unsigned long port, const void *buffer, unsigned long count)
-{
-        volatile unsigned char *port_addr;
-        const unsigned char *buf = buffer;
-
-        port_addr = (volatile unsigned char *)PORT2ADDR(port);
-
-        while (count--)
-                *port_addr = *buf++;
-}
-
-void microdev_outsw(unsigned long port, const void *buffer, unsigned long count)
-{
-        volatile unsigned short *port_addr;
-        const unsigned short *buf = buffer;
-
-        port_addr = (volatile unsigned short *)PORT2ADDR(port);
-
-        while (count--)
-                *port_addr = *buf++;
-}
-
-void microdev_outsl(unsigned long port, const void *buffer, unsigned long count)
-{
-        volatile unsigned long *port_addr;
-        const unsigned int *buf = buffer;
-
-        port_addr = (volatile unsigned long *)PORT2ADDR(port);
-
-        while (count--)
-                *port_addr = *buf++;
+        return (void __iomem *)result;
 }
diff --git a/arch/sh/boards/mach-microdev/irq.c b/arch/sh/boards/mach-microdev/irq.c
index a26d16669aa2..4fb00369f0e2 100644
--- a/arch/sh/boards/mach-microdev/irq.c
+++ b/arch/sh/boards/mach-microdev/irq.c
@@ -65,19 +65,9 @@ static const struct {
 #  error Inconsistancy in defining the IRQ# for primary IDE!
 #endif
 
-static void enable_microdev_irq(unsigned int irq);
-static void disable_microdev_irq(unsigned int irq);
-static void mask_and_ack_microdev(unsigned int);
-
-static struct irq_chip microdev_irq_type = {
-        .name = "MicroDev-IRQ",
-        .unmask = enable_microdev_irq,
-        .mask = disable_microdev_irq,
-        .ack = mask_and_ack_microdev,
-};
-
-static void disable_microdev_irq(unsigned int irq)
+static void disable_microdev_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned int fpgaIrq;
 
         if (irq >= NUM_EXTERNAL_IRQS)
@@ -91,8 +81,9 @@ static void disable_microdev_irq(unsigned int irq)
         __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
 }
 
-static void enable_microdev_irq(unsigned int irq)
+static void enable_microdev_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned long priorityReg, priorities, pri;
         unsigned int fpgaIrq;
 
@@ -116,17 +107,18 @@ static void enable_microdev_irq(unsigned int irq)
         __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
 }
 
+static struct irq_chip microdev_irq_type = {
+        .name = "MicroDev-IRQ",
+        .irq_unmask = enable_microdev_irq,
+        .irq_mask = disable_microdev_irq,
+};
+
 /* This function sets the desired irq handler to be a MicroDev type */
 static void __init make_microdev_irq(unsigned int irq)
 {
         disable_irq_nosync(irq);
-        set_irq_chip_and_handler(irq, &microdev_irq_type, handle_level_irq);
-        disable_microdev_irq(irq);
-}
-
-static void mask_and_ack_microdev(unsigned int irq)
-{
-        disable_microdev_irq(irq);
+        irq_set_chip_and_handler(irq, &microdev_irq_type, handle_level_irq);
+        disable_microdev_irq(irq_get_irq_data(irq));
 }
 
 extern void __init init_microdev_irq(void)
diff --git a/arch/sh/boards/mach-microdev/setup.c b/arch/sh/boards/mach-microdev/setup.c
index d1df2a4fb9b8..d8a747291e03 100644
--- a/arch/sh/boards/mach-microdev/setup.c
+++ b/arch/sh/boards/mach-microdev/setup.c
@@ -195,27 +195,6 @@ device_initcall(microdev_devices_setup);
 static struct sh_machine_vector mv_sh4202_microdev __initmv = {
         .mv_name                = "SH4-202 MicroDev",
         .mv_nr_irqs             = 72,
-
-        .mv_inb                 = microdev_inb,
-        .mv_inw                 = microdev_inw,
-        .mv_inl                 = microdev_inl,
-        .mv_outb                = microdev_outb,
-        .mv_outw                = microdev_outw,
-        .mv_outl                = microdev_outl,
-
-        .mv_inb_p               = microdev_inb_p,
-        .mv_inw_p               = microdev_inw_p,
-        .mv_inl_p               = microdev_inl_p,
-        .mv_outb_p              = microdev_outb_p,
-        .mv_outw_p              = microdev_outw_p,
-        .mv_outl_p              = microdev_outl_p,
-
-        .mv_insb                = microdev_insb,
-        .mv_insw                = microdev_insw,
-        .mv_insl                = microdev_insl,
-        .mv_outsb               = microdev_outsb,
-        .mv_outsw               = microdev_outsw,
-        .mv_outsl               = microdev_outsl,
-
+        .mv_ioport_map          = microdev_ioport_map,
         .mv_init_irq            = init_microdev_irq,
 };
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index 662debe4ead2..184fde169132 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -12,7 +12,8 @@
 #include <linux/interrupt.h>
 #include <linux/input.h>
 #include <linux/input/sh_keysc.h>
-#include <linux/mfd/sh_mobile_sdhi.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
 #include <linux/i2c.h>
@@ -213,51 +214,55 @@ static struct platform_device migor_nand_flash_device = {
         }
 };
 
+const static struct fb_videomode migor_lcd_modes[] = {
+        {
+#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
+                .name = "LB070WV1",
+                .xres = 800,
+                .yres = 480,
+                .left_margin = 64,
+                .right_margin = 16,
+                .hsync_len = 120,
+                .sync = 0,
+#elif defined(CONFIG_SH_MIGOR_QVGA)
+                .name = "PH240320T",
+                .xres = 320,
+                .yres = 240,
+                .left_margin = 0,
+                .right_margin = 16,
+                .hsync_len = 8,
+                .sync = FB_SYNC_HOR_HIGH_ACT,
+#endif
+                .upper_margin = 1,
+                .lower_margin = 17,
+                .vsync_len = 2,
+        },
+};
+
 static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
-#ifdef CONFIG_SH_MIGOR_RTA_WVGA
+#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
         .clock_source = LCDC_CLK_BUS,
         .ch[0] = {
                 .chan = LCDC_CHAN_MAINLCD,
                 .bpp = 16,
                 .interface_type = RGB16,
                 .clock_divider = 2,
-                .lcd_cfg = {
-                        .name = "LB070WV1",
-                        .xres = 800,
-                        .yres = 480,
-                        .left_margin = 64,
-                        .right_margin = 16,
-                        .hsync_len = 120,
-                        .upper_margin = 1,
-                        .lower_margin = 17,
-                        .vsync_len = 2,
-                        .sync = 0,
-                },
+                .lcd_cfg = migor_lcd_modes,
+                .num_cfg = ARRAY_SIZE(migor_lcd_modes),
                 .lcd_size_cfg = { /* 7.0 inch */
                         .width = 152,
                         .height = 91,
                 },
         }
-#endif
-#ifdef CONFIG_SH_MIGOR_QVGA
+#elif defined(CONFIG_SH_MIGOR_QVGA)
         .clock_source = LCDC_CLK_PERIPHERAL,
         .ch[0] = {
                 .chan = LCDC_CHAN_MAINLCD,
                 .bpp = 16,
                 .interface_type = SYS16A,
                 .clock_divider = 10,
-                .lcd_cfg = {
-                        .name = "PH240320T",
-                        .xres = 320,
-                        .yres = 240,
-                        .left_margin = 0,
-                        .right_margin = 16,
-                        .hsync_len = 8,
-                        .upper_margin = 1,
-                        .lower_margin = 17,
-                        .vsync_len = 2,
-                        .sync = FB_SYNC_HOR_HIGH_ACT,
-                },
+                .lcd_cfg = migor_lcd_modes,
+                .num_cfg = ARRAY_SIZE(migor_lcd_modes),
                 .lcd_size_cfg = { /* 2.4 inch */
                         .width = 49,
                         .height = 37,
@@ -394,7 +399,7 @@ static struct resource sdhi_cn9_resources[] = {
         [0] = {
                 .name   = "SDHI",
                 .start  = 0x04ce0000,
-                .end    = 0x04ce01ff,
+                .end    = 0x04ce00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -406,6 +411,7 @@ static struct resource sdhi_cn9_resources[] = {
 static struct sh_mobile_sdhi_info sh7724_sdhi_data = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
+        .tmio_caps      = MMC_CAP_SDIO_IRQ,
 };
 
 static struct platform_device sdhi_cn9_device = {
@@ -450,7 +456,6 @@ static struct soc_camera_link ov7725_link = {
         .power          = ov7725_power,
         .board_info     = &migor_i2c_camera[0],
         .i2c_adapter_id = 0,
-        .module_name    = "ov772x",
         .priv           = &ov7725_info,
 };
 
@@ -463,7 +468,6 @@ static struct soc_camera_link tw9910_link = {
         .power          = tw9910_power,
         .board_info     = &migor_i2c_camera[1],
         .i2c_adapter_id = 0,
-        .module_name    = "tw9910",
         .priv           = &tw9910_info,
 };
 
diff --git a/arch/sh/boards/mach-r2d/setup.c b/arch/sh/boards/mach-r2d/setup.c
index b84df6a3a93c..4b98a5251f83 100644
--- a/arch/sh/boards/mach-r2d/setup.c
+++ b/arch/sh/boards/mach-r2d/setup.c
@@ -258,7 +258,7 @@ static int __init rts7751r2d_devices_setup(void)
         return platform_add_devices(rts7751r2d_devices,
                                     ARRAY_SIZE(rts7751r2d_devices));
 }
-__initcall(rts7751r2d_devices_setup);
+device_initcall(rts7751r2d_devices_setup);
 
 static void rts7751r2d_power_off(void)
 {
diff --git a/arch/sh/boards/mach-rsk/devices-rsk7203.c b/arch/sh/boards/mach-rsk/devices-rsk7203.c
index 4fa08ba10253..a8089f79d058 100644
--- a/arch/sh/boards/mach-rsk/devices-rsk7203.c
+++ b/arch/sh/boards/mach-rsk/devices-rsk7203.c
@@ -1,7 +1,7 @@
 /*
  * Renesas Technology Europe RSK+ 7203 Support.
  *
- * Copyright (C) 2008 Paul Mundt
+ * Copyright (C) 2008 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -12,7 +12,9 @@
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/smsc911x.h>
+#include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/gpio_keys.h>
 #include <linux/leds.h>
 #include <asm/machvec.h>
 #include <asm/io.h>
@@ -84,9 +86,42 @@ static struct platform_device led_device = {
         },
 };
 
+static struct gpio_keys_button rsk7203_gpio_keys_table[] = {
+        {
+                .code           = BTN_0,
+                .gpio           = GPIO_PB0,
+                .active_low     = 1,
+                .desc           = "SW1",
+        }, {
+                .code           = BTN_1,
+                .gpio           = GPIO_PB1,
+                .active_low     = 1,
+                .desc           = "SW2",
+        }, {
+                .code           = BTN_2,
+                .gpio           = GPIO_PB2,
+                .active_low     = 1,
+                .desc           = "SW3",
+        },
+};
+
+static struct gpio_keys_platform_data rsk7203_gpio_keys_info = {
+        .buttons        = rsk7203_gpio_keys_table,
+        .nbuttons       = ARRAY_SIZE(rsk7203_gpio_keys_table),
+        .poll_interval  = 50, /* default to 50ms */
+};
+
+static struct platform_device keys_device = {
+        .name           = "gpio-keys-polled",
+        .dev            = {
+                .platform_data  = &rsk7203_gpio_keys_info,
+        },
+};
+
 static struct platform_device *rsk7203_devices[] __initdata = {
         &smsc911x_device,
         &led_device,
+        &keys_device,
 };
 
 static int __init rsk7203_devices_setup(void)
diff --git a/arch/sh/boards/mach-sdk7786/Makefile b/arch/sh/boards/mach-sdk7786/Makefile
index a29f19e85b63..8ae56e9560ac 100644
--- a/arch/sh/boards/mach-sdk7786/Makefile
+++ b/arch/sh/boards/mach-sdk7786/Makefile
@@ -1 +1,4 @@
-obj-y   := setup.o fpga.o irq.o
+obj-y   := fpga.o irq.o nmi.o setup.o
+
+obj-$(CONFIG_GENERIC_GPIO)      += gpio.o
+obj-$(CONFIG_HAVE_SRAM_POOL)    += sram.o
diff --git a/arch/sh/boards/mach-sdk7786/gpio.c b/arch/sh/boards/mach-sdk7786/gpio.c
new file mode 100644
index 000000000000..f71ce09d4e15
--- /dev/null
+++ b/arch/sh/boards/mach-sdk7786/gpio.c
@@ -0,0 +1,49 @@
+/*
+ * SDK7786 FPGA USRGPIR Support.
+ *
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <mach/fpga.h>
+
+#define NR_FPGA_GPIOS   8
+
+static const char *usrgpir_gpio_names[NR_FPGA_GPIOS] = {
+        "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7",
+};
+
+static int usrgpir_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+        /* always in */
+        return 0;
+}
+
+static int usrgpir_gpio_get(struct gpio_chip *chip, unsigned gpio)
+{
+        return !!(fpga_read_reg(USRGPIR) & (1 << gpio));
+}
+
+static struct gpio_chip usrgpir_gpio_chip = {
+        .label                  = "sdk7786-fpga",
+        .names                  = usrgpir_gpio_names,
+        .direction_input        = usrgpir_gpio_direction_input,
+        .get                    = usrgpir_gpio_get,
+        .base                   = -1, /* don't care */
+        .ngpio                  = NR_FPGA_GPIOS,
+};
+
+static int __init usrgpir_gpio_setup(void)
+{
+        return gpiochip_add(&usrgpir_gpio_chip);
+}
+device_initcall(usrgpir_gpio_setup);
diff --git a/arch/sh/boards/mach-sdk7786/nmi.c b/arch/sh/boards/mach-sdk7786/nmi.c
new file mode 100644
index 000000000000..edcfa1f568ba
--- /dev/null
+++ b/arch/sh/boards/mach-sdk7786/nmi.c
@@ -0,0 +1,83 @@
+/*
+ * SDK7786 FPGA NMI Support.
+ *
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <mach/fpga.h>
+
+enum {
+        NMI_MODE_MANUAL,
+        NMI_MODE_AUX,
+        NMI_MODE_MASKED,
+        NMI_MODE_ANY,
+        NMI_MODE_UNKNOWN,
+};
+
+/*
+ * Default to the manual NMI switch.
+ */
+static unsigned int __initdata nmi_mode = NMI_MODE_ANY;
+
+static int __init nmi_mode_setup(char *str)
+{
+        if (!str)
+                return 0;
+
+        if (strcmp(str, "manual") == 0)
+                nmi_mode = NMI_MODE_MANUAL;
+        else if (strcmp(str, "aux") == 0)
+                nmi_mode = NMI_MODE_AUX;
+        else if (strcmp(str, "masked") == 0)
+                nmi_mode = NMI_MODE_MASKED;
+        else if (strcmp(str, "any") == 0)
+                nmi_mode = NMI_MODE_ANY;
+        else {
+                nmi_mode = NMI_MODE_UNKNOWN;
+                pr_warning("Unknown NMI mode %s\n", str);
+        }
+
+        printk("Set NMI mode to %d\n", nmi_mode);
+        return 0;
+}
+early_param("nmi_mode", nmi_mode_setup);
+
+void __init sdk7786_nmi_init(void)
+{
+        unsigned int source, mask, tmp;
+
+        switch (nmi_mode) {
+        case NMI_MODE_MANUAL:
+                source = NMISR_MAN_NMI;
+                mask = NMIMR_MAN_NMIM;
+                break;
+        case NMI_MODE_AUX:
+                source = NMISR_AUX_NMI;
+                mask = NMIMR_AUX_NMIM;
+                break;
+        case NMI_MODE_ANY:
+                source = NMISR_MAN_NMI | NMISR_AUX_NMI;
+                mask = NMIMR_MAN_NMIM | NMIMR_AUX_NMIM;
+                break;
+        case NMI_MODE_MASKED:
+        case NMI_MODE_UNKNOWN:
+        default:
+                source = mask = 0;
+                break;
+        }
+
+        /* Set the NMI source */
+        tmp = fpga_read_reg(NMISR);
+        tmp &= ~NMISR_MASK;
+        tmp |= source;
+        fpga_write_reg(tmp, NMISR);
+
+        /* And the IRQ masking */
+        fpga_write_reg(NMIMR_MASK ^ mask, NMIMR);
+}
diff --git a/arch/sh/boards/mach-sdk7786/setup.c b/arch/sh/boards/mach-sdk7786/setup.c
index 2ec1ea5cf8ef..1521aa75ee3a 100644
--- a/arch/sh/boards/mach-sdk7786/setup.c
+++ b/arch/sh/boards/mach-sdk7786/setup.c
@@ -15,11 +15,13 @@
 #include <linux/i2c.h>
 #include <linux/irq.h>
 #include <linux/clk.h>
+#include <linux/clkdev.h>
 #include <mach/fpga.h>
 #include <mach/irq.h>
 #include <asm/machvec.h>
 #include <asm/heartbeat.h>
 #include <asm/sizes.h>
+#include <asm/clock.h>
 #include <asm/reboot.h>
 #include <asm/smp-ops.h>
 
@@ -133,13 +135,52 @@ static int __init sdk7786_devices_setup(void)
 
         return sdk7786_i2c_setup();
 }
-__initcall(sdk7786_devices_setup);
+device_initcall(sdk7786_devices_setup);
 
 static int sdk7786_mode_pins(void)
 {
         return fpga_read_reg(MODSWR);
 }
 
+/*
+ * FPGA-driven PCIe clocks
+ *
+ * Historically these include the oscillator, clock B (slots 2/3/4) and
+ * clock A (slot 1 and the CPU clock). Newer revs of the PCB shove
+ * everything under a single PCIe clocks enable bit that happens to map
+ * to the same bit position as the oscillator bit for earlier FPGA
+ * versions.
+ *
+ * Given that the legacy clocks have the side-effect of shutting the CPU
+ * off through the FPGA along with the PCI slots, we simply leave them in
+ * their initial state and don't bother registering them with the clock
+ * framework.
+ */
+static int sdk7786_pcie_clk_enable(struct clk *clk)
+{
+        fpga_write_reg(fpga_read_reg(PCIECR) | PCIECR_CLKEN, PCIECR);
+        return 0;
+}
+
+static void sdk7786_pcie_clk_disable(struct clk *clk)
+{
+        fpga_write_reg(fpga_read_reg(PCIECR) & ~PCIECR_CLKEN, PCIECR);
+}
+
+static struct clk_ops sdk7786_pcie_clk_ops = {
+        .enable         = sdk7786_pcie_clk_enable,
+        .disable        = sdk7786_pcie_clk_disable,
+};
+
+static struct clk sdk7786_pcie_clk = {
+        .ops            = &sdk7786_pcie_clk_ops,
+};
+
+static struct clk_lookup sdk7786_pcie_cl = {
+        .con_id         = "pcie_plat_clk",
+        .clk            = &sdk7786_pcie_clk,
+};
+
 static int sdk7786_clk_init(void)
 {
         struct clk *clk;
@@ -158,7 +199,18 @@ static int sdk7786_clk_init(void)
         ret = clk_set_rate(clk, 33333333);
         clk_put(clk);
 
-        return ret;
+        /*
+         * Setup the FPGA clocks.
+         */
+        ret = clk_register(&sdk7786_pcie_clk);
+        if (unlikely(ret)) {
+                pr_err("FPGA clock registration failed\n");
+                return ret;
+        }
+
+        clkdev_add(&sdk7786_pcie_cl);
+
+        return 0;
 }
 
 static void sdk7786_restart(char *cmd)
@@ -185,6 +237,7 @@ static void __init sdk7786_setup(char **cmdline_p)
         pr_info("Renesas Technology Europe SDK7786 support:\n");
 
         sdk7786_fpga_init();
+        sdk7786_nmi_init();
 
         pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
 
diff --git a/arch/sh/boards/mach-sdk7786/sram.c b/arch/sh/boards/mach-sdk7786/sram.c
new file mode 100644
index 000000000000..c81c3abbe01c
--- /dev/null
+++ b/arch/sh/boards/mach-sdk7786/sram.c
@@ -0,0 +1,72 @@
+/*
+ * SDK7786 FPGA SRAM Support.
+ *
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <linux/string.h>
+#include <mach/fpga.h>
+#include <asm/sram.h>
+#include <asm/sizes.h>
+
+static int __init fpga_sram_init(void)
+{
+        unsigned long phys;
+        unsigned int area;
+        void __iomem *vaddr;
+        int ret;
+        u16 data;
+
+        /* Enable FPGA SRAM */
+        data = fpga_read_reg(LCLASR);
+        data |= LCLASR_FRAMEN;
+        fpga_write_reg(data, LCLASR);
+
+        /*
+         * FPGA_SEL determines the area mapping
+         */
+        area = (data & LCLASR_FPGA_SEL_MASK) >> LCLASR_FPGA_SEL_SHIFT;
+        if (unlikely(area == LCLASR_AREA_MASK)) {
+                pr_err("FPGA memory unmapped.\n");
+                return -ENXIO;
+        }
+
+        /*
+         * The memory itself occupies a 2KiB range at the top of the area
+         * immediately below the system registers.
+         */
+        phys = (area << 26) + SZ_64M - SZ_4K;
+
+        /*
+         * The FPGA SRAM resides in translatable physical space, so set
+         * up a mapping prior to inserting it in to the pool.
+         */
+        vaddr = ioremap(phys, SZ_2K);
+        if (unlikely(!vaddr)) {
+                pr_err("Failed remapping FPGA memory.\n");
+                return -ENXIO;
+        }
+
+        pr_info("Adding %dKiB of FPGA memory at 0x%08lx-0x%08lx "
+                "(area %d) to pool.\n",
+                SZ_2K >> 10, phys, phys + SZ_2K - 1, area);
+
+        ret = gen_pool_add(sram_pool, (unsigned long)vaddr, SZ_2K, -1);
+        if (unlikely(ret < 0)) {
+                pr_err("Failed adding memory\n");
+                iounmap(vaddr);
+                return ret;
+        }
+
+        return 0;
+}
+postcore_initcall(fpga_sram_init);
diff --git a/arch/sh/boards/mach-se/7206/Makefile b/arch/sh/boards/mach-se/7206/Makefile
index 63e7ed699f39..5c9eaa0535b9 100644
--- a/arch/sh/boards/mach-se/7206/Makefile
+++ b/arch/sh/boards/mach-se/7206/Makefile
@@ -2,4 +2,4 @@
 # Makefile for the 7206 SolutionEngine specific parts of the kernel
 #
 
-obj-y    := setup.o io.o irq.o
+obj-y    := setup.o irq.o
diff --git a/arch/sh/boards/mach-se/7206/io.c b/arch/sh/boards/mach-se/7206/io.c
deleted file mode 100644
index adadc77532ee..000000000000
--- a/arch/sh/boards/mach-se/7206/io.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* $Id: io.c,v 1.5 2004/02/22 23:08:43 kkojima Exp $
- *
- * linux/arch/sh/boards/se/7206/io.c
- *
- * Copyright (C) 2006 Yoshinori Sato
- *
- * I/O routine for Hitachi 7206 SolutionEngine.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <asm/io.h>
-#include <mach-se/mach/se7206.h>
-
-
-static inline void delay(void)
-{
-        __raw_readw(0x20000000);  /* P2 ROM Area */
-}
-
-/* MS7750 requires special versions of in*, out* routines, since
-   PC-like io ports are located at upper half byte of 16-bit word which
-   can be accessed only with 16-bit wide.  */
-
-static inline volatile __u16 *
-port2adr(unsigned int port)
-{
-        if (port >= 0x2000 && port < 0x2020)
-                return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
-        else if (port >= 0x300 && port < 0x310)
-                return (volatile __u16 *) (PA_SMSC + (port - 0x300));
-
-        return (volatile __u16 *)port;
-}
-
-unsigned char se7206_inb(unsigned long port)
-{
-        return (*port2adr(port)) & 0xff;
-}
-
-unsigned char se7206_inb_p(unsigned long port)
-{
-        unsigned long v;
-
-        v = (*port2adr(port)) & 0xff;
-        delay();
-        return v;
-}
-
-unsigned short se7206_inw(unsigned long port)
-{
-        return *port2adr(port);
-}
-
-void se7206_outb(unsigned char value, unsigned long port)
-{
-        *(port2adr(port)) = value;
-}
-
-void se7206_outb_p(unsigned char value, unsigned long port)
-{
-        *(port2adr(port)) = value;
-        delay();
-}
-
-void se7206_outw(unsigned short value, unsigned long port)
-{
-        *port2adr(port) = value;
-}
-
-void se7206_insb(unsigned long port, void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        __u8 *ap = addr;
-
-        while (count--)
-                *ap++ = *p;
-}
-
-void se7206_insw(unsigned long port, void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        __u16 *ap = addr;
-        while (count--)
-                *ap++ = *p;
-}
-
-void se7206_outsb(unsigned long port, const void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        const __u8 *ap = addr;
-
-        while (count--)
-                *p = *ap++;
-}
-
-void se7206_outsw(unsigned long port, const void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        const __u16 *ap = addr;
-        while (count--)
-                *p = *ap++;
-}
diff --git a/arch/sh/boards/mach-se/7206/irq.c b/arch/sh/boards/mach-se/7206/irq.c
index 8d82175d83ab..0db058e709e9 100644
--- a/arch/sh/boards/mach-se/7206/irq.c
+++ b/arch/sh/boards/mach-se/7206/irq.c
@@ -25,8 +25,9 @@
 #define INTC_IPR01 0xfffe0818
 #define INTC_ICR1  0xfffe0802
 
-static void disable_se7206_irq(unsigned int irq)
+static void disable_se7206_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned short val;
         unsigned short mask = 0xffff ^ (0x0f << 4 * (3 - (IRQ0_IRQ - irq)));
         unsigned short msk0,msk1;
@@ -55,8 +56,9 @@ static void disable_se7206_irq(unsigned int irq)
         __raw_writew(msk1, INTMSK1);
 }
 
-static void enable_se7206_irq(unsigned int irq)
+static void enable_se7206_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned short val;
         unsigned short value = (0x0001 << 4 * (3 - (IRQ0_IRQ - irq)));
         unsigned short msk0,msk1;
@@ -86,13 +88,13 @@ static void enable_se7206_irq(unsigned int irq)
         __raw_writew(msk1, INTMSK1);
 }
 
-static void eoi_se7206_irq(unsigned int irq)
+static void eoi_se7206_irq(struct irq_data *data)
 {
         unsigned short sts0,sts1;
-        struct irq_desc *desc = irq_to_desc(irq);
+        unsigned int irq = data->irq;
 
-        if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
-                enable_se7206_irq(irq);
+        if (!irqd_irq_disabled(data) && !irqd_irq_inprogress(data))
+                enable_se7206_irq(data);
         /* FPGA isr clear */
         sts0 = __raw_readw(INTSTS0);
         sts1 = __raw_readw(INTSTS1);
@@ -115,18 +117,17 @@ static void eoi_se7206_irq(unsigned int irq)
 
 static struct irq_chip se7206_irq_chip __read_mostly = {
         .name           = "SE7206-FPGA",
-        .mask           = disable_se7206_irq,
-        .unmask         = enable_se7206_irq,
-        .mask_ack       = disable_se7206_irq,
-        .eoi            = eoi_se7206_irq,
+        .irq_mask       = disable_se7206_irq,
+        .irq_unmask     = enable_se7206_irq,
+        .irq_eoi        = eoi_se7206_irq,
 };
 
 static void make_se7206_irq(unsigned int irq)
 {
         disable_irq_nosync(irq);
-        set_irq_chip_and_handler_name(irq, &se7206_irq_chip,
+        irq_set_chip_and_handler_name(irq, &se7206_irq_chip,
                                       handle_level_irq, "level");
-        disable_se7206_irq(irq);
+        disable_se7206_irq(irq_get_irq_data(irq));
 }
 
 /*
@@ -137,11 +138,13 @@ void __init init_se7206_IRQ(void)
         make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */
         make_se7206_irq(IRQ1_IRQ); /* ATA */
         make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */
-        __raw_writew(inw(INTC_ICR1) | 0x000b ,INTC_ICR1 ) ; /* ICR1 */
+
+        __raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR1); /* ICR1 */
 
         /* FPGA System register setup*/
         __raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */
         __raw_writew(0x0000,INTSTS1); /* Clear INTSTS1 */
+
         /* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */
         __raw_writew(0x0001,INTSEL);
 }
diff --git a/arch/sh/boards/mach-se/7206/setup.c b/arch/sh/boards/mach-se/7206/setup.c
index 8f5c65d43d1d..8ab8330e3fd1 100644
--- a/arch/sh/boards/mach-se/7206/setup.c
+++ b/arch/sh/boards/mach-se/7206/setup.c
@@ -77,7 +77,12 @@ static int __init se7206_devices_setup(void)
 {
         return platform_add_devices(se7206_devices, ARRAY_SIZE(se7206_devices));
 }
-__initcall(se7206_devices_setup);
+device_initcall(se7206_devices_setup);
+
+static int se7206_mode_pins(void)
+{
+        return MODE_PIN1 | MODE_PIN2;
+}
 
 /*
  * The Machine Vector
@@ -86,20 +91,6 @@ __initcall(se7206_devices_setup);
 static struct sh_machine_vector mv_se __initmv = {
         .mv_name                = "SolutionEngine",
         .mv_nr_irqs             = 256,
-        .mv_inb                 = se7206_inb,
-        .mv_inw                 = se7206_inw,
-        .mv_outb                = se7206_outb,
-        .mv_outw                = se7206_outw,
-
-        .mv_inb_p               = se7206_inb_p,
-        .mv_inw_p               = se7206_inw,
-        .mv_outb_p              = se7206_outb_p,
-        .mv_outw_p              = se7206_outw,
-
-        .mv_insb                = se7206_insb,
-        .mv_insw                = se7206_insw,
-        .mv_outsb               = se7206_outsb,
-        .mv_outsw               = se7206_outsw,
-
         .mv_init_irq            = init_se7206_IRQ,
+        .mv_mode_pins           = se7206_mode_pins,
 };
diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c
index d4305c26e9f7..fd45ffc48340 100644
--- a/arch/sh/boards/mach-se/7343/irq.c
+++ b/arch/sh/boards/mach-se/7343/irq.c
@@ -18,23 +18,22 @@
 
 unsigned int se7343_fpga_irq[SE7343_FPGA_IRQ_NR] = { 0, };
 
-static void disable_se7343_irq(unsigned int irq)
+static void disable_se7343_irq(struct irq_data *data)
 {
-        unsigned int bit = (unsigned int)get_irq_chip_data(irq);
+        unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
         __raw_writew(__raw_readw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
 }
 
-static void enable_se7343_irq(unsigned int irq)
+static void enable_se7343_irq(struct irq_data *data)
 {
-        unsigned int bit = (unsigned int)get_irq_chip_data(irq);
+        unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
         __raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
 }
 
 static struct irq_chip se7343_irq_chip __read_mostly = {
-        .name           = "SE7343-FPGA",
-        .mask           = disable_se7343_irq,
-        .unmask         = enable_se7343_irq,
-        .mask_ack       = disable_se7343_irq,
+        .name           = "SE7343-FPGA",
+        .irq_mask       = disable_se7343_irq,
+        .irq_unmask     = enable_se7343_irq,
 };
 
 static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
@@ -68,19 +67,20 @@ void __init init_7343se_IRQ(void)
                         return;
                 se7343_fpga_irq[i] = irq;
 
-                set_irq_chip_and_handler_name(se7343_fpga_irq[i],
+                irq_set_chip_and_handler_name(se7343_fpga_irq[i],
                                               &se7343_irq_chip,
-                                              handle_level_irq, "level");
+                                              handle_level_irq,
+                                              "level");
 
-                set_irq_chip_data(se7343_fpga_irq[i], (void *)i);
+                irq_set_chip_data(se7343_fpga_irq[i], (void *)i);
         }
 
-        set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
-        set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
-        set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
-        set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
-        set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux);
-        set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
-        set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux);
-        set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);
+        irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);
+        irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);
+        irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);
+        irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
 }
diff --git a/arch/sh/boards/mach-se/770x/Makefile b/arch/sh/boards/mach-se/770x/Makefile
index 8e624b06d5ea..43ea14feef51 100644
--- a/arch/sh/boards/mach-se/770x/Makefile
+++ b/arch/sh/boards/mach-se/770x/Makefile
@@ -2,4 +2,4 @@
 # Makefile for the 770x SolutionEngine specific parts of the kernel
 #
 
-obj-y    := setup.o io.o irq.o
+obj-y    := setup.o irq.o
diff --git a/arch/sh/boards/mach-se/770x/io.c b/arch/sh/boards/mach-se/770x/io.c
deleted file mode 100644
index 28833c8786ea..000000000000
--- a/arch/sh/boards/mach-se/770x/io.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright (C) 2000  Kazumoto Kojima
- *
- * I/O routine for Hitachi SolutionEngine.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <asm/io.h>
-#include <mach-se/mach/se.h>
-
-/* MS7750 requires special versions of in*, out* routines, since
-   PC-like io ports are located at upper half byte of 16-bit word which
-   can be accessed only with 16-bit wide.  */
-
-static inline volatile __u16 *
-port2adr(unsigned int port)
-{
-        if (port & 0xff000000)
-                return ( volatile __u16 *) port;
-        if (port >= 0x2000)
-                return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
-        else if (port >= 0x1000)
-                return (volatile __u16 *) (PA_83902 + (port << 1));
-        else
-                return (volatile __u16 *) (PA_SUPERIO + (port << 1));
-}
-
-static inline int
-shifted_port(unsigned long port)
-{
-        /* For IDE registers, value is not shifted */
-        if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6)
-                return 0;
-        else
-                return 1;
-}
-
-unsigned char se_inb(unsigned long port)
-{
-        if (shifted_port(port))
-                return (*port2adr(port) >> 8);
-        else
-                return (*port2adr(port))&0xff;
-}
-
-unsigned char se_inb_p(unsigned long port)
-{
-        unsigned long v;
-
-        if (shifted_port(port))
-                v = (*port2adr(port) >> 8);
-        else
-                v = (*port2adr(port))&0xff;
-        ctrl_delay();
-        return v;
-}
-
-unsigned short se_inw(unsigned long port)
-{
-        if (port >= 0x2000)
-                return *port2adr(port);
-        else
-                maybebadio(port);
-        return 0;
-}
-
-unsigned int se_inl(unsigned long port)
-{
-        maybebadio(port);
-        return 0;
-}
-
-void se_outb(unsigned char value, unsigned long port)
-{
-        if (shifted_port(port))
-                *(port2adr(port)) = value << 8;
-        else
-                *(port2adr(port)) = value;
-}
-
-void se_outb_p(unsigned char value, unsigned long port)
-{
-        if (shifted_port(port))
-                *(port2adr(port)) = value << 8;
-        else
-                *(port2adr(port)) = value;
-        ctrl_delay();
-}
-
-void se_outw(unsigned short value, unsigned long port)
-{
-        if (port >= 0x2000)
-                *port2adr(port) = value;
-        else
-                maybebadio(port);
-}
-
-void se_outl(unsigned int value, unsigned long port)
-{
-        maybebadio(port);
-}
-
-void se_insb(unsigned long port, void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        __u8 *ap = addr;
-
-        if (shifted_port(port)) {
-                while (count--)
-                        *ap++ = *p >> 8;
-        } else {
-                while (count--)
-                        *ap++ = *p;
-        }
-}
-
-void se_insw(unsigned long port, void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        __u16 *ap = addr;
-        while (count--)
-                *ap++ = *p;
-}
-
-void se_insl(unsigned long port, void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
-
-void se_outsb(unsigned long port, const void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        const __u8 *ap = addr;
-
-        if (shifted_port(port)) {
-                while (count--)
-                        *p = *ap++ << 8;
-        } else {
-                while (count--)
-                        *p = *ap++;
-        }
-}
-
-void se_outsw(unsigned long port, const void *addr, unsigned long count)
-{
-        volatile __u16 *p = port2adr(port);
-        const __u16 *ap = addr;
-
-        while (count--)
-                *p = *ap++;
-}
-
-void se_outsl(unsigned long port, const void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
diff --git a/arch/sh/boards/mach-se/770x/setup.c b/arch/sh/boards/mach-se/770x/setup.c
index 66d39d1b0901..31330c65c0ce 100644
--- a/arch/sh/boards/mach-se/770x/setup.c
+++ b/arch/sh/boards/mach-se/770x/setup.c
@@ -195,27 +195,5 @@ static struct sh_machine_vector mv_se __initmv = {
 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
         .mv_nr_irqs             = 104,
 #endif
-
-        .mv_inb                 = se_inb,
-        .mv_inw                 = se_inw,
-        .mv_inl                 = se_inl,
-        .mv_outb                = se_outb,
-        .mv_outw                = se_outw,
-        .mv_outl                = se_outl,
-
-        .mv_inb_p               = se_inb_p,
-        .mv_inw_p               = se_inw,
-        .mv_inl_p               = se_inl,
-        .mv_outb_p              = se_outb_p,
-        .mv_outw_p              = se_outw,
-        .mv_outl_p              = se_outl,
-
-        .mv_insb                = se_insb,
-        .mv_insw                = se_insw,
-        .mv_insl                = se_insl,
-        .mv_outsb               = se_outsb,
-        .mv_outsw               = se_outsw,
-        .mv_outsl               = se_outsl,
-
         .mv_init_irq            = init_se_IRQ,
 };
diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c
index 61605db04ee6..aac92f21ebd2 100644
--- a/arch/sh/boards/mach-se/7722/irq.c
+++ b/arch/sh/boards/mach-se/7722/irq.c
@@ -18,23 +18,22 @@
 
 unsigned int se7722_fpga_irq[SE7722_FPGA_IRQ_NR] = { 0, };
 
-static void disable_se7722_irq(unsigned int irq)
+static void disable_se7722_irq(struct irq_data *data)
 {
-        unsigned int bit = (unsigned int)get_irq_chip_data(irq);
+        unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
         __raw_writew(__raw_readw(IRQ01_MASK) | 1 << bit, IRQ01_MASK);
 }
 
-static void enable_se7722_irq(unsigned int irq)
+static void enable_se7722_irq(struct irq_data *data)
 {
-        unsigned int bit = (unsigned int)get_irq_chip_data(irq);
+        unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
         __raw_writew(__raw_readw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK);
 }
 
 static struct irq_chip se7722_irq_chip __read_mostly = {
-        .name           = "SE7722-FPGA",
-        .mask           = disable_se7722_irq,
-        .unmask         = enable_se7722_irq,
-        .mask_ack       = disable_se7722_irq,
+        .name           = "SE7722-FPGA",
+        .irq_mask       = disable_se7722_irq,
+        .irq_unmask     = enable_se7722_irq,
 };
 
 static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
@@ -68,16 +67,17 @@ void __init init_se7722_IRQ(void)
                         return;
                 se7722_fpga_irq[i] = irq;
 
-                set_irq_chip_and_handler_name(se7722_fpga_irq[i],
+                irq_set_chip_and_handler_name(se7722_fpga_irq[i],
                                               &se7722_irq_chip,
-                                              handle_level_irq, "level");
+                                              handle_level_irq,
+                                              "level");
 
-                set_irq_chip_data(se7722_fpga_irq[i], (void *)i);
+                irq_set_chip_data(se7722_fpga_irq[i], (void *)i);
         }
 
-        set_irq_chained_handler(IRQ0_IRQ, se7722_irq_demux);
-        set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);
+        irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
 
-        set_irq_chained_handler(IRQ1_IRQ, se7722_irq_demux);
-        set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);
+        irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
 }
diff --git a/arch/sh/boards/mach-se/7724/irq.c b/arch/sh/boards/mach-se/7724/irq.c
index 0942be2daef6..c6342ce7768d 100644
--- a/arch/sh/boards/mach-se/7724/irq.c
+++ b/arch/sh/boards/mach-se/7724/irq.c
@@ -68,25 +68,26 @@ static struct fpga_irq get_fpga_irq(unsigned int irq)
         return set;
 }
 
-static void disable_se7724_irq(unsigned int irq)
+static void disable_se7724_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
         unsigned int bit = irq - set.base;
         __raw_writew(__raw_readw(set.mraddr) | 0x0001 << bit, set.mraddr);
 }
 
-static void enable_se7724_irq(unsigned int irq)
+static void enable_se7724_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
         unsigned int bit = irq - set.base;
         __raw_writew(__raw_readw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
 }
 
 static struct irq_chip se7724_irq_chip __read_mostly = {
-        .name           = "SE7724-FPGA",
-        .mask           = disable_se7724_irq,
-        .unmask         = enable_se7724_irq,
-        .mask_ack       = disable_se7724_irq,
+        .name           = "SE7724-FPGA",
+        .irq_mask       = disable_se7724_irq,
+        .irq_unmask     = enable_se7724_irq,
 };
 
 static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
@@ -139,17 +140,16 @@ void __init init_se7724_IRQ(void)
                         return;
                 }
 
-                set_irq_chip_and_handler_name(irq,
-                                              &se7724_irq_chip,
+                irq_set_chip_and_handler_name(irq, &se7724_irq_chip,
                                               handle_level_irq, "level");
         }
 
-        set_irq_chained_handler(IRQ0_IRQ, se7724_irq_demux);
-        set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ0_IRQ, se7724_irq_demux);
+        irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
 
-        set_irq_chained_handler(IRQ1_IRQ, se7724_irq_demux);
-        set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ1_IRQ, se7724_irq_demux);
+        irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
 
-        set_irq_chained_handler(IRQ2_IRQ, se7724_irq_demux);
-        set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ2_IRQ, se7724_irq_demux);
+        irq_set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW);
 }
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index 552ebd9ba82b..12357671023e 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -14,7 +14,8 @@
 #include <linux/device.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
-#include <linux/mfd/sh_mobile_sdhi.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mtd/physmap.h>
 #include <linux/delay.h>
 #include <linux/smc91x.h>
@@ -144,16 +145,42 @@ static struct platform_device nor_flash_device = {
 };
 
 /* LCDC */
+const static struct fb_videomode lcdc_720p_modes[] = {
+        {
+                .name           = "LB070WV1",
+                .sync           = 0, /* hsync and vsync are active low */
+                .xres           = 1280,
+                .yres           = 720,
+                .left_margin    = 220,
+                .right_margin   = 110,
+                .hsync_len      = 40,
+                .upper_margin   = 20,
+                .lower_margin   = 5,
+                .vsync_len      = 5,
+        },
+};
+
+const static struct fb_videomode lcdc_vga_modes[] = {
+        {
+                .name           = "LB070WV1",
+                .sync           = 0, /* hsync and vsync are active low */
+                .xres           = 640,
+                .yres           = 480,
+                .left_margin    = 105,
+                .right_margin   = 50,
+                .hsync_len      = 96,
+                .upper_margin   = 33,
+                .lower_margin   = 10,
+                .vsync_len      = 2,
+        },
+};
+
 static struct sh_mobile_lcdc_info lcdc_info = {
         .clock_source = LCDC_CLK_EXTERNAL,
         .ch[0] = {
                 .chan = LCDC_CHAN_MAINLCD,
                 .bpp = 16,
                 .clock_divider = 1,
-                .lcd_cfg = {
-                        .name = "LB070WV1",
-                        .sync = 0, /* hsync and vsync are active low */
-                },
                 .lcd_size_cfg = { /* 7.0 inch */
                         .width = 152,
                         .height = 91,
@@ -257,38 +284,9 @@ static struct platform_device ceu1_device = {
 };
 
 /* FSI */
-/*
- * FSI-A use external clock which came from ak464x.
- * So, we should change parent of fsi
- */
-#define FCLKACR         0xa4150008
-static void fsimck_init(struct clk *clk)
-{
-        u32 status = __raw_readl(clk->enable_reg);
-
-        /* use external clock */
-        status &= ~0x000000ff;
-        status |= 0x00000080;
-        __raw_writel(status, clk->enable_reg);
-}
-
-static struct clk_ops fsimck_clk_ops = {
-        .init = fsimck_init,
-};
-
-static struct clk fsimcka_clk = {
-        .ops            = &fsimck_clk_ops,
-        .enable_reg     = (void __iomem *)FCLKACR,
-        .rate           = 0, /* unknown */
-};
-
 /* change J20, J21, J22 pin to 1-2 connection to use slave mode */
 static struct sh_fsi_platform_info fsi_info = {
-        .porta_flags = SH_FSI_BRS_INV |
-                       SH_FSI_OUT_SLAVE_MODE |
-                       SH_FSI_IN_SLAVE_MODE |
-                       SH_FSI_OFMT(PCM) |
-                       SH_FSI_IFMT(PCM),
+        .porta_flags = SH_FSI_BRS_INV,
 };
 
 static struct resource fsi_resources[] = {
@@ -317,6 +315,10 @@ static struct platform_device fsi_device = {
         },
 };
 
+static struct platform_device fsi_ak4642_device = {
+        .name           = "sh_fsi_a_ak4642",
+};
+
 /* KEYSC in SoC (Needs SW33-2 set to ON) */
 static struct sh_keysc_info keysc_info = {
         .mode = SH_KEYSC_MODE_1,
@@ -454,7 +456,7 @@ static struct resource sdhi0_cn7_resources[] = {
         [0] = {
                 .name   = "SDHI0",
                 .start  = 0x04ce0000,
-                .end    = 0x04ce01ff,
+                .end    = 0x04ce00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -466,6 +468,7 @@ static struct resource sdhi0_cn7_resources[] = {
 static struct sh_mobile_sdhi_info sh7724_sdhi0_data = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
+        .tmio_caps      = MMC_CAP_SDIO_IRQ,
 };
 
 static struct platform_device sdhi0_cn7_device = {
@@ -485,7 +488,7 @@ static struct resource sdhi1_cn8_resources[] = {
         [0] = {
                 .name   = "SDHI1",
                 .start  = 0x04cf0000,
-                .end    = 0x04cf01ff,
+                .end    = 0x04cf00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -497,6 +500,7 @@ static struct resource sdhi1_cn8_resources[] = {
 static struct sh_mobile_sdhi_info sh7724_sdhi1_data = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
+        .tmio_caps      = MMC_CAP_SDIO_IRQ,
 };
 
 static struct platform_device sdhi1_cn8_device = {
@@ -550,7 +554,6 @@ static struct sh_vou_pdata sh_vou_pdata = {
         .flags          = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
         .board_info     = &ak8813,
         .i2c_adap       = 0,
-        .module_name    = "ak881x",
 };
 
 static struct resource sh_vou_resources[] = {
@@ -590,6 +593,7 @@ static struct platform_device *ms7724se_devices[] __initdata = {
         &sh7724_usb0_host_device,
         &sh7724_usb1_gadget_device,
         &fsi_device,
+        &fsi_ak4642_device,
         &sdhi0_cn7_device,
         &sdhi1_cn8_device,
         &irda_device,
@@ -827,37 +831,29 @@ static int __init devices_setup(void)
         gpio_request(GPIO_FN_KEYOUT0,     NULL);
 
         /* enable FSI */
-        gpio_request(GPIO_FN_FSIMCKB,    NULL);
         gpio_request(GPIO_FN_FSIMCKA,    NULL);
+        gpio_request(GPIO_FN_FSIIASD,    NULL);
         gpio_request(GPIO_FN_FSIOASD,    NULL);
         gpio_request(GPIO_FN_FSIIABCK,   NULL);
         gpio_request(GPIO_FN_FSIIALRCK,  NULL);
         gpio_request(GPIO_FN_FSIOABCK,   NULL);
         gpio_request(GPIO_FN_FSIOALRCK,  NULL);
         gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
-        gpio_request(GPIO_FN_FSIIBSD,    NULL);
-        gpio_request(GPIO_FN_FSIOBSD,    NULL);
-        gpio_request(GPIO_FN_FSIIBBCK,   NULL);
-        gpio_request(GPIO_FN_FSIIBLRCK,  NULL);
-        gpio_request(GPIO_FN_FSIOBBCK,   NULL);
-        gpio_request(GPIO_FN_FSIOBLRCK,  NULL);
-        gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
-        gpio_request(GPIO_FN_FSIIASD,    NULL);
 
         /* set SPU2 clock to 83.4 MHz */
         clk = clk_get(NULL, "spu_clk");
-        if (clk) {
+        if (!IS_ERR(clk)) {
                 clk_set_rate(clk, clk_round_rate(clk, 83333333));
                 clk_put(clk);
         }
 
         /* change parent of FSI A */
         clk = clk_get(NULL, "fsia_clk");
-        if (clk) {
-                clk_register(&fsimcka_clk);
-                clk_set_parent(clk, &fsimcka_clk);
-                clk_set_rate(clk, 11000);
-                clk_set_rate(&fsimcka_clk, 11000);
+        if (!IS_ERR(clk)) {
+                /* 48kHz dummy clock was used to make sure 1/1 divide */
+                clk_set_rate(&sh7724_fsimcka_clk, 48000);
+                clk_set_parent(clk, &sh7724_fsimcka_clk);
+                clk_set_rate(clk, 48000);
                 clk_put(clk);
         }
 
@@ -909,24 +905,12 @@ static int __init devices_setup(void)
 
         if (sw & SW41_B) {
                 /* 720p */
-                lcdc_info.ch[0].lcd_cfg.xres         = 1280;
-                lcdc_info.ch[0].lcd_cfg.yres         = 720;
-                lcdc_info.ch[0].lcd_cfg.left_margin  = 220;
-                lcdc_info.ch[0].lcd_cfg.right_margin = 110;
-                lcdc_info.ch[0].lcd_cfg.hsync_len    = 40;
-                lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
-                lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
-                lcdc_info.ch[0].lcd_cfg.vsync_len    = 5;
+                lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes;
+                lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes);
         } else {
                 /* VGA */
-                lcdc_info.ch[0].lcd_cfg.xres         = 640;
-                lcdc_info.ch[0].lcd_cfg.yres         = 480;
-                lcdc_info.ch[0].lcd_cfg.left_margin  = 105;
-                lcdc_info.ch[0].lcd_cfg.right_margin = 50;
-                lcdc_info.ch[0].lcd_cfg.hsync_len    = 96;
-                lcdc_info.ch[0].lcd_cfg.upper_margin = 33;
-                lcdc_info.ch[0].lcd_cfg.lower_margin = 10;
-                lcdc_info.ch[0].lcd_cfg.vsync_len    = 2;
+                lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes;
+                lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes);
         }
 
         if (sw & SW41_A) {
diff --git a/arch/sh/boards/mach-se/7751/Makefile b/arch/sh/boards/mach-se/7751/Makefile
index e6f4341bfe6e..a338fd9d5039 100644
--- a/arch/sh/boards/mach-se/7751/Makefile
+++ b/arch/sh/boards/mach-se/7751/Makefile
@@ -2,4 +2,4 @@
 # Makefile for the 7751 SolutionEngine specific parts of the kernel
 #
 
-obj-y    := setup.o io.o irq.o
+obj-y    := setup.o irq.o
diff --git a/arch/sh/boards/mach-se/7751/io.c b/arch/sh/boards/mach-se/7751/io.c
deleted file mode 100644
index 6e75bd4459e5..000000000000
--- a/arch/sh/boards/mach-se/7751/io.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright (C) 2001  Ian da Silva, Jeremy Siegel
- * Based largely on io_se.c.
- *
- * I/O routine for Hitachi 7751 SolutionEngine.
- *
- * Initial version only to support LAN access; some
- * placeholder code from io_se.c left in with the
- * expectation of later SuperIO and PCMCIA access.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <asm/io.h>
-#include <mach-se/mach/se7751.h>
-#include <asm/addrspace.h>
-
-static inline volatile u16 *port2adr(unsigned int port)
-{
-        if (port >= 0x2000)
-                return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
-        maybebadio((unsigned long)port);
-        return (volatile __u16*)port;
-}
-
-/*
- * General outline: remap really low stuff [eventually] to SuperIO,
- * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
- * is mapped through the PCI IO window.  Stuff with high bits (PXSEG)
- * should be way beyond the window, and is used  w/o translation for
- * compatibility.
- */
-unsigned char sh7751se_inb(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned char *)port;
-        else
-                return (*port2adr(port)) & 0xff;
-}
-
-unsigned char sh7751se_inb_p(unsigned long port)
-{
-        unsigned char v;
-
-        if (PXSEG(port))
-                v = *(volatile unsigned char *)port;
-        else
-                v = (*port2adr(port)) & 0xff;
-        ctrl_delay();
-        return v;
-}
-
-unsigned short sh7751se_inw(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned short *)port;
-        else if (port >= 0x2000)
-                return *port2adr(port);
-        else
-                maybebadio(port);
-        return 0;
-}
-
-unsigned int sh7751se_inl(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned long *)port;
-        else if (port >= 0x2000)
-                return *port2adr(port);
-        else
-                maybebadio(port);
-        return 0;
-}
-
-void sh7751se_outb(unsigned char value, unsigned long port)
-{
-
-        if (PXSEG(port))
-                *(volatile unsigned char *)port = value;
-        else
-                *(port2adr(port)) = value;
-}
-
-void sh7751se_outb_p(unsigned char value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned char *)port = value;
-        else
-                *(port2adr(port)) = value;
-        ctrl_delay();
-}
-
-void sh7751se_outw(unsigned short value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned short *)port = value;
-        else if (port >= 0x2000)
-                *port2adr(port) = value;
-        else
-                maybebadio(port);
-}
-
-void sh7751se_outl(unsigned int value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned long *)port = value;
-        else
-                maybebadio(port);
-}
-
-void sh7751se_insl(unsigned long port, void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
-
-void sh7751se_outsl(unsigned long port, const void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
diff --git a/arch/sh/boards/mach-se/7751/setup.c b/arch/sh/boards/mach-se/7751/setup.c
index 50572512e3e8..4ed60c5e221f 100644
--- a/arch/sh/boards/mach-se/7751/setup.c
+++ b/arch/sh/boards/mach-se/7751/setup.c
@@ -48,7 +48,7 @@ static int __init se7751_devices_setup(void)
 {
         return platform_add_devices(se7751_devices, ARRAY_SIZE(se7751_devices));
 }
-__initcall(se7751_devices_setup);
+device_initcall(se7751_devices_setup);
 
 /*
  * The Machine Vector
@@ -56,23 +56,5 @@ __initcall(se7751_devices_setup);
 static struct sh_machine_vector mv_7751se __initmv = {
         .mv_name                = "7751 SolutionEngine",
         .mv_nr_irqs             = 72,
-
-        .mv_inb                 = sh7751se_inb,
-        .mv_inw                 = sh7751se_inw,
-        .mv_inl                 = sh7751se_inl,
-        .mv_outb                = sh7751se_outb,
-        .mv_outw                = sh7751se_outw,
-        .mv_outl                = sh7751se_outl,
-
-        .mv_inb_p               = sh7751se_inb_p,
-        .mv_inw_p               = sh7751se_inw,
-        .mv_inl_p               = sh7751se_inl,
-        .mv_outb_p              = sh7751se_outb_p,
-        .mv_outw_p              = sh7751se_outw,
-        .mv_outl_p              = sh7751se_outl,
-
-        .mv_insl                = sh7751se_insl,
-        .mv_outsl               = sh7751se_outsl,
-
         .mv_init_irq            = init_7751se_IRQ,
 };
diff --git a/arch/sh/boards/mach-se/board-se7619.c b/arch/sh/boards/mach-se/board-se7619.c
index 1d0ef7faa10d..82b6d4a5dc02 100644
--- a/arch/sh/boards/mach-se/board-se7619.c
+++ b/arch/sh/boards/mach-se/board-se7619.c
@@ -11,6 +11,11 @@
 #include <asm/io.h>
 #include <asm/machvec.h>
 
+static int se7619_mode_pins(void)
+{
+        return MODE_PIN2 | MODE_PIN0;
+}
+
 /*
  * The Machine Vector
  */
@@ -18,4 +23,5 @@
 static struct sh_machine_vector mv_se __initmv = {
         .mv_name                = "SolutionEngine",
         .mv_nr_irqs             = 108,
+        .mv_mode_pins           = se7619_mode_pins,
 };
diff --git a/arch/sh/boards/mach-sh03/rtc.c b/arch/sh/boards/mach-sh03/rtc.c
index 1b200990500c..f83ac7995d0f 100644
--- a/arch/sh/boards/mach-sh03/rtc.c
+++ b/arch/sh/boards/mach-sh03/rtc.c
@@ -108,7 +108,7 @@ static int set_rtc_mmss(unsigned long nowtime)
                 __raw_writeb(real_minutes % 10, RTC_MIN1);
                 __raw_writeb(real_minutes / 10, RTC_MIN10);
         } else {
-                printk(KERN_WARNING
+                printk_once(KERN_NOTICE
                        "set_rtc_mmss: can't update from %d to %d\n",
                        cmos_minutes, real_minutes);
                 retval = -1;
diff --git a/arch/sh/boards/mach-sh03/setup.c b/arch/sh/boards/mach-sh03/setup.c
index af4a0c012a96..d4f79b2a6514 100644
--- a/arch/sh/boards/mach-sh03/setup.c
+++ b/arch/sh/boards/mach-sh03/setup.c
@@ -96,7 +96,7 @@ static int __init sh03_devices_setup(void)
 
         return platform_add_devices(sh03_devices, ARRAY_SIZE(sh03_devices));
 }
-__initcall(sh03_devices_setup);
+device_initcall(sh03_devices_setup);
 
 static struct sh_machine_vector mv_sh03 __initmv = {
         .mv_name                = "Interface (CTP/PCI-SH03)",
diff --git a/arch/sh/boards/mach-sh7763rdp/setup.c b/arch/sh/boards/mach-sh7763rdp/setup.c
index f64a6918224c..f3d828f133e5 100644
--- a/arch/sh/boards/mach-sh7763rdp/setup.c
+++ b/arch/sh/boards/mach-sh7763rdp/setup.c
@@ -75,6 +75,10 @@ static struct resource sh_eth_resources[] = {
                 .end    = 0xFEE00F7C - 1,
                 .flags  = IORESOURCE_MEM,
         }, {
+                .start  = 0xFEE01800,   /* TSU */
+                .end    = 0xFEE01FFF,
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start  = 57,   /* irq number */
                 .flags  = IORESOURCE_IRQ,
         },
@@ -83,6 +87,8 @@ static struct resource sh_eth_resources[] = {
 static struct sh_eth_plat_data sh7763_eth_pdata = {
         .phy = 1,
         .edmac_endian = EDMAC_LITTLE_ENDIAN,
+        .register_type = SH_ETH_REG_GIGABIT,
+        .phy_interface = PHY_INTERFACE_MODE_MII,
 };
 
 static struct platform_device sh7763rdp_eth_device = {
diff --git a/arch/sh/boards/mach-snapgear/Makefile b/arch/sh/boards/mach-snapgear/Makefile
deleted file mode 100644
index d2d2f4b6a502..000000000000
--- a/arch/sh/boards/mach-snapgear/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the SnapGear specific parts of the kernel
-#
-
-obj-y    := setup.o io.o
diff --git a/arch/sh/boards/mach-snapgear/io.c b/arch/sh/boards/mach-snapgear/io.c
deleted file mode 100644
index 476650e42dbc..000000000000
--- a/arch/sh/boards/mach-snapgear/io.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Copyright (C) 2002  David McCullough <davidm@snapgear.com>
- * Copyright (C) 2001  Ian da Silva, Jeremy Siegel
- * Based largely on io_se.c.
- *
- * I/O routine for Hitachi 7751 SolutionEngine.
- *
- * Initial version only to support LAN access; some
- * placeholder code from io_se.c left in with the
- * expectation of later SuperIO and PCMCIA access.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <asm/io.h>
-#include <asm/addrspace.h>
-
-#ifdef CONFIG_SH_SECUREEDGE5410
-unsigned short secureedge5410_ioport;
-#endif
-
-static inline volatile __u16 *port2adr(unsigned int port)
-{
-        maybebadio((unsigned long)port);
-        return (volatile __u16*)port;
-}
-
-/*
- * General outline: remap really low stuff [eventually] to SuperIO,
- * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
- * is mapped through the PCI IO window.  Stuff with high bits (PXSEG)
- * should be way beyond the window, and is used  w/o translation for
- * compatibility.
- */
-unsigned char snapgear_inb(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned char *)port;
-        else
-                return (*port2adr(port)) & 0xff;
-}
-
-unsigned char snapgear_inb_p(unsigned long port)
-{
-        unsigned char v;
-
-        if (PXSEG(port))
-                v = *(volatile unsigned char *)port;
-        else
-                v = (*port2adr(port))&0xff;
-        ctrl_delay();
-        return v;
-}
-
-unsigned short snapgear_inw(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned short *)port;
-        else if (port >= 0x2000)
-                return *port2adr(port);
-        else
-                maybebadio(port);
-        return 0;
-}
-
-unsigned int snapgear_inl(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned long *)port;
-        else if (port >= 0x2000)
-                return *port2adr(port);
-        else
-                maybebadio(port);
-        return 0;
-}
-
-void snapgear_outb(unsigned char value, unsigned long port)
-{
-
-        if (PXSEG(port))
-                *(volatile unsigned char *)port = value;
-        else
-                *(port2adr(port)) = value;
-}
-
-void snapgear_outb_p(unsigned char value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned char *)port = value;
-        else
-                *(port2adr(port)) = value;
-        ctrl_delay();
-}
-
-void snapgear_outw(unsigned short value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned short *)port = value;
-        else if (port >= 0x2000)
-                *port2adr(port) = value;
-        else
-                maybebadio(port);
-}
-
-void snapgear_outl(unsigned int value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned long *)port = value;
-        else
-                maybebadio(port);
-}
-
-void snapgear_insl(unsigned long port, void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
-
-void snapgear_outsl(unsigned long port, const void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
diff --git a/arch/sh/boards/mach-systemh/Makefile b/arch/sh/boards/mach-systemh/Makefile
deleted file mode 100644
index 2cc6a23d9d39..000000000000
--- a/arch/sh/boards/mach-systemh/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Makefile for the SystemH specific parts of the kernel
-#
-
-obj-y    := setup.o irq.o io.o
-
-# XXX: This wants to be consolidated in arch/sh/drivers/pci, and more
-# importantly, with the generic sh7751_pcic_init() code. For now, we'll
-# just abuse the hell out of kbuild, because we can..
-
-obj-$(CONFIG_PCI) += pci.o
-pci-y := ../../se/7751/pci.o
-
diff --git a/arch/sh/boards/mach-systemh/io.c b/arch/sh/boards/mach-systemh/io.c
deleted file mode 100644
index 15577ff1f715..000000000000
--- a/arch/sh/boards/mach-systemh/io.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * linux/arch/sh/boards/renesas/systemh/io.c
- *
- * Copyright (C) 2001  Ian da Silva, Jeremy Siegel
- * Based largely on io_se.c.
- *
- * I/O routine for Hitachi 7751 Systemh.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <mach/systemh7751.h>
-#include <asm/addrspace.h>
-#include <asm/io.h>
-
-#define ETHER_IOMAP(adr) (0xB3000000 + (adr)) /*map to 16bits access area
-                                                of smc lan chip*/
-static inline volatile __u16 *
-port2adr(unsigned int port)
-{
-        if (port >= 0x2000)
-                return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000));
-        maybebadio((unsigned long)port);
-        return (volatile __u16*)port;
-}
-
-/*
- * General outline: remap really low stuff [eventually] to SuperIO,
- * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
- * is mapped through the PCI IO window.  Stuff with high bits (PXSEG)
- * should be way beyond the window, and is used  w/o translation for
- * compatibility.
- */
-unsigned char sh7751systemh_inb(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned char *)port;
-        else if (port <= 0x3F1)
-                return *(volatile unsigned char *)ETHER_IOMAP(port);
-        else
-                return (*port2adr(port))&0xff;
-}
-
-unsigned char sh7751systemh_inb_p(unsigned long port)
-{
-        unsigned char v;
-
-        if (PXSEG(port))
-                v = *(volatile unsigned char *)port;
-        else if (port <= 0x3F1)
-                v = *(volatile unsigned char *)ETHER_IOMAP(port);
-        else
-                v = (*port2adr(port))&0xff;
-        ctrl_delay();
-        return v;
-}
-
-unsigned short sh7751systemh_inw(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned short *)port;
-        else if (port >= 0x2000)
-                return *port2adr(port);
-        else if (port <= 0x3F1)
-                return *(volatile unsigned int *)ETHER_IOMAP(port);
-        else
-                maybebadio(port);
-        return 0;
-}
-
-unsigned int sh7751systemh_inl(unsigned long port)
-{
-        if (PXSEG(port))
-                return *(volatile unsigned long *)port;
-        else if (port >= 0x2000)
-                return *port2adr(port);
-        else if (port <= 0x3F1)
-                return *(volatile unsigned int *)ETHER_IOMAP(port);
-        else
-                maybebadio(port);
-        return 0;
-}
-
-void sh7751systemh_outb(unsigned char value, unsigned long port)
-{
-
-        if (PXSEG(port))
-                *(volatile unsigned char *)port = value;
-        else if (port <= 0x3F1)
-                *(volatile unsigned char *)ETHER_IOMAP(port) = value;
-        else
-                *(port2adr(port)) = value;
-}
-
-void sh7751systemh_outb_p(unsigned char value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned char *)port = value;
-        else if (port <= 0x3F1)
-                *(volatile unsigned char *)ETHER_IOMAP(port) = value;
-        else
-                *(port2adr(port)) = value;
-        ctrl_delay();
-}
-
-void sh7751systemh_outw(unsigned short value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned short *)port = value;
-        else if (port >= 0x2000)
-                *port2adr(port) = value;
-        else if (port <= 0x3F1)
-                *(volatile unsigned short *)ETHER_IOMAP(port) = value;
-        else
-                maybebadio(port);
-}
-
-void sh7751systemh_outl(unsigned int value, unsigned long port)
-{
-        if (PXSEG(port))
-                *(volatile unsigned long *)port = value;
-        else
-                maybebadio(port);
-}
-
-void sh7751systemh_insb(unsigned long port, void *addr, unsigned long count)
-{
-        unsigned char *p = addr;
-        while (count--) *p++ = sh7751systemh_inb(port);
-}
-
-void sh7751systemh_insw(unsigned long port, void *addr, unsigned long count)
-{
-        unsigned short *p = addr;
-        while (count--) *p++ = sh7751systemh_inw(port);
-}
-
-void sh7751systemh_insl(unsigned long port, void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
-
-void sh7751systemh_outsb(unsigned long port, const void *addr, unsigned long count)
-{
-        unsigned char *p = (unsigned char*)addr;
-        while (count--) sh7751systemh_outb(*p++, port);
-}
-
-void sh7751systemh_outsw(unsigned long port, const void *addr, unsigned long count)
-{
-        unsigned short *p = (unsigned short*)addr;
-        while (count--) sh7751systemh_outw(*p++, port);
-}
-
-void sh7751systemh_outsl(unsigned long port, const void *addr, unsigned long count)
-{
-        maybebadio(port);
-}
diff --git a/arch/sh/boards/mach-systemh/irq.c b/arch/sh/boards/mach-systemh/irq.c
deleted file mode 100644
index 523aea5dc94e..000000000000
--- a/arch/sh/boards/mach-systemh/irq.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * linux/arch/sh/boards/renesas/systemh/irq.c
- *
- * Copyright (C) 2000  Kazumoto Kojima
- *
- * Hitachi SystemH Support.
- *
- * Modified for 7751 SystemH by
- * Jonathan Short.
- */
-
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-
-#include <mach/systemh7751.h>
-#include <asm/smc37c93x.h>
-
-/* address of external interrupt mask register
- * address must be set prior to use these (maybe in init_XXX_irq())
- * XXX : is it better to use .config than specifying it in code? */
-static unsigned long *systemh_irq_mask_register = (unsigned long *)0xB3F10004;
-static unsigned long *systemh_irq_request_register = (unsigned long *)0xB3F10000;
-
-/* forward declaration */
-static void enable_systemh_irq(unsigned int irq);
-static void disable_systemh_irq(unsigned int irq);
-static void mask_and_ack_systemh(unsigned int);
-
-static struct irq_chip systemh_irq_type = {
-        .name = " SystemH Register",
-        .unmask = enable_systemh_irq,
-        .mask = disable_systemh_irq,
-        .ack = mask_and_ack_systemh,
-};
-
-static void disable_systemh_irq(unsigned int irq)
-{
-        if (systemh_irq_mask_register) {
-                unsigned long val, mask = 0x01 << 1;
-
-                /* Clear the "irq"th bit in the mask and set it in the request */
-                val = __raw_readl((unsigned long)systemh_irq_mask_register);
-                val &= ~mask;
-                __raw_writel(val, (unsigned long)systemh_irq_mask_register);
-
-                val = __raw_readl((unsigned long)systemh_irq_request_register);
-                val |= mask;
-                __raw_writel(val, (unsigned long)systemh_irq_request_register);
-        }
-}
-
-static void enable_systemh_irq(unsigned int irq)
-{
-        if (systemh_irq_mask_register) {
-                unsigned long val, mask = 0x01 << 1;
-
-                /* Set "irq"th bit in the mask register */
-                val = __raw_readl((unsigned long)systemh_irq_mask_register);
-                val |= mask;
-                __raw_writel(val, (unsigned long)systemh_irq_mask_register);
-        }
-}
-
-static void mask_and_ack_systemh(unsigned int irq)
-{
-        disable_systemh_irq(irq);
-}
-
-void make_systemh_irq(unsigned int irq)
-{
-        disable_irq_nosync(irq);
-        set_irq_chip_and_handler(irq, &systemh_irq_type, handle_level_irq);
-        disable_systemh_irq(irq);
-}
diff --git a/arch/sh/boards/mach-systemh/setup.c b/arch/sh/boards/mach-systemh/setup.c
deleted file mode 100644
index 219fd800a43f..000000000000
--- a/arch/sh/boards/mach-systemh/setup.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * linux/arch/sh/boards/renesas/systemh/setup.c
- *
- * Copyright (C) 2000  Kazumoto Kojima
- * Copyright (C) 2003  Paul Mundt
- *
- * Hitachi SystemH Support.
- *
- * Modified for 7751 SystemH by Jonathan Short.
- *
- * Rewritten for 2.6 by Paul Mundt.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <asm/machvec.h>
-#include <mach/systemh7751.h>
-
-extern void make_systemh_irq(unsigned int irq);
-
-/*
- * Initialize IRQ setting
- */
-static void __init sh7751systemh_init_irq(void)
-{
-        make_systemh_irq(0xb);  /* Ethernet interrupt */
-}
-
-static struct sh_machine_vector mv_7751systemh __initmv = {
-        .mv_name                = "7751 SystemH",
-        .mv_nr_irqs             = 72,
-
-        .mv_inb                 = sh7751systemh_inb,
-        .mv_inw                 = sh7751systemh_inw,
-        .mv_inl                 = sh7751systemh_inl,
-        .mv_outb                = sh7751systemh_outb,
-        .mv_outw                = sh7751systemh_outw,
-        .mv_outl                = sh7751systemh_outl,
-
-        .mv_inb_p               = sh7751systemh_inb_p,
-        .mv_inw_p               = sh7751systemh_inw,
-        .mv_inl_p               = sh7751systemh_inl,
-        .mv_outb_p              = sh7751systemh_outb_p,
-        .mv_outw_p              = sh7751systemh_outw,
-        .mv_outl_p              = sh7751systemh_outl,
-
-        .mv_insb                = sh7751systemh_insb,
-        .mv_insw                = sh7751systemh_insw,
-        .mv_insl                = sh7751systemh_insl,
-        .mv_outsb               = sh7751systemh_outsb,
-        .mv_outsw               = sh7751systemh_outsw,
-        .mv_outsl               = sh7751systemh_outsl,
-
-        .mv_init_irq            = sh7751systemh_init_irq,
-};
diff --git a/arch/sh/boards/mach-x3proto/Makefile b/arch/sh/boards/mach-x3proto/Makefile
index 983e4551fecf..708c21c919ff 100644
--- a/arch/sh/boards/mach-x3proto/Makefile
+++ b/arch/sh/boards/mach-x3proto/Makefile
@@ -1 +1,3 @@
 obj-y += setup.o ilsel.o
+
+obj-$(CONFIG_GENERIC_GPIO)      += gpio.o
diff --git a/arch/sh/boards/mach-x3proto/gpio.c b/arch/sh/boards/mach-x3proto/gpio.c
new file mode 100644
index 000000000000..f33b2b57019c
--- /dev/null
+++ b/arch/sh/boards/mach-x3proto/gpio.c
@@ -0,0 +1,136 @@
+/*
+ * arch/sh/boards/mach-x3proto/gpio.c
+ *
+ * Renesas SH-X3 Prototype Baseboard GPIO Support.
+ *
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <mach/ilsel.h>
+#include <mach/hardware.h>
+
+#define KEYCTLR 0xb81c0000
+#define KEYOUTR 0xb81c0002
+#define KEYDETR 0xb81c0004
+
+static DEFINE_SPINLOCK(x3proto_gpio_lock);
+static unsigned int x3proto_gpio_irq_map[NR_BASEBOARD_GPIOS] = { 0, };
+
+static int x3proto_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+        unsigned long flags;
+        unsigned int data;
+
+        spin_lock_irqsave(&x3proto_gpio_lock, flags);
+        data = __raw_readw(KEYCTLR);
+        data |= (1 << gpio);
+        __raw_writew(data, KEYCTLR);
+        spin_unlock_irqrestore(&x3proto_gpio_lock, flags);
+
+        return 0;
+}
+
+static int x3proto_gpio_get(struct gpio_chip *chip, unsigned gpio)
+{
+        return !!(__raw_readw(KEYDETR) & (1 << gpio));
+}
+
+static int x3proto_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
+{
+        return x3proto_gpio_irq_map[gpio];
+}
+
+static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        struct irq_data *data = irq_get_irq_data(irq);
+        struct irq_chip *chip = irq_data_get_irq_chip(data);
+        unsigned long mask;
+        int pin;
+
+        chip->irq_mask_ack(data);
+
+        mask = __raw_readw(KEYDETR);
+
+        for_each_set_bit(pin, &mask, NR_BASEBOARD_GPIOS)
+                generic_handle_irq(x3proto_gpio_to_irq(NULL, pin));
+
+        chip->irq_unmask(data);
+}
+
+struct gpio_chip x3proto_gpio_chip = {
+        .label                  = "x3proto-gpio",
+        .direction_input        = x3proto_gpio_direction_input,
+        .get                    = x3proto_gpio_get,
+        .to_irq                 = x3proto_gpio_to_irq,
+        .base                   = -1,
+        .ngpio                  = NR_BASEBOARD_GPIOS,
+};
+
+int __init x3proto_gpio_setup(void)
+{
+        int ilsel;
+        int ret, i;
+
+        ilsel = ilsel_enable(ILSEL_KEY);
+        if (unlikely(ilsel < 0))
+                return ilsel;
+
+        ret = gpiochip_add(&x3proto_gpio_chip);
+        if (unlikely(ret))
+                goto err_gpio;
+
+        for (i = 0; i < NR_BASEBOARD_GPIOS; i++) {
+                unsigned long flags;
+                int irq = create_irq();
+
+                if (unlikely(irq < 0)) {
+                        ret = -EINVAL;
+                        goto err_irq;
+                }
+
+                spin_lock_irqsave(&x3proto_gpio_lock, flags);
+                x3proto_gpio_irq_map[i] = irq;
+                irq_set_chip_and_handler_name(irq, &dummy_irq_chip,
+                                              handle_simple_irq, "gpio");
+                spin_unlock_irqrestore(&x3proto_gpio_lock, flags);
+        }
+
+        pr_info("registering '%s' support, handling GPIOs %u -> %u, "
+                "bound to IRQ %u\n",
+                x3proto_gpio_chip.label, x3proto_gpio_chip.base,
+                x3proto_gpio_chip.base + x3proto_gpio_chip.ngpio,
+                ilsel);
+
+        irq_set_chained_handler(ilsel, x3proto_gpio_irq_handler);
+        irq_set_irq_wake(ilsel, 1);
+
+        return 0;
+
+err_irq:
+        for (; i >= 0; --i)
+                if (x3proto_gpio_irq_map[i])
+                        destroy_irq(x3proto_gpio_irq_map[i]);
+
+        ret = gpiochip_remove(&x3proto_gpio_chip);
+        if (unlikely(ret))
+                pr_err("Failed deregistering GPIO\n");
+
+err_gpio:
+        synchronize_irq(ilsel);
+
+        ilsel_disable(ILSEL_KEY);
+
+        return ret;
+}
diff --git a/arch/sh/boards/mach-x3proto/ilsel.c b/arch/sh/boards/mach-x3proto/ilsel.c
index 5c9842704c60..95e346139515 100644
--- a/arch/sh/boards/mach-x3proto/ilsel.c
+++ b/arch/sh/boards/mach-x3proto/ilsel.c
@@ -1,20 +1,22 @@
 /*
- * arch/sh/boards/renesas/x3proto/ilsel.c
+ * arch/sh/boards/mach-x3proto/ilsel.c
  *
  * Helper routines for SH-X3 proto board ILSEL.
  *
- * Copyright (C) 2007 Paul Mundt
+ * Copyright (C) 2007 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/bitmap.h>
 #include <linux/io.h>
-#include <asm/ilsel.h>
+#include <mach/ilsel.h>
 
 /*
  * ILSEL is split across:
@@ -64,6 +66,8 @@ static void __ilsel_enable(ilsel_source_t set, unsigned int bit)
         unsigned int tmp, shift;
         unsigned long addr;
 
+        pr_notice("enabling ILSEL set %d\n", set);
+
         addr = mk_ilsel_addr(bit);
         shift = mk_ilsel_shift(bit);
 
@@ -92,8 +96,10 @@ int ilsel_enable(ilsel_source_t set)
 {
         unsigned int bit;
 
-        /* Aliased sources must use ilsel_enable_fixed() */
-        BUG_ON(set > ILSEL_KEY);
+        if (unlikely(set > ILSEL_KEY)) {
+                pr_err("Aliased sources must use ilsel_enable_fixed()\n");
+                return -EINVAL;
+        }
 
         do {
                 bit = find_first_zero_bit(&ilsel_level_map, ILSEL_LEVELS);
@@ -140,6 +146,8 @@ void ilsel_disable(unsigned int irq)
         unsigned long addr;
         unsigned int tmp;
 
+        pr_notice("disabling ILSEL set %d\n", irq);
+
         addr = mk_ilsel_addr(irq);
 
         tmp = __raw_readw(addr);
diff --git a/arch/sh/boards/mach-x3proto/setup.c b/arch/sh/boards/mach-x3proto/setup.c
index 102bf56befb4..d682e2b6a856 100644
--- a/arch/sh/boards/mach-x3proto/setup.c
+++ b/arch/sh/boards/mach-x3proto/setup.c
@@ -1,9 +1,9 @@
 /*
- * arch/sh/boards/renesas/x3proto/setup.c
+ * arch/sh/boards/mach-x3proto/setup.c
  *
  * Renesas SH-X3 Prototype Board Support.
  *
- * Copyright (C) 2007 - 2008 Paul Mundt
+ * Copyright (C) 2007 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -16,9 +16,13 @@
 #include <linux/smc91x.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
+#include <linux/input.h>
 #include <linux/usb/r8a66597.h>
 #include <linux/usb/m66592.h>
-#include <asm/ilsel.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <mach/ilsel.h>
+#include <mach/hardware.h>
 #include <asm/smp-ops.h>
 
 static struct resource heartbeat_resources[] = {
@@ -122,15 +126,128 @@ static struct platform_device m66592_usb_peripheral_device = {
         .resource       = m66592_usb_peripheral_resources,
 };
 
+static struct gpio_keys_button baseboard_buttons[NR_BASEBOARD_GPIOS] = {
+        {
+                .desc           = "key44",
+                .code           = KEY_POWER,
+                .active_low     = 1,
+                .wakeup         = 1,
+        }, {
+                .desc           = "key43",
+                .code           = KEY_SUSPEND,
+                .active_low     = 1,
+                .wakeup         = 1,
+        }, {
+                .desc           = "key42",
+                .code           = KEY_KATAKANAHIRAGANA,
+                .active_low     = 1,
+        }, {
+                .desc           = "key41",
+                .code           = KEY_SWITCHVIDEOMODE,
+                .active_low     = 1,
+        }, {
+                .desc           = "key34",
+                .code           = KEY_F12,
+                .active_low     = 1,
+        }, {
+                .desc           = "key33",
+                .code           = KEY_F11,
+                .active_low     = 1,
+        }, {
+                .desc           = "key32",
+                .code           = KEY_F10,
+                .active_low     = 1,
+        }, {
+                .desc           = "key31",
+                .code           = KEY_F9,
+                .active_low     = 1,
+        }, {
+                .desc           = "key24",
+                .code           = KEY_F8,
+                .active_low     = 1,
+        }, {
+                .desc           = "key23",
+                .code           = KEY_F7,
+                .active_low     = 1,
+        }, {
+                .desc           = "key22",
+                .code           = KEY_F6,
+                .active_low     = 1,
+        }, {
+                .desc           = "key21",
+                .code           = KEY_F5,
+                .active_low     = 1,
+        }, {
+                .desc           = "key14",
+                .code           = KEY_F4,
+                .active_low     = 1,
+        }, {
+                .desc           = "key13",
+                .code           = KEY_F3,
+                .active_low     = 1,
+        }, {
+                .desc           = "key12",
+                .code           = KEY_F2,
+                .active_low     = 1,
+        }, {
+                .desc           = "key11",
+                .code           = KEY_F1,
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data baseboard_buttons_data = {
+        .buttons        = baseboard_buttons,
+        .nbuttons       = ARRAY_SIZE(baseboard_buttons),
+};
+
+static struct platform_device baseboard_buttons_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &baseboard_buttons_data,
+        },
+};
+
 static struct platform_device *x3proto_devices[] __initdata = {
         &heartbeat_device,
         &smc91x_device,
         &r8a66597_usb_host_device,
         &m66592_usb_peripheral_device,
+        &baseboard_buttons_device,
 };
 
+static void __init x3proto_init_irq(void)
+{
+        plat_irq_setup_pins(IRQ_MODE_IRL3210);
+
+        /* Set ICR0.LVLMODE */
+        __raw_writel(__raw_readl(0xfe410000) | (1 << 21), 0xfe410000);
+}
+
 static int __init x3proto_devices_setup(void)
 {
+        int ret, i;
+
+        /*
+         * IRLs are only needed for ILSEL mappings, so flip over the INTC
+         * pins at a later point to enable the GPIOs to settle.
+         */
+        x3proto_init_irq();
+
+        /*
+         * Now that ILSELs are available, set up the baseboard GPIOs.
+         */
+        ret = x3proto_gpio_setup();
+        if (unlikely(ret))
+                return ret;
+
+        /*
+         * Propagate dynamic GPIOs for the baseboard button device.
+         */
+        for (i = 0; i < ARRAY_SIZE(baseboard_buttons); i++)
+                baseboard_buttons[i].gpio = x3proto_gpio_chip.base + i;
+
         r8a66597_usb_host_resources[1].start =
                 r8a66597_usb_host_resources[1].end = ilsel_enable(ILSEL_USBH_I);
 
@@ -145,14 +262,6 @@ static int __init x3proto_devices_setup(void)
 }
 device_initcall(x3proto_devices_setup);
 
-static void __init x3proto_init_irq(void)
-{
-        plat_irq_setup_pins(IRQ_MODE_IRL3210);
-
-        /* Set ICR0.LVLMODE */
-        __raw_writel(__raw_readl(0xfe410000) | (1 << 21), 0xfe410000);
-}
-
 static void __init x3proto_setup(char **cmdline_p)
 {
         register_smp_ops(&shx3_smp_ops);
@@ -161,5 +270,4 @@ static void __init x3proto_setup(char **cmdline_p)
 static struct sh_machine_vector mv_x3proto __initmv = {
         .mv_name                = "x3proto",
         .mv_setup               = x3proto_setup,
-        .mv_init_irq            = x3proto_init_irq,
 };
diff --git a/arch/sh/boot/Makefile b/arch/sh/boot/Makefile
index 1ce63624c9b9..ba515d800245 100644
--- a/arch/sh/boot/Makefile
+++ b/arch/sh/boot/Makefile
@@ -24,12 +24,13 @@ suffix-y := bin
 suffix-$(CONFIG_KERNEL_GZIP)    := gz
 suffix-$(CONFIG_KERNEL_BZIP2)   := bz2
 suffix-$(CONFIG_KERNEL_LZMA)    := lzma
+suffix-$(CONFIG_KERNEL_XZ)      := xz
 suffix-$(CONFIG_KERNEL_LZO)     := lzo
 
 targets := zImage vmlinux.srec romImage uImage uImage.srec uImage.gz \
-           uImage.bz2 uImage.lzma uImage.lzo uImage.bin
+           uImage.bz2 uImage.lzma uImage.xz uImage.lzo uImage.bin
 extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma \
-           vmlinux.bin.lzo
+           vmlinux.bin.xz vmlinux.bin.lzo
 subdir- := compressed romimage
 
 $(obj)/zImage: $(obj)/compressed/vmlinux FORCE
@@ -76,6 +77,9 @@ $(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
 $(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
         $(call if_changed,lzma)
 
+$(obj)/vmlinux.bin.xz: $(obj)/vmlinux.bin FORCE
+        $(call if_changed,xzkern)
+
 $(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
         $(call if_changed,lzo)
 
@@ -88,6 +92,9 @@ $(obj)/uImage.gz: $(obj)/vmlinux.bin.gz
 $(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma
         $(call if_changed,uimage,lzma)
 
+$(obj)/uImage.xz: $(obj)/vmlinux.bin.xz
+        $(call if_changed,uimage,xz)
+
 $(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo
         $(call if_changed,uimage,lzo)
 
diff --git a/arch/sh/boot/compressed/Makefile b/arch/sh/boot/compressed/Makefile
index cfa5a087a886..23bc849d9c64 100644
--- a/arch/sh/boot/compressed/Makefile
+++ b/arch/sh/boot/compressed/Makefile
@@ -6,11 +6,13 @@
 
 targets         := vmlinux vmlinux.bin vmlinux.bin.gz \
                    vmlinux.bin.bz2 vmlinux.bin.lzma \
-                   vmlinux.bin.lzo \
+                   vmlinux.bin.xz vmlinux.bin.lzo \
                    head_$(BITS).o misc.o piggy.o
 
 OBJECTS = $(obj)/head_$(BITS).o $(obj)/misc.o $(obj)/cache.o
 
+GCOV_PROFILE := n
+
 #
 # IMAGE_OFFSET is the load offset of the compression loader
 #
@@ -25,8 +27,6 @@ IMAGE_OFFSET	:= $(shell /bin/bash -c 'printf "0x%08x" \
                         $(CONFIG_BOOT_LINK_OFFSET)]')
 endif
 
-LIBGCC  := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
-
 ifeq ($(CONFIG_MCOUNT),y)
 ORIG_CFLAGS := $(KBUILD_CFLAGS)
 KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
@@ -35,7 +35,25 @@ endif
 LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext $(IMAGE_OFFSET) -e startup \
                    -T $(obj)/../../kernel/vmlinux.lds
 
-$(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o $(LIBGCC) FORCE
+#
+# Pull in the necessary libgcc bits from the in-kernel implementation.
+#
+lib1funcs-$(CONFIG_SUPERH32)    := ashiftrt.S ashldi3.c ashrsi3.S ashlsi3.S \
+                                   lshrsi3.S
+lib1funcs-obj                   := \
+        $(addsuffix .o, $(basename $(addprefix $(obj)/, $(lib1funcs-y))))
+
+lib1funcs-dir           := $(srctree)/arch/$(SRCARCH)/lib
+ifeq ($(BITS),64)
+        lib1funcs-dir   := $(addsuffix $(BITS), $(lib1funcs-dir))
+endif
+
+KBUILD_CFLAGS += -I$(lib1funcs-dir)
+
+$(addprefix $(obj)/,$(lib1funcs-y)): $(obj)/%: $(lib1funcs-dir)/% FORCE
+        $(call cmd,shipped)
+
+$(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o $(lib1funcs-obj) FORCE
         $(call if_changed,ld)
         @:
 
@@ -50,6 +68,8 @@ $(obj)/vmlinux.bin.bz2: $(vmlinux.bin.all-y) FORCE
         $(call if_changed,bzip2)
 $(obj)/vmlinux.bin.lzma: $(vmlinux.bin.all-y) FORCE
         $(call if_changed,lzma)
+$(obj)/vmlinux.bin.xz: $(vmlinux.bin.all-y) FORCE
+        $(call if_changed,xzkern)
 $(obj)/vmlinux.bin.lzo: $(vmlinux.bin.all-y) FORCE
         $(call if_changed,lzo)
 
diff --git a/arch/sh/boot/compressed/head_32.S b/arch/sh/boot/compressed/head_32.S
index 200c1d4f1efe..3e150326f1fd 100644
--- a/arch/sh/boot/compressed/head_32.S
+++ b/arch/sh/boot/compressed/head_32.S
@@ -91,7 +91,9 @@ bss_start_addr:
 end_addr:
         .long   _end
 init_sr:
-        .long   0x400000F0      /* Privileged mode, Bank=0, Block=0, IMASK=0xF */
+        .long   0x500000F0      /* Privileged mode, Bank=0, Block=1, IMASK=0xF */
+kexec_magic:
+        .long   0x400000F0      /* magic used by kexec to parse zImage format */
 init_stack_addr:
         .long   stack_start
 decompress_kernel_addr:
diff --git a/arch/sh/boot/compressed/misc.c b/arch/sh/boot/compressed/misc.c
index 27140a6b365d..95470a472d2c 100644
--- a/arch/sh/boot/compressed/misc.c
+++ b/arch/sh/boot/compressed/misc.c
@@ -61,6 +61,10 @@ static unsigned long free_mem_end_ptr;
 #include "../../../../lib/decompress_unlzma.c"
 #endif
 
+#ifdef CONFIG_KERNEL_XZ
+#include "../../../../lib/decompress_unxz.c"
+#endif
+
 #ifdef CONFIG_KERNEL_LZO
 #include "../../../../lib/decompress_unlzo.c"
 #endif
diff --git a/arch/sh/boot/romimage/mmcif-sh7724.c b/arch/sh/boot/romimage/mmcif-sh7724.c
index 14863d7292cb..16b122510c84 100644
--- a/arch/sh/boot/romimage/mmcif-sh7724.c
+++ b/arch/sh/boot/romimage/mmcif-sh7724.c
@@ -9,6 +9,7 @@
  */
 
 #include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/boot.h>
 #include <mach/romimage.h>
 
 #define MMCIF_BASE      (void __iomem *)0xa4ca0000
@@ -21,9 +22,6 @@
 #define HIZCRC          0xa405015c
 #define DRVCRA          0xa405018a
 
-enum { MMCIF_PROGRESS_ENTER, MMCIF_PROGRESS_INIT,
-       MMCIF_PROGRESS_LOAD, MMCIF_PROGRESS_DONE };
-
 /* SH7724 specific MMCIF loader
  *
  * loads the romImage from an MMC card starting from block 512
@@ -32,7 +30,7 @@ enum { MMCIF_PROGRESS_ENTER, MMCIF_PROGRESS_INIT,
  */
 asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes)
 {
-        mmcif_update_progress(MMCIF_PROGRESS_ENTER);
+        mmcif_update_progress(MMC_PROGRESS_ENTER);
 
         /* enable clock to the MMCIF hardware block */
         __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2);
@@ -55,18 +53,20 @@ asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes)
         /* high drive capability for MMC pins */
         __raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA);
 
-        mmcif_update_progress(MMCIF_PROGRESS_INIT);
+        mmcif_update_progress(MMC_PROGRESS_INIT);
 
         /* setup MMCIF hardware */
         sh_mmcif_boot_init(MMCIF_BASE);
 
-        mmcif_update_progress(MMCIF_PROGRESS_LOAD);
+        mmcif_update_progress(MMC_PROGRESS_LOAD);
 
         /* load kernel via MMCIF interface */
-        sh_mmcif_boot_slurp(MMCIF_BASE, buf, no_bytes);
+        sh_mmcif_boot_do_read(MMCIF_BASE, 512,
+                              (no_bytes + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS,
+                              buf);
 
         /* disable clock to the MMCIF hardware block */
         __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2);
 
-        mmcif_update_progress(MMCIF_PROGRESS_DONE);
+        mmcif_update_progress(MMC_PROGRESS_DONE);
 }
diff --git a/arch/sh/cchips/hd6446x/Makefile b/arch/sh/cchips/hd6446x/Makefile
index 9682e3ab668f..59c348337bb8 100644
--- a/arch/sh/cchips/hd6446x/Makefile
+++ b/arch/sh/cchips/hd6446x/Makefile
@@ -1,3 +1,3 @@
 obj-$(CONFIG_HD64461)   += hd64461.o
 
-EXTRA_CFLAGS += -Werror
+ccflags-y := -Werror
diff --git a/arch/sh/cchips/hd6446x/hd64461.c b/arch/sh/cchips/hd6446x/hd64461.c
index bcb31ae84a51..eb4ea4d44d59 100644
--- a/arch/sh/cchips/hd6446x/hd64461.c
+++ b/arch/sh/cchips/hd6446x/hd64461.c
@@ -17,8 +17,9 @@
 /* This belongs in cpu specific */
 #define INTC_ICR1 0xA4140010UL
 
-static void hd64461_mask_irq(unsigned int irq)
+static void hd64461_mask_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned short nimr;
         unsigned short mask = 1 << (irq - HD64461_IRQBASE);
 
@@ -27,8 +28,9 @@ static void hd64461_mask_irq(unsigned int irq)
         __raw_writew(nimr, HD64461_NIMR);
 }
 
-static void hd64461_unmask_irq(unsigned int irq)
+static void hd64461_unmask_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned short nimr;
         unsigned short mask = 1 << (irq - HD64461_IRQBASE);
 
@@ -37,20 +39,21 @@ static void hd64461_unmask_irq(unsigned int irq)
         __raw_writew(nimr, HD64461_NIMR);
 }
 
-static void hd64461_mask_and_ack_irq(unsigned int irq)
+static void hd64461_mask_and_ack_irq(struct irq_data *data)
 {
-        hd64461_mask_irq(irq);
+        hd64461_mask_irq(data);
+
 #ifdef CONFIG_HD64461_ENABLER
-        if (irq == HD64461_IRQBASE + 13)
+        if (data->irq == HD64461_IRQBASE + 13)
                 __raw_writeb(0x00, HD64461_PCC1CSCR);
 #endif
 }
 
 static struct irq_chip hd64461_irq_chip = {
         .name           = "HD64461-IRQ",
-        .mask           = hd64461_mask_irq,
-        .mask_ack       = hd64461_mask_and_ack_irq,
-        .unmask         = hd64461_unmask_irq,
+        .irq_mask       = hd64461_mask_irq,
+        .irq_mask_ack   = hd64461_mask_and_ack_irq,
+        .irq_unmask     = hd64461_unmask_irq,
 };
 
 static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
@@ -104,12 +107,12 @@ int __init setup_hd64461(void)
                         return -EINVAL;
                 }
 
-                set_irq_chip_and_handler(i, &hd64461_irq_chip,
+                irq_set_chip_and_handler(i, &hd64461_irq_chip,
                                          handle_level_irq);
         }
 
-        set_irq_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
-        set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
+        irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
 
 #ifdef CONFIG_HD64461_ENABLER
         printk(KERN_INFO "HD64461: enabling PCMCIA devices\n");
diff --git a/arch/sh/configs/ap325rxa_defconfig b/arch/sh/configs/ap325rxa_defconfig
index 238d6833ac70..e5335123b5e9 100644
--- a/arch/sh/configs/ap325rxa_defconfig
+++ b/arch/sh/configs/ap325rxa_defconfig
@@ -3,7 +3,6 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_KALLSYMS is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
diff --git a/arch/sh/configs/apsh4a3a_defconfig b/arch/sh/configs/apsh4a3a_defconfig
new file mode 100644
index 000000000000..6cb327977d13
--- /dev/null
+++ b/arch/sh/configs/apsh4a3a_defconfig
@@ -0,0 +1,102 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SLAB=y
+CONFIG_PROFILING=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_CPU_SUBTYPE_SH7785=y
+CONFIG_MEMORY_START=0x0C000000
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_SH_STORE_QUEUES=y
+CONFIG_SH_APSH4A3A=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_KEXEC=y
+CONFIG_PREEMPT=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMSC911X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=6
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_HW_RANDOM=y
+# CONFIG_HWMON is not set
+CONFIG_FB=y
+CONFIG_FB_SH7785FB=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_NTFS_RW=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V4=y
+CONFIG_CIFS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_FTRACE is not set
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
diff --git a/arch/sh/configs/apsh4ad0a_defconfig b/arch/sh/configs/apsh4ad0a_defconfig
new file mode 100644
index 000000000000..e7583484cc07
--- /dev/null
+++ b/arch/sh/configs/apsh4ad0a_defconfig
@@ -0,0 +1,131 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_RCU_TRACE=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_BLK_CGROUP=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_PROFILING=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_CFQ_GROUP_IOSCHED=y
+CONFIG_CPU_SUBTYPE_SH7786=y
+CONFIG_MEMORY_SIZE=0x10000000
+CONFIG_HUGETLB_PAGE_SIZE_1MB=y
+CONFIG_MEMORY_HOTPLUG=y
+CONFIG_MEMORY_HOTREMOVE=y
+CONFIG_KSM=y
+CONFIG_SH_STORE_QUEUES=y
+CONFIG_SH_APSH4AD0A=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_SH_CPU_FREQ=y
+CONFIG_KEXEC=y
+CONFIG_SECCOMP=y
+CONFIG_PREEMPT=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_MISC=y
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_RUNTIME=y
+CONFIG_CPU_IDLE=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CFI=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMSC911X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=6
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_FB_SH7785FB=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_MON=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_NTFS_RW=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_HUGETLBFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V4=y
+CONFIG_CIFS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_VM=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_DWARF_UNWINDER=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/sh/configs/cayman_defconfig b/arch/sh/configs/cayman_defconfig
index b3bf11bcf025..67e150631ea5 100644
--- a/arch/sh/configs/cayman_defconfig
+++ b/arch/sh/configs/cayman_defconfig
@@ -1,7 +1,6 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
diff --git a/arch/sh/configs/dreamcast_defconfig b/arch/sh/configs/dreamcast_defconfig
index 3cdee4f0c184..ec243ca29529 100644
--- a/arch/sh/configs/dreamcast_defconfig
+++ b/arch/sh/configs/dreamcast_defconfig
@@ -2,7 +2,6 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_SLAB=y
 CONFIG_PROFILING=y
diff --git a/arch/sh/configs/ecovec24-romimage_defconfig b/arch/sh/configs/ecovec24-romimage_defconfig
index 021633b02835..5fcb17bff24a 100644
--- a/arch/sh/configs/ecovec24-romimage_defconfig
+++ b/arch/sh/configs/ecovec24-romimage_defconfig
@@ -5,7 +5,6 @@ CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_KALLSYMS is not set
 CONFIG_SLAB=y
diff --git a/arch/sh/configs/ecovec24_defconfig b/arch/sh/configs/ecovec24_defconfig
index 8d13e8a5a750..911e30c9abfd 100644
--- a/arch/sh/configs/ecovec24_defconfig
+++ b/arch/sh/configs/ecovec24_defconfig
@@ -115,7 +115,7 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_FILE_STORAGE=m
 CONFIG_MMC=y
 CONFIG_MMC_SPI=y
-CONFIG_MMC_TMIO=y
+CONFIG_MMC_SDHI=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_RS5C372=y
 CONFIG_UIO=y
diff --git a/arch/sh/configs/edosk7760_defconfig b/arch/sh/configs/edosk7760_defconfig
index 365f2318e9b5..e1077a041ac3 100644
--- a/arch/sh/configs/edosk7760_defconfig
+++ b/arch/sh/configs/edosk7760_defconfig
@@ -5,7 +5,6 @@ CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
diff --git a/arch/sh/configs/espt_defconfig b/arch/sh/configs/espt_defconfig
index ca7fc1b3d567..67cb1094a033 100644
--- a/arch/sh/configs/espt_defconfig
+++ b/arch/sh/configs/espt_defconfig
@@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_NAMESPACES=y
 CONFIG_UTS_NS=y
 CONFIG_IPC_NS=y
diff --git a/arch/sh/configs/hp6xx_defconfig b/arch/sh/configs/hp6xx_defconfig
index 45c18a3830d2..496edcdf95a3 100644
--- a/arch/sh/configs/hp6xx_defconfig
+++ b/arch/sh/configs/hp6xx_defconfig
@@ -3,7 +3,6 @@ CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_SLAB=y
diff --git a/arch/sh/configs/kfr2r09-romimage_defconfig b/arch/sh/configs/kfr2r09-romimage_defconfig
index d4268b1953bc..029a506ca325 100644
--- a/arch/sh/configs/kfr2r09-romimage_defconfig
+++ b/arch/sh/configs/kfr2r09-romimage_defconfig
@@ -5,7 +5,6 @@ CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_KALLSYMS is not set
 CONFIG_SLAB=y
diff --git a/arch/sh/configs/kfr2r09_defconfig b/arch/sh/configs/kfr2r09_defconfig
index ad5d296b375f..fac13ded07b2 100644
--- a/arch/sh/configs/kfr2r09_defconfig
+++ b/arch/sh/configs/kfr2r09_defconfig
@@ -5,7 +5,6 @@ CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_KALLSYMS is not set
 CONFIG_SLAB=y
diff --git a/arch/sh/configs/landisk_defconfig b/arch/sh/configs/landisk_defconfig
index 14e658e9318f..3670e937f2b7 100644
--- a/arch/sh/configs/landisk_defconfig
+++ b/arch/sh/configs/landisk_defconfig
@@ -1,7 +1,6 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_SLAB=y
diff --git a/arch/sh/configs/lboxre2_defconfig b/arch/sh/configs/lboxre2_defconfig
index 6be7eaaa8bb6..e3c0894b1bb4 100644
--- a/arch/sh/configs/lboxre2_defconfig
+++ b/arch/sh/configs/lboxre2_defconfig
@@ -1,7 +1,6 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_SLAB=y
diff --git a/arch/sh/configs/magicpanelr2_defconfig b/arch/sh/configs/magicpanelr2_defconfig
index 4d61b7711b40..9479872b1ae6 100644
--- a/arch/sh/configs/magicpanelr2_defconfig
+++ b/arch/sh/configs/magicpanelr2_defconfig
@@ -5,7 +5,6 @@ CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BSD_PROCESS_ACCT_V3=y
 CONFIG_AUDIT=y
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_RELAY=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
diff --git a/arch/sh/configs/microdev_defconfig b/arch/sh/configs/microdev_defconfig
index 0e32a24fed53..f1d2e1b5ee41 100644
--- a/arch/sh/configs/microdev_defconfig
+++ b/arch/sh/configs/microdev_defconfig
@@ -1,7 +1,6 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 # CONFIG_SYSCTL_SYSCALL is not set
diff --git a/arch/sh/configs/migor_defconfig b/arch/sh/configs/migor_defconfig
index c19fcdfdee37..cc61eda44922 100644
--- a/arch/sh/configs/migor_defconfig
+++ b/arch/sh/configs/migor_defconfig
@@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 # CONFIG_SYSCTL_SYSCALL is not set
@@ -55,6 +54,8 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_SH_KEYSC=y
 # CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_MIGOR=y
 # CONFIG_SERIO is not set
 CONFIG_VT_HW_CONSOLE_BINDING=y
 CONFIG_SERIAL_SH_SCI=y
diff --git a/arch/sh/configs/polaris_defconfig b/arch/sh/configs/polaris_defconfig
index 984e3fe1ce5d..f3d5d9f76310 100644
--- a/arch/sh/configs/polaris_defconfig
+++ b/arch/sh/configs/polaris_defconfig
@@ -7,7 +7,6 @@ CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BSD_PROCESS_ACCT_V3=y
 CONFIG_AUDIT=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
diff --git a/arch/sh/configs/r7780mp_defconfig b/arch/sh/configs/r7780mp_defconfig
index e8b5472e6d84..920b8471ceb7 100644
--- a/arch/sh/configs/r7780mp_defconfig
+++ b/arch/sh/configs/r7780mp_defconfig
@@ -4,7 +4,6 @@ CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_FUTEX is not set
 # CONFIG_EPOLL is not set
diff --git a/arch/sh/configs/r7785rp_defconfig b/arch/sh/configs/r7785rp_defconfig
index fd8848060982..c77da6be06b8 100644
--- a/arch/sh/configs/r7785rp_defconfig
+++ b/arch/sh/configs/r7785rp_defconfig
@@ -8,7 +8,6 @@ CONFIG_RCU_TRACE=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_SLAB=y
 CONFIG_PROFILING=y
diff --git a/arch/sh/configs/rts7751r2d1_defconfig b/arch/sh/configs/rts7751r2d1_defconfig
index a42f7c22ca1a..a3d081095ce2 100644
--- a/arch/sh/configs/rts7751r2d1_defconfig
+++ b/arch/sh/configs/rts7751r2d1_defconfig
@@ -1,7 +1,6 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_SLAB=y
diff --git a/arch/sh/configs/rts7751r2dplus_defconfig b/arch/sh/configs/rts7751r2dplus_defconfig
index 742aa61f2427..b1a04f3c598b 100644
--- a/arch/sh/configs/rts7751r2dplus_defconfig
+++ b/arch/sh/configs/rts7751r2dplus_defconfig
@@ -1,7 +1,6 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_SLAB=y
diff --git a/arch/sh/configs/sdk7780_defconfig b/arch/sh/configs/sdk7780_defconfig
index aed394d89346..ae1115849dda 100644
--- a/arch/sh/configs/sdk7780_defconfig
+++ b/arch/sh/configs/sdk7780_defconfig
@@ -6,7 +6,6 @@ CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=18
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_RELAY=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_MODULES=y
diff --git a/arch/sh/configs/sdk7786_defconfig b/arch/sh/configs/sdk7786_defconfig
index dc4a2eb6a616..8a7dd7b59c5c 100644
--- a/arch/sh/configs/sdk7786_defconfig
+++ b/arch/sh/configs/sdk7786_defconfig
@@ -12,7 +12,6 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_CGROUPS=y
 CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_FREEZER=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CPUSETS=y
@@ -83,7 +82,6 @@ CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
 CONFIG_BINFMT_MISC=y
 CONFIG_PM=y
 CONFIG_PM_DEBUG=y
-CONFIG_PM_VERBOSE=y
 CONFIG_PM_RUNTIME=y
 CONFIG_CPU_IDLE=y
 CONFIG_NET=y
diff --git a/arch/sh/configs/se7206_defconfig b/arch/sh/configs/se7206_defconfig
index a468ff227fc6..72c3fad7383f 100644
--- a/arch/sh/configs/se7206_defconfig
+++ b/arch/sh/configs/se7206_defconfig
@@ -8,7 +8,6 @@ CONFIG_RCU_TRACE=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CGROUPS=y
 CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
diff --git a/arch/sh/configs/se7343_defconfig b/arch/sh/configs/se7343_defconfig
index 7a7e13853cfd..be9c474197b3 100644
--- a/arch/sh/configs/se7343_defconfig
+++ b/arch/sh/configs/se7343_defconfig
@@ -3,7 +3,6 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_FUTEX is not set
 # CONFIG_EPOLL is not set
diff --git a/arch/sh/configs/se7712_defconfig b/arch/sh/configs/se7712_defconfig
index 3620a7f4c821..1248635e4f88 100644
--- a/arch/sh/configs/se7712_defconfig
+++ b/arch/sh/configs/se7712_defconfig
@@ -5,7 +5,6 @@ CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_KALLSYMS_ALL=y
 # CONFIG_BUG is not set
diff --git a/arch/sh/configs/se7721_defconfig b/arch/sh/configs/se7721_defconfig
index fe22f599c0cb..c3ba6e8a9818 100644
--- a/arch/sh/configs/se7721_defconfig
+++ b/arch/sh/configs/se7721_defconfig
@@ -5,7 +5,6 @@ CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_KALLSYMS_ALL=y
 # CONFIG_BUG is not set
diff --git a/arch/sh/configs/se7722_defconfig b/arch/sh/configs/se7722_defconfig
index b9b64c38810e..ae998c7e2ee0 100644
--- a/arch/sh/configs/se7722_defconfig
+++ b/arch/sh/configs/se7722_defconfig
@@ -4,7 +4,6 @@ CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_PROFILING=y
 CONFIG_MODULES=y
diff --git a/arch/sh/configs/se7724_defconfig b/arch/sh/configs/se7724_defconfig
index 03e736781c2e..ed35093e3758 100644
--- a/arch/sh/configs/se7724_defconfig
+++ b/arch/sh/configs/se7724_defconfig
@@ -3,7 +3,6 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_KALLSYMS is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
diff --git a/arch/sh/configs/se7750_defconfig b/arch/sh/configs/se7750_defconfig
index 1a686b6d5cd4..912c98590e22 100644
--- a/arch/sh/configs/se7750_defconfig
+++ b/arch/sh/configs/se7750_defconfig
@@ -5,7 +5,6 @@ CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 # CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_HOTPLUG is not set
diff --git a/arch/sh/configs/se7751_defconfig b/arch/sh/configs/se7751_defconfig
index 7e03451a9fad..75c92fc1876b 100644
--- a/arch/sh/configs/se7751_defconfig
+++ b/arch/sh/configs/se7751_defconfig
@@ -2,7 +2,6 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 # CONFIG_SYSCTL_SYSCALL is not set
diff --git a/arch/sh/configs/se7780_defconfig b/arch/sh/configs/se7780_defconfig
index 4cfc4deff135..c8c5e7f7a68d 100644
--- a/arch/sh/configs/se7780_defconfig
+++ b/arch/sh/configs/se7780_defconfig
@@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_KALLSYMS is not set
 # CONFIG_HOTPLUG is not set
 # CONFIG_EPOLL is not set
diff --git a/arch/sh/configs/snapgear_defconfig b/arch/sh/configs/secureedge5410_defconfig
index f38c98341f15..7eae4e59d7f0 100644
--- a/arch/sh/configs/snapgear_defconfig
+++ b/arch/sh/configs/secureedge5410_defconfig
@@ -1,7 +1,6 @@
 CONFIG_EXPERIMENTAL=y
 # CONFIG_SWAP is not set
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_HOTPLUG is not set
diff --git a/arch/sh/configs/sh03_defconfig b/arch/sh/configs/sh03_defconfig
index b95dc76b04c1..2051821724c6 100644
--- a/arch/sh/configs/sh03_defconfig
+++ b/arch/sh/configs/sh03_defconfig
@@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_SYSCTL_SYSCALL is not set
 CONFIG_SLAB=y
diff --git a/arch/sh/configs/sh2007_defconfig b/arch/sh/configs/sh2007_defconfig
new file mode 100644
index 000000000000..0d2f41472a19
--- /dev/null
+++ b/arch/sh/configs/sh2007_defconfig
@@ -0,0 +1,212 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_IKCONFIG=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_KALLSYMS_ALL=y
+CONFIG_SLAB=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_CPU_SUBTYPE_SH7780=y
+CONFIG_MEMORY_SIZE=0x08000000
+# CONFIG_VSYSCALL is not set
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_SH_SH2007=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SH_DMA=y
+CONFIG_SH_DMA_API=y
+CONFIG_NR_DMA_CHANNELS_BOOL=y
+CONFIG_HZ_100=y
+CONFIG_CMDLINE_OVERWRITE=y
+CONFIG_CMDLINE="console=ttySC1,115200 ip=dhcp root=/dev/nfs rw nfsroot=/nfs/rootfs,rsize=1024,wsize=1024 earlyprintk=sh-sci.1"
+CONFIG_PCCARD=y
+CONFIG_BINFMT_MISC=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPIP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NET_PKTGEN=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_CDROM_PKTCDVD=y
+# CONFIG_MISC_DEVICES is not set
+CONFIG_RAID_ATTRS=y
+CONFIG_SCSI=y
+CONFIG_SCSI_TGT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_ATTRS=y
+CONFIG_SCSI_ISCSI_ATTRS=y
+CONFIG_SCSI_SRP_ATTRS=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_EQUALIZER=y
+CONFIG_TUN=y
+CONFIG_VETH=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMSC911X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_SH_WDT=y
+CONFIG_SSB=y
+CONFIG_FB=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_LOGO=y
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_MON=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_DMADEVICES=y
+CONFIG_TIMB_DMA=y
+CONFIG_EXT3_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=932
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_SH_STANDARD_BIOS=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ANUBIS=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_FCRYPT=y
+CONFIG_CRYPTO_KHAZAD=y
+CONFIG_CRYPTO_SEED=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_LIBCRC32C=y
diff --git a/arch/sh/configs/sh7710voipgw_defconfig b/arch/sh/configs/sh7710voipgw_defconfig
index b804641c8dd2..f92ad17cd629 100644
--- a/arch/sh/configs/sh7710voipgw_defconfig
+++ b/arch/sh/configs/sh7710voipgw_defconfig
@@ -3,7 +3,6 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_FUTEX is not set
 # CONFIG_EPOLL is not set
diff --git a/arch/sh/configs/sh7757lcr_defconfig b/arch/sh/configs/sh7757lcr_defconfig
new file mode 100644
index 000000000000..cfde98ddb29d
--- /dev/null
+++ b/arch/sh/configs/sh7757lcr_defconfig
@@ -0,0 +1,91 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS_ALL=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_CPU_SUBTYPE_SH7757=y
+CONFIG_MEMORY_START=0x40000000
+CONFIG_MEMORY_SIZE=0x0f000000
+CONFIG_PMB=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_SH_SH7757LCR=y
+CONFIG_HEARTBEAT=y
+CONFIG_SECCOMP=y
+CONFIG_CMDLINE_OVERWRITE=y
+CONFIG_CMDLINE="console=ttySC2,115200 root=/dev/nfs ip=dhcp"
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_LRO is not set
+CONFIG_IPV6=y
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_VITESSE_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SH_ETH=y
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=3
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_SPI=y
+CONFIG_SPI_SH=y
+# CONFIG_HWMON is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_SH=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_SH=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SH_MMCIF=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_SQUASHFS=y
+CONFIG_MINIX_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_FTRACE is not set
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/sh/configs/sh7763rdp_defconfig b/arch/sh/configs/sh7763rdp_defconfig
index 361876786932..479536440264 100644
--- a/arch/sh/configs/sh7763rdp_defconfig
+++ b/arch/sh/configs/sh7763rdp_defconfig
@@ -3,7 +3,6 @@ CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_NAMESPACES=y
 CONFIG_UTS_NS=y
 CONFIG_IPC_NS=y
diff --git a/arch/sh/configs/sh7785lcr_defconfig b/arch/sh/configs/sh7785lcr_defconfig
index ee6b81f7539e..51561f5677d8 100644
--- a/arch/sh/configs/sh7785lcr_defconfig
+++ b/arch/sh/configs/sh7785lcr_defconfig
@@ -4,7 +4,6 @@ CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_SLAB=y
 CONFIG_PROFILING=y
 CONFIG_MODULES=y
diff --git a/arch/sh/configs/shx3_defconfig b/arch/sh/configs/shx3_defconfig
index bb4f60c0f866..6bb413036892 100644
--- a/arch/sh/configs/shx3_defconfig
+++ b/arch/sh/configs/shx3_defconfig
@@ -9,13 +9,11 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CGROUPS=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_FREEZER=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
 CONFIG_CGROUP_MEM_RES_CTLR=y
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_RELAY=y
 CONFIG_NAMESPACES=y
 CONFIG_UTS_NS=y
diff --git a/arch/sh/configs/systemh_defconfig b/arch/sh/configs/systemh_defconfig
deleted file mode 100644
index 7007d00c67e0..000000000000
--- a/arch/sh/configs/systemh_defconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_HOTPLUG is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_CPU_SUBTYPE_SH7751R=y
-CONFIG_MEMORY_START=0x0c000000
-CONFIG_MEMORY_SIZE=0x00400000
-CONFIG_FLATMEM_MANUAL=y
-CONFIG_SH_7751_SYSTEMH=y
-CONFIG_PREEMPT=y
-# CONFIG_STANDALONE is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=1024
-# CONFIG_INPUT is not set
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_VT is not set
-CONFIG_HW_RANDOM=y
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
diff --git a/arch/sh/configs/titan_defconfig b/arch/sh/configs/titan_defconfig
index 45c309ff447e..e2cbd92d520b 100644
--- a/arch/sh/configs/titan_defconfig
+++ b/arch/sh/configs/titan_defconfig
@@ -5,7 +5,6 @@ CONFIG_POSIX_MQUEUE=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 # CONFIG_SYSCTL_SYSCALL is not set
@@ -228,7 +227,7 @@ CONFIG_USB_SERIAL=m
 CONFIG_USB_SERIAL_GENERIC=y
 CONFIG_USB_SERIAL_ARK3116=m
 CONFIG_USB_SERIAL_PL2303=m
-CONFIG_RTC_CLASS=m
+CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_SH=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
diff --git a/arch/sh/configs/ul2_defconfig b/arch/sh/configs/ul2_defconfig
index e107d424acf0..2d288b887fbd 100644
--- a/arch/sh/configs/ul2_defconfig
+++ b/arch/sh/configs/ul2_defconfig
@@ -4,7 +4,6 @@ CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_PROFILING=y
 CONFIG_MODULES=y
diff --git a/arch/sh/configs/urquell_defconfig b/arch/sh/configs/urquell_defconfig
index 7b3daec6fefe..8bfa4d056d7a 100644
--- a/arch/sh/configs/urquell_defconfig
+++ b/arch/sh/configs/urquell_defconfig
@@ -9,7 +9,6 @@ CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CGROUPS=y
 CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_FREEZER=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CPUSETS=y
diff --git a/arch/sh/drivers/dma/dma-api.c b/arch/sh/drivers/dma/dma-api.c
index 4a277224a871..f46848f088e4 100644
--- a/arch/sh/drivers/dma/dma-api.c
+++ b/arch/sh/drivers/dma/dma-api.c
@@ -412,8 +412,8 @@ EXPORT_SYMBOL(unregister_dmac);
 static int __init dma_api_init(void)
 {
         printk(KERN_NOTICE "DMA: Registering DMA API.\n");
-        create_proc_read_entry("dma", 0, 0, dma_read_proc, 0);
-        return 0;
+        return create_proc_read_entry("dma", 0, 0, dma_read_proc, 0)
+                    ? 0 : -ENOMEM;
 }
 subsys_initcall(dma_api_init);
 
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index 4a59e6890876..82f0a335fd19 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_SH_RTS7751R2D)		+= fixups-rts7751r2d.o
 obj-$(CONFIG_SH_SH03)                   += fixups-sh03.o
 obj-$(CONFIG_SH_HIGHLANDER)             += fixups-r7780rp.o
 obj-$(CONFIG_SH_SH7785LCR)              += fixups-r7780rp.o
+obj-$(CONFIG_SH_SDK7786)                += fixups-sdk7786.o
 obj-$(CONFIG_SH_SDK7780)                += fixups-sdk7780.o
 obj-$(CONFIG_SH_7780_SOLUTION_ENGINE)   += fixups-sdk7780.o
 obj-$(CONFIG_SH_TITAN)                  += fixups-titan.o
diff --git a/arch/sh/drivers/pci/fixups-landisk.c b/arch/sh/drivers/pci/fixups-landisk.c
index bb1a6bb5149e..95c6e2d94a0a 100644
--- a/arch/sh/drivers/pci/fixups-landisk.c
+++ b/arch/sh/drivers/pci/fixups-landisk.c
@@ -1,9 +1,10 @@
 /*
- * arch/sh/drivers/pci/ops-landisk.c
+ * arch/sh/drivers/pci/fixups-landisk.c
  *
  * PCI initialization for the I-O DATA Device, Inc. LANDISK board
  *
  * Copyright (C) 2006 kogiidena
+ * Copyright (C) 2010 Nobuhiro Iwamatsu
  *
  * May be copied or modified under the terms of the GNU General Public
  * License.  See linux/COPYING for more information.
@@ -15,6 +16,9 @@
 #include <linux/pci.h>
 #include "pci-sh4.h"
 
+#define PCIMCR_MRSET_OFF        0xBFFFFFFF
+#define PCIMCR_RFSH_OFF         0xFFFFFFFB
+
 int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
 {
         /*
@@ -26,9 +30,29 @@ int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
         int irq = ((slot + pin - 1) & 0x3) + 5;
 
         if ((slot | (pin - 1)) > 0x3) {
-                printk("PCI: Bad IRQ mapping request for slot %d pin %c\n",
+                printk(KERN_WARNING "PCI: Bad IRQ mapping request for slot %d pin %c\n",
                        slot, pin - 1 + 'A');
                 return -1;
         }
         return irq;
 }
+
+int pci_fixup_pcic(struct pci_channel *chan)
+{
+        unsigned long bcr1, mcr;
+
+        bcr1 = __raw_readl(SH7751_BCR1);
+        bcr1 |= 0x40080000;     /* Enable Bit 19 BREQEN, set PCIC to slave */
+        pci_write_reg(chan, bcr1, SH4_PCIBCR1);
+
+        mcr = __raw_readl(SH7751_MCR);
+        mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
+        pci_write_reg(chan, mcr, SH4_PCIMCR);
+
+        pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
+        pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
+        pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
+        pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
+
+        return 0;
+}
diff --git a/arch/sh/drivers/pci/fixups-sdk7786.c b/arch/sh/drivers/pci/fixups-sdk7786.c
new file mode 100644
index 000000000000..0e18ee332553
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-sdk7786.c
@@ -0,0 +1,67 @@
+/*
+ * SDK7786 FPGA PCIe mux handling
+ *
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#define pr_fmt(fmt) "PCI: " fmt
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <mach/fpga.h>
+
+/*
+ * The SDK7786 FPGA supports mangling of most of the slots in some way or
+ * another. Slots 3/4 are special in that only one can be supported at a
+ * time, and both appear on port 3 to the PCI bus scan. Enabling slot 4
+ * (the horizontal edge connector) will disable slot 3 entirely.
+ *
+ * Misconfigurations can be detected through the FPGA via the slot
+ * resistors to determine card presence. Hotplug remains unsupported.
+ */
+static unsigned int slot4en __devinitdata;
+
+char *__devinit pcibios_setup(char *str)
+{
+        if (strcmp(str, "slot4en") == 0) {
+                slot4en = 1;
+                return NULL;
+        }
+
+        return str;
+}
+
+static int __init sdk7786_pci_init(void)
+{
+        u16 data = fpga_read_reg(PCIECR);
+
+        /*
+         * Enable slot #4 if it's been specified on the command line.
+         *
+         * Optionally reroute if slot #4 has a card present while slot #3
+         * does not, regardless of command line value.
+         *
+         * Card presence is logically inverted.
+         */
+        slot4en ?: (!(data & PCIECR_PRST4) && (data & PCIECR_PRST3));
+        if (slot4en) {
+                pr_info("Activating PCIe slot#4 (disabling slot#3)\n");
+
+                data &= ~PCIECR_PCIEMUX1;
+                fpga_write_reg(data, PCIECR);
+
+                /* Warn about forced rerouting if slot#3 is occupied */
+                if ((data & PCIECR_PRST3) == 0) {
+                        pr_warning("Unreachable card detected in slot#3\n");
+                        return -EBUSY;
+                }
+        } else
+                pr_info("PCIe slot#4 disabled\n");
+
+        return 0;
+}
+postcore_initcall(sdk7786_pci_init);
diff --git a/arch/sh/drivers/pci/fixups-se7751.c b/arch/sh/drivers/pci/fixups-se7751.c
index a4c7d3a4efca..fd3e6b02f289 100644
--- a/arch/sh/drivers/pci/fixups-se7751.c
+++ b/arch/sh/drivers/pci/fixups-se7751.c
@@ -6,7 +6,7 @@
 #include <linux/io.h>
 #include "pci-sh4.h"
 
-int __init pcibios_map_platform_irq(u8 slot, u8 pin)
+int __init pcibios_map_platform_irq(struct pci_dev *, u8 slot, u8 pin)
 {
         switch (slot) {
         case 0: return 13;
diff --git a/arch/sh/drivers/pci/ops-sh4.c b/arch/sh/drivers/pci/ops-sh4.c
index 0b81999fb88b..b6234203e0ac 100644
--- a/arch/sh/drivers/pci/ops-sh4.c
+++ b/arch/sh/drivers/pci/ops-sh4.c
@@ -9,6 +9,7 @@
  */
 #include <linux/pci.h>
 #include <linux/io.h>
+#include <linux/spinlock.h>
 #include <asm/addrspace.h>
 #include "pci-sh4.h"
 
@@ -18,8 +19,6 @@
 #define CONFIG_CMD(bus, devfn, where) \
         (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
 
-static DEFINE_SPINLOCK(sh4_pci_lock);
-
 /*
  * Functions for accessing PCI configuration space with type 1 accesses
  */
@@ -34,10 +33,10 @@ static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
          * PCIPDR may only be accessed as 32 bit words,
          * so we must do byte alignment by hand
          */
-        spin_lock_irqsave(&sh4_pci_lock, flags);
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
         pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
         data = pci_read_reg(chan, SH4_PCIPDR);
-        spin_unlock_irqrestore(&sh4_pci_lock, flags);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 
         switch (size) {
         case 1:
@@ -69,10 +68,10 @@ static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
         int shift;
         u32 data;
 
-        spin_lock_irqsave(&sh4_pci_lock, flags);
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
         pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
         data = pci_read_reg(chan, SH4_PCIPDR);
-        spin_unlock_irqrestore(&sh4_pci_lock, flags);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
 
         switch (size) {
         case 1:
diff --git a/arch/sh/drivers/pci/ops-sh7786.c b/arch/sh/drivers/pci/ops-sh7786.c
index 48f594b9582b..128421009e3f 100644
--- a/arch/sh/drivers/pci/ops-sh7786.c
+++ b/arch/sh/drivers/pci/ops-sh7786.c
@@ -1,7 +1,7 @@
 /*
  * Generic SH7786 PCI-Express operations.
  *
- *  Copyright (C) 2009  Paul Mundt
+ *  Copyright (C) 2009 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License v2. See the file "COPYING" in the main directory of this archive
@@ -19,37 +19,72 @@ enum {
         PCI_ACCESS_WRITE,
 };
 
-static DEFINE_SPINLOCK(sh7786_pcie_lock);
-
 static int sh7786_pcie_config_access(unsigned char access_type,
                 struct pci_bus *bus, unsigned int devfn, int where, u32 *data)
 {
         struct pci_channel *chan = bus->sysdata;
-        int dev, func;
+        int dev, func, type, reg;
 
         dev = PCI_SLOT(devfn);
         func = PCI_FUNC(devfn);
+        type = !!bus->parent;
+        reg = where & ~3;
 
         if (bus->number > 255 || dev > 31 || func > 7)
                 return PCIBIOS_FUNC_NOT_SUPPORTED;
-        if (devfn)
-                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        /*
+         * While each channel has its own memory-mapped extended config
+         * space, it's generally only accessible when in endpoint mode.
+         * When in root complex mode, the controller is unable to target
+         * itself with either type 0 or type 1 accesses, and indeed, any
+         * controller initiated target transfer to its own config space
+         * result in a completer abort.
+         *
+         * Each channel effectively only supports a single device, but as
+         * the same channel <-> device access works for any PCI_SLOT()
+         * value, we cheat a bit here and bind the controller's config
+         * space to devfn 0 in order to enable self-enumeration. In this
+         * case the regular PAR/PDR path is sidelined and the mangled
+         * config access itself is initiated as a SuperHyway transaction.
+         */
+        if (pci_is_root_bus(bus)) {
+                if (dev == 0) {
+                        if (access_type == PCI_ACCESS_READ)
+                                *data = pci_read_reg(chan, PCI_REG(reg));
+                        else
+                                pci_write_reg(chan, *data, PCI_REG(reg));
+
+                        return PCIBIOS_SUCCESSFUL;
+                } else if (dev > 1)
+                        return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        /* Clear errors */
+        pci_write_reg(chan, pci_read_reg(chan, SH4A_PCIEERRFR), SH4A_PCIEERRFR);
 
         /* Set the PIO address */
         pci_write_reg(chan, (bus->number << 24) | (dev << 19) |
-                                (func << 16) | (where & ~3), SH4A_PCIEPAR);
+                                (func << 16) | reg, SH4A_PCIEPAR);
 
         /* Enable the configuration access */
-        pci_write_reg(chan, (1 << 31), SH4A_PCIEPCTLR);
+        pci_write_reg(chan, (1 << 31) | (type << 8), SH4A_PCIEPCTLR);
+
+        /* Check for errors */
+        if (pci_read_reg(chan, SH4A_PCIEERRFR) & 0x10)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        /* Check for master and target aborts */
+        if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
+                return PCIBIOS_DEVICE_NOT_FOUND;
 
         if (access_type == PCI_ACCESS_READ)
                 *data = pci_read_reg(chan, SH4A_PCIEPDR);
         else
                 pci_write_reg(chan, *data, SH4A_PCIEPDR);
 
-        /* Check for master and target aborts */
-        if (pci_read_reg(chan, SH4A_PCIEPCICONF1) & ((1 << 29) | (1 << 28)))
-                return PCIBIOS_DEVICE_NOT_FOUND;
+        /* Disable the configuration access */
+        pci_write_reg(chan, 0, SH4A_PCIEPCTLR);
 
         return PCIBIOS_SUCCESSFUL;
 }
@@ -66,11 +101,13 @@ static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn,
         else if ((size == 4) && (where & 3))
                 return PCIBIOS_BAD_REGISTER_NUMBER;
 
-        spin_lock_irqsave(&sh7786_pcie_lock, flags);
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
         ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
                                         devfn, where, &data);
-        if (ret != PCIBIOS_SUCCESSFUL)
+        if (ret != PCIBIOS_SUCCESSFUL) {
+                *val = 0xffffffff;
                 goto out;
+        }
 
         if (size == 1)
                 *val = (data >> ((where & 3) << 3)) & 0xff;
@@ -84,7 +121,7 @@ static int sh7786_pcie_read(struct pci_bus *bus, unsigned int devfn,
                 devfn, where, size, (unsigned long)*val);
 
 out:
-        spin_unlock_irqrestore(&sh7786_pcie_lock, flags);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
         return ret;
 }
 
@@ -100,7 +137,7 @@ static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn,
         else if ((size == 4) && (where & 3))
                 return PCIBIOS_BAD_REGISTER_NUMBER;
 
-        spin_lock_irqsave(&sh7786_pcie_lock, flags);
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
         ret = sh7786_pcie_config_access(PCI_ACCESS_READ, bus,
                                         devfn, where, &data);
         if (ret != PCIBIOS_SUCCESSFUL)
@@ -124,7 +161,7 @@ static int sh7786_pcie_write(struct pci_bus *bus, unsigned int devfn,
         ret = sh7786_pcie_config_access(PCI_ACCESS_WRITE, bus,
                                         devfn, where, &data);
 out:
-        spin_unlock_irqrestore(&sh7786_pcie_lock, flags);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
         return ret;
 }
 
diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c
index f98141b3b7d7..86adb1e235cd 100644
--- a/arch/sh/drivers/pci/pci-sh7751.c
+++ b/arch/sh/drivers/pci/pci-sh7751.c
@@ -81,7 +81,7 @@ static int __init sh7751_pci_init(void)
         unsigned int id;
         u32 word, reg;
 
-        printk(KERN_NOTICE "PCI: Starting intialization.\n");
+        printk(KERN_NOTICE "PCI: Starting initialization.\n");
 
         chan->reg_base = 0xfe200000;
 
diff --git a/arch/sh/drivers/pci/pci-sh7751.h b/arch/sh/drivers/pci/pci-sh7751.h
index 4983a4d20355..5ede38c330d3 100644
--- a/arch/sh/drivers/pci/pci-sh7751.h
+++ b/arch/sh/drivers/pci/pci-sh7751.h
@@ -61,7 +61,7 @@
   #define SH7751_PCICONF3_BIST7      0x80000000  /* Bist Supported */
   #define SH7751_PCICONF3_BIST6      0x40000000  /* Bist Executing */
   #define SH7751_PCICONF3_BIST3_0    0x0F000000  /* Bist Passed */
-  #define SH7751_PCICONF3_HD7        0x00800000  /* Single Funtion device */
+  #define SH7751_PCICONF3_HD7        0x00800000  /* Single Function device */
   #define SH7751_PCICONF3_HD6_0      0x007F0000  /* Configuration Layout */
   #define SH7751_PCICONF3_LAT        0x0000FF00  /* Latency Timer */
   #define SH7751_PCICONF3_CLS        0x000000FF  /* Cache Line Size */
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
index ffdcbf10b95e..edb7cca14882 100644
--- a/arch/sh/drivers/pci/pci-sh7780.c
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -246,7 +246,7 @@ static int __init sh7780_pci_init(void)
         const char *type;
         int ret, i;
 
-        printk(KERN_NOTICE "PCI: Starting intialization.\n");
+        printk(KERN_NOTICE "PCI: Starting initialization.\n");
 
         chan->reg_base = 0xfe040000;
 
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h
index 205dcbefe275..1742e2c9db7a 100644
--- a/arch/sh/drivers/pci/pci-sh7780.h
+++ b/arch/sh/drivers/pci/pci-sh7780.h
@@ -12,12 +12,6 @@
 #ifndef _PCI_SH7780_H_
 #define _PCI_SH7780_H_
 
-#define PCI_VENDOR_ID_RENESAS           0x1912
-#define PCI_DEVICE_ID_RENESAS_SH7781    0x0001
-#define PCI_DEVICE_ID_RENESAS_SH7780    0x0002
-#define PCI_DEVICE_ID_RENESAS_SH7763    0x0004
-#define PCI_DEVICE_ID_RENESAS_SH7785    0x0007
-
 /* SH7780 Control Registers */
 #define PCIECR                  0xFE000008
 #define PCIECR_ENBL             0x01
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index 1e9598d2bbf4..194231cb5a70 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -19,6 +19,7 @@
 #include <linux/dma-debug.h>
 #include <linux/io.h>
 #include <linux/mutex.h>
+#include <linux/spinlock.h>
 
 unsigned long PCIBIOS_MIN_IO = 0x0000;
 unsigned long PCIBIOS_MIN_MEM = 0;
@@ -56,6 +57,11 @@ static void __devinit pcibios_scanbus(struct pci_channel *hose)
         }
 }
 
+/*
+ * This interrupt-safe spinlock protects all accesses to PCI
+ * configuration space.
+ */
+DEFINE_RAW_SPINLOCK(pci_config_lock);
 static DEFINE_MUTEX(pci_scan_mutex);
 
 int __devinit register_pci_controller(struct pci_channel *hose)
@@ -78,7 +84,7 @@ int __devinit register_pci_controller(struct pci_channel *hose)
         hose_tail = &hose->next;
 
         /*
-         * Do not panic here but later - this might hapen before console init.
+         * Do not panic here but later - this might happen before console init.
          */
         if (!hose->io_map_base) {
                 printk(KERN_WARNING
@@ -233,40 +239,7 @@ void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 
 int pcibios_enable_device(struct pci_dev *dev, int mask)
 {
-        u16 cmd, old_cmd;
-        int idx;
-        struct resource *r;
-
-        pci_read_config_word(dev, PCI_COMMAND, &cmd);
-        old_cmd = cmd;
-        for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
-                /* Only set up the requested stuff */
-                if (!(mask & (1<<idx)))
-                        continue;
-
-                r = &dev->resource[idx];
-                if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
-                        continue;
-                if ((idx == PCI_ROM_RESOURCE) &&
-                                (!(r->flags & IORESOURCE_ROM_ENABLE)))
-                        continue;
-                if (!r->start && r->end) {
-                        printk(KERN_ERR "PCI: Device %s not available "
-                               "because of resource collisions\n",
-                               pci_name(dev));
-                        return -EINVAL;
-                }
-                if (r->flags & IORESOURCE_IO)
-                        cmd |= PCI_COMMAND_IO;
-                if (r->flags & IORESOURCE_MEM)
-                        cmd |= PCI_COMMAND_MEMORY;
-        }
-        if (cmd != old_cmd) {
-                printk("PCI: Enabling device %s (%04x -> %04x)\n",
-                       pci_name(dev), old_cmd, cmd);
-                pci_write_config_word(dev, PCI_COMMAND, cmd);
-        }
-        return 0;
+        return pci_enable_resources(dev, mask);
 }
 
 /*
@@ -295,7 +268,7 @@ void __init pcibios_update_irq(struct pci_dev *dev, int irq)
         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 }
 
-char * __devinit pcibios_setup(char *str)
+char * __devinit __weak pcibios_setup(char *str)
 {
         return str;
 }
@@ -409,14 +382,13 @@ static void __iomem *ioport_map_pci(struct pci_dev *dev,
         struct pci_channel *chan = dev->sysdata;
 
         if (unlikely(!chan->io_map_base)) {
-                chan->io_map_base = generic_io_base;
+                chan->io_map_base = sh_io_port_base;
 
                 if (pci_domains_supported)
                         panic("To avoid data corruption io_map_base MUST be "
                               "set with multiple PCI domains.");
         }
 
-
         return (void __iomem *)(chan->io_map_base + port);
 }
 
diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index 68cb9b0ac9d2..4418f9070ed1 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -1,23 +1,29 @@
 /*
  * Low-Level PCI Express Support for the SH7786
  *
- *  Copyright (C) 2009 - 2010  Paul Mundt
+ *  Copyright (C) 2009 - 2011  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  */
+#define pr_fmt(fmt) "PCI: " fmt
+
 #include <linux/pci.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <linux/async.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/sh_clk.h>
 #include "pcie-sh7786.h"
 #include <asm/sizes.h>
 
 struct sh7786_pcie_port {
         struct pci_channel      *hose;
+        struct clk              *fclk, phy_clk;
         unsigned int            index;
         int                     endpoint;
         int                     link;
@@ -28,7 +34,7 @@ static unsigned int nr_ports;
 
 static struct sh7786_pcie_hwops {
         int (*core_init)(void);
-        int (*port_init_hw)(struct sh7786_pcie_port *port);
+        async_func_ptr *port_init_hw;
 } *sh7786_pcie_hwops;
 
 static struct resource sh7786_pci0_resources[] = {
@@ -51,6 +57,7 @@ static struct resource sh7786_pci0_resources[] = {
                 .name   = "PCIe0 MEM 2",
                 .start  = 0xfe100000,
                 .end    = 0xfe100000 + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
         },
 };
 
@@ -74,6 +81,7 @@ static struct resource sh7786_pci1_resources[] = {
                 .name   = "PCIe1 MEM 2",
                 .start  = 0xfe300000,
                 .end    = 0xfe300000 + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
         },
 };
 
@@ -82,6 +90,7 @@ static struct resource sh7786_pci2_resources[] = {
                 .name   = "PCIe2 IO",
                 .start  = 0xfc800000,
                 .end    = 0xfc800000 + SZ_4M - 1,
+                .flags  = IORESOURCE_IO,
         }, {
                 .name   = "PCIe2 MEM 0",
                 .start  = 0x80000000,
@@ -96,6 +105,7 @@ static struct resource sh7786_pci2_resources[] = {
                 .name   = "PCIe2 MEM 2",
                 .start  = 0xfcd00000,
                 .end    = 0xfcd00000 + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
         },
 };
 
@@ -117,7 +127,29 @@ static struct pci_channel sh7786_pci_channels[] = {
         DEFINE_CONTROLLER(0xfcc00000, 2),
 };
 
-static int phy_wait_for_ack(struct pci_channel *chan)
+static struct clk fixed_pciexclkp = {
+        .rate = 100000000,      /* 100 MHz reference clock */
+};
+
+static void __devinit sh7786_pci_fixup(struct pci_dev *dev)
+{
+        /*
+         * Prevent enumeration of root complex resources.
+         */
+        if (pci_is_root_bus(dev->bus) && dev->devfn == 0) {
+                int i;
+
+                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+                        dev->resource[i].start  = 0;
+                        dev->resource[i].end    = 0;
+                        dev->resource[i].flags  = 0;
+                }
+        }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_SH7786,
+                         sh7786_pci_fixup);
+
+static int __init phy_wait_for_ack(struct pci_channel *chan)
 {
         unsigned int timeout = 100;
 
@@ -131,7 +163,7 @@ static int phy_wait_for_ack(struct pci_channel *chan)
         return -ETIMEDOUT;
 }
 
-static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
+static int __init pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
 {
         unsigned int timeout = 100;
 
@@ -145,19 +177,14 @@ static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
         return -ETIMEDOUT;
 }
 
-static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
-                          unsigned int lane, unsigned int data)
+static void __init phy_write_reg(struct pci_channel *chan, unsigned int addr,
+                                 unsigned int lane, unsigned int data)
 {
-        unsigned long phyaddr, ctrl;
+        unsigned long phyaddr;
 
         phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) +
                         ((addr & 0xff) << BITS_ADR);
 
-        /* Enable clock */
-        ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
-        ctrl |= (1 << BITS_CKE);
-        pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
-
         /* Set write data */
         pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
         pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);
@@ -165,20 +192,74 @@ static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
         phy_wait_for_ack(chan);
 
         /* Clear command */
+        pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
         pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);
 
         phy_wait_for_ack(chan);
+}
 
-        /* Disable clock */
-        ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
-        ctrl &= ~(1 << BITS_CKE);
-        pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
+static int __init pcie_clk_init(struct sh7786_pcie_port *port)
+{
+        struct pci_channel *chan = port->hose;
+        struct clk *clk;
+        char fclk_name[16];
+        int ret;
+
+        /*
+         * First register the fixed clock
+         */
+        ret = clk_register(&fixed_pciexclkp);
+        if (unlikely(ret != 0))
+                return ret;
+
+        /*
+         * Grab the port's function clock, which the PHY clock depends
+         * on. clock lookups don't help us much at this point, since no
+         * dev_id is available this early. Lame.
+         */
+        snprintf(fclk_name, sizeof(fclk_name), "pcie%d_fck", port->index);
+
+        port->fclk = clk_get(NULL, fclk_name);
+        if (IS_ERR(port->fclk)) {
+                ret = PTR_ERR(port->fclk);
+                goto err_fclk;
+        }
+
+        clk_enable(port->fclk);
+
+        /*
+         * And now, set up the PHY clock
+         */
+        clk = &port->phy_clk;
+
+        memset(clk, 0, sizeof(struct clk));
+
+        clk->parent = &fixed_pciexclkp;
+        clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR);
+        clk->enable_bit = BITS_CKE;
+
+        ret = sh_clk_mstp32_register(clk, 1);
+        if (unlikely(ret < 0))
+                goto err_phy;
+
+        return 0;
+
+err_phy:
+        clk_disable(port->fclk);
+        clk_put(port->fclk);
+err_fclk:
+        clk_unregister(&fixed_pciexclkp);
+
+        return ret;
 }
 
-static int phy_init(struct pci_channel *chan)
+static int __init phy_init(struct sh7786_pcie_port *port)
 {
+        struct pci_channel *chan = port->hose;
         unsigned int timeout = 100;
 
+        clk_enable(&port->phy_clk);
+
         /* Initialize the phy */
         phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
         phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
@@ -187,9 +268,13 @@ static int phy_init(struct pci_channel *chan)
         phy_write_reg(chan, 0x66, 0xf, 0x00000010);
         phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
         phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
+        phy_write_reg(chan, 0xb0, 0xf, 0x00000610);
 
         /* Deassert Standby */
-        phy_write_reg(chan, 0x67, 0xf, 0x00000400);
+        phy_write_reg(chan, 0x67, 0x1, 0x00000400);
+
+        /* Disable clock */
+        clk_disable(&port->phy_clk);
 
         while (timeout--) {
                 if (pci_read_reg(chan, SH4A_PCIEPHYSR))
@@ -201,22 +286,33 @@ static int phy_init(struct pci_channel *chan)
         return -ETIMEDOUT;
 }
 
-static int pcie_init(struct sh7786_pcie_port *port)
+static void __init pcie_reset(struct sh7786_pcie_port *port)
+{
+        struct pci_channel *chan = port->hose;
+
+        pci_write_reg(chan, 1, SH4A_PCIESRSTR);
+        pci_write_reg(chan, 0, SH4A_PCIETCTLR);
+        pci_write_reg(chan, 0, SH4A_PCIESRSTR);
+        pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
+}
+
+static int __init pcie_init(struct sh7786_pcie_port *port)
 {
         struct pci_channel *chan = port->hose;
         unsigned int data;
         phys_addr_t memphys;
         size_t memsize;
-        int ret, i;
+        int ret, i, win;
 
         /* Begin initialization */
-        pci_write_reg(chan, 0, SH4A_PCIETCTLR);
+        pcie_reset(port);
 
-        /* Initialize as type1. */
-        data = pci_read_reg(chan, SH4A_PCIEPCICONF3);
-        data &= ~(0x7f << 16);
-        data |= PCI_HEADER_TYPE_BRIDGE << 16;
-        pci_write_reg(chan, data, SH4A_PCIEPCICONF3);
+        /*
+         * Initial header for port config space is type 1, set the device
+         * class to match. Hardware takes care of propagating the IDSETR
+         * settings, so there is no need to bother with a quirk.
+         */
+        pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI << 16, SH4A_PCIEIDSETR1);
 
         /* Initialize default capabilities. */
         data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);
@@ -268,30 +364,33 @@ static int pcie_init(struct sh7786_pcie_port *port)
          * LAR1/LAMR1.
          */
         if (memsize > SZ_512M) {
-                __raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);
-                __raw_writel(((memsize - SZ_512M) - SZ_256) | 1,
-                             chan->reg_base + SH4A_PCIELAMR1);
+                pci_write_reg(chan, memphys + SZ_512M, SH4A_PCIELAR1);
+                pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1,
+                              SH4A_PCIELAMR1);
                 memsize = SZ_512M;
         } else {
                 /*
                  * Otherwise just zero it out and disable it.
                  */
-                __raw_writel(0, chan->reg_base + SH4A_PCIELAR1);
-                __raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);
+                pci_write_reg(chan, 0, SH4A_PCIELAR1);
+                pci_write_reg(chan, 0, SH4A_PCIELAMR1);
         }
 
         /*
          * LAR0/LAMR0 covers up to the first 512MB, which is enough to
          * cover all of lowmem on most platforms.
          */
-        __raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
-        __raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);
+        pci_write_reg(chan, memphys, SH4A_PCIELAR0);
+        pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0);
 
         /* Finish initialization */
         data = pci_read_reg(chan, SH4A_PCIETCTLR);
         data |= 0x1;
         pci_write_reg(chan, data, SH4A_PCIETCTLR);
 
+        /* Let things settle down a bit.. */
+        mdelay(100);
+
         /* Enable DL_Active Interrupt generation */
         data = pci_read_reg(chan, SH4A_PCIEDLINTENR);
         data |= PCIEDLINTENR_DLL_ACT_ENABLE;
@@ -302,9 +401,12 @@ static int pcie_init(struct sh7786_pcie_port *port)
         data |= PCIEMACCTLR_SCR_DIS | (0xff << 16);
         pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
 
+        /*
+         * This will timeout if we don't have a link, but we permit the
+         * port to register anyways in order to support hotplug on future
+         * hardware.
+         */
         ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL);
-        if (unlikely(ret != 0))
-                return -ENODEV;
 
         data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
         data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
@@ -317,35 +419,48 @@ static int pcie_init(struct sh7786_pcie_port *port)
 
         wmb();
 
-        data = pci_read_reg(chan, SH4A_PCIEMACSR);
-        printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
-               port->index, (data >> 20) & 0x3f);
-
+        if (ret == 0) {
+                data = pci_read_reg(chan, SH4A_PCIEMACSR);
+                printk(KERN_NOTICE "PCI: PCIe#%d x%d link detected\n",
+                       port->index, (data >> 20) & 0x3f);
+        } else
+                printk(KERN_NOTICE "PCI: PCIe#%d link down\n",
+                       port->index);
 
-        for (i = 0; i < chan->nr_resources; i++) {
+        for (i = win = 0; i < chan->nr_resources; i++) {
                 struct resource *res = chan->resources + i;
                 resource_size_t size;
-                u32 enable_mask;
+                u32 mask;
 
-                pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(i));
+                /*
+                 * We can't use the 32-bit mode windows in legacy 29-bit
+                 * mode, so just skip them entirely.
+                 */
+                if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())
+                        continue;
 
-                size = resource_size(res);
+                pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
 
                 /*
                  * The PAMR mask is calculated in units of 256kB, which
                  * keeps things pretty simple.
                  */
-                __raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
-                             chan->reg_base + SH4A_PCIEPAMR(i));
+                size = resource_size(res);
+                mask = (roundup_pow_of_two(size) / SZ_256K) - 1;
+                pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win));
 
-                pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i));
-                pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL(i));
+                pci_write_reg(chan, upper_32_bits(res->start),
+                              SH4A_PCIEPARH(win));
+                pci_write_reg(chan, lower_32_bits(res->start),
+                              SH4A_PCIEPARL(win));
 
-                enable_mask = MASK_PARE;
+                mask = MASK_PARE;
                 if (res->flags & IORESOURCE_IO)
-                        enable_mask |= MASK_SPC;
+                        mask |= MASK_SPC;
+
+                pci_write_reg(chan, mask, SH4A_PCIEPTCTLR(win));
 
-                pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(i));
+                win++;
         }
 
         return 0;
@@ -356,31 +471,51 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
         return 71;
 }
 
-static int sh7786_pcie_core_init(void)
+static int __init sh7786_pcie_core_init(void)
 {
         /* Return the number of ports */
         return test_mode_pin(MODE_PIN12) ? 3 : 2;
 }
 
-static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
+static void __init sh7786_pcie_init_hw(void *data, async_cookie_t cookie)
 {
+        struct sh7786_pcie_port *port = data;
         int ret;
 
-        ret = phy_init(port->hose);
-        if (unlikely(ret < 0))
-                return ret;
-
         /*
          * Check if we are configured in endpoint or root complex mode,
          * this is a fixed pin setting that applies to all PCIe ports.
          */
         port->endpoint = test_mode_pin(MODE_PIN11);
 
+        /*
+         * Setup clocks, needed both for PHY and PCIe registers.
+         */
+        ret = pcie_clk_init(port);
+        if (unlikely(ret < 0)) {
+                pr_err("clock initialization failed for port#%d\n",
+                       port->index);
+                return;
+        }
+
+        ret = phy_init(port);
+        if (unlikely(ret < 0)) {
+                pr_err("phy initialization failed for port#%d\n",
+                       port->index);
+                return;
+        }
+
         ret = pcie_init(port);
-        if (unlikely(ret < 0))
-                return ret;
+        if (unlikely(ret < 0)) {
+                pr_err("core initialization failed for port#%d\n",
+                               port->index);
+                return;
+        }
 
-        return register_pci_controller(port->hose);
+        /* In the interest of preserving device ordering, synchronize */
+        async_synchronize_cookie(cookie);
+
+        register_pci_controller(port->hose);
 }
 
 static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
@@ -390,9 +525,10 @@ static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
 
 static int __init sh7786_pcie_init(void)
 {
-        int ret = 0, i;
+        struct clk *platclk;
+        int i;
 
-        printk(KERN_NOTICE "PCI: Starting intialization.\n");
+        printk(KERN_NOTICE "PCI: Starting initialization.\n");
 
         sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops;
 
@@ -407,6 +543,22 @@ static int __init sh7786_pcie_init(void)
         if (unlikely(!sh7786_pcie_ports))
                 return -ENOMEM;
 
+        /*
+         * Fetch any optional platform clock associated with this block.
+         *
+         * This is a rather nasty hack for boards with spec-mocking FPGAs
+         * that have a secondary set of clocks outside of the on-chip
+         * ones that need to be accounted for before there is any chance
+         * of touching the existing MSTP bits or CPG clocks.
+         */
+        platclk = clk_get(NULL, "pcie_plat_clk");
+        if (IS_ERR(platclk)) {
+                /* Sane hardware should probably get a WARN_ON.. */
+                platclk = NULL;
+        }
+
+        clk_enable(platclk);
+
         printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);
 
         for (i = 0; i < nr_ports; i++) {
@@ -416,11 +568,10 @@ static int __init sh7786_pcie_init(void)
                 port->hose              = sh7786_pci_channels + i;
                 port->hose->io_map_base = port->hose->resources[0].start;
 
-                ret |= sh7786_pcie_hwops->port_init_hw(port);
+                async_schedule(sh7786_pcie_hwops->port_init_hw, port);
         }
 
-        if (unlikely(ret))
-                return ret;
+        async_synchronize_full();
 
         return 0;
 }
diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h
index 90a6992576b0..1ee054e47eae 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.h
+++ b/arch/sh/drivers/pci/pcie-sh7786.h
@@ -55,8 +55,11 @@
 #define         BITS_ERRRCV     (0)             /* 0 ERRRCV 0 */
 #define         MASK_ERRRCV     (1<<BITS_ERRRCV)
 
+/*      PCIEENBLR        */
+#define SH4A_PCIEENBLR          (0x000008)      /* R/W - 0x0000 0001 32 */
+
 /*      PCIEECR         */
-#define SH4A_PCIEECR            (0x000008)      /* R/W - 0x0000 0000 32 */
+#define SH4A_PCIEECR            (0x00000C)      /* R/W - 0x0000 0000 32 */
 #define         BITS_ENBL       (0)     /* 0 ENBL 0 R/W */
 #define         MASK_ENBL       (1<<BITS_ENBL)
 
@@ -113,6 +116,27 @@
 #define         BITS_MDATA      (0)
 #define         MASK_MDATA      (0xffffffff<<BITS_MDATA)
 
+/*      PCIEUNLOCKCR    */
+#define SH4A_PCIEUNLOCKCR       (0x000048)      /* R/W - 0x0000 0000 32 */
+
+/*      PCIEIDR         */
+#define SH4A_PCIEIDR            (0x000060)      /* R/W - 0x0101 1101 32 */
+
+/*      PCIEDBGCTLR     */
+#define SH4A_PCIEDBGCTLR        (0x000100)      /* R/W - 0x0000 0000 32 */
+
+/*      PCIEINTXR       */
+#define SH4A_PCIEINTXR          (0x004000)      /* R/W - 0x0000 0000 32 */
+
+/*      PCIERMSGR       */
+#define SH4A_PCIERMSGR          (0x004010)      /* R/W - 0x0000 0000 32 */
+
+/*      PCIERSTR        */
+#define SH4A_PCIERSTR(x)        (0x008000 + ((x) * 0x4)) /* R/W - 0x0000 0000 32 */
+
+/*      PCIESRSTR        */
+#define SH4A_PCIESRSTR          (0x008040)      /* R/W - 0x0000 0000 32 */
+
 /*      PCIEPHYCTLR     */
 #define SH4A_PCIEPHYCTLR        (0x010000)      /* R/W - 0x0000 0000 32 */
 #define         BITS_CKE        (0)
@@ -121,6 +145,9 @@
 /*      PCIERMSGIER     */
 #define SH4A_PCIERMSGIER        (0x004040)      /* R/W - 0x0000 0000 32 */
 
+/*      PCIEPHYCTLR     */
+#define SH4A_PCIEPHYCTLR        (0x010000)      /* R/W - 0x0000 0000 32 */
+
 /*      PCIEPHYADRR     */
 #define SH4A_PCIEPHYADRR        (0x010004)      /* R/W - 0x0000 0000 32 */
 #define         BITS_ACK        (24)                    // Rev1.171
@@ -152,7 +179,7 @@
 #define         MASK_CFINT      (1<<BITS_CFINT)
 
 /*      PCIETSTR        */
-#define SH4A_PCIETSTR           (0x020004)      /* R/W R/W 0x0000 0000 32  */
+#define SH4A_PCIETSTR           (0x020004)      /* R 0x0000 0000 32  */
 
 /*      PCIEINTR        */
 #define SH4A_PCIEINTR           (0x020008)      /* R/W R/W 0x0000 0000 32  */
@@ -236,6 +263,9 @@
 #define         BITS_INTPM                      (8)
 #define         MASK_INTPM                      (1<<BITS_INTPM)
 
+/*      PCIEEH0R        */
+#define SH4A_PCIEEHR(x)         (0x020010 + ((x) * 0x4)) /* R - 0x0000 0000 32 */
+
 /*      PCIEAIR  */
 #define SH4A_PCIEAIR            (SH4A_PCIE_BASE + 0x020010)     /* R/W R/W 0xxxxx xxxx 32 */
 
@@ -244,6 +274,25 @@
 
 /*       PCIEERRFR       */                                                             // Rev1.18
 #define SH4A_PCIEERRFR          (0x020020)              /* R/W R/W 0xxxxx xxxx 32 */    // Rev1.18
+
+/*      PCIEERRFER      */
+#define SH4A_PCIEERRFER         (0x020024)              /* R/W R/W 0x0000 0000 32 */
+
+/*      PCIEERRFR2      */
+#define SH4A_PCIEERRFR2         (0x020028)              /* R/W R/W 0x0000 0000 32 */
+
+/*      PCIEMSIR        */
+#define SH4A_PCIEMSIR           (0x020040)              /* R/W - 0x0000 0000 32 */
+
+/*      PCIEMSIFR       */
+#define SH4A_PCIEMSIFR          (0x020044)              /* R/W R/W 0x0000 0000 32 */
+
+/*      PCIEPWRCTLR     */
+#define SH4A_PCIEPWRCTLR        (0x020100)              /* R/W - 0x0000 0000 32 */
+
+/*      PCIEPCCTLR      */
+#define SH4A_PCIEPCCTLR         (0x020180)              /* R/W - 0x0000 0000 32 */
+
                                                                                         // Rev1.18
 /*      PCIELAR0        */
 #define SH4A_PCIELAR0           (0x020200)      /* R/W R/W 0x0000 0000 32 */
@@ -352,6 +401,7 @@
 #define SH4A_PCIEDMCCR0         (0x021120)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMCC2R0        (0x021124)      /* R/W R/W 0x0000 0000 - */
 #define SH4A_PCIEDMCCCR0        (0x021128)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCHSR0        (0x02112C)      /* R/W - 0x0000 0000 32 */
 #define SH4A_PCIEDMSAR1         (0x021140)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMSAHR1        (0x021144)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMDAR1         (0x021148)      /* R/W R/W 0x0000 0000 32 */
@@ -363,6 +413,7 @@
 #define SH4A_PCIEDMCCR1         (0x021160)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMCC2R1        (0x021164)      /* R/W R/W 0x0000 0000 - */
 #define SH4A_PCIEDMCCCR1        (0x021168)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCHSR1        (0x02116C)      /* R/W - 0x0000 0000 32 */
 #define SH4A_PCIEDMSAR2         (0x021180)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMSAHR2        (0x021184)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMDAR2         (0x021188)      /* R/W R/W 0x0000 0000 32 */
@@ -385,6 +436,7 @@
 #define SH4A_PCIEDMCCR3         (0x0211E0)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMCC2R3        (0x0211E4)      /* R/W R/W 0x0000 0000 -  */
 #define SH4A_PCIEDMCCCR3        (0x0211E8)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCHSR3        (0x0211EC)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEPCICONF0       (0x040000)      /* R R - 8/16/32 */
 #define SH4A_PCIEPCICONF1       (0x040004)      /* R/W R/W 0x0008 0000 8/16/32 */
 #define SH4A_PCIEPCICONF2       (0x040008)      /* R/W R/W 0xFF00 0000 8/16/32 */
diff --git a/arch/sh/drivers/push-switch.c b/arch/sh/drivers/push-switch.c
index 7b42c247316c..afc24556572b 100644
--- a/arch/sh/drivers/push-switch.c
+++ b/arch/sh/drivers/push-switch.c
@@ -107,7 +107,7 @@ static int switch_drv_remove(struct platform_device *pdev)
                 device_remove_file(&pdev->dev, &dev_attr_switch);
 
         platform_set_drvdata(pdev, NULL);
-        flush_scheduled_work();
+        flush_work_sync(&psw->work);
         del_timer_sync(&psw->debounce);
         free_irq(irq, pdev);
 
diff --git a/arch/sh/include/asm/Kbuild b/arch/sh/include/asm/Kbuild
index 0eed47b236ab..7beb42322f60 100644
--- a/arch/sh/include/asm/Kbuild
+++ b/arch/sh/include/asm/Kbuild
@@ -5,5 +5,7 @@ header-y += cpu-features.h
 header-y += hw_breakpoint.h
 header-y += posix_types_32.h
 header-y += posix_types_64.h
+header-y += ptrace_32.h
+header-y += ptrace_64.h
 header-y += unistd_32.h
 header-y += unistd_64.h
diff --git a/arch/sh/include/asm/addrspace.h b/arch/sh/include/asm/addrspace.h
index 446b3831c214..3d1ae2bfaa6f 100644
--- a/arch/sh/include/asm/addrspace.h
+++ b/arch/sh/include/asm/addrspace.h
@@ -44,10 +44,10 @@
 /*
  * These will never work in 32-bit, don't even bother.
  */
-#define P1SEGADDR(a)    __futile_remapping_attempt
-#define P2SEGADDR(a)    __futile_remapping_attempt
-#define P3SEGADDR(a)    __futile_remapping_attempt
-#define P4SEGADDR(a)    __futile_remapping_attempt
+#define P1SEGADDR(a)    ({ (void)(a); BUG(); NULL; })
+#define P2SEGADDR(a)    ({ (void)(a); BUG(); NULL; })
+#define P3SEGADDR(a)    ({ (void)(a); BUG(); NULL; })
+#define P4SEGADDR(a)    ({ (void)(a); BUG(); NULL; })
 #endif
 #endif /* P1SEG */
 
diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h
index 98511e4d28cb..90fa3e48b4d6 100644
--- a/arch/sh/include/asm/bitops.h
+++ b/arch/sh/include/asm/bitops.h
@@ -94,9 +94,8 @@ static inline unsigned long ffz(unsigned long word)
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 #include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/ext2-non-atomic.h>
+#include <asm-generic/bitops/le.h>
 #include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/minix.h>
 #include <asm-generic/bitops/fls.h>
 #include <asm-generic/bitops/__fls.h>
 #include <asm-generic/bitops/fls64.h>
diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h
index 1f4e562c5e8c..82e1eabeac98 100644
--- a/arch/sh/include/asm/cacheflush.h
+++ b/arch/sh/include/asm/cacheflush.h
@@ -96,7 +96,7 @@ void kmap_coherent_init(void);
 void *kmap_coherent(struct page *page, unsigned long addr);
 void kunmap_coherent(void *kvaddr);
 
-#define PG_dcache_dirty PG_arch_1
+#define PG_dcache_clean PG_arch_1
 
 void cpu_cache_init(void);
 
diff --git a/arch/sh/include/asm/clkdev.h b/arch/sh/include/asm/clkdev.h
index 5645f358128b..6ba91868201c 100644
--- a/arch/sh/include/asm/clkdev.h
+++ b/arch/sh/include/asm/clkdev.h
@@ -1,9 +1,5 @@
 /*
- *  arch/sh/include/asm/clkdev.h
- *
- * Cloned from arch/arm/include/asm/clkdev.h:
- *
- *  Copyright (C) 2008 Russell King.
+ *  Copyright (C) 2010 Paul Mundt <lethal@linux-sh.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -11,25 +7,25 @@
  *
  * Helper for the clk API to assist looking up a struct clk.
  */
-#ifndef __ASM_CLKDEV_H
-#define __ASM_CLKDEV_H
 
-struct clk;
+#ifndef __CLKDEV__H_
+#define __CLKDEV__H_
 
-struct clk_lookup {
-        struct list_head        node;
-        const char              *dev_id;
-        const char              *con_id;
-        struct clk              *clk;
-};
+#include <linux/bootmem.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
 
-struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
-        const char *dev_fmt, ...);
+#include <asm/clock.h>
 
-void clkdev_add(struct clk_lookup *cl);
-void clkdev_drop(struct clk_lookup *cl);
+static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
+{
+        if (!slab_is_available())
+                return alloc_bootmem_low_pages(size);
+        else
+                return kzalloc(size, GFP_KERNEL);
+}
 
-void clkdev_add_table(struct clk_lookup *, size_t);
-int clk_add_alias(const char *, const char *, char *, struct device *);
+#define __clk_put(clk)
+#define __clk_get(clk) ({ 1; })
 
-#endif
+#endif /* __CLKDEV_H__ */
diff --git a/arch/sh/include/asm/cmpxchg-grb.h b/arch/sh/include/asm/cmpxchg-grb.h
index 4676bf57693a..f848dec9e483 100644
--- a/arch/sh/include/asm/cmpxchg-grb.h
+++ b/arch/sh/include/asm/cmpxchg-grb.h
@@ -15,8 +15,9 @@ static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
                 "   mov.l   %2,   @%1     \n\t" /* store new value */
                 "1: mov     r1,   r15     \n\t" /* LOGOUT */
                 : "=&r" (retval),
-                  "+r"  (m)
-                : "r"   (val)
+                  "+r"  (m),
+                  "+r"  (val)           /* inhibit r15 overloading */
+                :
                 : "memory", "r0", "r1");
 
         return retval;
@@ -36,8 +37,9 @@ static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
                 "   mov.b   %2,   @%1     \n\t" /* store new value */
                 "1: mov     r1,   r15     \n\t" /* LOGOUT */
                 : "=&r" (retval),
-                  "+r"  (m)
-                : "r"   (val)
+                  "+r"  (m),
+                  "+r"  (val)           /* inhibit r15 overloading */
+                :
                 : "memory" , "r0", "r1");
 
         return retval;
@@ -54,13 +56,14 @@ static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
                 "   nop                   \n\t"
                 "   mov    r15,   r1      \n\t" /* r1 = saved sp */
                 "   mov    #-8,   r15     \n\t" /* LOGIN */
-                "   mov.l  @%1,   %0      \n\t" /* load  old value */
-                "   cmp/eq  %0,   %2      \n\t"
+                "   mov.l  @%3,   %0      \n\t" /* load  old value */
+                "   cmp/eq  %0,   %1      \n\t"
                 "   bf            1f      \n\t" /* if not equal */
-                "   mov.l   %3,   @%1     \n\t" /* store new value */
+                "   mov.l   %2,   @%3     \n\t" /* store new value */
                 "1: mov     r1,   r15     \n\t" /* LOGOUT */
-                : "=&r" (retval)
-                :  "r"  (m), "r"  (old), "r"  (new)
+                : "=&r" (retval),
+                  "+r"  (old), "+r"  (new) /* old or new can be r15 */
+                :  "r"  (m)
                 : "memory" , "r0", "r1", "t");
 
         return retval;
diff --git a/arch/sh/include/asm/elf.h b/arch/sh/include/asm/elf.h
index ce830faeebbf..f38112be67d2 100644
--- a/arch/sh/include/asm/elf.h
+++ b/arch/sh/include/asm/elf.h
@@ -50,25 +50,14 @@
 #define R_SH_GOTPC              167
 
 /* FDPIC relocs */
-#define R_SH_GOT20              70
-#define R_SH_GOTOFF20           71
-#define R_SH_GOTFUNCDESC        72
-#define R_SH_GOTFUNCDESC20      73
-#define R_SH_GOTOFFFUNCDESC     74
-#define R_SH_GOTOFFFUNCDESC20   75
-#define R_SH_FUNCDESC           76
-#define R_SH_FUNCDESC_VALUE     77
-
-#if 0 /* XXX - later .. */
-#define R_SH_GOT20              198
-#define R_SH_GOTOFF20           199
-#define R_SH_GOTFUNCDESC        200
-#define R_SH_GOTFUNCDESC20      201
-#define R_SH_GOTOFFFUNCDESC     202
-#define R_SH_GOTOFFFUNCDESC20   203
-#define R_SH_FUNCDESC           204
-#define R_SH_FUNCDESC_VALUE     205
-#endif
+#define R_SH_GOT20              201
+#define R_SH_GOTOFF20           202
+#define R_SH_GOTFUNCDESC        203
+#define R_SH_GOTFUNCDESC20      204
+#define R_SH_GOTOFFFUNCDESC     205
+#define R_SH_GOTOFFFUNCDESC20   206
+#define R_SH_FUNCDESC           207
+#define R_SH_FUNCDESC_VALUE     208
 
 /* SHmedia relocs */
 #define R_SH_IMM_LOW16          246
diff --git a/arch/sh/include/asm/fixmap.h b/arch/sh/include/asm/fixmap.h
index 6e7cea453895..bd7e79a12653 100644
--- a/arch/sh/include/asm/fixmap.h
+++ b/arch/sh/include/asm/fixmap.h
@@ -58,7 +58,7 @@ enum fixed_addresses {
 
 #ifdef CONFIG_HIGHMEM
         FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
-        FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
+        FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_TYPE_NR * NR_CPUS) - 1,
 #endif
 
 #ifdef CONFIG_IOREMAP_FIXED
@@ -69,7 +69,7 @@ enum fixed_addresses {
          */
 #define FIX_N_IOREMAPS  32
         FIX_IOREMAP_BEGIN,
-        FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS,
+        FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS - 1,
 #endif
 
         __end_of_fixed_addresses
diff --git a/arch/sh/include/asm/futex-irq.h b/arch/sh/include/asm/futex-irq.h
index a9f16a7f9aea..6cb9f193a95e 100644
--- a/arch/sh/include/asm/futex-irq.h
+++ b/arch/sh/include/asm/futex-irq.h
@@ -3,7 +3,7 @@
 
 #include <asm/system.h>
 
-static inline int atomic_futex_op_xchg_set(int oparg, int __user *uaddr,
+static inline int atomic_futex_op_xchg_set(int oparg, u32 __user *uaddr,
                                            int *oldval)
 {
         unsigned long flags;
@@ -20,7 +20,7 @@ static inline int atomic_futex_op_xchg_set(int oparg, int __user *uaddr,
         return ret;
 }
 
-static inline int atomic_futex_op_xchg_add(int oparg, int __user *uaddr,
+static inline int atomic_futex_op_xchg_add(int oparg, u32 __user *uaddr,
                                            int *oldval)
 {
         unsigned long flags;
@@ -37,7 +37,7 @@ static inline int atomic_futex_op_xchg_add(int oparg, int __user *uaddr,
         return ret;
 }
 
-static inline int atomic_futex_op_xchg_or(int oparg, int __user *uaddr,
+static inline int atomic_futex_op_xchg_or(int oparg, u32 __user *uaddr,
                                           int *oldval)
 {
         unsigned long flags;
@@ -54,7 +54,7 @@ static inline int atomic_futex_op_xchg_or(int oparg, int __user *uaddr,
         return ret;
 }
 
-static inline int atomic_futex_op_xchg_and(int oparg, int __user *uaddr,
+static inline int atomic_futex_op_xchg_and(int oparg, u32 __user *uaddr,
                                            int *oldval)
 {
         unsigned long flags;
@@ -71,7 +71,7 @@ static inline int atomic_futex_op_xchg_and(int oparg, int __user *uaddr,
         return ret;
 }
 
-static inline int atomic_futex_op_xchg_xor(int oparg, int __user *uaddr,
+static inline int atomic_futex_op_xchg_xor(int oparg, u32 __user *uaddr,
                                            int *oldval)
 {
         unsigned long flags;
@@ -88,11 +88,13 @@ static inline int atomic_futex_op_xchg_xor(int oparg, int __user *uaddr,
         return ret;
 }
 
-static inline int atomic_futex_op_cmpxchg_inatomic(int __user *uaddr,
-                                                   int oldval, int newval)
+static inline int atomic_futex_op_cmpxchg_inatomic(u32 *uval,
+                                                   u32 __user *uaddr,
+                                                   u32 oldval, u32 newval)
 {
         unsigned long flags;
-        int ret, prev = 0;
+        int ret;
+        u32 prev = 0;
 
         local_irq_save(flags);
 
@@ -102,10 +104,8 @@ static inline int atomic_futex_op_cmpxchg_inatomic(int __user *uaddr,
 
         local_irq_restore(flags);
 
-        if (ret)
-                return ret;
-
-        return prev;
+        *uval = prev;
+        return ret;
 }
 
 #endif /* __ASM_SH_FUTEX_IRQ_H */
diff --git a/arch/sh/include/asm/futex.h b/arch/sh/include/asm/futex.h
index 68256ec5fa35..7be39a646fbd 100644
--- a/arch/sh/include/asm/futex.h
+++ b/arch/sh/include/asm/futex.h
@@ -10,7 +10,7 @@
 /* XXX: UP variants, fix for SH-4A and SMP.. */
 #include <asm/futex-irq.h>
 
-static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
+static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
 {
         int op = (encoded_op >> 28) & 7;
         int cmp = (encoded_op >> 24) & 15;
@@ -21,7 +21,7 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
         if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
                 oparg = 1 << oparg;
 
-        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
                 return -EFAULT;
 
         pagefault_disable();
@@ -65,12 +65,13 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
 }
 
 static inline int
-futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
+futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
+                              u32 oldval, u32 newval)
 {
-        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
                 return -EFAULT;
 
-        return atomic_futex_op_cmpxchg_inatomic(uaddr, oldval, newval);
+        return atomic_futex_op_cmpxchg_inatomic(uval, uaddr, oldval, newval);
 }
 
 #endif /* __KERNEL__ */
diff --git a/arch/sh/include/asm/gpio.h b/arch/sh/include/asm/gpio.h
index f8d9a731e903..04f53d31489f 100644
--- a/arch/sh/include/asm/gpio.h
+++ b/arch/sh/include/asm/gpio.h
@@ -41,14 +41,12 @@ static inline int gpio_cansleep(unsigned gpio)
 
 static inline int gpio_to_irq(unsigned gpio)
 {
-        WARN_ON(1);
-        return -ENOSYS;
+        return __gpio_to_irq(gpio);
 }
 
 static inline int irq_to_gpio(unsigned int irq)
 {
-        WARN_ON(1);
-        return -EINVAL;
+        return -ENOSYS;
 }
 
 #endif /* CONFIG_GPIOLIB */
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index b237d525d592..28c5aa58bb45 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -1,5 +1,6 @@
 #ifndef __ASM_SH_IO_H
 #define __ASM_SH_IO_H
+
 /*
  * Convention:
  *    read{b,w,l,q}/write{b,w,l,q} are for PCI,
@@ -10,17 +11,6 @@
  *
  * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
  * automatically, there are also __raw versions, which do not.
- *
- * Historically, we have also had ctrl_in{b,w,l,q}/ctrl_out{b,w,l,q} for
- * SuperH specific I/O (raw I/O to on-chip CPU peripherals). In practice
- * these have the same semantics as the __raw variants, and as such, all
- * new code should be using the __raw versions.
- *
- * All ISA I/O routines are wrapped through the machine vector. If a
- * board does not provide overrides, a generic set that are copied in
- * from the default machine vector are used instead. These are largely
- * for old compat code for I/O offseting to SuperIOs, all of which are
- * better handled through the machvec ioport mapping routines these days.
  */
 #include <linux/errno.h>
 #include <asm/cache.h>
@@ -31,39 +21,10 @@
 #include <asm-generic/iomap.h>
 
 #ifdef __KERNEL__
-/*
- * Depending on which platform we are running on, we need different
- * I/O functions.
- */
-#define __IO_PREFIX     generic
+#define __IO_PREFIX     generic
 #include <asm/io_generic.h>
 #include <asm/io_trapped.h>
 
-#ifdef CONFIG_HAS_IOPORT
-
-#define inb(p)                  sh_mv.mv_inb((p))
-#define inw(p)                  sh_mv.mv_inw((p))
-#define inl(p)                  sh_mv.mv_inl((p))
-#define outb(x,p)               sh_mv.mv_outb((x),(p))
-#define outw(x,p)               sh_mv.mv_outw((x),(p))
-#define outl(x,p)               sh_mv.mv_outl((x),(p))
-
-#define inb_p(p)                sh_mv.mv_inb_p((p))
-#define inw_p(p)                sh_mv.mv_inw_p((p))
-#define inl_p(p)                sh_mv.mv_inl_p((p))
-#define outb_p(x,p)             sh_mv.mv_outb_p((x),(p))
-#define outw_p(x,p)             sh_mv.mv_outw_p((x),(p))
-#define outl_p(x,p)             sh_mv.mv_outl_p((x),(p))
-
-#define insb(p,b,c)             sh_mv.mv_insb((p), (b), (c))
-#define insw(p,b,c)             sh_mv.mv_insw((p), (b), (c))
-#define insl(p,b,c)             sh_mv.mv_insl((p), (b), (c))
-#define outsb(p,b,c)            sh_mv.mv_outsb((p), (b), (c))
-#define outsw(p,b,c)            sh_mv.mv_outsw((p), (b), (c))
-#define outsl(p,b,c)            sh_mv.mv_outsl((p), (b), (c))
-
-#endif
-
 #define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile u8  __force *)(a) = (v))
 #define __raw_writew(v,a)       (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
 #define __raw_writel(v,a)       (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
@@ -74,68 +35,39 @@
 #define __raw_readl(a)          (__chk_io_ptr(a), *(volatile u32 __force *)(a))
 #define __raw_readq(a)          (__chk_io_ptr(a), *(volatile u64 __force *)(a))
 
-#define readb(a)                ({ u8  r_ = __raw_readb(a); mb(); r_; })
-#define readw(a)                ({ u16 r_ = __raw_readw(a); mb(); r_; })
-#define readl(a)                ({ u32 r_ = __raw_readl(a); mb(); r_; })
-#define readq(a)                ({ u64 r_ = __raw_readq(a); mb(); r_; })
-
-#define writeb(v,a)             ({ __raw_writeb((v),(a)); mb(); })
-#define writew(v,a)             ({ __raw_writew((v),(a)); mb(); })
-#define writel(v,a)             ({ __raw_writel((v),(a)); mb(); })
-#define writeq(v,a)             ({ __raw_writeq((v),(a)); mb(); })
-
-/*
- * Legacy SuperH on-chip I/O functions
- *
- * These are all deprecated, all new (and especially cross-platform) code
- * should be using the __raw_xxx() routines directly.
- */
-static inline u8 __deprecated ctrl_inb(unsigned long addr)
-{
-        return __raw_readb(addr);
-}
-
-static inline u16 __deprecated ctrl_inw(unsigned long addr)
-{
-        return __raw_readw(addr);
-}
-
-static inline u32 __deprecated ctrl_inl(unsigned long addr)
-{
-        return __raw_readl(addr);
-}
-
-static inline u64 __deprecated ctrl_inq(unsigned long addr)
-{
-        return __raw_readq(addr);
-}
-
-static inline void __deprecated ctrl_outb(u8 v, unsigned long addr)
-{
-        __raw_writeb(v, addr);
-}
-
-static inline void __deprecated ctrl_outw(u16 v, unsigned long addr)
-{
-        __raw_writew(v, addr);
-}
-
-static inline void __deprecated ctrl_outl(u32 v, unsigned long addr)
-{
-        __raw_writel(v, addr);
-}
-
-static inline void __deprecated ctrl_outq(u64 v, unsigned long addr)
-{
-        __raw_writeq(v, addr);
-}
-
-extern unsigned long generic_io_base;
-
-static inline void ctrl_delay(void)
-{
-        __raw_readw(generic_io_base);
-}
+#define readb_relaxed(c)        ({ u8  __v = __raw_readb(c); __v; })
+#define readw_relaxed(c)        ({ u16 __v = le16_to_cpu((__force __le16) \
+                                        __raw_readw(c)); __v; })
+#define readl_relaxed(c)        ({ u32 __v = le32_to_cpu((__force __le32) \
+                                        __raw_readl(c)); __v; })
+#define readq_relaxed(c)        ({ u64 __v = le64_to_cpu((__force __le64) \
+                                        __raw_readq(c)); __v; })
+
+#define writeb_relaxed(v,c)     ((void)__raw_writeb(v,c))
+#define writew_relaxed(v,c)     ((void)__raw_writew((__force u16) \
+                                        cpu_to_le16(v),c))
+#define writel_relaxed(v,c)     ((void)__raw_writel((__force u32) \
+                                        cpu_to_le32(v),c))
+#define writeq_relaxed(v,c)     ((void)__raw_writeq((__force u64) \
+                                        cpu_to_le64(v),c))
+
+#define readb(a)                ({ u8  r_ = readb_relaxed(a); rmb(); r_; })
+#define readw(a)                ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
+#define readl(a)                ({ u32 r_ = readl_relaxed(a); rmb(); r_; })
+#define readq(a)                ({ u64 r_ = readq_relaxed(a); rmb(); r_; })
+
+#define writeb(v,a)             ({ wmb(); writeb_relaxed((v),(a)); })
+#define writew(v,a)             ({ wmb(); writew_relaxed((v),(a)); })
+#define writel(v,a)             ({ wmb(); writel_relaxed((v),(a)); })
+#define writeq(v,a)             ({ wmb(); writeq_relaxed((v),(a)); })
+
+#define readsb(p,d,l)           __raw_readsb(p,d,l)
+#define readsw(p,d,l)           __raw_readsw(p,d,l)
+#define readsl(p,d,l)           __raw_readsl(p,d,l)
+
+#define writesb(p,d,l)          __raw_writesb(p,d,l)
+#define writesw(p,d,l)          __raw_writesw(p,d,l)
+#define writesl(p,d,l)          __raw_writesl(p,d,l)
 
 #define __BUILD_UNCACHED_IO(bwlq, type)                                 \
 static inline type read##bwlq##_uncached(unsigned long addr)            \
@@ -159,10 +91,11 @@ __BUILD_UNCACHED_IO(w, u16)
 __BUILD_UNCACHED_IO(l, u32)
 __BUILD_UNCACHED_IO(q, u64)
 
-#define __BUILD_MEMORY_STRING(bwlq, type)                               \
+#define __BUILD_MEMORY_STRING(pfx, bwlq, type)                          \
                                                                         \
-static inline void __raw_writes##bwlq(volatile void __iomem *mem,       \
-                                const void *addr, unsigned int count)   \
+static inline void                                                      \
+pfx##writes##bwlq(volatile void __iomem *mem, const void *addr,         \
+                  unsigned int count)                                   \
 {                                                                       \
         const volatile type *__addr = addr;                             \
                                                                         \
@@ -172,8 +105,8 @@ static inline void __raw_writes##bwlq(volatile void __iomem *mem,	\
         }                                                               \
 }                                                                       \
                                                                         \
-static inline void __raw_reads##bwlq(volatile void __iomem *mem,        \
-                               void *addr, unsigned int count)          \
+static inline void pfx##reads##bwlq(volatile void __iomem *mem,         \
+                                    void *addr, unsigned int count)     \
 {                                                                       \
         volatile type *__addr = addr;                                   \
                                                                         \
@@ -183,86 +116,121 @@ static inline void __raw_reads##bwlq(volatile void __iomem *mem,	\
         }                                                               \
 }
 
-__BUILD_MEMORY_STRING(b, u8)
-__BUILD_MEMORY_STRING(w, u16)
+__BUILD_MEMORY_STRING(__raw_, b, u8)
+__BUILD_MEMORY_STRING(__raw_, w, u16)
 
 #ifdef CONFIG_SUPERH32
 void __raw_writesl(void __iomem *addr, const void *data, int longlen);
 void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 #else
-__BUILD_MEMORY_STRING(l, u32)
-#endif
-
-__BUILD_MEMORY_STRING(q, u64)
-
-#define writesb                 __raw_writesb
-#define writesw                 __raw_writesw
-#define writesl                 __raw_writesl
-
-#define readsb                  __raw_readsb
-#define readsw                  __raw_readsw
-#define readsl                  __raw_readsl
-
-#define readb_relaxed(a)        readb(a)
-#define readw_relaxed(a)        readw(a)
-#define readl_relaxed(a)        readl(a)
-#define readq_relaxed(a)        readq(a)
-
-#ifndef CONFIG_GENERIC_IOMAP
-/* Simple MMIO */
-#define ioread8(a)              __raw_readb(a)
-#define ioread16(a)             __raw_readw(a)
-#define ioread16be(a)           be16_to_cpu(__raw_readw((a)))
-#define ioread32(a)             __raw_readl(a)
-#define ioread32be(a)           be32_to_cpu(__raw_readl((a)))
-
-#define iowrite8(v,a)           __raw_writeb((v),(a))
-#define iowrite16(v,a)          __raw_writew((v),(a))
-#define iowrite16be(v,a)        __raw_writew(cpu_to_be16((v)),(a))
-#define iowrite32(v,a)          __raw_writel((v),(a))
-#define iowrite32be(v,a)        __raw_writel(cpu_to_be32((v)),(a))
-
-#define ioread8_rep(a, d, c)    __raw_readsb((a), (d), (c))
-#define ioread16_rep(a, d, c)   __raw_readsw((a), (d), (c))
-#define ioread32_rep(a, d, c)   __raw_readsl((a), (d), (c))
-
-#define iowrite8_rep(a, s, c)   __raw_writesb((a), (s), (c))
-#define iowrite16_rep(a, s, c)  __raw_writesw((a), (s), (c))
-#define iowrite32_rep(a, s, c)  __raw_writesl((a), (s), (c))
+__BUILD_MEMORY_STRING(__raw_, l, u32)
 #endif
 
-#define mmio_insb(p,d,c)        __raw_readsb(p,d,c)
-#define mmio_insw(p,d,c)        __raw_readsw(p,d,c)
-#define mmio_insl(p,d,c)        __raw_readsl(p,d,c)
-
-#define mmio_outsb(p,s,c)       __raw_writesb(p,s,c)
-#define mmio_outsw(p,s,c)       __raw_writesw(p,s,c)
-#define mmio_outsl(p,s,c)       __raw_writesl(p,s,c)
-
-/* synco on SH-4A, otherwise a nop */
-#define mmiowb()                wmb()
-
-#define IO_SPACE_LIMIT 0xffffffff
+__BUILD_MEMORY_STRING(__raw_, q, u64)
 
 #ifdef CONFIG_HAS_IOPORT
 
 /*
- * This function provides a method for the generic case where a
- * board-specific ioport_map simply needs to return the port + some
- * arbitrary port base.
- *
- * We use this at board setup time to implicitly set the port base, and
- * as a result, we can use the generic ioport_map.
+ * Slowdown I/O port space accesses for antique hardware.
+ */
+#undef CONF_SLOWDOWN_IO
+
+/*
+ * On SuperH I/O ports are memory mapped, so we access them using normal
+ * load/store instructions. sh_io_port_base is the virtual address to
+ * which all ports are being mapped.
  */
+extern const unsigned long sh_io_port_base;
+
 static inline void __set_io_port_base(unsigned long pbase)
 {
-        generic_io_base = pbase;
+        *(unsigned long *)&sh_io_port_base = pbase;
+        barrier();
+}
+
+#ifdef CONFIG_GENERIC_IOMAP
+#define __ioport_map ioport_map
+#else
+extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
+#endif
+
+#ifdef CONF_SLOWDOWN_IO
+#define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
+#else
+#define SLOW_DOWN_IO
+#endif
+
+#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)                 \
+                                                                        \
+static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
+{                                                                       \
+        volatile type *__addr;                                          \
+                                                                        \
+        __addr = __ioport_map(port, sizeof(type));                      \
+        *__addr = val;                                                  \
+        slow;                                                           \
+}                                                                       \
+                                                                        \
+static inline type pfx##in##bwlq##p(unsigned long port)                 \
+{                                                                       \
+        volatile type *__addr;                                          \
+        type __val;                                                     \
+                                                                        \
+        __addr = __ioport_map(port, sizeof(type));                      \
+        __val = *__addr;                                                \
+        slow;                                                           \
+                                                                        \
+        return __val;                                                   \
+}
+
+#define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
+        __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                       \
+        __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
+
+#define BUILDIO_IOPORT(bwlq, type)                                      \
+        __BUILD_IOPORT_PFX(, bwlq, type)
+
+BUILDIO_IOPORT(b, u8)
+BUILDIO_IOPORT(w, u16)
+BUILDIO_IOPORT(l, u32)
+BUILDIO_IOPORT(q, u64)
+
+#define __BUILD_IOPORT_STRING(bwlq, type)                               \
+                                                                        \
+static inline void outs##bwlq(unsigned long port, const void *addr,     \
+                              unsigned int count)                       \
+{                                                                       \
+        const volatile type *__addr = addr;                             \
+                                                                        \
+        while (count--) {                                               \
+                out##bwlq(*__addr, port);                               \
+                __addr++;                                               \
+        }                                                               \
+}                                                                       \
+                                                                        \
+static inline void ins##bwlq(unsigned long port, void *addr,            \
+                             unsigned int count)                        \
+{                                                                       \
+        volatile type *__addr = addr;                                   \
+                                                                        \
+        while (count--) {                                               \
+                *__addr = in##bwlq(port);                               \
+                __addr++;                                               \
+        }                                                               \
 }
 
-#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
+__BUILD_IOPORT_STRING(b, u8)
+__BUILD_IOPORT_STRING(w, u16)
+__BUILD_IOPORT_STRING(l, u32)
+__BUILD_IOPORT_STRING(q, u64)
 
 #endif
 
+#define IO_SPACE_LIMIT 0xffffffff
+
+/* synco on SH-4A, otherwise a nop */
+#define mmiowb()                wmb()
+
 /* We really want to try and get these to memcpy etc */
 void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
 void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
@@ -322,7 +290,15 @@ __ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot)
          * mapping must be done by the PMB or by using page tables.
          */
         if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
-                if (unlikely(pgprot_val(prot) & _PAGE_CACHABLE))
+                u64 flags = pgprot_val(prot);
+
+                /*
+                 * Anything using the legacy PTEA space attributes needs
+                 * to be kicked down to page table mappings.
+                 */
+                if (unlikely(flags & _PAGE_PCC_MASK))
+                        return NULL;
+                if (unlikely(flags & _PAGE_CACHABLE))
                         return (void __iomem *)P1SEGADDR(offset);
 
                 return (void __iomem *)P2SEGADDR(offset);
@@ -395,10 +371,6 @@ static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
 #define ioremap_nocache ioremap
 #define iounmap         __iounmap
 
-#define maybebadio(port) \
-        printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
-               __func__, __LINE__, (port), (u32)__builtin_return_address(0))
-
 /*
  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
  * access
diff --git a/arch/sh/include/asm/io_generic.h b/arch/sh/include/asm/io_generic.h
index 491df93cbf8e..b5f6956f19c8 100644
--- a/arch/sh/include/asm/io_generic.h
+++ b/arch/sh/include/asm/io_generic.h
@@ -11,31 +11,6 @@
 #error "Don't include this header without a valid system prefix"
 #endif
 
-u8 IO_CONCAT(__IO_PREFIX,inb)(unsigned long);
-u16 IO_CONCAT(__IO_PREFIX,inw)(unsigned long);
-u32 IO_CONCAT(__IO_PREFIX,inl)(unsigned long);
-
-void IO_CONCAT(__IO_PREFIX,outb)(u8, unsigned long);
-void IO_CONCAT(__IO_PREFIX,outw)(u16, unsigned long);
-void IO_CONCAT(__IO_PREFIX,outl)(u32, unsigned long);
-
-u8 IO_CONCAT(__IO_PREFIX,inb_p)(unsigned long);
-u16 IO_CONCAT(__IO_PREFIX,inw_p)(unsigned long);
-u32 IO_CONCAT(__IO_PREFIX,inl_p)(unsigned long);
-void IO_CONCAT(__IO_PREFIX,outb_p)(u8, unsigned long);
-void IO_CONCAT(__IO_PREFIX,outw_p)(u16, unsigned long);
-void IO_CONCAT(__IO_PREFIX,outl_p)(u32, unsigned long);
-
-void IO_CONCAT(__IO_PREFIX,insb)(unsigned long, void *dst, unsigned long count);
-void IO_CONCAT(__IO_PREFIX,insw)(unsigned long, void *dst, unsigned long count);
-void IO_CONCAT(__IO_PREFIX,insl)(unsigned long, void *dst, unsigned long count);
-void IO_CONCAT(__IO_PREFIX,outsb)(unsigned long, const void *src, unsigned long count);
-void IO_CONCAT(__IO_PREFIX,outsw)(unsigned long, const void *src, unsigned long count);
-void IO_CONCAT(__IO_PREFIX,outsl)(unsigned long, const void *src, unsigned long count);
-
-void *IO_CONCAT(__IO_PREFIX,ioremap)(unsigned long offset, unsigned long size);
-void IO_CONCAT(__IO_PREFIX,iounmap)(void *addr);
-
 void __iomem *IO_CONCAT(__IO_PREFIX,ioport_map)(unsigned long addr, unsigned int size);
 void IO_CONCAT(__IO_PREFIX,ioport_unmap)(void __iomem *addr);
 void IO_CONCAT(__IO_PREFIX,mem_init)(void);
diff --git a/arch/sh/include/asm/ioctls.h b/arch/sh/include/asm/ioctls.h
index eb6c4c687972..a6769f352bf6 100644
--- a/arch/sh/include/asm/ioctls.h
+++ b/arch/sh/include/asm/ioctls.h
@@ -85,7 +85,9 @@
 #define TCSETSF2        _IOW('T', 45, struct termios2)
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+#define TIOCGDEV        _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */
 #define TIOCSIG         _IOW('T',0x36, int)  /* Generate signal on Pty slave */
+#define TIOCVHANGUP     _IO('T', 0x37)
 
 #define TIOCSERCONFIG   _IO('T', 83) /* 0x5453 */
 #define TIOCSERGWILD    _IOR('T', 84,  int) /* 0x5454 */
diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h
index 02c2f0102cfa..45d08b6a5ef7 100644
--- a/arch/sh/include/asm/irq.h
+++ b/arch/sh/include/asm/irq.h
@@ -9,7 +9,7 @@
  * advised to cap this at the hard limit that they're interested in
  * through the machvec.
  */
-#define NR_IRQS                 256
+#define NR_IRQS                 512
 #define NR_IRQS_LEGACY          8       /* Legacy external IRQ0-7 */
 
 /*
diff --git a/arch/sh/include/asm/irqflags.h b/arch/sh/include/asm/irqflags.h
index a741153b41c2..43b7608606c3 100644
--- a/arch/sh/include/asm/irqflags.h
+++ b/arch/sh/include/asm/irqflags.h
@@ -1,8 +1,8 @@
 #ifndef __ASM_SH_IRQFLAGS_H
 #define __ASM_SH_IRQFLAGS_H
 
-#define RAW_IRQ_DISABLED        0xf0
-#define RAW_IRQ_ENABLED         0x00
+#define ARCH_IRQ_DISABLED       0xf0
+#define ARCH_IRQ_ENABLED        0x00
 
 #include <asm-generic/irqflags.h>
 
diff --git a/arch/sh/include/asm/kgdb.h b/arch/sh/include/asm/kgdb.h
index 4235e228d921..f3613952d1ae 100644
--- a/arch/sh/include/asm/kgdb.h
+++ b/arch/sh/include/asm/kgdb.h
@@ -34,5 +34,6 @@ static inline void arch_kgdb_breakpoint(void)
 
 #define CACHE_FLUSH_IS_SAFE     1
 #define BREAK_INSTR_SIZE        2
+#define GDB_ADJUSTS_BREAK_OFFSET
 
 #endif /* __ASM_SH_KGDB_H */
diff --git a/arch/sh/include/asm/kprobes.h b/arch/sh/include/asm/kprobes.h
index 036c3311233c..134f3980e44a 100644
--- a/arch/sh/include/asm/kprobes.h
+++ b/arch/sh/include/asm/kprobes.h
@@ -16,7 +16,6 @@ typedef insn_size_t kprobe_opcode_t;
         ? (MAX_STACK_SIZE) \
         : (((unsigned long)current_thread_info()) + THREAD_SIZE - (ADDR)))
 
-#define regs_return_value(_regs)                ((_regs)->regs[0])
 #define flush_insn_slot(p)              do { } while (0)
 #define kretprobe_blacklist_size        0
 
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
index a0b0cf79cf8a..57c5c3d0f39f 100644
--- a/arch/sh/include/asm/machvec.h
+++ b/arch/sh/include/asm/machvec.h
@@ -23,27 +23,6 @@ struct sh_machine_vector {
         void (*mv_init_irq)(void);
 
 #ifdef CONFIG_HAS_IOPORT
-        u8 (*mv_inb)(unsigned long);
-        u16 (*mv_inw)(unsigned long);
-        u32 (*mv_inl)(unsigned long);
-        void (*mv_outb)(u8, unsigned long);
-        void (*mv_outw)(u16, unsigned long);
-        void (*mv_outl)(u32, unsigned long);
-
-        u8 (*mv_inb_p)(unsigned long);
-        u16 (*mv_inw_p)(unsigned long);
-        u32 (*mv_inl_p)(unsigned long);
-        void (*mv_outb_p)(u8, unsigned long);
-        void (*mv_outw_p)(u16, unsigned long);
-        void (*mv_outl_p)(u32, unsigned long);
-
-        void (*mv_insb)(unsigned long, void *dst, unsigned long count);
-        void (*mv_insw)(unsigned long, void *dst, unsigned long count);
-        void (*mv_insl)(unsigned long, void *dst, unsigned long count);
-        void (*mv_outsb)(unsigned long, const void *src, unsigned long count);
-        void (*mv_outsw)(unsigned long, const void *src, unsigned long count);
-        void (*mv_outsl)(unsigned long, const void *src, unsigned long count);
-
         void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
         void (*mv_ioport_unmap)(void __iomem *);
 #endif
@@ -52,6 +31,7 @@ struct sh_machine_vector {
         int (*mv_mode_pins)(void);
 
         void (*mv_mem_init)(void);
+        void (*mv_mem_reserve)(void);
 };
 
 extern struct sh_machine_vector sh_mv;
diff --git a/arch/sh/include/asm/memblock.h b/arch/sh/include/asm/memblock.h
index dfe683b88075..e87063fad2ea 100644
--- a/arch/sh/include/asm/memblock.h
+++ b/arch/sh/include/asm/memblock.h
@@ -1,6 +1,4 @@
 #ifndef __ASM_SH_MEMBLOCK_H
 #define __ASM_SH_MEMBLOCK_H
 
-#define MEMBLOCK_REAL_LIMIT     0
-
 #endif /* __ASM_SH_MEMBLOCK_H */
diff --git a/arch/sh/include/asm/mmzone.h b/arch/sh/include/asm/mmzone.h
index 8887baff5eff..15a8496960e6 100644
--- a/arch/sh/include/asm/mmzone.h
+++ b/arch/sh/include/asm/mmzone.h
@@ -9,10 +9,6 @@
 extern struct pglist_data *node_data[];
 #define NODE_DATA(nid)          (node_data[nid])
 
-#define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
-#define node_end_pfn(nid)       (NODE_DATA(nid)->node_start_pfn + \
-                                 NODE_DATA(nid)->node_spanned_pages)
-
 static inline int pfn_to_nid(unsigned long pfn)
 {
         int nid;
diff --git a/arch/sh/include/asm/page.h b/arch/sh/include/asm/page.h
index c4e0b3d472b9..822d6084195b 100644
--- a/arch/sh/include/asm/page.h
+++ b/arch/sh/include/asm/page.h
@@ -186,7 +186,7 @@ typedef struct page *pgtable_t;
 /*
  * While BYTES_PER_WORD == 4 on the current sh64 ABI, GCC will still
  * happily generate {ld/st}.q pairs, requiring us to have 8-byte
- * alignment to avoid traps. The kmalloc alignment is gauranteed by
+ * alignment to avoid traps. The kmalloc alignment is guaranteed by
  * virtue of L1_CACHE_BYTES, requiring this to only be special cased
  * for slab caches.
  */
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index 8bd952fcf3ba..f0efe97f1750 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -37,6 +37,8 @@ struct pci_channel {
 };
 
 /* arch/sh/drivers/pci/pci.c */
+extern raw_spinlock_t pci_config_lock;
+
 extern int register_pci_controller(struct pci_channel *hose);
 extern void pcibios_report_status(unsigned int status_mask, int warn);
 
diff --git a/arch/sh/include/asm/perf_event.h b/arch/sh/include/asm/perf_event.h
index 3d0c9f36d150..14308bed7ea5 100644
--- a/arch/sh/include/asm/perf_event.h
+++ b/arch/sh/include/asm/perf_event.h
@@ -26,11 +26,4 @@ extern int register_sh_pmu(struct sh_pmu *);
 extern int reserve_pmc_hardware(void);
 extern void release_pmc_hardware(void);
 
-static inline void set_perf_event_pending(void)
-{
-        /* Nothing to see here, move along. */
-}
-
-#define PERF_EVENT_INDEX_OFFSET 0
-
 #endif /* __ASM_SH_PERF_EVENT_H */
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index 02f77450cd8f..9210e93a92c3 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -18,6 +18,7 @@
 #include <asm/pgtable-2level.h>
 #endif
 #include <asm/page.h>
+#include <asm/mmu.h>
 
 #ifndef __ASSEMBLY__
 #include <asm/addrspace.h>
@@ -66,7 +67,6 @@ static inline unsigned long long neff_sign_extend(unsigned long val)
 #define PHYS_ADDR_MASK29                0x1fffffff
 #define PHYS_ADDR_MASK32                0xffffffff
 
-#ifdef CONFIG_PMB
 static inline unsigned long phys_addr_mask(void)
 {
         /* Is the MMU in 29bit mode? */
@@ -75,17 +75,6 @@ static inline unsigned long phys_addr_mask(void)
 
         return PHYS_ADDR_MASK32;
 }
-#elif defined(CONFIG_32BIT)
-static inline unsigned long phys_addr_mask(void)
-{
-        return PHYS_ADDR_MASK32;
-}
-#else
-static inline unsigned long phys_addr_mask(void)
-{
-        return PHYS_ADDR_MASK29;
-}
-#endif
 
 #define PTE_PHYS_MASK           (phys_addr_mask() & PAGE_MASK)
 #define PTE_FLAGS_MASK          (~(PTE_PHYS_MASK) << PAGE_SHIFT)
@@ -146,6 +135,7 @@ typedef pte_t *pte_addr_t;
 extern void pgtable_cache_init(void);
 
 struct vm_area_struct;
+struct mm_struct;
 
 extern void __update_cache(struct vm_area_struct *vma,
                            unsigned long address, pte_t pte);
@@ -169,6 +159,8 @@ extern void page_table_range_init(unsigned long start, unsigned long end,
 #define HAVE_ARCH_UNMAPPED_AREA
 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 
+#define __HAVE_ARCH_PTE_SPECIAL
+
 #include <asm-generic/pgtable.h>
 
 #endif /* __ASM_SH_PGTABLE_H */
diff --git a/arch/sh/include/asm/pgtable_32.h b/arch/sh/include/asm/pgtable_32.h
index e172d696e52b..0bce3d81569e 100644
--- a/arch/sh/include/asm/pgtable_32.h
+++ b/arch/sh/include/asm/pgtable_32.h
@@ -76,6 +76,10 @@
 /* Wrapper for extended mode pgprot twiddling */
 #define _PAGE_EXT(x)            ((unsigned long long)(x) << 32)
 
+#ifdef CONFIG_X2TLB
+#define _PAGE_PCC_MASK  0x00000000      /* No legacy PTEA support */
+#else
+
 /* software: moves to PTEA.TC (Timing Control) */
 #define _PAGE_PCC_AREA5 0x00000000      /* use BSC registers for area5 */
 #define _PAGE_PCC_AREA6 0x80000000      /* use BSC registers for area6 */
@@ -89,7 +93,8 @@
 #define _PAGE_PCC_ATR8  0x60000000      /* Attribute Memory space, 8 bit bus */
 #define _PAGE_PCC_ATR16 0x60000001      /* Attribute Memory space, 6 bit bus */
 
-#ifndef CONFIG_X2TLB
+#define _PAGE_PCC_MASK  0xe0000001
+
 /* copy the ptea attributes */
 static inline unsigned long copy_ptea_attributes(unsigned long x)
 {
@@ -162,7 +167,7 @@ static inline unsigned long copy_ptea_attributes(unsigned long x)
 #endif
 
 /*
- * Mask of bits that are to be preserved accross pgprot changes.
+ * Mask of bits that are to be preserved across pgprot changes.
  */
 #define _PAGE_CHG_MASK \
         (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | \
@@ -231,13 +236,7 @@ static inline unsigned long copy_ptea_attributes(unsigned long x)
                                            _PAGE_EXT_KERN_EXEC))
 
 #define PAGE_KERNEL_PCC(slot, type) \
-                        __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
-                                 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
-                                 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
-                                           _PAGE_EXT_KERN_WRITE | \
-                                           _PAGE_EXT_KERN_EXEC) \
-                                 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
-                                 (type))
+                        __pgprot(0)
 
 #elif defined(CONFIG_MMU) /* SH-X TLB */
 #define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
@@ -378,8 +377,6 @@ PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
 PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
 PTE_BIT_FUNC(low, mkspecial, |= _PAGE_SPECIAL);
 
-#define __HAVE_ARCH_PTE_SPECIAL
-
 /*
  * Macro and implementation to make a page protection as uncachable.
  */
@@ -429,10 +426,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 #define pte_offset_kernel(dir, address) \
         ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
 #define pte_offset_map(dir, address)            pte_offset_kernel(dir, address)
-#define pte_offset_map_nested(dir, address)     pte_offset_kernel(dir, address)
-
 #define pte_unmap(pte)          do { } while (0)
-#define pte_unmap_nested(pte)   do { } while (0)
 
 #ifdef CONFIG_X2TLB
 #define pte_ERROR(e) \
diff --git a/arch/sh/include/asm/pgtable_64.h b/arch/sh/include/asm/pgtable_64.h
index 0ee46776dad6..42cb9dd52161 100644
--- a/arch/sh/include/asm/pgtable_64.h
+++ b/arch/sh/include/asm/pgtable_64.h
@@ -84,9 +84,7 @@ static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
                 ((pte_t *) ((pmd_val(*(dir))) & PAGE_MASK) + pte_index((addr)))
 
 #define pte_offset_map(dir,addr)        pte_offset_kernel(dir, addr)
-#define pte_offset_map_nested(dir,addr) pte_offset_kernel(dir, addr)
 #define pte_unmap(pte)          do { } while (0)
-#define pte_unmap_nested(pte)   do { } while (0)
 
 #ifndef __ASSEMBLY__
 #define IOBASE_VADDR    0xff000000
@@ -132,6 +130,7 @@ static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
  * anything above the PPN field.
  */
 #define _PAGE_WIRED     _PAGE_EXT(0x001) /* software: wire the tlb entry */
+#define _PAGE_SPECIAL   _PAGE_EXT(0x002)
 
 #define _PAGE_CLEAR_FLAGS       (_PAGE_PRESENT | _PAGE_FILE | _PAGE_SHARED | \
                                  _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_WIRED)
@@ -175,7 +174,8 @@ static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
 /* Default flags for a User page */
 #define _PAGE_TABLE     (_KERNPG_TABLE | _PAGE_USER)
 
-#define _PAGE_CHG_MASK  (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
+#define _PAGE_CHG_MASK  (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
+                         _PAGE_SPECIAL)
 
 /*
  * We have full permissions (Read/Write/Execute/Shared).
@@ -265,7 +265,7 @@ static inline int pte_dirty(pte_t pte)  { return pte_val(pte) & _PAGE_DIRTY; }
 static inline int pte_young(pte_t pte)  { return pte_val(pte) & _PAGE_ACCESSED; }
 static inline int pte_file(pte_t pte)   { return pte_val(pte) & _PAGE_FILE; }
 static inline int pte_write(pte_t pte)  { return pte_val(pte) & _PAGE_WRITE; }
-static inline int pte_special(pte_t pte){ return 0; }
+static inline int pte_special(pte_t pte){ return pte_val(pte) & _PAGE_SPECIAL; }
 
 static inline pte_t pte_wrprotect(pte_t pte)    { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_WRITE)); return pte; }
 static inline pte_t pte_mkclean(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; }
@@ -274,8 +274,7 @@ static inline pte_t pte_mkwrite(pte_t pte)	{ set_pte(&pte, __pte(pte_val(pte) |
 static inline pte_t pte_mkdirty(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; }
 static inline pte_t pte_mkyoung(pte_t pte)      { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; }
 static inline pte_t pte_mkhuge(pte_t pte)       { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SZHUGE)); return pte; }
-static inline pte_t pte_mkspecial(pte_t pte)    { return pte; }
-
+static inline pte_t pte_mkspecial(pte_t pte)    { set_pte(&pte, __pte(pte_val(pte) | _PAGE_SPECIAL)); return pte; }
 
 /*
  * Conversion functions: convert a page and protection to a page entry.
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 0a58cb25a658..9c7bdfcaebbd 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -35,7 +35,7 @@ enum cpu_type {
         CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3,
 
         /* SH4AL-DSP types */
-        CPU_SH7343, CPU_SH7722, CPU_SH7366,
+        CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372,
 
         /* SH-5 types */
         CPU_SH5_101, CPU_SH5_103,
@@ -89,6 +89,7 @@ struct sh_cpuinfo {
         struct task_struct *idle;
 #endif
 
+        unsigned int phys_bits;
         unsigned long flags;
 } __attribute__ ((aligned(L1_CACHE_BYTES)));
 
diff --git a/arch/sh/include/asm/processor_32.h b/arch/sh/include/asm/processor_32.h
index 61a445d2d02a..900f8d72ffe2 100644
--- a/arch/sh/include/asm/processor_32.h
+++ b/arch/sh/include/asm/processor_32.h
@@ -13,7 +13,6 @@
 #include <linux/linkage.h>
 #include <asm/page.h>
 #include <asm/types.h>
-#include <asm/ptrace.h>
 #include <asm/hw_breakpoint.h>
 
 /*
@@ -194,18 +193,21 @@ extern unsigned long get_wchan(struct task_struct *p);
 #define KSTK_EIP(tsk)  (task_pt_regs(tsk)->pc)
 #define KSTK_ESP(tsk)  (task_pt_regs(tsk)->regs[15])
 
-#define user_stack_pointer(_regs)       ((_regs)->regs[15])
-
 #if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
+
 #define PREFETCH_STRIDE         L1_CACHE_BYTES
 #define ARCH_HAS_PREFETCH
 #define ARCH_HAS_PREFETCHW
-static inline void prefetch(void *x)
+
+static inline void prefetch(const void *x)
 {
-        __asm__ __volatile__ ("pref @%0\n\t" : : "r" (x) : "memory");
+        __builtin_prefetch(x, 0, 3);
 }
 
-#define prefetchw(x)    prefetch(x)
+static inline void prefetchw(const void *x)
+{
+        __builtin_prefetch(x, 1, 3);
+}
 #endif
 
 #endif /* __KERNEL__ */
diff --git a/arch/sh/include/asm/processor_64.h b/arch/sh/include/asm/processor_64.h
index 621bc4618c6b..e25c4c7d6b63 100644
--- a/arch/sh/include/asm/processor_64.h
+++ b/arch/sh/include/asm/processor_64.h
@@ -17,7 +17,6 @@
 #include <linux/compiler.h>
 #include <asm/page.h>
 #include <asm/types.h>
-#include <asm/ptrace.h>
 #include <cpu/registers.h>
 
 /*
@@ -151,7 +150,6 @@ struct thread_struct {
 #define SR_USER (SR_MMU | SR_FD)
 
 #define start_thread(_regs, new_pc, new_sp)                     \
-        set_fs(USER_DS);                                        \
         _regs->sr = SR_USER;    /* User mode. */                \
         _regs->pc = new_pc - 4; /* Compensate syscall exit */   \
         _regs->pc |= 1;         /* Set SHmedia ! */             \
@@ -231,7 +229,5 @@ extern unsigned long get_wchan(struct task_struct *p);
 #define KSTK_EIP(tsk)  ((tsk)->thread.pc)
 #define KSTK_ESP(tsk)  ((tsk)->thread.sp)
 
-#define user_stack_pointer(_regs)       ((_regs)->regs[15])
-
 #endif  /* __ASSEMBLY__ */
 #endif /* __ASM_SH_PROCESSOR_64_H */
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index 2168fde25611..88bd6be168a9 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -3,90 +3,7 @@
 
 /*
  * Copyright (C) 1999, 2000  Niibe Yutaka
- *
- */
-#if defined(__SH5__)
-struct pt_regs {
-        unsigned long long pc;
-        unsigned long long sr;
-        long long syscall_nr;
-        unsigned long long regs[63];
-        unsigned long long tregs[8];
-        unsigned long long pad[2];
-};
-#else
-/*
- * GCC defines register number like this:
- * -----------------------------
- *       0 - 15 are integer registers
- *      17 - 22 are control/special registers
- *      24 - 39 fp registers
- *      40 - 47 xd registers
- *      48 -    fpscr register
- * -----------------------------
- *
- * We follows above, except:
- *      16 --- program counter (PC)
- *      22 --- syscall #
- *      23 --- floating point communication register
- */
-#define REG_REG0         0
-#define REG_REG15       15
-
-#define REG_PC          16
-
-#define REG_PR          17
-#define REG_SR          18
-#define REG_GBR         19
-#define REG_MACH        20
-#define REG_MACL        21
-
-#define REG_SYSCALL     22
-
-#define REG_FPREG0      23
-#define REG_FPREG15     38
-#define REG_XFREG0      39
-#define REG_XFREG15     54
-
-#define REG_FPSCR       55
-#define REG_FPUL        56
-
-/*
- * This struct defines the way the registers are stored on the
- * kernel stack during a system call or other kernel entry.
- */
-struct pt_regs {
-        unsigned long regs[16];
-        unsigned long pc;
-        unsigned long pr;
-        unsigned long sr;
-        unsigned long gbr;
-        unsigned long mach;
-        unsigned long macl;
-        long tra;
-};
-
-/*
- * This struct defines the way the DSP registers are stored on the
- * kernel stack during a system call or other kernel entry.
  */
-struct pt_dspregs {
-        unsigned long   a1;
-        unsigned long   a0g;
-        unsigned long   a1g;
-        unsigned long   m0;
-        unsigned long   m1;
-        unsigned long   a0;
-        unsigned long   x0;
-        unsigned long   x1;
-        unsigned long   y0;
-        unsigned long   y1;
-        unsigned long   dsr;
-        unsigned long   rs;
-        unsigned long   re;
-        unsigned long   mod;
-};
-#endif
 
 #define PTRACE_GETREGS          12      /* General registers */
 #define PTRACE_SETREGS          13
@@ -107,22 +24,103 @@ struct pt_dspregs {
 #define PT_DATA_ADDR            248     /* &(struct user)->start_data */
 #define PT_TEXT_LEN             252
 
+#if defined(__SH5__) || defined(CONFIG_CPU_SH5)
+#include "ptrace_64.h"
+#else
+#include "ptrace_32.h"
+#endif
+
 #ifdef __KERNEL__
+
+#include <linux/stringify.h>
+#include <linux/stddef.h>
+#include <linux/thread_info.h>
 #include <asm/addrspace.h>
 #include <asm/page.h>
 #include <asm/system.h>
 
 #define user_mode(regs)                 (((regs)->sr & 0x40000000)==0)
-#define instruction_pointer(regs)       ((unsigned long)(regs)->pc)
+#define kernel_stack_pointer(_regs)     ((unsigned long)(_regs)->regs[15])
+
+#define GET_FP(regs)    ((regs)->regs[14])
+#define GET_USP(regs)   ((regs)->regs[15])
 
 extern void show_regs(struct pt_regs *);
 
+#define arch_has_single_step()  (1)
+
 /*
- * These are defined as per linux/ptrace.h.
+ * kprobe-based event tracer support
  */
-struct task_struct;
+struct pt_regs_offset {
+        const char *name;
+        int offset;
+};
 
-#define arch_has_single_step()  (1)
+#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
+#define REGS_OFFSET_NAME(num)   \
+        {.name = __stringify(r##num), .offset = offsetof(struct pt_regs, regs[num])}
+#define TREGS_OFFSET_NAME(num)  \
+        {.name = __stringify(tr##num), .offset = offsetof(struct pt_regs, tregs[num])}
+#define REG_OFFSET_END {.name = NULL, .offset = 0}
+
+/* Query offset/name of register from its name/offset */
+extern int regs_query_register_offset(const char *name);
+extern const char *regs_query_register_name(unsigned int offset);
+
+extern const struct pt_regs_offset regoffset_table[];
+
+/**
+ * regs_get_register() - get register value from its offset
+ * @regs:       pt_regs from which register value is gotten.
+ * @offset:     offset number of the register.
+ *
+ * regs_get_register returns the value of a register. The @offset is the
+ * offset of the register in struct pt_regs address which specified by @regs.
+ * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
+ */
+static inline unsigned long regs_get_register(struct pt_regs *regs,
+                                              unsigned int offset)
+{
+        if (unlikely(offset > MAX_REG_OFFSET))
+                return 0;
+        return *(unsigned long *)((unsigned long)regs + offset);
+}
+
+/**
+ * regs_within_kernel_stack() - check the address in the stack
+ * @regs:       pt_regs which contains kernel stack pointer.
+ * @addr:       address which is checked.
+ *
+ * regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
+ * If @addr is within the kernel stack, it returns true. If not, returns false.
+ */
+static inline int regs_within_kernel_stack(struct pt_regs *regs,
+                                           unsigned long addr)
+{
+        return ((addr & ~(THREAD_SIZE - 1))  ==
+                (kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
+}
+
+/**
+ * regs_get_kernel_stack_nth() - get Nth entry of the stack
+ * @regs:       pt_regs which contains kernel stack pointer.
+ * @n:          stack entry number.
+ *
+ * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
+ * is specified by @regs. If the @n th entry is NOT in the kernel stack,
+ * this returns 0.
+ */
+static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
+                                                      unsigned int n)
+{
+        unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
+        addr += n;
+        if (regs_within_kernel_stack(regs, (unsigned long)addr))
+                return *addr;
+        else
+                return 0;
+}
 
 struct perf_event;
 struct perf_sample_data;
@@ -135,13 +133,16 @@ extern void ptrace_triggered(struct perf_event *bp, int nmi,
 
 static inline unsigned long profile_pc(struct pt_regs *regs)
 {
-        unsigned long pc = instruction_pointer(regs);
+        unsigned long pc = regs->pc;
 
         if (virt_addr_uncached(pc))
                 return CAC_ADDR(pc);
 
         return pc;
 }
+#define profile_pc profile_pc
+
+#include <asm-generic/ptrace.h>
 #endif /* __KERNEL__ */
 
 #endif /* __ASM_SH_PTRACE_H */
diff --git a/arch/sh/include/asm/ptrace_32.h b/arch/sh/include/asm/ptrace_32.h
new file mode 100644
index 000000000000..6c2239cca1a2
--- /dev/null
+++ b/arch/sh/include/asm/ptrace_32.h
@@ -0,0 +1,83 @@
+#ifndef __ASM_SH_PTRACE_32_H
+#define __ASM_SH_PTRACE_32_H
+
+/*
+ * GCC defines register number like this:
+ * -----------------------------
+ *       0 - 15 are integer registers
+ *      17 - 22 are control/special registers
+ *      24 - 39 fp registers
+ *      40 - 47 xd registers
+ *      48 -    fpscr register
+ * -----------------------------
+ *
+ * We follows above, except:
+ *      16 --- program counter (PC)
+ *      22 --- syscall #
+ *      23 --- floating point communication register
+ */
+#define REG_REG0         0
+#define REG_REG15       15
+
+#define REG_PC          16
+
+#define REG_PR          17
+#define REG_SR          18
+#define REG_GBR         19
+#define REG_MACH        20
+#define REG_MACL        21
+
+#define REG_SYSCALL     22
+
+#define REG_FPREG0      23
+#define REG_FPREG15     38
+#define REG_XFREG0      39
+#define REG_XFREG15     54
+
+#define REG_FPSCR       55
+#define REG_FPUL        56
+
+/*
+ * This struct defines the way the registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_regs {
+        unsigned long regs[16];
+        unsigned long pc;
+        unsigned long pr;
+        unsigned long sr;
+        unsigned long gbr;
+        unsigned long mach;
+        unsigned long macl;
+        long tra;
+};
+
+/*
+ * This struct defines the way the DSP registers are stored on the
+ * kernel stack during a system call or other kernel entry.
+ */
+struct pt_dspregs {
+        unsigned long   a1;
+        unsigned long   a0g;
+        unsigned long   a1g;
+        unsigned long   m0;
+        unsigned long   m1;
+        unsigned long   a0;
+        unsigned long   x0;
+        unsigned long   x1;
+        unsigned long   y0;
+        unsigned long   y1;
+        unsigned long   dsr;
+        unsigned long   rs;
+        unsigned long   re;
+        unsigned long   mod;
+};
+
+#ifdef __KERNEL__
+
+#define MAX_REG_OFFSET          offsetof(struct pt_regs, tra)
+#define regs_return_value(_regs)        ((_regs)->regs[0])
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_PTRACE_32_H */
diff --git a/arch/sh/include/asm/ptrace_64.h b/arch/sh/include/asm/ptrace_64.h
new file mode 100644
index 000000000000..bf9be7764d69
--- /dev/null
+++ b/arch/sh/include/asm/ptrace_64.h
@@ -0,0 +1,20 @@
+#ifndef __ASM_SH_PTRACE_64_H
+#define __ASM_SH_PTRACE_64_H
+
+struct pt_regs {
+        unsigned long long pc;
+        unsigned long long sr;
+        long long syscall_nr;
+        unsigned long long regs[63];
+        unsigned long long tregs[8];
+        unsigned long long pad[2];
+};
+
+#ifdef __KERNEL__
+
+#define MAX_REG_OFFSET          offsetof(struct pt_regs, tregs[7])
+#define regs_return_value(_regs)        ((_regs)->regs[3])
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASM_SH_PTRACE_64_H */
diff --git a/arch/sh/include/asm/rwsem.h b/arch/sh/include/asm/rwsem.h
index 06e2251a5e48..edab57265293 100644
--- a/arch/sh/include/asm/rwsem.h
+++ b/arch/sh/include/asm/rwsem.h
@@ -11,64 +11,13 @@
 #endif
 
 #ifdef __KERNEL__
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <asm/atomic.h>
-#include <asm/system.h>
 
-/*
- * the semaphore definition
- */
-struct rw_semaphore {
-        long            count;
 #define RWSEM_UNLOCKED_VALUE            0x00000000
 #define RWSEM_ACTIVE_BIAS               0x00000001
 #define RWSEM_ACTIVE_MASK               0x0000ffff
 #define RWSEM_WAITING_BIAS              (-0x00010000)
 #define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
 #define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
-        spinlock_t              wait_lock;
-        struct list_head        wait_list;
-#ifdef CONFIG_DEBUG_LOCK_ALLOC
-        struct lockdep_map      dep_map;
-#endif
-};
-
-#ifdef CONFIG_DEBUG_LOCK_ALLOC
-# define __RWSEM_DEP_MAP_INIT(lockname) , .dep_map = { .name = #lockname }
-#else
-# define __RWSEM_DEP_MAP_INIT(lockname)
-#endif
-
-#define __RWSEM_INITIALIZER(name) \
-        { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \
-          LIST_HEAD_INIT((name).wait_list) \
-          __RWSEM_DEP_MAP_INIT(name) }
-
-#define DECLARE_RWSEM(name)             \
-        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
-
-extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
-extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
-extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
-extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
-
-extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
-                         struct lock_class_key *key);
-
-#define init_rwsem(sem)                         \
-do {                                            \
-        static struct lock_class_key __key;     \
-                                                \
-        __init_rwsem((sem), #sem, &__key);      \
-} while (0)
-
-static inline void init_rwsem(struct rw_semaphore *sem)
-{
-        sem->count = RWSEM_UNLOCKED_VALUE;
-        spin_lock_init(&sem->wait_lock);
-        INIT_LIST_HEAD(&sem->wait_list);
-}
 
 /*
  * lock for reading
@@ -179,10 +128,5 @@ static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
         return atomic_add_return(delta, (atomic_t *)(&sem->count));
 }
 
-static inline int rwsem_is_locked(struct rw_semaphore *sem)
-{
-        return (sem->count != 0);
-}
-
 #endif /* __KERNEL__ */
 #endif /* _ASM_SH_RWSEM_H */
diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h
index a78701da775b..4a5350037c8f 100644
--- a/arch/sh/include/asm/sections.h
+++ b/arch/sh/include/asm/sections.h
@@ -3,7 +3,7 @@
 
 #include <asm-generic/sections.h>
 
-extern void __nosave_begin, __nosave_end;
+extern long __nosave_begin, __nosave_end;
 extern long __machvec_start, __machvec_end;
 extern char __uncached_start, __uncached_end;
 extern char _ebss[];
diff --git a/arch/sh/include/asm/sh_eth.h b/arch/sh/include/asm/sh_eth.h
index f739061e2ee4..0f325da0f923 100644
--- a/arch/sh/include/asm/sh_eth.h
+++ b/arch/sh/include/asm/sh_eth.h
@@ -1,11 +1,21 @@
 #ifndef __ASM_SH_ETH_H__
 #define __ASM_SH_ETH_H__
 
+#include <linux/phy.h>
+
 enum {EDMAC_LITTLE_ENDIAN, EDMAC_BIG_ENDIAN};
+enum {
+        SH_ETH_REG_GIGABIT,
+        SH_ETH_REG_FAST_SH4,
+        SH_ETH_REG_FAST_SH3_SH2
+};
 
 struct sh_eth_plat_data {
         int phy;
         int edmac_endian;
+        int register_type;
+        phy_interface_t phy_interface;
+        void (*set_mdio_gate)(unsigned long addr);
 
         unsigned char mac_addr[6];
         unsigned no_ether_link:1;
diff --git a/arch/sh/include/asm/sizes.h b/arch/sh/include/asm/sizes.h
index 3a1fb97770f1..dd248c2e1085 100644
--- a/arch/sh/include/asm/sizes.h
+++ b/arch/sh/include/asm/sizes.h
@@ -1,61 +1 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- *                 from .s file by awk -f s2h.awk
- */
-/*  Size definitions
- *  Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __sizes_h
-#define __sizes_h                       1
-
-/* handy sizes */
-#define SZ_16                           0x00000010
-#define SZ_32                           0x00000020
-#define SZ_64                           0x00000040
-#define SZ_128                          0x00000080
-#define SZ_256                          0x00000100
-#define SZ_512                          0x00000200
-
-#define SZ_1K                           0x00000400
-#define SZ_4K                           0x00001000
-#define SZ_8K                           0x00002000
-#define SZ_16K                          0x00004000
-#define SZ_32K                          0x00008000
-#define SZ_64K                          0x00010000
-#define SZ_128K                         0x00020000
-#define SZ_256K                         0x00040000
-#define SZ_512K                         0x00080000
-
-#define SZ_1M                           0x00100000
-#define SZ_2M                           0x00200000
-#define SZ_4M                           0x00400000
-#define SZ_8M                           0x00800000
-#define SZ_16M                          0x01000000
-#define SZ_26M                          0x01a00000
-#define SZ_32M                          0x02000000
-#define SZ_64M                          0x04000000
-#define SZ_128M                         0x08000000
-#define SZ_256M                         0x10000000
-#define SZ_512M                         0x20000000
-
-#define SZ_1G                           0x40000000
-#define SZ_2G                           0x80000000
-
-#endif
-
-/*         END */
+#include <asm-generic/sizes.h>
diff --git a/arch/sh/include/asm/sram.h b/arch/sh/include/asm/sram.h
new file mode 100644
index 000000000000..a2808ce4c0aa
--- /dev/null
+++ b/arch/sh/include/asm/sram.h
@@ -0,0 +1,38 @@
+#ifndef __ASM_SRAM_H
+#define __ASM_SRAM_H
+
+#ifdef CONFIG_HAVE_SRAM_POOL
+
+#include <linux/spinlock.h>
+#include <linux/genalloc.h>
+
+/* arch/sh/mm/sram.c */
+extern struct gen_pool *sram_pool;
+
+static inline unsigned long sram_alloc(size_t len)
+{
+        if (!sram_pool)
+                return 0UL;
+
+        return gen_pool_alloc(sram_pool, len);
+}
+
+static inline void sram_free(unsigned long addr, size_t len)
+{
+        return gen_pool_free(sram_pool, addr, len);
+}
+
+#else
+
+static inline unsigned long sram_alloc(size_t len)
+{
+        return 0;
+}
+
+static inline void sram_free(unsigned long addr, size_t len)
+{
+}
+
+#endif /* CONFIG_HAVE_SRAM_POOL */
+
+#endif /* __ASM_SRAM_H */
diff --git a/arch/sh/include/asm/stacktrace.h b/arch/sh/include/asm/stacktrace.h
index 797018213718..a7e2d4dfd087 100644
--- a/arch/sh/include/asm/stacktrace.h
+++ b/arch/sh/include/asm/stacktrace.h
@@ -10,9 +10,6 @@
 /* Generic stack tracer with callbacks */
 
 struct stacktrace_ops {
-        void (*warning)(void *data, char *msg);
-        /* msg must contain %s for the symbol */
-        void (*warning_symbol)(void *data, char *msg, unsigned long symbol);
         void (*address)(void *data, unsigned long address, int reliable);
         /* On negative return stop dumping */
         int (*stack)(void *data, char *name);
diff --git a/arch/sh/include/asm/suspend.h b/arch/sh/include/asm/suspend.h
index 64eb41a063e8..e14567a7e9a1 100644
--- a/arch/sh/include/asm/suspend.h
+++ b/arch/sh/include/asm/suspend.h
@@ -3,7 +3,6 @@
 
 #ifndef __ASSEMBLY__
 #include <linux/notifier.h>
-static inline int arch_prepare_suspend(void) { return 0; }
 
 #include <asm/ptrace.h>
 
diff --git a/arch/sh/include/asm/syscalls_32.h b/arch/sh/include/asm/syscalls_32.h
index be201fdc97aa..ae717e3c26d6 100644
--- a/arch/sh/include/asm/syscalls_32.h
+++ b/arch/sh/include/asm/syscalls_32.h
@@ -19,9 +19,10 @@ asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
 asmlinkage int sys_vfork(unsigned long r4, unsigned long r5,
                          unsigned long r6, unsigned long r7,
                          struct pt_regs __regs);
-asmlinkage int sys_execve(const char __user *ufilename, char __user * __user *uargv,
-                          char __user * __user *uenvp, unsigned long r7,
-                          struct pt_regs __regs);
+asmlinkage int sys_execve(const char __user *ufilename,
+                          const char __user *const __user *uargv,
+                          const char __user *const __user *uenvp,
+                          unsigned long r7, struct pt_regs __regs);
 asmlinkage int sys_sigsuspend(old_sigset_t mask, unsigned long r5,
                               unsigned long r6, unsigned long r7,
                               struct pt_regs __regs);
diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h
index 0bd7a17d5e1a..10c8b1823a18 100644
--- a/arch/sh/include/asm/system.h
+++ b/arch/sh/include/asm/system.h
@@ -10,6 +10,7 @@
 #include <linux/compiler.h>
 #include <linux/linkage.h>
 #include <asm/types.h>
+#include <asm/uncached.h>
 
 #define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
 
@@ -137,11 +138,6 @@ extern unsigned int instruction_size(unsigned int insn);
 #define instruction_size(insn)  (4)
 #endif
 
-extern unsigned long cached_to_uncached;
-extern unsigned long uncached_size;
-
-extern struct dentry *sh_debugfs_root;
-
 void per_cpu_trap_init(void);
 void default_idle(void);
 void cpu_idle_wait(void);
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
index 51296b36770e..a4ad1cd9bc4d 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@ -145,42 +145,6 @@ do {								\
                 __restore_dsp(prev);                            \
 } while (0)
 
-/*
- * Jump to uncached area.
- * When handling TLB or caches, we need to do it from an uncached area.
- */
-#define jump_to_uncached()                      \
-do {                                            \
-        unsigned long __dummy;                  \
-                                                \
-        __asm__ __volatile__(                   \
-                "mova   1f, %0\n\t"             \
-                "add    %1, %0\n\t"             \
-                "jmp    @%0\n\t"                \
-                " nop\n\t"                      \
-                ".balign 4\n"                   \
-                "1:"                            \
-                : "=&z" (__dummy)               \
-                : "r" (cached_to_uncached));    \
-} while (0)
-
-/*
- * Back to cached area.
- */
-#define back_to_cached()                                \
-do {                                                    \
-        unsigned long __dummy;                          \
-        ctrl_barrier();                                 \
-        __asm__ __volatile__(                           \
-                "mov.l  1f, %0\n\t"                     \
-                "jmp    @%0\n\t"                        \
-                " nop\n\t"                              \
-                ".balign 4\n"                           \
-                "1:     .long 2f\n"                     \
-                "2:"                                    \
-                : "=&r" (__dummy));                     \
-} while (0)
-
 #ifdef CONFIG_CPU_HAS_SR_RB
 #define lookup_exception_vector()       \
 ({                                      \
@@ -212,17 +176,16 @@ static inline reg_size_t register_align(void *val)
 }
 
 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
-                            struct mem_access *ma, int);
+                            struct mem_access *ma, int, unsigned long address);
 
 static inline void trigger_address_error(void)
 {
-        if (__in_29bit_mode())
-                __asm__ __volatile__ (
-                        "ldc %0, sr\n\t"
-                        "mov.l @%1, %0"
-                        :
-                        : "r" (0x10000000), "r" (0x80000001)
-                );
+        __asm__ __volatile__ (
+                "ldc %0, sr\n\t"
+                "mov.l @%1, %0"
+                :
+                : "r" (0x10000000), "r" (0x80000001)
+        );
 }
 
 asmlinkage void do_address_error(struct pt_regs *regs,
diff --git a/arch/sh/include/asm/system_64.h b/arch/sh/include/asm/system_64.h
index 36338646dfc8..8593bc8d1a4e 100644
--- a/arch/sh/include/asm/system_64.h
+++ b/arch/sh/include/asm/system_64.h
@@ -34,9 +34,6 @@ do {								\
                               &next->thread);                   \
 } while (0)
 
-#define jump_to_uncached()      do { } while (0)
-#define back_to_cached()        do { } while (0)
-
 #define __icbi(addr)    __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
 #define __ocbp(addr)    __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
 #define __ocbi(addr)    __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))
diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h
index c228946926ed..ea2d5089de1e 100644
--- a/arch/sh/include/asm/thread_info.h
+++ b/arch/sh/include/asm/thread_info.h
@@ -95,7 +95,7 @@ static inline struct thread_info *current_thread_info(void)
 
 #endif
 
-extern struct thread_info *alloc_thread_info(struct task_struct *tsk);
+extern struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node);
 extern void free_thread_info(struct thread_info *ti);
 extern void arch_task_cache_init(void);
 #define arch_task_cache_init arch_task_cache_init
diff --git a/arch/sh/include/asm/tlb.h b/arch/sh/include/asm/tlb.h
index 75abb38dffd5..ec88bfcdf7ce 100644
--- a/arch/sh/include/asm/tlb.h
+++ b/arch/sh/include/asm/tlb.h
@@ -9,6 +9,7 @@
 #include <linux/pagemap.h>
 
 #ifdef CONFIG_MMU
+#include <linux/swap.h>
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
 #include <asm/mmu_context.h>
@@ -23,8 +24,6 @@ struct mmu_gather {
         unsigned long           start, end;
 };
 
-DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 static inline void init_tlb_gather(struct mmu_gather *tlb)
 {
         tlb->start = TASK_SIZE;
@@ -36,17 +35,13 @@ static inline void init_tlb_gather(struct mmu_gather *tlb)
         }
 }
 
-static inline struct mmu_gather *
-tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
+static inline void
+tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
-
         tlb->mm = mm;
         tlb->fullmm = full_mm_flush;
 
         init_tlb_gather(tlb);
-
-        return tlb;
 }
 
 static inline void
@@ -57,8 +52,6 @@ tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 
         /* keep the page table cache within bounds */
         check_pgt_cache();
-
-        put_cpu_var(mmu_gathers);
 }
 
 static inline void
@@ -91,7 +84,21 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
         }
 }
 
-#define tlb_remove_page(tlb,page)       free_page_and_swap_cache(page)
+static inline void tlb_flush_mmu(struct mmu_gather *tlb)
+{
+}
+
+static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+        free_page_and_swap_cache(page);
+        return 1; /* avoid calling tlb_flush_mmu */
+}
+
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+        __tlb_remove_page(tlb, page);
+}
+
 #define pte_free_tlb(tlb, ptep, addr)   pte_free((tlb)->mm, ptep)
 #define pmd_free_tlb(tlb, pmdp, addr)   pmd_free((tlb)->mm, pmdp)
 #define pud_free_tlb(tlb, pudp, addr)   pud_free((tlb)->mm, pudp)
diff --git a/arch/sh/include/asm/tlbflush.h b/arch/sh/include/asm/tlbflush.h
index e0ac97221ae6..0df66f0c7284 100644
--- a/arch/sh/include/asm/tlbflush.h
+++ b/arch/sh/include/asm/tlbflush.h
@@ -21,6 +21,8 @@ extern void local_flush_tlb_kernel_range(unsigned long start,
                                          unsigned long end);
 extern void local_flush_tlb_one(unsigned long asid, unsigned long page);
 
+extern void __flush_tlb_global(void);
+
 #ifdef CONFIG_SMP
 
 extern void flush_tlb_all(void);
diff --git a/arch/sh/include/asm/unaligned-sh4a.h b/arch/sh/include/asm/unaligned-sh4a.h
index 9f4dd252c981..95adc500cabc 100644
--- a/arch/sh/include/asm/unaligned-sh4a.h
+++ b/arch/sh/include/asm/unaligned-sh4a.h
@@ -9,7 +9,7 @@
  * struct.
  *
  * The same note as with the movli.l/movco.l pair applies here, as long
- * as the load is gauranteed to be inlined, nothing else will hook in to
+ * as the load is guaranteed to be inlined, nothing else will hook in to
  * r0 and we get the return value for free.
  *
  * NOTE: Due to the fact we require r0 encoding, care should be taken to
@@ -18,10 +18,20 @@
  * of spill registers and blowing up when building at low optimization
  * levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777.
  */
+#include <linux/unaligned/packed_struct.h>
 #include <linux/types.h>
 #include <asm/byteorder.h>
 
-static __always_inline u32 __get_unaligned_cpu32(const u8 *p)
+static inline u16 sh4a_get_unaligned_cpu16(const u8 *p)
+{
+#ifdef __LITTLE_ENDIAN
+        return p[0] | p[1] << 8;
+#else
+        return p[0] << 8 | p[1];
+#endif
+}
+
+static __always_inline u32 sh4a_get_unaligned_cpu32(const u8 *p)
 {
         unsigned long unaligned;
 
@@ -34,218 +44,148 @@ static __always_inline u32 __get_unaligned_cpu32(const u8 *p)
         return unaligned;
 }
 
-struct __una_u16 { u16 x __attribute__((packed)); };
-struct __una_u32 { u32 x __attribute__((packed)); };
-struct __una_u64 { u64 x __attribute__((packed)); };
-
-static inline u16 __get_unaligned_cpu16(const u8 *p)
-{
-#ifdef __LITTLE_ENDIAN
-        return p[0] | p[1] << 8;
-#else
-        return p[0] << 8 | p[1];
-#endif
-}
-
 /*
  * Even though movua.l supports auto-increment on the read side, it can
  * only store to r0 due to instruction encoding constraints, so just let
  * the compiler sort it out on its own.
  */
-static inline u64 __get_unaligned_cpu64(const u8 *p)
+static inline u64 sh4a_get_unaligned_cpu64(const u8 *p)
 {
 #ifdef __LITTLE_ENDIAN
-        return (u64)__get_unaligned_cpu32(p + 4) << 32 |
-                    __get_unaligned_cpu32(p);
+        return (u64)sh4a_get_unaligned_cpu32(p + 4) << 32 |
+                    sh4a_get_unaligned_cpu32(p);
 #else
-        return (u64)__get_unaligned_cpu32(p) << 32 |
-                    __get_unaligned_cpu32(p + 4);
+        return (u64)sh4a_get_unaligned_cpu32(p) << 32 |
+                    sh4a_get_unaligned_cpu32(p + 4);
 #endif
 }
 
 static inline u16 get_unaligned_le16(const void *p)
 {
-        return le16_to_cpu(__get_unaligned_cpu16(p));
+        return le16_to_cpu(sh4a_get_unaligned_cpu16(p));
 }
 
 static inline u32 get_unaligned_le32(const void *p)
 {
-        return le32_to_cpu(__get_unaligned_cpu32(p));
+        return le32_to_cpu(sh4a_get_unaligned_cpu32(p));
 }
 
 static inline u64 get_unaligned_le64(const void *p)
 {
-        return le64_to_cpu(__get_unaligned_cpu64(p));
+        return le64_to_cpu(sh4a_get_unaligned_cpu64(p));
 }
 
 static inline u16 get_unaligned_be16(const void *p)
 {
-        return be16_to_cpu(__get_unaligned_cpu16(p));
+        return be16_to_cpu(sh4a_get_unaligned_cpu16(p));
 }
 
 static inline u32 get_unaligned_be32(const void *p)
 {
-        return be32_to_cpu(__get_unaligned_cpu32(p));
+        return be32_to_cpu(sh4a_get_unaligned_cpu32(p));
 }
 
 static inline u64 get_unaligned_be64(const void *p)
 {
-        return be64_to_cpu(__get_unaligned_cpu64(p));
+        return be64_to_cpu(sh4a_get_unaligned_cpu64(p));
 }
 
-static inline void __put_le16_noalign(u8 *p, u16 val)
+static inline void nonnative_put_le16(u16 val, u8 *p)
 {
         *p++ = val;
         *p++ = val >> 8;
 }
 
-static inline void __put_le32_noalign(u8 *p, u32 val)
+static inline void nonnative_put_le32(u32 val, u8 *p)
 {
-        __put_le16_noalign(p, val);
-        __put_le16_noalign(p + 2, val >> 16);
+        nonnative_put_le16(val, p);
+        nonnative_put_le16(val >> 16, p + 2);
 }
 
-static inline void __put_le64_noalign(u8 *p, u64 val)
+static inline void nonnative_put_le64(u64 val, u8 *p)
 {
-        __put_le32_noalign(p, val);
-        __put_le32_noalign(p + 4, val >> 32);
+        nonnative_put_le32(val, p);
+        nonnative_put_le32(val >> 32, p + 4);
 }
 
-static inline void __put_be16_noalign(u8 *p, u16 val)
+static inline void nonnative_put_be16(u16 val, u8 *p)
 {
         *p++ = val >> 8;
         *p++ = val;
 }
 
-static inline void __put_be32_noalign(u8 *p, u32 val)
+static inline void nonnative_put_be32(u32 val, u8 *p)
 {
-        __put_be16_noalign(p, val >> 16);
-        __put_be16_noalign(p + 2, val);
+        nonnative_put_be16(val >> 16, p);
+        nonnative_put_be16(val, p + 2);
 }
 
-static inline void __put_be64_noalign(u8 *p, u64 val)
+static inline void nonnative_put_be64(u64 val, u8 *p)
 {
-        __put_be32_noalign(p, val >> 32);
-        __put_be32_noalign(p + 4, val);
+        nonnative_put_be32(val >> 32, p);
+        nonnative_put_be32(val, p + 4);
 }
 
 static inline void put_unaligned_le16(u16 val, void *p)
 {
 #ifdef __LITTLE_ENDIAN
-        ((struct __una_u16 *)p)->x = val;
+        __put_unaligned_cpu16(val, p);
 #else
-        __put_le16_noalign(p, val);
+        nonnative_put_le16(val, p);
 #endif
 }
 
 static inline void put_unaligned_le32(u32 val, void *p)
 {
 #ifdef __LITTLE_ENDIAN
-        ((struct __una_u32 *)p)->x = val;
+        __put_unaligned_cpu32(val, p);
 #else
-        __put_le32_noalign(p, val);
+        nonnative_put_le32(val, p);
 #endif
 }
 
 static inline void put_unaligned_le64(u64 val, void *p)
 {
 #ifdef __LITTLE_ENDIAN
-        ((struct __una_u64 *)p)->x = val;
+        __put_unaligned_cpu64(val, p);
 #else
-        __put_le64_noalign(p, val);
+        nonnative_put_le64(val, p);
 #endif
 }
 
 static inline void put_unaligned_be16(u16 val, void *p)
 {
 #ifdef __BIG_ENDIAN
-        ((struct __una_u16 *)p)->x = val;
+        __put_unaligned_cpu16(val, p);
 #else
-        __put_be16_noalign(p, val);
+        nonnative_put_be16(val, p);
 #endif
 }
 
 static inline void put_unaligned_be32(u32 val, void *p)
 {
 #ifdef __BIG_ENDIAN
-        ((struct __una_u32 *)p)->x = val;
+        __put_unaligned_cpu32(val, p);
 #else
-        __put_be32_noalign(p, val);
+        nonnative_put_be32(val, p);
 #endif
 }
 
 static inline void put_unaligned_be64(u64 val, void *p)
 {
 #ifdef __BIG_ENDIAN
-        ((struct __una_u64 *)p)->x = val;
+        __put_unaligned_cpu64(val, p);
 #else
-        __put_be64_noalign(p, val);
+        nonnative_put_be64(val, p);
 #endif
 }
 
 /*
- * Cause a link-time error if we try an unaligned access other than
- * 1,2,4 or 8 bytes long
+ * While it's a bit non-obvious, even though the generic le/be wrappers
+ * use the __get/put_xxx prefixing, they actually wrap in to the
+ * non-prefixed get/put_xxx variants as provided above.
  */
-extern void __bad_unaligned_access_size(void);
-
-#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({                     \
-        __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr),                      \
-        __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)),   \
-        __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)),   \
-        __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)),   \
-        __bad_unaligned_access_size()))));                                      \
-        }))
-
-#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({                     \
-        __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr),                      \
-        __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)),   \
-        __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)),   \
-        __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)),   \
-        __bad_unaligned_access_size()))));                                      \
-        }))
-
-#define __put_unaligned_le(val, ptr) ({                                 \
-        void *__gu_p = (ptr);                                           \
-        switch (sizeof(*(ptr))) {                                       \
-        case 1:                                                         \
-                *(u8 *)__gu_p = (__force u8)(val);                      \
-                break;                                                  \
-        case 2:                                                         \
-                put_unaligned_le16((__force u16)(val), __gu_p);         \
-                break;                                                  \
-        case 4:                                                         \
-                put_unaligned_le32((__force u32)(val), __gu_p);         \
-                break;                                                  \
-        case 8:                                                         \
-                put_unaligned_le64((__force u64)(val), __gu_p);         \
-                break;                                                  \
-        default:                                                        \
-                __bad_unaligned_access_size();                          \
-                break;                                                  \
-        }                                                               \
-        (void)0; })
-
-#define __put_unaligned_be(val, ptr) ({                                 \
-        void *__gu_p = (ptr);                                           \
-        switch (sizeof(*(ptr))) {                                       \
-        case 1:                                                         \
-                *(u8 *)__gu_p = (__force u8)(val);                      \
-                break;                                                  \
-        case 2:                                                         \
-                put_unaligned_be16((__force u16)(val), __gu_p);         \
-                break;                                                  \
-        case 4:                                                         \
-                put_unaligned_be32((__force u32)(val), __gu_p);         \
-                break;                                                  \
-        case 8:                                                         \
-                put_unaligned_be64((__force u64)(val), __gu_p);         \
-                break;                                                  \
-        default:                                                        \
-                __bad_unaligned_access_size();                          \
-                break;                                                  \
-        }                                                               \
-        (void)0; })
+#include <linux/unaligned/generic.h>
 
 #ifdef __LITTLE_ENDIAN
 # define get_unaligned __get_unaligned_le
diff --git a/arch/sh/include/asm/uncached.h b/arch/sh/include/asm/uncached.h
index e3419f96626a..6f8816b79cf1 100644
--- a/arch/sh/include/asm/uncached.h
+++ b/arch/sh/include/asm/uncached.h
@@ -4,15 +4,55 @@
 #include <linux/bug.h>
 
 #ifdef CONFIG_UNCACHED_MAPPING
+extern unsigned long cached_to_uncached;
+extern unsigned long uncached_size;
 extern unsigned long uncached_start, uncached_end;
 
 extern int virt_addr_uncached(unsigned long kaddr);
 extern void uncached_init(void);
 extern void uncached_resize(unsigned long size);
+
+/*
+ * Jump to uncached area.
+ * When handling TLB or caches, we need to do it from an uncached area.
+ */
+#define jump_to_uncached()                      \
+do {                                            \
+        unsigned long __dummy;                  \
+                                                \
+        __asm__ __volatile__(                   \
+                "mova   1f, %0\n\t"             \
+                "add    %1, %0\n\t"             \
+                "jmp    @%0\n\t"                \
+                " nop\n\t"                      \
+                ".balign 4\n"                   \
+                "1:"                            \
+                : "=&z" (__dummy)               \
+                : "r" (cached_to_uncached));    \
+} while (0)
+
+/*
+ * Back to cached area.
+ */
+#define back_to_cached()                                \
+do {                                                    \
+        unsigned long __dummy;                          \
+        ctrl_barrier();                                 \
+        __asm__ __volatile__(                           \
+                "mov.l  1f, %0\n\t"                     \
+                "jmp    @%0\n\t"                        \
+                " nop\n\t"                              \
+                ".balign 4\n"                           \
+                "1:     .long 2f\n"                     \
+                "2:"                                    \
+                : "=&r" (__dummy));                     \
+} while (0)
 #else
 #define virt_addr_uncached(kaddr)       (0)
 #define uncached_init()                 do { } while (0)
 #define uncached_resize(size)           BUG()
+#define jump_to_uncached()              do { } while (0)
+#define back_to_cached()                do { } while (0)
 #endif
 
 #endif /* __ASM_SH_UNCACHED_H */
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
index 0e7f0fc8f086..3432008d2888 100644
--- a/arch/sh/include/asm/unistd_32.h
+++ b/arch/sh/include/asm/unistd_32.h
@@ -345,12 +345,40 @@
 #define __NR_pwritev            334
 #define __NR_rt_tgsigqueueinfo  335
 #define __NR_perf_event_open    336
+#define __NR_fanotify_init      337
+#define __NR_fanotify_mark      338
+#define __NR_prlimit64          339
 
-#define NR_syscalls 337
+/* Non-multiplexed socket family */
+#define __NR_socket             340
+#define __NR_bind               341
+#define __NR_connect            342
+#define __NR_listen             343
+#define __NR_accept             344
+#define __NR_getsockname        345
+#define __NR_getpeername        346
+#define __NR_socketpair         347
+#define __NR_send               348
+#define __NR_sendto             349
+#define __NR_recv               350
+#define __NR_recvfrom           351
+#define __NR_shutdown           352
+#define __NR_setsockopt         353
+#define __NR_getsockopt         354
+#define __NR_sendmsg            355
+#define __NR_recvmsg            356
+#define __NR_recvmmsg           357
+#define __NR_accept4            358
+#define __NR_name_to_handle_at  359
+#define __NR_open_by_handle_at  360
+#define __NR_clock_adjtime      361
+#define __NR_syncfs             362
+#define __NR_sendmmsg           363
+#define __NR_setns              364
 
-#ifdef __KERNEL__
+#define NR_syscalls 365
 
-#define __IGNORE_recvmmsg
+#ifdef __KERNEL__
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h
index 0580c33a1e04..ec9898665f23 100644
--- a/arch/sh/include/asm/unistd_64.h
+++ b/arch/sh/include/asm/unistd_64.h
@@ -387,10 +387,19 @@
 #define __NR_perf_event_open    364
 #define __NR_recvmmsg           365
 #define __NR_accept4            366
+#define __NR_fanotify_init      367
+#define __NR_fanotify_mark      368
+#define __NR_prlimit64          369
+#define __NR_name_to_handle_at  370
+#define __NR_open_by_handle_at  371
+#define __NR_clock_adjtime      372
+#define __NR_syncfs             373
+#define __NR_sendmmsg           374
+#define __NR_setns              375
 
 #ifdef __KERNEL__
 
-#define NR_syscalls 367
+#define NR_syscalls 376
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/sh/include/cpu-sh3/cpu/mmu_context.h b/arch/sh/include/cpu-sh3/cpu/mmu_context.h
index ab09da73ce77..0c7c735ea82a 100644
--- a/arch/sh/include/cpu-sh3/cpu/mmu_context.h
+++ b/arch/sh/include/cpu-sh3/cpu/mmu_context.h
@@ -16,6 +16,7 @@
 #define MMU_TEA         0xFFFFFFFC      /* TLB Exception Address */
 
 #define MMUCR           0xFFFFFFE0      /* MMU Control Register */
+#define MMUCR_TI        (1 << 2)        /* TLB flush bit */
 
 #define MMU_TLB_ADDRESS_ARRAY   0xF2000000
 #define MMU_PAGE_ASSOC_BIT      0x80
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-register.h b/arch/sh/include/cpu-sh4/cpu/dma-register.h
index 9a6125eb0079..18fa80aba15e 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma-register.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma-register.h
@@ -40,6 +40,11 @@
 #define CHCR_TS_LOW_SHIFT       3
 #define CHCR_TS_HIGH_MASK       0
 #define CHCR_TS_HIGH_SHIFT      0
+#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
+#define CHCR_TS_LOW_MASK        0x00000018
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0x00100000
+#define CHCR_TS_HIGH_SHIFT      (20 - 2)        /* 2 bits for shifted low TS */
 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 #define CHCR_TS_LOW_MASK        0x00000018
 #define CHCR_TS_LOW_SHIFT       3
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index e1e90960ee9a..cffd25ed0240 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -56,7 +56,9 @@
 #define FRQCR1                  0xffc40004
 #define FRQMR1                  0xffc40014
 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
-#define FRQCR                   0xffc00014
+#define FRQCR0                  0xffc00000
+#define FRQCR1                  0xffc00004
+#define FRQMR1                  0xffc00014
 #else
 #define FRQCR                   0xffc00000
 #define FRQCR_PSTBY             0x0200
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7722.h b/arch/sh/include/cpu-sh4/cpu/sh7722.h
index 7a5b8a331b4a..bd0622788d64 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7722.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7722.h
@@ -236,6 +236,7 @@ enum {
 };
 
 enum {
+        SHDMA_SLAVE_INVALID,
         SHDMA_SLAVE_SCIF0_TX,
         SHDMA_SLAVE_SCIF0_RX,
         SHDMA_SLAVE_SCIF1_TX,
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h
index 4c27b68789b3..cbc47e6bcab5 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7724.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h
@@ -285,6 +285,7 @@ enum {
 };
 
 enum {
+        SHDMA_SLAVE_INVALID,
         SHDMA_SLAVE_SCIF0_TX,
         SHDMA_SLAVE_SCIF0_RX,
         SHDMA_SLAVE_SCIF1_TX,
@@ -297,10 +298,21 @@ enum {
         SHDMA_SLAVE_SCIF4_RX,
         SHDMA_SLAVE_SCIF5_TX,
         SHDMA_SLAVE_SCIF5_RX,
+        SHDMA_SLAVE_USB0D0_TX,
+        SHDMA_SLAVE_USB0D0_RX,
+        SHDMA_SLAVE_USB0D1_TX,
+        SHDMA_SLAVE_USB0D1_RX,
+        SHDMA_SLAVE_USB1D0_TX,
+        SHDMA_SLAVE_USB1D0_RX,
+        SHDMA_SLAVE_USB1D1_TX,
+        SHDMA_SLAVE_USB1D1_RX,
         SHDMA_SLAVE_SDHI0_TX,
         SHDMA_SLAVE_SDHI0_RX,
         SHDMA_SLAVE_SDHI1_TX,
         SHDMA_SLAVE_SDHI1_RX,
 };
 
+extern struct clk sh7724_fsimcka_clk;
+extern struct clk sh7724_fsimckb_clk;
+
 #endif /* __ASM_SH7724_H__ */
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7757.h b/arch/sh/include/cpu-sh4/cpu/sh7757.h
index f4d267efad71..41f9f8b9db73 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7757.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7757.h
@@ -3,241 +3,285 @@
 
 enum {
         /* PTA */
-        GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
-        GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
+        GPIO_PTA0, GPIO_PTA1, GPIO_PTA2, GPIO_PTA3,
+        GPIO_PTA4, GPIO_PTA5, GPIO_PTA6, GPIO_PTA7,
 
         /* PTB */
-        GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
-        GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
+        GPIO_PTB0, GPIO_PTB1, GPIO_PTB2, GPIO_PTB3,
+        GPIO_PTB4, GPIO_PTB5, GPIO_PTB6, GPIO_PTB7,
 
         /* PTC */
-        GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
-        GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
+        GPIO_PTC0, GPIO_PTC1, GPIO_PTC2, GPIO_PTC3,
+        GPIO_PTC4, GPIO_PTC5, GPIO_PTC6, GPIO_PTC7,
 
         /* PTD */
-        GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
-        GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
+        GPIO_PTD0, GPIO_PTD1, GPIO_PTD2, GPIO_PTD3,
+        GPIO_PTD4, GPIO_PTD5, GPIO_PTD6, GPIO_PTD7,
 
         /* PTE */
-        GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4,
-        GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
+        GPIO_PTE0, GPIO_PTE1, GPIO_PTE2, GPIO_PTE3,
+        GPIO_PTE4, GPIO_PTE5, GPIO_PTE6, GPIO_PTE7,
 
         /* PTF */
-        GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4,
-        GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0,
+        GPIO_PTF0, GPIO_PTF1, GPIO_PTF2, GPIO_PTF3,
+        GPIO_PTF4, GPIO_PTF5, GPIO_PTF6, GPIO_PTF7,
 
         /* PTG */
-        GPIO_PTG7, GPIO_PTG6, GPIO_PTG5, GPIO_PTG4,
-        GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0,
+        GPIO_PTG0, GPIO_PTG1, GPIO_PTG2, GPIO_PTG3,
+        GPIO_PTG4, GPIO_PTG5, GPIO_PTG6, GPIO_PTG7,
 
         /* PTH */
-        GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4,
-        GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
+        GPIO_PTH0, GPIO_PTH1, GPIO_PTH2, GPIO_PTH3,
+        GPIO_PTH4, GPIO_PTH5, GPIO_PTH6, GPIO_PTH7,
 
         /* PTI */
-        GPIO_PTI7, GPIO_PTI6, GPIO_PTI5, GPIO_PTI4,
-        GPIO_PTI3, GPIO_PTI2, GPIO_PTI1, GPIO_PTI0,
+        GPIO_PTI0, GPIO_PTI1, GPIO_PTI2, GPIO_PTI3,
+        GPIO_PTI4, GPIO_PTI5, GPIO_PTI6, GPIO_PTI7,
 
         /* PTJ */
-        GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4,
-        GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
+        GPIO_PTJ0, GPIO_PTJ1, GPIO_PTJ2, GPIO_PTJ3,
+        GPIO_PTJ4, GPIO_PTJ5, GPIO_PTJ6, GPIO_PTJ7_RESV,
 
         /* PTK */
-        GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4,
-        GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
+        GPIO_PTK0, GPIO_PTK1, GPIO_PTK2, GPIO_PTK3,
+        GPIO_PTK4, GPIO_PTK5, GPIO_PTK6, GPIO_PTK7,
 
         /* PTL */
-        GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4,
-        GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0,
+        GPIO_PTL0, GPIO_PTL1, GPIO_PTL2, GPIO_PTL3,
+        GPIO_PTL4, GPIO_PTL5, GPIO_PTL6, GPIO_PTL7_RESV,
 
         /* PTM */
-                   GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
-        GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
+        GPIO_PTM0, GPIO_PTM1, GPIO_PTM2, GPIO_PTM3,
+        GPIO_PTM4, GPIO_PTM5, GPIO_PTM6, GPIO_PTM7,
 
         /* PTN */
-        GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4,
-        GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
+        GPIO_PTN0, GPIO_PTN1, GPIO_PTN2, GPIO_PTN3,
+        GPIO_PTN4, GPIO_PTN5, GPIO_PTN6, GPIO_PTN7_RESV,
 
         /* PTO */
-        GPIO_PTO7, GPIO_PTO6, GPIO_PTO5, GPIO_PTO4,
-        GPIO_PTO3, GPIO_PTO2, GPIO_PTO1, GPIO_PTO0,
+        GPIO_PTO0, GPIO_PTO1, GPIO_PTO2, GPIO_PTO3,
+        GPIO_PTO4, GPIO_PTO5, GPIO_PTO6, GPIO_PTO7,
 
         /* PTP */
-                   GPIO_PTP6, GPIO_PTP5, GPIO_PTP4,
-        GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0,
+        GPIO_PTP0, GPIO_PTP1, GPIO_PTP2, GPIO_PTP3,
+        GPIO_PTP4, GPIO_PTP5, GPIO_PTP6, GPIO_PTP7,
 
         /* PTQ */
-                   GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
-        GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
+        GPIO_PTQ0, GPIO_PTQ1, GPIO_PTQ2, GPIO_PTQ3,
+        GPIO_PTQ4, GPIO_PTQ5, GPIO_PTQ6, GPIO_PTQ7_RESV,
 
         /* PTR */
-        GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
-        GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
+        GPIO_PTR0, GPIO_PTR1, GPIO_PTR2, GPIO_PTR3,
+        GPIO_PTR4, GPIO_PTR5, GPIO_PTR6, GPIO_PTR7,
 
         /* PTS */
-        GPIO_PTS7, GPIO_PTS6, GPIO_PTS5, GPIO_PTS4,
-        GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
+        GPIO_PTS0, GPIO_PTS1, GPIO_PTS2, GPIO_PTS3,
+        GPIO_PTS4, GPIO_PTS5, GPIO_PTS6, GPIO_PTS7,
 
         /* PTT */
-                              GPIO_PTT5, GPIO_PTT4,
-        GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
+        GPIO_PTT0, GPIO_PTT1, GPIO_PTT2, GPIO_PTT3,
+        GPIO_PTT4, GPIO_PTT5, GPIO_PTT6, GPIO_PTT7,
 
         /* PTU */
-        GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4,
-        GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
+        GPIO_PTU0, GPIO_PTU1, GPIO_PTU2, GPIO_PTU3,
+        GPIO_PTU4, GPIO_PTU5, GPIO_PTU6, GPIO_PTU7,
 
         /* PTV */
-        GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4,
-        GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
+        GPIO_PTV0, GPIO_PTV1, GPIO_PTV2, GPIO_PTV3,
+        GPIO_PTV4, GPIO_PTV5, GPIO_PTV6, GPIO_PTV7,
 
         /* PTW */
-        GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4,
-        GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0,
+        GPIO_PTW0, GPIO_PTW1, GPIO_PTW2, GPIO_PTW3,
+        GPIO_PTW4, GPIO_PTW5, GPIO_PTW6, GPIO_PTW7,
 
         /* PTX */
-        GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4,
-        GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0,
+        GPIO_PTX0, GPIO_PTX1, GPIO_PTX2, GPIO_PTX3,
+        GPIO_PTX4, GPIO_PTX5, GPIO_PTX6, GPIO_PTX7,
 
         /* PTY */
-        GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4,
-        GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0,
+        GPIO_PTY0, GPIO_PTY1, GPIO_PTY2, GPIO_PTY3,
+        GPIO_PTY4, GPIO_PTY5, GPIO_PTY6, GPIO_PTY7,
 
         /* PTZ */
-        GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4,
-        GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0,
+        GPIO_PTZ0, GPIO_PTZ1, GPIO_PTZ2, GPIO_PTZ3,
+        GPIO_PTZ4, GPIO_PTZ5, GPIO_PTZ6, GPIO_PTZ7,
 
 
-        /* PTA (mobule: LBSC, CPG, LPC) */
+        /* PTA (mobule: LBSC, RGMII) */
         GPIO_FN_BS,     GPIO_FN_RDWR,   GPIO_FN_WE1,    GPIO_FN_RDY,
-        GPIO_FN_MD10,   GPIO_FN_MD9,    GPIO_FN_MD8,
-        GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4,
-        GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0,
-
-        /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
-        GPIO_FN_D15,    GPIO_FN_D14,    GPIO_FN_D13,    GPIO_FN_D12,
-        GPIO_FN_D11,    GPIO_FN_D10,    GPIO_FN_D9,     GPIO_FN_D8,
-        GPIO_FN_ET0_MDC,                GPIO_FN_ET0_MDIO,
-        GPIO_FN_ET1_MDC,                GPIO_FN_ET1_MDIO,
-        GPIO_FN_SIM_D,  GPIO_FN_SIM_CLK,                GPIO_FN_SIM_RST,
-        GPIO_FN_WPSZ1,  GPIO_FN_WPSZ0,  GPIO_FN_FWID,   GPIO_FN_FLSHSZ,
-        GPIO_FN_LPC_SPIEN,              GPIO_FN_BASEL,
+        GPIO_FN_ET0_MDC,        GPIO_FN_ET0_MDIO,
+        GPIO_FN_ET1_MDC,        GPIO_FN_ET1_MDIO,
 
-        /* PTC (mobule: SD) */
-        GPIO_FN_SD_WP,  GPIO_FN_SD_CD,  GPIO_FN_SD_CLK, GPIO_FN_SD_CMD,
-        GPIO_FN_SD_D3,  GPIO_FN_SD_D2,  GPIO_FN_SD_D1,  GPIO_FN_SD_D0,
+        /* PTB (mobule: INTC, ONFI, TMU) */
+        GPIO_FN_IRQ15,  GPIO_FN_IRQ14,  GPIO_FN_IRQ13,  GPIO_FN_IRQ12,
+        GPIO_FN_IRQ11,  GPIO_FN_IRQ10,  GPIO_FN_IRQ9,   GPIO_FN_IRQ8,
+        GPIO_FN_ON_NRE, GPIO_FN_ON_NWE, GPIO_FN_ON_NWP, GPIO_FN_ON_NCE0,
+        GPIO_FN_ON_R_B0,        GPIO_FN_ON_ALE, GPIO_FN_ON_CLE,
+        GPIO_FN_TCLK,
 
-        /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
+        /* PTC (mobule: IRQ, PWMU) */
         GPIO_FN_IRQ7,   GPIO_FN_IRQ6,   GPIO_FN_IRQ5,   GPIO_FN_IRQ4,
         GPIO_FN_IRQ3,   GPIO_FN_IRQ2,   GPIO_FN_IRQ1,   GPIO_FN_IRQ0,
-        GPIO_FN_MD6,    GPIO_FN_MD5,    GPIO_FN_MD3,    GPIO_FN_MD2,
-        GPIO_FN_MD1,    GPIO_FN_MD0,    GPIO_FN_ADTRG1, GPIO_FN_ADTRG0,
-
-        /* PTE (mobule: EtherC) */
-        GPIO_FN_ET0_CRS_DV,             GPIO_FN_ET0_TXD1,
-        GPIO_FN_ET0_TXD0,               GPIO_FN_ET0_TX_EN,
-        GPIO_FN_ET0_REF_CLK,            GPIO_FN_ET0_RXD1,
-        GPIO_FN_ET0_RXD0,               GPIO_FN_ET0_RX_ER,
-
-        /* PTF (mobule: EtherC) */
-        GPIO_FN_ET1_CRS_DV,             GPIO_FN_ET1_TXD1,
-        GPIO_FN_ET1_TXD0,               GPIO_FN_ET1_TX_EN,
-        GPIO_FN_ET1_REF_CLK,            GPIO_FN_ET1_RXD1,
-        GPIO_FN_ET1_RXD0,               GPIO_FN_ET1_RX_ER,
-
-        /* PTG (mobule: SYSTEM, PWMX, LPC) */
-        GPIO_FN_STATUS0,                GPIO_FN_STATUS1,
-        GPIO_FN_PWX0,   GPIO_FN_PWX1,   GPIO_FN_PWX2,   GPIO_FN_PWX3,
-        GPIO_FN_SERIRQ, GPIO_FN_CLKRUN, GPIO_FN_LPCPD,  GPIO_FN_LDRQ,
-
-        /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
-        GPIO_FN_TCLK,   GPIO_FN_RXD4,   GPIO_FN_TXD4,
+        GPIO_FN_PWMU0,  GPIO_FN_PWMU1,  GPIO_FN_PWMU2,  GPIO_FN_PWMU3,
+        GPIO_FN_PWMU4,  GPIO_FN_PWMU5,
+
+        /* PTD (mobule: SPI0, DMAC) */
+        GPIO_FN_SP0_MOSI,       GPIO_FN_SP0_MISO,       GPIO_FN_SP0_SCK,
+        GPIO_FN_SP0_SCK_FB,     GPIO_FN_SP0_SS0,        GPIO_FN_SP0_SS1,
+        GPIO_FN_SP0_SS2,        GPIO_FN_SP0_SS3,        GPIO_FN_DREQ0,
+        GPIO_FN_DACK0,          GPIO_FN_TEND0,
+
+        /* PTE (mobule: RMII) */
+        GPIO_FN_RMII0_CRS_DV,   GPIO_FN_RMII0_TXD1,     GPIO_FN_RMII0_TXD0,
+        GPIO_FN_RMII0_TXEN,     GPIO_FN_RMII0_REFCLK,   GPIO_FN_RMII0_RXD1,
+        GPIO_FN_RMII0_RXD0,     GPIO_FN_RMII0_RX_ER,
+
+        /* PTF (mobule: RMII, SerMux) */
+        GPIO_FN_RMII1_CRS_DV,   GPIO_FN_RMII1_TXD1,     GPIO_FN_RMII1_TXD0,
+        GPIO_FN_RMII1_TXEN,     GPIO_FN_RMII1_REFCLK,   GPIO_FN_RMII1_RXD1,
+        GPIO_FN_RMII1_RXD0,     GPIO_FN_RMII1_RX_ER,    GPIO_FN_RAC_RI,
+
+        /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
+        GPIO_FN_BOOTFMS,                GPIO_FN_BOOTWP,
+        GPIO_FN_A25,    GPIO_FN_A24,    GPIO_FN_SERIRQ, GPIO_FN_WDTOVF,
+        GPIO_FN_LPCPD,  GPIO_FN_LDRQ,   GPIO_FN_MMCCLK, GPIO_FN_MMCCMD,
+
+        /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
         GPIO_FN_SP1_MOSI,               GPIO_FN_SP1_MISO,
         GPIO_FN_SP1_SCK,                GPIO_FN_SP1_SCK_FB,
         GPIO_FN_SP1_SS0,                GPIO_FN_SP1_SS1,
-        GPIO_FN_SP0_SS1,
-
-        /* PTI (mobule: INTC) */
-        GPIO_FN_IRQ15,  GPIO_FN_IRQ14,  GPIO_FN_IRQ13,  GPIO_FN_IRQ12,
-        GPIO_FN_IRQ11,  GPIO_FN_IRQ10,  GPIO_FN_IRQ9,   GPIO_FN_IRQ8,
+        GPIO_FN_WP,     GPIO_FN_FMS0,   GPIO_FN_TEND1,  GPIO_FN_DREQ1,
+        GPIO_FN_DACK1,  GPIO_FN_ADTRG1, GPIO_FN_ADTRG0,
 
-        /* PTJ (mobule: SCIF234, SERMUX) */
-        GPIO_FN_RXD3,   GPIO_FN_TXD3,   GPIO_FN_RXD2,   GPIO_FN_TXD2,
-        GPIO_FN_COM1_TXD,               GPIO_FN_COM1_RXD,
-        GPIO_FN_COM1_RTS,               GPIO_FN_COM1_CTS,
-
-        /* PTK (mobule: SERMUX) */
-        GPIO_FN_COM2_TXD,               GPIO_FN_COM2_RXD,
-        GPIO_FN_COM2_RTS,               GPIO_FN_COM2_CTS,
-        GPIO_FN_COM2_DTR,               GPIO_FN_COM2_DSR,
-        GPIO_FN_COM2_DCD,               GPIO_FN_COM2_RI,
-
-        /* PTL (mobule: SERMUX) */
-        GPIO_FN_RAC_TXD,                GPIO_FN_RAC_RXD,
-        GPIO_FN_RAC_RTS,                GPIO_FN_RAC_CTS,
-        GPIO_FN_RAC_DTR,                GPIO_FN_RAC_DSR,
-        GPIO_FN_RAC_DCD,                GPIO_FN_RAC_RI,
+        /* PTI (mobule: LBSC, SDHI) */
+        GPIO_FN_D15,    GPIO_FN_D14,    GPIO_FN_D13,    GPIO_FN_D12,
+        GPIO_FN_D11,    GPIO_FN_D10,    GPIO_FN_D9,     GPIO_FN_D8,
+        GPIO_FN_SD_WP,  GPIO_FN_SD_CD,  GPIO_FN_SD_CLK, GPIO_FN_SD_CMD,
+        GPIO_FN_SD_D3,  GPIO_FN_SD_D2,  GPIO_FN_SD_D1,  GPIO_FN_SD_D0,
 
-        /* PTM (mobule: IIC, LPC) */
+        /* PTJ (mobule: SCIF234) */
+        GPIO_FN_RTS3,   GPIO_FN_CTS3,   GPIO_FN_TXD3,   GPIO_FN_RXD3,
+        GPIO_FN_RTS4,   GPIO_FN_RXD4,   GPIO_FN_TXD4,
+
+        /* PTK (mobule: SERMUX, LBSC, SCIF) */
+        GPIO_FN_COM2_TXD,       GPIO_FN_COM2_RXD,       GPIO_FN_COM2_RTS,
+        GPIO_FN_COM2_CTS,       GPIO_FN_COM2_DTR,       GPIO_FN_COM2_DSR,
+        GPIO_FN_COM2_DCD,       GPIO_FN_CLKOUT,
+        GPIO_FN_SCK2,           GPIO_FN_SCK4,   GPIO_FN_SCK3,
+
+        /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
+        GPIO_FN_RAC_RXD,        GPIO_FN_RAC_RTS,        GPIO_FN_RAC_CTS,
+        GPIO_FN_RAC_DTR,        GPIO_FN_RAC_DSR,        GPIO_FN_RAC_DCD,
+        GPIO_FN_RAC_TXD,        GPIO_FN_RXD2,           GPIO_FN_CS5,
+        GPIO_FN_CS6,            GPIO_FN_AUDSYNC,        GPIO_FN_AUDCK,
+        GPIO_FN_TXD2,
+
+        /* PTM (mobule: LBSC, IIC) */
+        GPIO_FN_CS4,    GPIO_FN_RD,     GPIO_FN_WE0,    GPIO_FN_CS0,
         GPIO_FN_SDA6,   GPIO_FN_SCL6,   GPIO_FN_SDA7,   GPIO_FN_SCL7,
-        GPIO_FN_WP,     GPIO_FN_FMS0,   GPIO_FN_FMS1,
 
-        /* PTN (mobule: SCIF234, EVC) */
-        GPIO_FN_SCK2,   GPIO_FN_RTS4,   GPIO_FN_RTS3,   GPIO_FN_RTS2,
-        GPIO_FN_CTS4,   GPIO_FN_CTS3,   GPIO_FN_CTS2,
-        GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_EVENT5, GPIO_FN_EVENT4,
-        GPIO_FN_EVENT3, GPIO_FN_EVENT2, GPIO_FN_EVENT1, GPIO_FN_EVENT0,
+        /* PTN (mobule: USB, JMC, SGPIO, WDT) */
+        GPIO_FN_VBUS_EN,        GPIO_FN_VBUS_OC,        GPIO_FN_JMCTCK,
+        GPIO_FN_JMCTMS,         GPIO_FN_JMCTDO,         GPIO_FN_JMCTDI,
+        GPIO_FN_JMCTRST,
+        GPIO_FN_SGPIO1_CLK,     GPIO_FN_SGPIO1_LOAD,    GPIO_FN_SGPIO1_DI,
+        GPIO_FN_SGPIO1_DO,      GPIO_FN_SUB_CLKIN,
 
-        /* PTO (mobule: SGPIO) */
-        GPIO_FN_SGPIO0_CLK,             GPIO_FN_SGPIO0_LOAD,
-        GPIO_FN_SGPIO0_DI,              GPIO_FN_SGPIO0_DO,
-        GPIO_FN_SGPIO1_CLK,             GPIO_FN_SGPIO1_LOAD,
-        GPIO_FN_SGPIO1_DI,              GPIO_FN_SGPIO1_DO,
-
-        /* PTP (mobule: JMC, SCIF234) */
-        GPIO_FN_JMCTCK, GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI,
-        GPIO_FN_JMCRST, GPIO_FN_SCK4,   GPIO_FN_SCK3,
+        /* PTO (mobule: SGPIO, SerMux) */
+        GPIO_FN_SGPIO0_CLK,     GPIO_FN_SGPIO0_LOAD,    GPIO_FN_SGPIO0_DI,
+        GPIO_FN_SGPIO0_DO,      GPIO_FN_SGPIO2_CLK,     GPIO_FN_SGPIO2_LOAD,
+        GPIO_FN_SGPIO2_DI,      GPIO_FN_SGPIO2_DO,      GPIO_FN_COM1_TXD,
+        GPIO_FN_COM1_RXD,       GPIO_FN_COM1_RTS,       GPIO_FN_COM1_CTS,
 
         /* PTQ (mobule: LPC) */
         GPIO_FN_LAD3,   GPIO_FN_LAD2,   GPIO_FN_LAD1,   GPIO_FN_LAD0,
         GPIO_FN_LFRAME, GPIO_FN_LRESET, GPIO_FN_LCLK,
 
         /* PTR (mobule: GRA, IIC) */
-        GPIO_FN_DDC3,   GPIO_FN_DDC2,
-        GPIO_FN_SDA8,   GPIO_FN_SCL8,   GPIO_FN_SDA2,   GPIO_FN_SCL2,
+        GPIO_FN_DDC3,   GPIO_FN_DDC2,   GPIO_FN_SDA2,   GPIO_FN_SCL2,
         GPIO_FN_SDA1,   GPIO_FN_SCL1,   GPIO_FN_SDA0,   GPIO_FN_SCL0,
+        GPIO_FN_SDA8,   GPIO_FN_SCL8,
 
         /* PTS (mobule: GRA, IIC) */
-        GPIO_FN_DDC1,   GPIO_FN_DDC0,
-        GPIO_FN_SDA9,   GPIO_FN_SCL9,   GPIO_FN_SDA5,   GPIO_FN_SCL5,
+        GPIO_FN_DDC1,   GPIO_FN_DDC0,   GPIO_FN_SDA5,   GPIO_FN_SCL5,
         GPIO_FN_SDA4,   GPIO_FN_SCL4,   GPIO_FN_SDA3,   GPIO_FN_SCL3,
+        GPIO_FN_SDA9,   GPIO_FN_SCL9,
 
-        /* PTT (mobule: SYSTEM, PWMX) */
-        GPIO_FN_AUDSYNC,                GPIO_FN_AUDCK,
-        GPIO_FN_AUDATA3,                GPIO_FN_AUDATA2,
-        GPIO_FN_AUDATA1,                GPIO_FN_AUDATA0,
-        GPIO_FN_PWX7,   GPIO_FN_PWX6,   GPIO_FN_PWX5,   GPIO_FN_PWX4,
+        /* PTT (mobule: PWMX, AUD) */
+        GPIO_FN_PWMX7,  GPIO_FN_PWMX6,  GPIO_FN_PWMX5,  GPIO_FN_PWMX4,
+        GPIO_FN_PWMX3,  GPIO_FN_PWMX2,  GPIO_FN_PWMX1,  GPIO_FN_PWMX0,
+        GPIO_FN_AUDATA3,        GPIO_FN_AUDATA2,        GPIO_FN_AUDATA1,
+        GPIO_FN_AUDATA0,        GPIO_FN_STATUS1,        GPIO_FN_STATUS0,
 
-        /* PTU (mobule: LBSC, DMAC) */
-        GPIO_FN_CS6,    GPIO_FN_CS5,    GPIO_FN_CS4,    GPIO_FN_CS0,
-        GPIO_FN_RD,     GPIO_FN_WE0,    GPIO_FN_A25,    GPIO_FN_A24,
-        GPIO_FN_DREQ0,  GPIO_FN_DACK0,
+        /* PTU (mobule: LPC, APM) */
+        GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4,
+        GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0,
+        GPIO_FN_APMONCTL_O,     GPIO_FN_APMPWBTOUT_O,   GPIO_FN_APMSCI_O,
+        GPIO_FN_APMVDDON,       GPIO_FN_APMSLPBTN,      GPIO_FN_APMPWRBTN,
+        GPIO_FN_APMS5N,         GPIO_FN_APMS3N,
 
-        /* PTV (mobule: LBSC, DMAC) */
+        /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
         GPIO_FN_A23,    GPIO_FN_A22,    GPIO_FN_A21,    GPIO_FN_A20,
         GPIO_FN_A19,    GPIO_FN_A18,    GPIO_FN_A17,    GPIO_FN_A16,
-        GPIO_FN_TEND0,  GPIO_FN_DREQ1,  GPIO_FN_DACK1,  GPIO_FN_TEND1,
+        GPIO_FN_COM2_RI,        GPIO_FN_R_SPI_MOSI,     GPIO_FN_R_SPI_MISO,
+        GPIO_FN_R_SPI_RSPCK,    GPIO_FN_R_SPI_SSL0,     GPIO_FN_R_SPI_SSL1,
+        GPIO_FN_EVENT7,         GPIO_FN_EVENT6,         GPIO_FN_VBIOS_DI,
+        GPIO_FN_VBIOS_DO,       GPIO_FN_VBIOS_CLK,      GPIO_FN_VBIOS_CS,
 
-        /* PTW (mobule: LBSC) */
+        /* PTW (mobule: LBSC, EVC, SCIF) */
         GPIO_FN_A15,    GPIO_FN_A14,    GPIO_FN_A13,    GPIO_FN_A12,
         GPIO_FN_A11,    GPIO_FN_A10,    GPIO_FN_A9,     GPIO_FN_A8,
+        GPIO_FN_EVENT5, GPIO_FN_EVENT4, GPIO_FN_EVENT3, GPIO_FN_EVENT2,
+        GPIO_FN_EVENT1, GPIO_FN_EVENT0, GPIO_FN_CTS4,   GPIO_FN_CTS2,
 
-        /* PTX (mobule: LBSC) */
+        /* PTX (mobule: LBSC, SCIF, SIM) */
         GPIO_FN_A7,     GPIO_FN_A6,     GPIO_FN_A5,     GPIO_FN_A4,
         GPIO_FN_A3,     GPIO_FN_A2,     GPIO_FN_A1,     GPIO_FN_A0,
+        GPIO_FN_RTS2,   GPIO_FN_SIM_D,  GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST,
 
         /* PTY (mobule: LBSC) */
         GPIO_FN_D7,     GPIO_FN_D6,     GPIO_FN_D5,     GPIO_FN_D4,
         GPIO_FN_D3,     GPIO_FN_D2,     GPIO_FN_D1,     GPIO_FN_D0,
+
+        /* PTZ (mobule: eMMC, ONFI) */
+        GPIO_FN_MMCDAT7,        GPIO_FN_MMCDAT6,        GPIO_FN_MMCDAT5,
+        GPIO_FN_MMCDAT4,        GPIO_FN_MMCDAT3,        GPIO_FN_MMCDAT2,
+        GPIO_FN_MMCDAT1,        GPIO_FN_MMCDAT0,
+        GPIO_FN_ON_DQ7, GPIO_FN_ON_DQ6, GPIO_FN_ON_DQ5, GPIO_FN_ON_DQ4,
+        GPIO_FN_ON_DQ3, GPIO_FN_ON_DQ2, GPIO_FN_ON_DQ1, GPIO_FN_ON_DQ0,
 };
 
+enum {
+        SHDMA_SLAVE_INVALID,
+        SHDMA_SLAVE_SDHI_TX,
+        SHDMA_SLAVE_SDHI_RX,
+        SHDMA_SLAVE_MMCIF_TX,
+        SHDMA_SLAVE_MMCIF_RX,
+        SHDMA_SLAVE_SCIF2_TX,
+        SHDMA_SLAVE_SCIF2_RX,
+        SHDMA_SLAVE_SCIF3_TX,
+        SHDMA_SLAVE_SCIF3_RX,
+        SHDMA_SLAVE_SCIF4_TX,
+        SHDMA_SLAVE_SCIF4_RX,
+        SHDMA_SLAVE_RIIC0_TX,
+        SHDMA_SLAVE_RIIC0_RX,
+        SHDMA_SLAVE_RIIC1_TX,
+        SHDMA_SLAVE_RIIC1_RX,
+        SHDMA_SLAVE_RIIC2_TX,
+        SHDMA_SLAVE_RIIC2_RX,
+        SHDMA_SLAVE_RIIC3_TX,
+        SHDMA_SLAVE_RIIC3_RX,
+        SHDMA_SLAVE_RIIC4_TX,
+        SHDMA_SLAVE_RIIC4_RX,
+        SHDMA_SLAVE_RIIC5_TX,
+        SHDMA_SLAVE_RIIC5_RX,
+        SHDMA_SLAVE_RIIC6_TX,
+        SHDMA_SLAVE_RIIC6_RX,
+        SHDMA_SLAVE_RIIC7_TX,
+        SHDMA_SLAVE_RIIC7_RX,
+        SHDMA_SLAVE_RIIC8_TX,
+        SHDMA_SLAVE_RIIC8_RX,
+        SHDMA_SLAVE_RIIC9_TX,
+        SHDMA_SLAVE_RIIC9_RX,
+};
 #endif /* __ASM_SH7757_H__ */
diff --git a/arch/sh/include/cpu-sh4/cpu/shx3.h b/arch/sh/include/cpu-sh4/cpu/shx3.h
new file mode 100644
index 000000000000..68d9080a8da9
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/shx3.h
@@ -0,0 +1,64 @@
+#ifndef __CPU_SHX3_H
+#define __CPU_SHX3_H
+
+enum {
+        /* PA */
+        GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
+        GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
+
+        /* PB */
+        GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
+        GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
+
+        /* PC */
+        GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
+        GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
+
+        /* PD */
+        GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
+        GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
+
+        /* PE */
+        GPIO_PE7, GPIO_PE6, GPIO_PE5, GPIO_PE4,
+        GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0,
+
+        /* PF */
+        GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
+        GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
+
+        /* PG */
+        GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
+        GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
+
+        /* PH */
+        GPIO_PH5, GPIO_PH4,
+        GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
+
+        /* SCIF */
+        GPIO_FN_SCK3, GPIO_FN_TXD3, GPIO_FN_RXD3,
+        GPIO_FN_SCK2, GPIO_FN_TXD2, GPIO_FN_RXD2,
+        GPIO_FN_SCK1, GPIO_FN_TXD1, GPIO_FN_RXD1,
+        GPIO_FN_SCK0, GPIO_FN_TXD0, GPIO_FN_RXD0,
+
+        /* LBSC */
+        GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28,
+        GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24,
+        GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20,
+        GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16,
+        GPIO_FN_WE3, GPIO_FN_WE2, GPIO_FN_CS6, GPIO_FN_CS5,
+        GPIO_FN_CS4, GPIO_FN_CLKOUTENB, GPIO_FN_BREQ,
+        GPIO_FN_IOIS16, GPIO_FN_CE2B, GPIO_FN_CE2A, GPIO_FN_BACK,
+
+        /* DMAC */
+        GPIO_FN_DACK0, GPIO_FN_DREQ0, GPIO_FN_DRAK0,
+        GPIO_FN_DACK1, GPIO_FN_DREQ1, GPIO_FN_DRAK1,
+        GPIO_FN_DACK2, GPIO_FN_DREQ2, GPIO_FN_DRAK2,
+        GPIO_FN_DACK3, GPIO_FN_DREQ3, GPIO_FN_DRAK3,
+
+        /* INTC */
+        GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0,
+        GPIO_FN_IRL3, GPIO_FN_IRL2, GPIO_FN_IRL1, GPIO_FN_IRL0,
+        GPIO_FN_IRQOUT, GPIO_FN_STATUS1, GPIO_FN_STATUS0,
+};
+
+#endif /* __CPU_SHX3_H */
diff --git a/arch/sh/include/mach-common/mach/edosk7705.h b/arch/sh/include/mach-common/mach/edosk7705.h
deleted file mode 100644
index efc43b323466..000000000000
--- a/arch/sh/include/mach-common/mach/edosk7705.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_SH_EDOSK7705_H
-#define __ASM_SH_EDOSK7705_H
-
-#define __IO_PREFIX sh_edosk7705
-#include <asm/io_generic.h>
-
-#endif /* __ASM_SH_EDOSK7705_H */
diff --git a/arch/sh/include/mach-common/mach/highlander.h b/arch/sh/include/mach-common/mach/highlander.h
index 5d9d4d5154be..6ce944e33e59 100644
--- a/arch/sh/include/mach-common/mach/highlander.h
+++ b/arch/sh/include/mach-common/mach/highlander.h
@@ -24,7 +24,7 @@
 #define PA_OBLED        (PA_BCR+0x001c) /* On Board LED control */
 #define PA_OBSW         (PA_BCR+0x001e) /* On Board Switch control */
 #define PA_AUDIOSEL     (PA_BCR+0x0020) /* Sound Interface Select control */
-#define PA_EXTPLR       (PA_BCR+0x001e) /* Extention Pin Polarity control */
+#define PA_EXTPLR       (PA_BCR+0x001e) /* Extension Pin Polarity control */
 #define PA_TPCTL        (PA_BCR+0x0100) /* Touch Panel Access control */
 #define PA_TPDCKCTL     (PA_BCR+0x0102) /* Touch Panel Access data control */
 #define PA_TPCTLCLR     (PA_BCR+0x0104) /* Touch Panel Access control */
@@ -89,7 +89,7 @@
 #define PA_OBLED        (PA_BCR+0x0018) /* On Board LED control */
 #define PA_OBSW         (PA_BCR+0x001a) /* On Board Switch control */
 #define PA_AUDIOSEL     (PA_BCR+0x001c) /* Sound Interface Select control */
-#define PA_EXTPLR       (PA_BCR+0x001e) /* Extention Pin Polarity control */
+#define PA_EXTPLR       (PA_BCR+0x001e) /* Extension Pin Polarity control */
 #define PA_TPCTL        (PA_BCR+0x0100) /* Touch Panel Access control */
 #define PA_TPDCKCTL     (PA_BCR+0x0102) /* Touch Panel Access data control */
 #define PA_TPCTLCLR     (PA_BCR+0x0104) /* Touch Panel Access control */
diff --git a/arch/sh/include/mach-common/mach/microdev.h b/arch/sh/include/mach-common/mach/microdev.h
index 1aed15856e11..dcb05fa8c164 100644
--- a/arch/sh/include/mach-common/mach/microdev.h
+++ b/arch/sh/include/mach-common/mach/microdev.h
@@ -68,13 +68,4 @@ extern void microdev_print_fpga_intc_status(void);
 #define __IO_PREFIX microdev
 #include <asm/io_generic.h>
 
-#if defined(CONFIG_PCI)
-unsigned char  microdev_pci_inb(unsigned long port);
-unsigned short microdev_pci_inw(unsigned long port);
-unsigned long  microdev_pci_inl(unsigned long port);
-void           microdev_pci_outb(unsigned char  data, unsigned long port);
-void           microdev_pci_outw(unsigned short data, unsigned long port);
-void           microdev_pci_outl(unsigned long  data, unsigned long port);
-#endif
-
 #endif /* __ASM_SH_MICRODEV_H */
diff --git a/arch/sh/include/mach-common/mach/r2d.h b/arch/sh/include/mach-common/mach/r2d.h
index 0a800157b826..e04f75eaa153 100644
--- a/arch/sh/include/mach-common/mach/r2d.h
+++ b/arch/sh/include/mach-common/mach/r2d.h
@@ -18,18 +18,18 @@
 #define PA_DISPCTL      0xa4000008      /* Display Timing control */
 #define PA_SDMPOW       0xa400000a      /* SD Power control */
 #define PA_RTCCE        0xa400000c      /* RTC(9701) Enable control */
-#define PA_PCICD        0xa400000e      /* PCI Extention detect control */
+#define PA_PCICD        0xa400000e      /* PCI Extension detect control */
 #define PA_VOYAGERRTS   0xa4000020      /* VOYAGER Reset control */
 
 #define PA_R2D1_AXRST           0xa4000022      /* AX_LAN Reset control */
 #define PA_R2D1_CFRST           0xa4000024      /* CF Reset control */
 #define PA_R2D1_ADMRTS          0xa4000026      /* SD Reset control */
-#define PA_R2D1_EXTRST          0xa4000028      /* Extention Reset control */
+#define PA_R2D1_EXTRST          0xa4000028      /* Extension Reset control */
 #define PA_R2D1_CFCDINTCLR      0xa400002a      /* CF Insert Interrupt clear */
 
 #define PA_R2DPLUS_CFRST        0xa4000022      /* CF Reset control */
 #define PA_R2DPLUS_ADMRTS       0xa4000024      /* SD Reset control */
-#define PA_R2DPLUS_EXTRST       0xa4000026      /* Extention Reset control */
+#define PA_R2DPLUS_EXTRST       0xa4000026      /* Extension Reset control */
 #define PA_R2DPLUS_CFCDINTCLR   0xa4000028      /* CF Insert Interrupt clear */
 #define PA_R2DPLUS_KEYCTLCLR    0xa400002a      /* Key Interrupt clear */
 
diff --git a/arch/sh/include/mach-common/mach/romimage.h b/arch/sh/include/mach-common/mach/romimage.h
index 08fb42269ecd..3670455faaac 100644
--- a/arch/sh/include/mach-common/mach/romimage.h
+++ b/arch/sh/include/mach-common/mach/romimage.h
@@ -4,7 +4,7 @@
 
 #else /* __ASSEMBLY__ */
 
-extern inline void mmcif_update_progress(int nr)
+static inline void mmcif_update_progress(int nr)
 {
 }
 
diff --git a/arch/sh/include/mach-common/mach/snapgear.h b/arch/sh/include/mach-common/mach/secureedge5410.h
index 042d95f51c4d..3653b9a4bacc 100644
--- a/arch/sh/include/mach-common/mach/snapgear.h
+++ b/arch/sh/include/mach-common/mach/secureedge5410.h
@@ -12,30 +12,9 @@
 #ifndef _ASM_SH_IO_SNAPGEAR_H
 #define _ASM_SH_IO_SNAPGEAR_H
 
-#if defined(CONFIG_CPU_SH4)
-/*
- * The external interrupt lines, these take up ints 0 - 15 inclusive
- * depending on the priority for the interrupt.  In fact the priority
- * is the interrupt :-)
- */
-
-#define IRL0_IRQ        2
-#define IRL0_PRIORITY   13
-
-#define IRL1_IRQ        5
-#define IRL1_PRIORITY   10
-
-#define IRL2_IRQ        8
-#define IRL2_PRIORITY   7
-
-#define IRL3_IRQ        11
-#define IRL3_PRIORITY   4
-#endif
-
 #define __IO_PREFIX     snapgear
 #include <asm/io_generic.h>
 
-#ifdef CONFIG_SH_SECUREEDGE5410
 /*
  * We need to remember what was written to the ioport as some bits
  * are shared with other functions and you cannot read back what was
@@ -66,6 +45,5 @@ extern unsigned short secureedge5410_ioport;
                         ((secureedge5410_ioport & ~(mask)) | ((val) & (mask)))))
 #define SECUREEDGE_READ_IOPORT() \
          ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817))
-#endif
 
 #endif /* _ASM_SH_IO_SNAPGEAR_H */
diff --git a/arch/sh/include/mach-common/mach/sh2007.h b/arch/sh/include/mach-common/mach/sh2007.h
new file mode 100644
index 000000000000..48180b9aa03d
--- /dev/null
+++ b/arch/sh/include/mach-common/mach/sh2007.h
@@ -0,0 +1,117 @@
+#ifndef __MACH_SH2007_H
+#define __MACH_SH2007_H
+
+#define CS5BCR          0xff802050
+#define CS5WCR          0xff802058
+#define CS5PCR          0xff802070
+
+#define BUS_SZ8         1
+#define BUS_SZ16        2
+#define BUS_SZ32        3
+
+#define PCMCIA_IODYN    1
+#define PCMCIA_ATA      0
+#define PCMCIA_IO8      2
+#define PCMCIA_IO16     3
+#define PCMCIA_COMM8    4
+#define PCMCIA_COMM16   5
+#define PCMCIA_ATTR8    6
+#define PCMCIA_ATTR16   7
+
+#define TYPE_SRAM       0
+#define TYPE_PCMCIA     4
+
+/* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
+#define IWW5            0
+#define IWW6            3
+/* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
+#define IWRWD5          2
+#define IWRWD6          2
+/* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
+#define IWRWS5          2
+#define IWRWS6          2
+/* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
+#define IWRRD5          2
+#define IWRRD6          2
+/* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */
+#define IWRRS5          0
+#define IWRRS6          2
+/* burst count (0-3:4,8,16,32) */
+#define BST5            0
+#define BST6            0
+/* bus size */
+#define SZ5             BUS_SZ16
+#define SZ6             BUS_SZ16
+/* RD hold for SRAM (0-1:0,1) */
+#define RDSPL5          0
+#define RDSPL6          0
+/* Burst pitch (0-7:0,1,2,3,4,5,6,7) */
+#define BW5             0
+#define BW6             0
+/* Multiplex (0-1:0,1) */
+#define MPX5            0
+#define MPX6            0
+/* device type */
+#define TYPE5           TYPE_PCMCIA
+#define TYPE6           TYPE_PCMCIA
+/* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
+#define ADS5            0
+#define ADS6            0
+/* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */
+#define ADH5            0
+#define ADH6            0
+/* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
+#define RDS5            0
+#define RDS6            0
+/* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
+#define RDH5            0
+#define RDH6            0
+/* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
+#define WTS5            0
+#define WTS6            0
+/* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */
+#define WTH5            0
+#define WTH6            0
+/* BS hold (0-1:1,2) */
+#define BSH5            0
+#define BSH6            0
+/* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
+#define IW5             6       /* 60ns PIO mode 4 */
+#define IW6             15      /* 250ns */
+
+#define SAA5            PCMCIA_IODYN    /* IDE area b4000000-b5ffffff */
+#define SAB5            PCMCIA_IODYN    /* CF  area b6000000-b7ffffff */
+#define PCWA5           0       /* additional wait A (0-3:0,15,30,50) */
+#define PCWB5           0       /* additional wait B (0-3:0,15,30,50) */
+/* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */
+#define PCIW5           12
+/* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */
+#define TEDA5           2
+/* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */
+#define TEDB5           4
+/* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */
+#define TEHA5           2
+/* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */
+#define TEHB5           3
+
+#define CS5BCR_D        ((IWW5<<28)|(IWRWD5<<24)|(IWRWS5<<20)|          \
+                        (IWRRD5<<16)|(IWRRS5<<12)|(BST5<<10)|           \
+                        (SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5)
+#define CS5WCR_D        ((ADS5<<28)|(ADH5<<24)|(RDS5<<20)|      \
+                        (RDH5<<16)|(WTS5<<12)|(WTH5<<8)|(BSH5<<4)|IW5)
+#define CS5PCR_D        ((SAA5<<28)|(SAB5<<24)|(PCWA5<<22)|             \
+                        (PCWB5<<20)|(PCIW5<<16)|(TEDA5<<12)|            \
+                        (TEDB5<<8)|(TEHA5<<4)|TEHB5)
+
+#define SMC0_BASE       0xb0800000      /* eth0 */
+#define SMC1_BASE       0xb0900000      /* eth1 */
+#define CF_BASE         0xb6100000      /* Compact Flash (I/O area) */
+#define IDE_BASE        0xb4000000      /* IDE */
+#define PC104_IO_BASE   0xb8000000
+#define PC104_MEM_BASE  0xba000000
+#define SMC_IO_SIZE     0x100
+
+#define CF_OFFSET       0x1f0
+#define IDE_OFFSET      0x170
+
+#endif /* __MACH_SH2007_H */
diff --git a/arch/sh/include/mach-common/mach/systemh7751.h b/arch/sh/include/mach-common/mach/systemh7751.h
deleted file mode 100644
index 4161122c84ef..000000000000
--- a/arch/sh/include/mach-common/mach/systemh7751.h
+++ /dev/null
@@ -1,71 +0,0 @@
-#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H
-#define __ASM_SH_SYSTEMH_7751SYSTEMH_H
-
-/*
- * linux/include/asm-sh/systemh/7751systemh.h
- *
- * Copyright (C) 2000  Kazumoto Kojima
- *
- * Hitachi SystemH support
-
- * Modified for 7751 SystemH by
- * Jonathan Short, 2002.
- */
-
-/* Box specific addresses.  */
-
-#define PA_ROM          0x00000000      /* EPROM */
-#define PA_ROM_SIZE     0x00400000      /* EPROM size 4M byte */
-#define PA_FROM         0x01000000      /* EPROM */
-#define PA_FROM_SIZE    0x00400000      /* EPROM size 4M byte */
-#define PA_EXT1         0x04000000
-#define PA_EXT1_SIZE    0x04000000
-#define PA_EXT2         0x08000000
-#define PA_EXT2_SIZE    0x04000000
-#define PA_SDRAM        0x0c000000
-#define PA_SDRAM_SIZE   0x04000000
-
-#define PA_EXT4         0x12000000
-#define PA_EXT4_SIZE    0x02000000
-#define PA_EXT5         0x14000000
-#define PA_EXT5_SIZE    0x04000000
-#define PA_PCIC         0x18000000      /* MR-SHPC-01 PCMCIA */
-
-#define PA_DIPSW0       0xb9000000      /* Dip switch 5,6 */
-#define PA_DIPSW1       0xb9000002      /* Dip switch 7,8 */
-#define PA_LED          0xba000000      /* LED */
-#define PA_BCR          0xbb000000      /* FPGA on the MS7751SE01 */
-
-#define PA_MRSHPC       0xb83fffe0      /* MR-SHPC-01 PCMCIA controller */
-#define PA_MRSHPC_MW1   0xb8400000      /* MR-SHPC-01 memory window base */
-#define PA_MRSHPC_MW2   0xb8500000      /* MR-SHPC-01 attribute window base */
-#define PA_MRSHPC_IO    0xb8600000      /* MR-SHPC-01 I/O window base */
-#define MRSHPC_MODE     (PA_MRSHPC + 4)
-#define MRSHPC_OPTION   (PA_MRSHPC + 6)
-#define MRSHPC_CSR      (PA_MRSHPC + 8)
-#define MRSHPC_ISR      (PA_MRSHPC + 10)
-#define MRSHPC_ICR      (PA_MRSHPC + 12)
-#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
-#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
-#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
-#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
-#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
-#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
-#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
-#define MRSHPC_CDCR     (PA_MRSHPC + 28)
-#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
-
-#define BCR_ILCRA       (PA_BCR + 0)
-#define BCR_ILCRB       (PA_BCR + 2)
-#define BCR_ILCRC       (PA_BCR + 4)
-#define BCR_ILCRD       (PA_BCR + 6)
-#define BCR_ILCRE       (PA_BCR + 8)
-#define BCR_ILCRF       (PA_BCR + 10)
-#define BCR_ILCRG       (PA_BCR + 12)
-
-#define IRQ_79C973      13
-
-#define __IO_PREFIX     sh7751systemh
-#include <asm/io_generic.h>
-
-#endif  /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */
diff --git a/arch/sh/include/mach-ecovec24/mach/romimage.h b/arch/sh/include/mach-ecovec24/mach/romimage.h
index 1dcf5e6c8d83..d63ef51ec186 100644
--- a/arch/sh/include/mach-ecovec24/mach/romimage.h
+++ b/arch/sh/include/mach-ecovec24/mach/romimage.h
@@ -35,7 +35,7 @@
 #define HIZCRA          0xa4050158
 #define PGDR            0xa405012c
 
-extern inline void mmcif_update_progress(int nr)
+static inline void mmcif_update_progress(int nr)
 {
         /* disable Hi-Z for LED pins */
         __raw_writew(__raw_readw(HIZCRA) & ~(1 << 1), HIZCRA);
diff --git a/arch/sh/include/mach-kfr2r09/mach/romimage.h b/arch/sh/include/mach-kfr2r09/mach/romimage.h
index 976256a323f2..7a883167c846 100644
--- a/arch/sh/include/mach-kfr2r09/mach/romimage.h
+++ b/arch/sh/include/mach-kfr2r09/mach/romimage.h
@@ -23,7 +23,7 @@
 
 #else /* __ASSEMBLY__ */
 
-extern inline void mmcif_update_progress(int nr)
+static inline void mmcif_update_progress(int nr)
 {
 }
 
diff --git a/arch/sh/include/mach-landisk/mach/iodata_landisk.h b/arch/sh/include/mach-landisk/mach/iodata_landisk.h
index 6fb04ab38b9f..f432773a9571 100644
--- a/arch/sh/include/mach-landisk/mach/iodata_landisk.h
+++ b/arch/sh/include/mach-landisk/mach/iodata_landisk.h
@@ -2,7 +2,7 @@
 #define __ASM_SH_IODATA_LANDISK_H
 
 /*
- * linux/include/asm-sh/landisk/iodata_landisk.h
+ * arch/sh/include/mach-landisk/mach/iodata_landisk.h
  *
  * Copyright (C) 2000  Atom Create Engineering Co., Ltd.
  *
@@ -27,7 +27,7 @@
 
 #define IRQ_PCIINTA     5               /* PCI INTA IRQ */
 #define IRQ_PCIINTB     6               /* PCI INTB IRQ */
-#define IRQ_PCIINDC     7               /* PCI INTC IRQ */
+#define IRQ_PCIINTC     7               /* PCI INTC IRQ */
 #define IRQ_PCIINTD     8               /* PCI INTD IRQ */
 #define IRQ_ATA         9               /* ATA IRQ */
 #define IRQ_FATA        10              /* FATA IRQ */
@@ -35,6 +35,8 @@
 #define IRQ_BUTTON      12              /* USL-5P Button IRQ */
 #define IRQ_FAULT       13              /* USL-5P Fault  IRQ */
 
+void init_landisk_IRQ(void);
+
 #define __IO_PREFIX landisk
 #include <asm/io_generic.h>
 
diff --git a/arch/sh/include/mach-sdk7786/mach/fpga.h b/arch/sh/include/mach-sdk7786/mach/fpga.h
index 416b621d94d1..a9cdac469927 100644
--- a/arch/sh/include/mach-sdk7786/mach/fpga.h
+++ b/arch/sh/include/mach-sdk7786/mach/fpga.h
@@ -14,11 +14,16 @@
 #define INTTESTR        0x040
 #define SYSSR           0x050
 #define NRGPR           0x060
+
 #define NMISR           0x070
+#define  NMISR_MAN_NMI  BIT(0)
+#define  NMISR_AUX_NMI  BIT(1)
+#define  NMISR_MASK     (NMISR_MAN_NMI | NMISR_AUX_NMI)
 
 #define NMIMR           0x080
 #define  NMIMR_MAN_NMIM BIT(0)  /* Manual NMI mask */
 #define  NMIMR_AUX_NMIM BIT(1)  /* Auxiliary NMI mask */
+#define  NMIMR_MASK     (NMIMR_MAN_NMIM | NMIMR_AUX_NMIM)
 
 #define INTBSR          0x090
 #define INTBMR          0x0a0
@@ -31,11 +36,35 @@
 #define EXTASR          0x110
 #define SPCAR           0x120
 #define INTMSR          0x130
+
 #define PCIECR          0x140
+#define  PCIECR_PCIEMUX1        BIT(15)
+#define  PCIECR_PCIEMUX0        BIT(14)
+#define  PCIECR_PRST4           BIT(12) /* slot 4 card present */
+#define  PCIECR_PRST3           BIT(11) /* slot 3 card present */
+#define  PCIECR_PRST2           BIT(10) /* slot 2 card present */
+#define  PCIECR_PRST1           BIT(9)  /* slot 1 card present */
+#define  PCIECR_CLKEN           BIT(4)  /* oscillator enable */
+
 #define FAER            0x150
 #define USRGPIR         0x160
+
 /* 0x170 reserved */
-#define LCLASR          0x180
+
+#define LCLASR                  0x180
+#define  LCLASR_FRAMEN          BIT(15)
+
+#define  LCLASR_FPGA_SEL_SHIFT  12
+#define  LCLASR_NAND_SEL_SHIFT  8
+#define  LCLASR_NORB_SEL_SHIFT  4
+#define  LCLASR_NORA_SEL_SHIFT  0
+
+#define  LCLASR_AREA_MASK       0x7
+
+#define  LCLASR_FPGA_SEL_MASK   (LCLASR_AREA_MASK << LCLASR_FPGA_SEL_SHIFT)
+#define  LCLASR_NAND_SEL_MASK   (LCLASR_AREA_MASK << LCLASR_NAND_SEL_SHIFT)
+#define  LCLASR_NORB_SEL_MASK   (LCLASR_AREA_MASK << LCLASR_NORB_SEL_SHIFT)
+#define  LCLASR_NORA_SEL_MASK   (LCLASR_AREA_MASK << LCLASR_NORA_SEL_SHIFT)
 
 #define SBCR            0x190
 #define  SCBR_I2CMEN    BIT(0)  /* FPGA I2C master enable */
@@ -102,6 +131,9 @@
 extern void __iomem *sdk7786_fpga_base;
 extern void sdk7786_fpga_init(void);
 
+/* arch/sh/boards/mach-sdk7786/nmi.c */
+extern void sdk7786_nmi_init(void);
+
 #define SDK7786_FPGA_REGADDR(reg)       (sdk7786_fpga_base + (reg))
 
 /*
diff --git a/arch/sh/include/mach-x3proto/mach/hardware.h b/arch/sh/include/mach-x3proto/mach/hardware.h
new file mode 100644
index 000000000000..52bca57bfeb6
--- /dev/null
+++ b/arch/sh/include/mach-x3proto/mach/hardware.h
@@ -0,0 +1,12 @@
+#ifndef __MACH_X3PROTO_HARDWARE_H
+#define __MACH_X3PROTO_HARDWARE_H
+
+struct gpio_chip;
+
+/* arch/sh/boards/mach-x3proto/gpio.c */
+int x3proto_gpio_setup(void);
+extern struct gpio_chip x3proto_gpio_chip;
+
+#define NR_BASEBOARD_GPIOS      16
+
+#endif /* __MACH_X3PROTO_HARDWARE_H */
diff --git a/arch/sh/include/asm/ilsel.h b/arch/sh/include/mach-x3proto/mach/ilsel.h
index e3d304b280f6..e3d304b280f6 100644
--- a/arch/sh/include/asm/ilsel.h
+++ b/arch/sh/include/mach-x3proto/mach/ilsel.h
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile
index e25f3c69525d..77f7ae1d4647 100644
--- a/arch/sh/kernel/Makefile
+++ b/arch/sh/kernel/Makefile
@@ -11,15 +11,20 @@ endif
 
 CFLAGS_REMOVE_return_address.o = -pg
 
-obj-y   := clkdev.o debugtraps.o dma-nommu.o dumpstack.o                \
-           idle.o io.o irq.o                                            \
-           irq_$(BITS).o machvec.o nmi_debug.o process.o                \
-           process_$(BITS).o ptrace_$(BITS).o                           \
+obj-y   := debugtraps.o dma-nommu.o dumpstack.o                 \
+           idle.o io.o irq.o irq_$(BITS).o kdebugfs.o                   \
+           machvec.o nmi_debug.o process.o                              \
+           process_$(BITS).o ptrace.o ptrace_$(BITS).o                  \
            reboot.o return_address.o                                    \
            setup.o signal_$(BITS).o sys_sh.o sys_sh$(BITS).o            \
            syscalls_$(BITS).o time.o topology.o traps.o                 \
            traps_$(BITS).o unwinder.o
 
+ifndef CONFIG_GENERIC_IOMAP
+obj-y                           += iomap.o
+obj-$(CONFIG_HAS_IOPORT)        += ioport.o
+endif
+
 obj-y                           += cpu/
 obj-$(CONFIG_VSYSCALL)          += vsyscall/
 obj-$(CONFIG_SMP)               += smp.o
@@ -39,9 +44,8 @@ obj-$(CONFIG_DUMP_CODE)		+= disassemble.o
 obj-$(CONFIG_HIBERNATION)       += swsusp.o
 obj-$(CONFIG_DWARF_UNWINDER)    += dwarf.o
 obj-$(CONFIG_PERF_EVENTS)       += perf_event.o perf_callchain.o
-obj-$(CONFIG_HAS_IOPORT)        += io_generic.o
 
 obj-$(CONFIG_HAVE_HW_BREAKPOINT)                += hw_breakpoint.o
 obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)     += localtimer.o
 
-EXTRA_CFLAGS += -Werror
+ccflags-y := -Werror
diff --git a/arch/sh/kernel/clkdev.c b/arch/sh/kernel/clkdev.c
deleted file mode 100644
index befc255830a4..000000000000
--- a/arch/sh/kernel/clkdev.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * arch/sh/kernel/clkdev.c
- *
- * Cloned from arch/arm/common/clkdev.c:
- *
- *  Copyright (C) 2008 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Helper for the clk API to assist looking up a struct clk.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/mutex.h>
-#include <linux/clk.h>
-#include <linux/slab.h>
-#include <linux/bootmem.h>
-#include <linux/mm.h>
-#include <asm/clock.h>
-#include <asm/clkdev.h>
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-/*
- * Find the correct struct clk for the device and connection ID.
- * We do slightly fuzzy matching here:
- *  An entry with a NULL ID is assumed to be a wildcard.
- *  If an entry has a device ID, it must match
- *  If an entry has a connection ID, it must match
- * Then we take the most specific entry - with the following
- * order of precedence: dev+con > dev only > con only.
- */
-static struct clk *clk_find(const char *dev_id, const char *con_id)
-{
-        struct clk_lookup *p;
-        struct clk *clk = NULL;
-        int match, best = 0;
-
-        list_for_each_entry(p, &clocks, node) {
-                match = 0;
-                if (p->dev_id) {
-                        if (!dev_id || strcmp(p->dev_id, dev_id))
-                                continue;
-                        match += 2;
-                }
-                if (p->con_id) {
-                        if (!con_id || strcmp(p->con_id, con_id))
-                                continue;
-                        match += 1;
-                }
-                if (match == 0)
-                        continue;
-
-                if (match > best) {
-                        clk = p->clk;
-                        best = match;
-                }
-        }
-        return clk;
-}
-
-struct clk *clk_get_sys(const char *dev_id, const char *con_id)
-{
-        struct clk *clk;
-
-        mutex_lock(&clocks_mutex);
-        clk = clk_find(dev_id, con_id);
-        mutex_unlock(&clocks_mutex);
-
-        return clk ? clk : ERR_PTR(-ENOENT);
-}
-EXPORT_SYMBOL(clk_get_sys);
-
-void clkdev_add(struct clk_lookup *cl)
-{
-        mutex_lock(&clocks_mutex);
-        list_add_tail(&cl->node, &clocks);
-        mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clkdev_add);
-
-void __init clkdev_add_table(struct clk_lookup *cl, size_t num)
-{
-        mutex_lock(&clocks_mutex);
-        while (num--) {
-                list_add_tail(&cl->node, &clocks);
-                cl++;
-        }
-        mutex_unlock(&clocks_mutex);
-}
-
-#define MAX_DEV_ID      20
-#define MAX_CON_ID      16
-
-struct clk_lookup_alloc {
-        struct clk_lookup cl;
-        char    dev_id[MAX_DEV_ID];
-        char    con_id[MAX_CON_ID];
-};
-
-struct clk_lookup * __init_refok
-clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
-{
-        struct clk_lookup_alloc *cla;
-
-        if (!slab_is_available())
-                cla = alloc_bootmem_low_pages(sizeof(*cla));
-        else
-                cla = kzalloc(sizeof(*cla), GFP_KERNEL);
-
-        if (!cla)
-                return NULL;
-
-        cla->cl.clk = clk;
-        if (con_id) {
-                strlcpy(cla->con_id, con_id, sizeof(cla->con_id));
-                cla->cl.con_id = cla->con_id;
-        }
-
-        if (dev_fmt) {
-                va_list ap;
-
-                va_start(ap, dev_fmt);
-                vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
-                cla->cl.dev_id = cla->dev_id;
-                va_end(ap);
-        }
-
-        return &cla->cl;
-}
-EXPORT_SYMBOL(clkdev_alloc);
-
-int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
-        struct device *dev)
-{
-        struct clk *r = clk_get(dev, id);
-        struct clk_lookup *l;
-
-        if (IS_ERR(r))
-                return PTR_ERR(r);
-
-        l = clkdev_alloc(r, alias, alias_dev_name);
-        clk_put(r);
-        if (!l)
-                return -ENODEV;
-        clkdev_add(l);
-        return 0;
-}
-EXPORT_SYMBOL(clk_add_alias);
-
-/*
- * clkdev_drop - remove a clock dynamically allocated
- */
-void clkdev_drop(struct clk_lookup *cl)
-{
-        mutex_lock(&clocks_mutex);
-        list_del(&cl->node);
-        mutex_unlock(&clocks_mutex);
-        kfree(cl);
-}
-EXPORT_SYMBOL(clkdev_drop);
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index 4edcb60a1355..ae95935d93cd 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -17,7 +17,5 @@ obj-$(CONFIG_ARCH_SHMOBILE)	+= shmobile/
 
 obj-$(CONFIG_SH_ADC)            += adc.o
 obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
-obj-$(CONFIG_SH_FPU)            += fpu.o
-obj-$(CONFIG_SH_FPU_EMU)        += fpu.o
 
-obj-y   += irq/ init.o clock.o hwblk.o
+obj-y   += irq/ init.o clock.o fpu.o hwblk.o proc.o
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
index e2f63d68da51..8f63a264a842 100644
--- a/arch/sh/kernel/cpu/clock-cpg.c
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -2,7 +2,7 @@
 #include <linux/compiler.h>
 #include <linux/slab.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 
 static struct clk master_clk = {
@@ -67,7 +67,7 @@ int __init __deprecated cpg_clk_init(void)
 }
 
 /*
- * Placeholder for compatability, until the lazy CPUs do this
+ * Placeholder for compatibility, until the lazy CPUs do this
  * on their own.
  */
 int __init __weak arch_clk_init(void)
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 50f887dda565..4187cf4fe185 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -48,20 +48,4 @@ int __init clk_init(void)
         return ret;
 }
 
-/*
- * Returns a clock. Note that we first try to use device id on the bus
- * and clock name. If this fails, we try to use clock name only.
- */
-struct clk *clk_get(struct device *dev, const char *con_id)
-{
-        const char *dev_id = dev ? dev_name(dev) : NULL;
-
-        return clk_get_sys(dev_id, con_id);
-}
-EXPORT_SYMBOL_GPL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL_GPL(clk_put);
 
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index 97661061ff20..fac742e514ee 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -340,6 +340,8 @@ asmlinkage void __cpuinit cpu_init(void)
          */
         current_cpu_data.asid_cache = NO_CONTEXT;
 
+        current_cpu_data.phys_bits = __in_29bit_mode() ? 29 : 32;
+
         speculative_execution_init();
         expmask_init();
 
diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c
index a351ed84eec5..39b6a24c159d 100644
--- a/arch/sh/kernel/cpu/irq/imask.c
+++ b/arch/sh/kernel/cpu/irq/imask.c
@@ -51,16 +51,20 @@ static inline void set_interrupt_registers(int ip)
                      : "t");
 }
 
-static void mask_imask_irq(unsigned int irq)
+static void mask_imask_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
+
         clear_bit(irq, imask_mask);
         if (interrupt_priority < IMASK_PRIORITY - irq)
                 interrupt_priority = IMASK_PRIORITY - irq;
         set_interrupt_registers(interrupt_priority);
 }
 
-static void unmask_imask_irq(unsigned int irq)
+static void unmask_imask_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
+
         set_bit(irq, imask_mask);
         interrupt_priority = IMASK_PRIORITY -
                 find_first_zero_bit(imask_mask, IMASK_PRIORITY);
@@ -69,13 +73,13 @@ static void unmask_imask_irq(unsigned int irq)
 
 static struct irq_chip imask_irq_chip = {
         .name           = "SR.IMASK",
-        .mask           = mask_imask_irq,
-        .unmask         = unmask_imask_irq,
-        .mask_ack       = mask_imask_irq,
+        .irq_mask       = mask_imask_irq,
+        .irq_unmask     = unmask_imask_irq,
+        .irq_mask_ack   = mask_imask_irq,
 };
 
 void make_imask_irq(unsigned int irq)
 {
-        set_irq_chip_and_handler_name(irq, &imask_irq_chip,
-                                      handle_level_irq, "level");
+        irq_set_chip_and_handler_name(irq, &imask_irq_chip, handle_level_irq,
+                                      "level");
 }
diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c
index 96a239583948..9e056a3a0c73 100644
--- a/arch/sh/kernel/cpu/irq/intc-sh5.c
+++ b/arch/sh/kernel/cpu/irq/intc-sh5.c
@@ -76,39 +76,11 @@ int intc_evt_to_irq[(0xE20/0x20)+1] = {
 };
 
 static unsigned long intc_virt;
-
-static unsigned int startup_intc_irq(unsigned int irq);
-static void shutdown_intc_irq(unsigned int irq);
-static void enable_intc_irq(unsigned int irq);
-static void disable_intc_irq(unsigned int irq);
-static void mask_and_ack_intc(unsigned int);
-static void end_intc_irq(unsigned int irq);
-
-static struct irq_chip intc_irq_type = {
-        .name = "INTC",
-        .startup = startup_intc_irq,
-        .shutdown = shutdown_intc_irq,
-        .enable = enable_intc_irq,
-        .disable = disable_intc_irq,
-        .ack = mask_and_ack_intc,
-        .end = end_intc_irq
-};
-
 static int irlm;                /* IRL mode */
 
-static unsigned int startup_intc_irq(unsigned int irq)
-{
-        enable_intc_irq(irq);
-        return 0; /* never anything pending */
-}
-
-static void shutdown_intc_irq(unsigned int irq)
-{
-        disable_intc_irq(irq);
-}
-
-static void enable_intc_irq(unsigned int irq)
+static void enable_intc_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned long reg;
         unsigned long bitmask;
 
@@ -126,8 +98,9 @@ static void enable_intc_irq(unsigned int irq)
         __raw_writel(bitmask, reg);
 }
 
-static void disable_intc_irq(unsigned int irq)
+static void disable_intc_irq(struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         unsigned long reg;
         unsigned long bitmask;
 
@@ -142,15 +115,11 @@ static void disable_intc_irq(unsigned int irq)
         __raw_writel(bitmask, reg);
 }
 
-static void mask_and_ack_intc(unsigned int irq)
-{
-        disable_intc_irq(irq);
-}
-
-static void end_intc_irq(unsigned int irq)
-{
-        enable_intc_irq(irq);
-}
+static struct irq_chip intc_irq_type = {
+        .name = "INTC",
+        .irq_enable = enable_intc_irq,
+        .irq_disable = disable_intc_irq,
+};
 
 void __init plat_irq_setup(void)
 {
@@ -166,7 +135,7 @@ void __init plat_irq_setup(void)
 
         /* Set default: per-line enable/disable, priority driven ack/eoi */
         for (i = 0; i < NR_INTC_IRQS; i++)
-                set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
 
 
         /* Disable all interrupts and set all priorities to 0 to avoid trouble */
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 9282d965a1b6..5de6dff5c21b 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -24,25 +24,25 @@
 #include <linux/module.h>
 #include <linux/topology.h>
 
-static inline struct ipr_desc *get_ipr_desc(unsigned int irq)
+static inline struct ipr_desc *get_ipr_desc(struct irq_data *data)
 {
-        struct irq_chip *chip = get_irq_chip(irq);
+        struct irq_chip *chip = irq_data_get_irq_chip(data);
         return container_of(chip, struct ipr_desc, chip);
 }
 
-static void disable_ipr_irq(unsigned int irq)
+static void disable_ipr_irq(struct irq_data *data)
 {
-        struct ipr_data *p = get_irq_chip_data(irq);
-        unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
+        struct ipr_data *p = irq_data_get_irq_chip_data(data);
+        unsigned long addr = get_ipr_desc(data)->ipr_offsets[p->ipr_idx];
         /* Set the priority in IPR to 0 */
         __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr);
         (void)__raw_readw(addr);        /* Read back to flush write posting */
 }
 
-static void enable_ipr_irq(unsigned int irq)
+static void enable_ipr_irq(struct irq_data *data)
 {
-        struct ipr_data *p = get_irq_chip_data(irq);
-        unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
+        struct ipr_data *p = irq_data_get_irq_chip_data(data);
+        unsigned long addr = get_ipr_desc(data)->ipr_offsets[p->ipr_idx];
         /* Set priority in IPR back to original value */
         __raw_writew(__raw_readw(addr) | (p->priority << p->shift), addr);
 }
@@ -56,29 +56,28 @@ void register_ipr_controller(struct ipr_desc *desc)
 {
         int i;
 
-        desc->chip.mask = disable_ipr_irq;
-        desc->chip.unmask = enable_ipr_irq;
-        desc->chip.mask_ack = disable_ipr_irq;
+        desc->chip.irq_mask = disable_ipr_irq;
+        desc->chip.irq_unmask = enable_ipr_irq;
 
         for (i = 0; i < desc->nr_irqs; i++) {
                 struct ipr_data *p = desc->ipr_data + i;
-                struct irq_desc *irq_desc;
+                int res;
 
                 BUG_ON(p->ipr_idx >= desc->nr_offsets);
                 BUG_ON(!desc->ipr_offsets[p->ipr_idx]);
 
-                irq_desc = irq_to_desc_alloc_node(p->irq, numa_node_id());
-                if (unlikely(!irq_desc)) {
+                res = irq_alloc_desc_at(p->irq, numa_node_id());
+                if (unlikely(res != p->irq && res != -EEXIST)) {
                         printk(KERN_INFO "can not get irq_desc for %d\n",
                                p->irq);
                         continue;
                 }
 
                 disable_irq_nosync(p->irq);
-                set_irq_chip_and_handler_name(p->irq, &desc->chip,
-                                      handle_level_irq, "level");
-                set_irq_chip_data(p->irq, p);
-                disable_ipr_irq(p->irq);
+                irq_set_chip_and_handler_name(p->irq, &desc->chip,
+                                              handle_level_irq, "level");
+                irq_set_chip_data(p->irq, p);
+                disable_ipr_irq(irq_get_irq_data(p->irq));
         }
 }
 EXPORT_SYMBOL(register_ipr_controller);
diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c
new file mode 100644
index 000000000000..f47be8727b3b
--- /dev/null
+++ b/arch/sh/kernel/cpu/proc.c
@@ -0,0 +1,148 @@
+#include <linux/seq_file.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/machvec.h>
+#include <asm/processor.h>
+
+static const char *cpu_name[] = {
+        [CPU_SH7201]    = "SH7201",
+        [CPU_SH7203]    = "SH7203",     [CPU_SH7263]    = "SH7263",
+        [CPU_SH7206]    = "SH7206",     [CPU_SH7619]    = "SH7619",
+        [CPU_SH7705]    = "SH7705",     [CPU_SH7706]    = "SH7706",
+        [CPU_SH7707]    = "SH7707",     [CPU_SH7708]    = "SH7708",
+        [CPU_SH7709]    = "SH7709",     [CPU_SH7710]    = "SH7710",
+        [CPU_SH7712]    = "SH7712",     [CPU_SH7720]    = "SH7720",
+        [CPU_SH7721]    = "SH7721",     [CPU_SH7729]    = "SH7729",
+        [CPU_SH7750]    = "SH7750",     [CPU_SH7750S]   = "SH7750S",
+        [CPU_SH7750R]   = "SH7750R",    [CPU_SH7751]    = "SH7751",
+        [CPU_SH7751R]   = "SH7751R",    [CPU_SH7760]    = "SH7760",
+        [CPU_SH4_202]   = "SH4-202",    [CPU_SH4_501]   = "SH4-501",
+        [CPU_SH7763]    = "SH7763",     [CPU_SH7770]    = "SH7770",
+        [CPU_SH7780]    = "SH7780",     [CPU_SH7781]    = "SH7781",
+        [CPU_SH7343]    = "SH7343",     [CPU_SH7785]    = "SH7785",
+        [CPU_SH7786]    = "SH7786",     [CPU_SH7757]    = "SH7757",
+        [CPU_SH7722]    = "SH7722",     [CPU_SHX3]      = "SH-X3",
+        [CPU_SH5_101]   = "SH5-101",    [CPU_SH5_103]   = "SH5-103",
+        [CPU_MXG]       = "MX-G",       [CPU_SH7723]    = "SH7723",
+        [CPU_SH7366]    = "SH7366",     [CPU_SH7724]    = "SH7724",
+        [CPU_SH7372]    = "SH7372",     [CPU_SH_NONE]   = "Unknown"
+};
+
+const char *get_cpu_subtype(struct sh_cpuinfo *c)
+{
+        return cpu_name[c->type];
+}
+EXPORT_SYMBOL(get_cpu_subtype);
+
+#ifdef CONFIG_PROC_FS
+/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
+static const char *cpu_flags[] = {
+        "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
+        "ptea", "llsc", "l2", "op32", "pteaex", NULL
+};
+
+static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
+{
+        unsigned long i;
+
+        seq_printf(m, "cpu flags\t:");
+
+        if (!c->flags) {
+                seq_printf(m, " %s\n", cpu_flags[0]);
+                return;
+        }
+
+        for (i = 0; cpu_flags[i]; i++)
+                if ((c->flags & (1 << i)))
+                        seq_printf(m, " %s", cpu_flags[i+1]);
+
+        seq_printf(m, "\n");
+}
+
+static void show_cacheinfo(struct seq_file *m, const char *type,
+                           struct cache_info info)
+{
+        unsigned int cache_size;
+
+        cache_size = info.ways * info.sets * info.linesz;
+
+        seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",
+                   type, cache_size >> 10, info.ways);
+}
+
+/*
+ *      Get CPU information for use by the procfs.
+ */
+static int show_cpuinfo(struct seq_file *m, void *v)
+{
+        struct sh_cpuinfo *c = v;
+        unsigned int cpu = c - cpu_data;
+
+        if (!cpu_online(cpu))
+                return 0;
+
+        if (cpu == 0)
+                seq_printf(m, "machine\t\t: %s\n", get_system_type());
+        else
+                seq_printf(m, "\n");
+
+        seq_printf(m, "processor\t: %d\n", cpu);
+        seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
+        seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
+        if (c->cut_major == -1)
+                seq_printf(m, "cut\t\t: unknown\n");
+        else if (c->cut_minor == -1)
+                seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
+        else
+                seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
+
+        show_cpuflags(m, c);
+
+        seq_printf(m, "cache type\t: ");
+
+        /*
+         * Check for what type of cache we have, we support both the
+         * unified cache on the SH-2 and SH-3, as well as the harvard
+         * style cache on the SH-4.
+         */
+        if (c->icache.flags & SH_CACHE_COMBINED) {
+                seq_printf(m, "unified\n");
+                show_cacheinfo(m, "cache", c->icache);
+        } else {
+                seq_printf(m, "split (harvard)\n");
+                show_cacheinfo(m, "icache", c->icache);
+                show_cacheinfo(m, "dcache", c->dcache);
+        }
+
+        /* Optional secondary cache */
+        if (c->flags & CPU_HAS_L2_CACHE)
+                show_cacheinfo(m, "scache", c->scache);
+
+        seq_printf(m, "address sizes\t: %u bits physical\n", c->phys_bits);
+
+        seq_printf(m, "bogomips\t: %lu.%02lu\n",
+                     c->loops_per_jiffy/(500000/HZ),
+                     (c->loops_per_jiffy/(5000/HZ)) % 100);
+
+        return 0;
+}
+
+static void *c_start(struct seq_file *m, loff_t *pos)
+{
+        return *pos < NR_CPUS ? cpu_data + *pos : NULL;
+}
+static void *c_next(struct seq_file *m, void *v, loff_t *pos)
+{
+        ++*pos;
+        return c_start(m, pos);
+}
+static void c_stop(struct seq_file *m, void *v)
+{
+}
+const struct seq_operations cpuinfo_op = {
+        .start  = c_start,
+        .next   = c_next,
+        .stop   = c_stop,
+        .show   = show_cpuinfo,
+};
+#endif /* CONFIG_PROC_FS */
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index 0c9f24d7a02f..5b7f12e58a8d 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -14,24 +14,18 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/io.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
-#include <asm/io.h>
+#include <asm/processor.h>
 
 static const int pll1rate[] = {1,2};
 static const int pfc_divisors[] = {1,2,0,4};
-
-#if (CONFIG_SH_CLK_MD == 1) || (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 5) || (CONFIG_SH_CLK_MD == 6)
-#define PLL2 (2)
-#else
-#error "Illigal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
+        clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
 }
 
 static struct clk_ops sh7619_master_clk_ops = {
@@ -70,6 +64,14 @@ static struct clk_ops *sh7619_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN2 | MODE_PIN0) ||
+            test_mode_pin(MODE_PIN2 | MODE_PIN1))
+                pll2_mult = 2;
+        else if (test_mode_pin(MODE_PIN0) || test_mode_pin(MODE_PIN1))
+                pll2_mult = 4;
+
+        BUG_ON(!pll2_mult);
+
         if (idx < ARRAY_SIZE(sh7619_clk_ops))
                 *ops = sh7619_clk_ops[idx];
 }
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index c3638516bffc..0f8befccf9fa 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -62,6 +62,8 @@ static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xf8400000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 88, 88, 88, 88 },
 };
@@ -77,6 +79,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xf8410000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 92, 92, 92, 92 },
 };
@@ -92,6 +96,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xf8420000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 96, 96, 96, 96 },
 };
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index b26264dc2aef..1174e2d96c03 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -22,19 +22,12 @@ static const int pll1rate[]={1,2,3,4,6,8};
 static const int pfc_divisors[]={1,2,3,4,6,8,12};
 #define ifc_divisors pfc_divisors
 
-#if (CONFIG_SH_CLK_MD == 0)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (2)
-#elif (CONFIG_SH_CLK_MD == 3)
-#define PLL2 (1)
-#else
-#error "Illegal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        return 10000000 * PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
+        clk->rate = 10000000 * pll2_mult *
+               pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
 static struct clk_ops sh7201_master_clk_ops = {
@@ -80,6 +73,13 @@ static struct clk_ops *sh7201_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
+                pll2_mult = 1;
+        else if (test_mode_pin(MODE_PIN1))
+                pll2_mult = 2;
+        else
+                pll2_mult = 4;
+
         if (idx < ARRAY_SIZE(sh7201_clk_ops))
                 *ops = sh7201_clk_ops[idx];
 }
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index 7e75d8f79502..95a008e8b735 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -25,21 +25,11 @@ static const int pll1rate[]={8,12,16,0};
 static const int pfc_divisors[]={1,2,3,4,6,8,12};
 #define ifc_divisors pfc_divisors
 
-#if (CONFIG_SH_CLK_MD == 0)
-#define PLL2 (1)
-#elif (CONFIG_SH_CLK_MD == 1)
-#define PLL2 (2)
-#elif (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 3)
-#define PLL2 (4)
-#else
-#error "Illegal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * PLL2 ;
+        clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
 }
 
 static struct clk_ops sh7203_master_clk_ops = {
@@ -79,6 +69,13 @@ static struct clk_ops *sh7203_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN1))
+                pll2_mult = 4;
+        else if (test_mode_pin(MODE_PIN0))
+                pll2_mult = 2;
+        else
+                pll2_mult = 1;
+
         if (idx < ARRAY_SIZE(sh7203_clk_ops))
                 *ops = sh7203_clk_ops[idx];
 }
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index b27a5e2687ab..3c314d7cd6e6 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -22,19 +22,11 @@ static const int pll1rate[]={1,2,3,4,6,8};
 static const int pfc_divisors[]={1,2,3,4,6,8,12};
 #define ifc_divisors pfc_divisors
 
-#if (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 6)
-#define PLL2 (2)
-#elif (CONFIG_SH_CLK_MD == 7)
-#define PLL2 (1)
-#else
-#error "Illigal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
+        clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
 static struct clk_ops sh7206_master_clk_ops = {
@@ -79,7 +71,13 @@ static struct clk_ops *sh7206_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
+                pll2_mult = 1;
+        else if (test_mode_pin(MODE_PIN2 | MODE_PIN1))
+                pll2_mult = 2;
+        else if (test_mode_pin(MODE_PIN1))
+                pll2_mult = 4;
+
         if (idx < ARRAY_SIZE(sh7206_clk_ops))
                 *ops = sh7206_clk_ops[idx];
 }
-
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index 6c96ea02bf8d..949bf2bac28c 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -201,6 +201,8 @@ static struct platform_device mtu2_2_device = {
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xff804000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 220, 220, 220, 220 },
 };
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index d08bf4c07d60..9df558dcdb86 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -180,6 +180,8 @@ static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xfffe8000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 180, 180, 180, 180 }
 };
@@ -195,6 +197,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xfffe8800,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 184, 184, 184, 184 }
 };
@@ -210,6 +214,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xfffe9000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 188, 188, 188, 188 }
 };
@@ -225,6 +231,8 @@ static struct platform_device scif2_device = {
 static struct plat_sci_port scif3_platform_data = {
         .mapbase        = 0xfffe9800,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 192, 192, 192, 192 }
 };
@@ -240,6 +248,8 @@ static struct platform_device scif3_device = {
 static struct plat_sci_port scif4_platform_data = {
         .mapbase        = 0xfffea000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 196, 196, 196, 196 }
 };
@@ -255,6 +265,8 @@ static struct platform_device scif4_device = {
 static struct plat_sci_port scif5_platform_data = {
         .mapbase        = 0xfffea800,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 200, 200, 200, 200 }
 };
@@ -270,6 +282,8 @@ static struct platform_device scif5_device = {
 static struct plat_sci_port scif6_platform_data = {
         .mapbase        = 0xfffeb000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 204, 204, 204, 204 }
 };
@@ -285,6 +299,8 @@ static struct platform_device scif6_device = {
 static struct plat_sci_port scif7_platform_data = {
         .mapbase        = 0xfffeb800,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 208, 208, 208, 208 }
 };
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index 832f401b5860..a43124e608c3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -176,6 +176,8 @@ static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xfffe8000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           =  { 192, 192, 192, 192 },
 };
@@ -191,6 +193,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xfffe8800,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           =  { 196, 196, 196, 196 },
 };
@@ -206,6 +210,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xfffe9000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           =  { 200, 200, 200, 200 },
 };
@@ -221,6 +227,8 @@ static struct platform_device scif2_device = {
 static struct plat_sci_port scif3_platform_data = {
         .mapbase        = 0xfffe9800,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           =  { 204, 204, 204, 204 },
 };
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index dc47b04e1049..5d14f849aea3 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -136,6 +136,8 @@ static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xfffe8000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 240, 240, 240, 240 },
 };
@@ -151,6 +153,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xfffe8800,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 244, 244, 244, 244 },
 };
@@ -166,6 +170,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xfffe9000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 248, 248, 248, 248 },
 };
@@ -181,6 +187,8 @@ static struct platform_device scif2_device = {
 static struct plat_sci_port scif3_platform_data = {
         .mapbase        = 0xfffe9800,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 252, 252, 252, 252 },
 };
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index baadd7f54d94..cd2e702feb7e 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -70,6 +70,9 @@ static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xa4410000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TIE | SCSCR_RIE  | SCSCR_TE |
+                          SCSCR_RE  | SCSCR_CKE1 | SCSCR_CKE0,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
         .type           = PORT_SCIF,
         .irqs           = { 56, 56, 56 },
 };
@@ -85,6 +88,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xa4400000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
         .type           = PORT_SCIF,
         .irqs           = { 52, 52, 52 },
 };
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 3cf8c8ef7b32..4551ad647c2c 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -109,6 +109,8 @@ static struct platform_device rtc_device = {
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xfffffe80,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TE | SCSCR_RE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCI,
         .irqs           = { 23, 23, 23, 0 },
 };
@@ -126,6 +128,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xa4000150,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TE | SCSCR_RE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 56, 56, 56, 56 },
 };
@@ -143,6 +147,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xa4000140,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TE | SCSCR_RE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_IRDA,
         .irqs           = { 52, 52, 52, 52 },
 };
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index b0c2fb4ab479..78f6b01d42c3 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -99,6 +99,9 @@ static struct platform_device rtc_device = {
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xa4400000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
+                          SCSCR_CKE1 | SCSCR_CKE0,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 52, 52, 52, 52 },
 };
@@ -114,6 +117,9 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xa4410000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
+                          SCSCR_CKE1 | SCSCR_CKE0,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 56, 56, 56, 56 },
 };
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 24b17135d5d2..365b94a6fcb7 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -1,5 +1,5 @@
 /*
- * SH7720 Setup
+ * Setup code for SH7720, SH7721.
  *
  *  Copyright (C) 2007  Markus Brunner, Mark Jonas
  *  Copyright (C) 2009  Paul Mundt
@@ -51,6 +51,8 @@ static struct platform_device rtc_device = {
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xa4430000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
         .type           = PORT_SCIF,
         .irqs           = { 80, 80, 80, 80 },
 };
@@ -66,6 +68,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xa4438000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_4,
         .type           = PORT_SCIF,
         .irqs           = { 81, 81, 81, 81 },
 };
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index 4eabc68cd753..3f6f8e98635c 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -13,7 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/err.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 
@@ -81,8 +81,7 @@ static void shoc_clk_init(struct clk *clk)
         for (i = 0; i < ARRAY_SIZE(frqcr3_divisors); i++) {
                 int divisor = frqcr3_divisors[i];
 
-                if (clk->ops->set_rate(clk, clk->parent->rate /
-                                                divisor, 0) == 0)
+                if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0)
                         break;
         }
 
@@ -110,7 +109,7 @@ static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate)
         return 0;
 }
 
-static int shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id)
+static int shoc_clk_set_rate(struct clk *clk, unsigned long rate)
 {
         unsigned long frqcr3;
         unsigned int tmp;
diff --git a/arch/sh/kernel/cpu/sh4/perf_event.c b/arch/sh/kernel/cpu/sh4/perf_event.c
index 7f9ecc9c2d02..748955df018d 100644
--- a/arch/sh/kernel/cpu/sh4/perf_event.c
+++ b/arch/sh/kernel/cpu/sh4/perf_event.c
@@ -225,7 +225,7 @@ static void sh7750_pmu_enable_all(void)
 }
 
 static struct sh_pmu sh7750_pmu = {
-        .name           = "SH7750",
+        .name           = "sh7750",
         .num_events     = 2,
         .event_map      = sh7750_event_map,
         .max_events     = ARRAY_SIZE(sh7750_general_events),
@@ -250,4 +250,4 @@ static int __init sh7750_pmu_init(void)
 
         return register_sh_pmu(&sh7750_pmu);
 }
-arch_initcall(sh7750_pmu_init);
+early_initcall(sh7750_pmu_init);
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index d180f16281ed..971cf0fce4f5 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -150,9 +150,15 @@ void __cpuinit cpu_probe(void)
                         boot_cpu_data.type = CPU_SH7724;
                         boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
                         break;
-                case 0x50:
+                case 0x10:
+                case 0x11:
                         boot_cpu_data.type = CPU_SH7757;
                         break;
+                case 0xd0:
+                case 0x40: /* yon-ten-go */
+                        boot_cpu_data.type = CPU_SH7372;
+                        break;
+
                 }
                 break;
         case 0x4000:    /* 1st cut */
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index e916b18e1f7c..5b2833159b7d 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -18,6 +18,8 @@
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xffe80000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 40, 41, 43, 42 },
 };
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 911d196e86b5..e53b4b38bd11 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <linux/sh_timer.h>
 #include <linux/serial_sci.h>
+#include <generated/machtypes.h>
 
 static struct resource rtc_resources[] = {
         [0] = {
@@ -35,33 +36,37 @@ static struct platform_device rtc_device = {
         .resource       = rtc_resources,
 };
 
-static struct plat_sci_port scif0_platform_data = {
+static struct plat_sci_port sci_platform_data = {
         .mapbase        = 0xffe00000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TE | SCSCR_RE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCI,
         .irqs           = { 23, 23, 23, 0 },
 };
 
-static struct platform_device scif0_device = {
+static struct platform_device sci_device = {
         .name           = "sh-sci",
         .id             = 0,
         .dev            = {
-                .platform_data  = &scif0_platform_data,
+                .platform_data  = &sci_platform_data,
         },
 };
 
-static struct plat_sci_port scif1_platform_data = {
+static struct plat_sci_port scif_platform_data = {
         .mapbase        = 0xffe80000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 40, 40, 40, 40 },
 };
 
-static struct platform_device scif1_device = {
+static struct platform_device scif_device = {
         .name           = "sh-sci",
         .id             = 1,
         .dev            = {
-                .platform_data  = &scif1_platform_data,
+                .platform_data  = &scif_platform_data,
         },
 };
 
@@ -210,8 +215,6 @@ static struct platform_device tmu4_device = {
 #endif
 
 static struct platform_device *sh7750_devices[] __initdata = {
-        &scif0_device,
-        &scif1_device,
         &rtc_device,
         &tmu0_device,
         &tmu1_device,
@@ -226,14 +229,19 @@ static struct platform_device *sh7750_devices[] __initdata = {
 
 static int __init sh7750_devices_setup(void)
 {
+        if (mach_is_rts7751r2d()) {
+                platform_device_register(&scif_device);
+        } else {
+                platform_device_register(&sci_device);
+                platform_device_register(&scif_device);
+        }
+
         return platform_add_devices(sh7750_devices,
                                     ARRAY_SIZE(sh7750_devices));
 }
 arch_initcall(sh7750_devices_setup);
 
 static struct platform_device *sh7750_early_devices[] __initdata = {
-        &scif0_device,
-        &scif1_device,
         &tmu0_device,
         &tmu1_device,
         &tmu2_device,
@@ -247,6 +255,19 @@ static struct platform_device *sh7750_early_devices[] __initdata = {
 
 void __init plat_early_device_setup(void)
 {
+        struct platform_device *dev[1];
+
+        if (mach_is_rts7751r2d()) {
+                scif_platform_data.scscr |= SCSCR_CKE1;
+                dev[0] = &scif_device;
+                early_platform_add_devices(dev, 1);
+        } else {
+                dev[0] = &sci_device;
+                early_platform_add_devices(dev, 1);
+                dev[0] = &scif_device;
+                early_platform_add_devices(dev, 1);
+        }
+
         early_platform_add_devices(sh7750_early_devices,
                                    ARRAY_SIZE(sh7750_early_devices));
 }
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 48ea8fe85dc5..78bbf232e391 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -129,6 +129,8 @@ static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xfe600000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 52, 53, 55, 54 },
 };
@@ -145,6 +147,8 @@ static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xfe610000,
         .flags          = UPF_BOOT_AUTOCONF,
         .type           = PORT_SCIF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .irqs           = { 72, 73, 75, 74 },
 };
 
@@ -159,6 +163,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xfe620000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 76, 77, 79, 78 },
 };
@@ -174,6 +180,8 @@ static struct platform_device scif2_device = {
 static struct plat_sci_port scif3_platform_data = {
         .mapbase        = 0xfe480000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCI,
         .irqs           = { 80, 81, 82, 0 },
 };
diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c
index 14726eef1ce0..f0907995b4c9 100644
--- a/arch/sh/kernel/cpu/sh4/sq.c
+++ b/arch/sh/kernel/cpu/sh4/sq.c
@@ -20,6 +20,7 @@
 #include <linux/vmalloc.h>
 #include <linux/mm.h>
 #include <linux/io.h>
+#include <linux/prefetch.h>
 #include <asm/page.h>
 #include <asm/cacheflush.h>
 #include <cpu/sq.h>
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index b144e8af89dc..cc122b1d3035 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -8,13 +8,13 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7763)	+= setup-sh7763.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7770)        += setup-sh7770.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7780)        += setup-sh7780.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7785)        += setup-sh7785.o
-obj-$(CONFIG_CPU_SUBTYPE_SH7786)        += setup-sh7786.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7786)        += setup-sh7786.o intc-shx3.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7343)        += setup-sh7343.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7722)        += setup-sh7722.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7723)        += setup-sh7723.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7724)        += setup-sh7724.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7366)        += setup-sh7366.o
-obj-$(CONFIG_CPU_SUBTYPE_SHX3)          += setup-shx3.o
+obj-$(CONFIG_CPU_SUBTYPE_SHX3)          += setup-shx3.o intc-shx3.o
 
 # SMP setup
 smp-$(CONFIG_CPU_SHX3)                  := smp-shx3.o
@@ -40,6 +40,7 @@ pinmux-$(CONFIG_CPU_SUBTYPE_SH7724)	:= pinmux-sh7724.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7757)     := pinmux-sh7757.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7785)     := pinmux-sh7785.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7786)     := pinmux-sh7786.o
+pinmux-$(CONFIG_CPU_SUBTYPE_SHX3)       := pinmux-shx3.o
 
 obj-y                                   += $(clock-y)
 obj-$(CONFIG_SMP)                       += $(smp-y)
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index 71291ae201b9..93c646072c1b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -21,7 +21,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 
 /* SH7343 registers */
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index 7ce5bbcd4084..049dc0628ccc 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -21,7 +21,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 
 /* SH7366 registers */
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 2030f3d9fac7..9d23a36f0647 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -21,7 +21,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/hwblk.h>
 #include <cpu/sh7722.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index d3938f0d3702..55493cd5bd8f 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -22,7 +22,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/clk.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/hwblk.h>
 #include <cpu/sh7723.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 2d9700c6b53a..d08fa953c88b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -22,7 +22,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/clk.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/hwblk.h>
 #include <cpu/sh7724.h>
@@ -48,7 +48,7 @@ static struct clk r_clk = {
  * Default rate for the root input clock, reset this with clk_set_rate()
  * from the platform code.
  */
-struct clk extal_clk = {
+static struct clk extal_clk = {
         .rate           = 33333333,
 };
 
@@ -111,12 +111,21 @@ static struct clk div3_clk = {
         .parent         = &pll_clk,
 };
 
-struct clk *main_clks[] = {
+/* External input clock (pin name: FSIMCKA/FSIMCKB ) */
+struct clk sh7724_fsimcka_clk = {
+};
+
+struct clk sh7724_fsimckb_clk = {
+};
+
+static struct clk *main_clks[] = {
         &r_clk,
         &extal_clk,
         &fll_clk,
         &pll_clk,
         &div3_clk,
+        &sh7724_fsimcka_clk,
+        &sh7724_fsimckb_clk,
 };
 
 static void div4_kick(struct clk *clk)
@@ -154,16 +163,38 @@ struct clk div4_clks[DIV4_NR] = {
         [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
 };
 
-enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
+enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR };
 
-struct clk div6_clks[DIV6_NR] = {
+static struct clk div6_clks[DIV6_NR] = {
         [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
-        [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
-        [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),
         [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
         [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
 };
 
+enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR };
+
+/* Indices are important - they are the actual src selecting values */
+static struct clk *fclkacr_parent[] = {
+        [0] = &div3_clk,
+        [1] = NULL,
+        [2] = &sh7724_fsimcka_clk,
+        [3] = NULL,
+};
+
+static struct clk *fclkbcr_parent[] = {
+        [0] = &div3_clk,
+        [1] = NULL,
+        [2] = &sh7724_fsimckb_clk,
+        [3] = NULL,
+};
+
+static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
+        [DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0,
+                                      fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
+        [DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0,
+                                      fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
+};
+
 static struct clk mstp_clks[HWBLK_NR] = {
         SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
         SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
@@ -240,8 +271,8 @@ static struct clk_lookup lookups[] = {
 
         /* DIV6 clocks */
         CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
-        CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
-        CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]),
+        CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]),
+        CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]),
         CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
         CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
 
@@ -376,6 +407,9 @@ int __init arch_clk_init(void)
                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 
         if (!ret)
+                ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
+
+        if (!ret)
                 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
 
         return ret;
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index 0a752bd324ac..eedddad13835 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -3,7 +3,7 @@
  *
  * SH7757 support for the clock framework
  *
- *  Copyright (C) 2009  Renesas Solutions Corp.
+ *  Copyright (C) 2009-2010  Renesas Solutions Corp.
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -12,128 +12,156 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 
-static int ifc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
-                              16, 1, 1, 32, 1, 1, 1, 1 };
-static int sfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
-                              16, 1, 1, 32, 1, 1, 1, 1 };
-static int bfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
-                              16, 1, 1, 32, 1, 1, 1, 1 };
-static int p1fc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
-                               16, 1, 1, 32, 1, 1, 1, 1 };
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+static struct clk extal_clk = {
+        .rate           = 48000000,
+};
 
-static void master_clk_init(struct clk *clk)
+static unsigned long pll_recalc(struct clk *clk)
 {
-        clk->rate = CONFIG_SH_PCLK_FREQ * 16;
-}
+        int multiplier;
 
-static struct clk_ops sh7757_master_clk_ops = {
-        .init           = master_clk_init,
-};
+        multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16;
 
-static void module_clk_recalc(struct clk *clk)
-{
-        int idx = __raw_readl(FRQCR) & 0x0000000f;
-        clk->rate = clk->parent->rate / p1fc_divisors[idx];
+        return clk->parent->rate * multiplier;
 }
 
-static struct clk_ops sh7757_module_clk_ops = {
-        .recalc         = module_clk_recalc,
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
 };
 
-static void bus_clk_recalc(struct clk *clk)
-{
-        int idx = (__raw_readl(FRQCR) >> 8) & 0x0000000f;
-        clk->rate = clk->parent->rate / bfc_divisors[idx];
-}
+static struct clk pll_clk = {
+        .ops            = &pll_clk_ops,
+        .parent         = &extal_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
 
-static struct clk_ops sh7757_bus_clk_ops = {
-        .recalc         = bus_clk_recalc,
+static struct clk *clks[] = {
+        &extal_clk,
+        &pll_clk,
 };
 
-static void cpu_clk_recalc(struct clk *clk)
-{
-        int idx = (__raw_readl(FRQCR) >> 20) & 0x0000000f;
-        clk->rate = clk->parent->rate / ifc_divisors[idx];
-}
+static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6,
+                               1, 1, 1, 16, 1, 24, 1, 1 };
 
-static struct clk_ops sh7757_cpu_clk_ops = {
-        .recalc         = cpu_clk_recalc,
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = div2,
+        .nr_divisors = ARRAY_SIZE(div2),
 };
 
-static struct clk_ops *sh7757_clk_ops[] = {
-        &sh7757_master_clk_ops,
-        &sh7757_module_clk_ops,
-        &sh7757_bus_clk_ops,
-        &sh7757_cpu_clk_ops,
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
-{
-        if (idx < ARRAY_SIZE(sh7757_clk_ops))
-                *ops = sh7757_clk_ops[idx];
-}
+enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR };
 
-static void shyway_clk_recalc(struct clk *clk)
-{
-        int idx = (__raw_readl(FRQCR) >> 12) & 0x0000000f;
-        clk->rate = clk->parent->rate / sfc_divisors[idx];
-}
-
-static struct clk_ops sh7757_shyway_clk_ops = {
-        .recalc         = shyway_clk_recalc,
-};
+#define DIV4(_bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
 
-static struct clk sh7757_shyway_clk = {
-        .flags          = CLK_ENABLE_ON_INIT,
-        .ops            = &sh7757_shyway_clk_ops,
+struct clk div4_clks[DIV4_NR] = {
+        /*
+         * P clock is always enable, because some P clock modules is used
+         * by Host PC.
+         */
+        [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
+        [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
 };
 
-/*
- * Additional sh7757-specific on-chip clocks that aren't already part of the
- * clock framework
- */
-static struct clk *sh7757_onchip_clocks[] = {
-        &sh7757_shyway_clk,
+#define MSTPCR0         0xffc80030
+#define MSTPCR1         0xffc80034
+#define MSTPCR2         0xffc10028
+
+enum { MSTP004, MSTP000, MSTP114, MSTP113, MSTP112,
+       MSTP111, MSTP110, MSTP103, MSTP102, MSTP220,
+       MSTP_NR };
+
+static struct clk mstp_clks[MSTP_NR] = {
+        /* MSTPCR0 */
+        [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
+        [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
+
+        /* MSTPCR1 */
+        [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
+        [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
+        [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
+        [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
+        [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
+        [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
+        [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
+
+        /* MSTPCR2 */
+        [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
 };
 
 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 
 static struct clk_lookup lookups[] = {
         /* main clocks */
-        CLKDEV_CON_ID("shyway_clk", &sh7757_shyway_clk),
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+
+        /* MSTP32 clocks */
+        CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP004]),
+        CLKDEV_CON_ID("riic", &mstp_clks[MSTP000]),
+        {
+                /* TMU0 */
+                .dev_id         = "sh_tmu.0",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP113],
+        }, {
+                /* TMU1 */
+                .dev_id         = "sh_tmu.1",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP114],
+        },
+        {
+                /* SCIF4 (But, ID is 2) */
+                .dev_id         = "sh-sci.2",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP112],
+        }, {
+                /* SCIF3 */
+                .dev_id         = "sh-sci.1",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP111],
+        }, {
+                /* SCIF2 */
+                .dev_id         = "sh-sci.0",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP110],
+        },
+        CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]),
+        CLKDEV_CON_ID("mmc0", &mstp_clks[MSTP220]),
 };
 
-static int __init sh7757_clk_init(void)
+int __init arch_clk_init(void)
 {
-        struct clk *clk = clk_get(NULL, "master_clk");
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(sh7757_onchip_clocks); i++) {
-                struct clk *clkp = sh7757_onchip_clocks[i];
+        int i, ret = 0;
 
-                clkp->parent = clk;
-                clk_register(clkp);
-                clk_enable(clkp);
-        }
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                ret |= clk_register(clks[i]);
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
 
-        /*
-         * Now that we have the rest of the clocks registered, we need to
-         * force the parent clock to propagate so that these clocks will
-         * automatically figure out their rate. We cheat by handing the
-         * parent clock its current rate and forcing child propagation.
-         */
-        clk_set_rate(clk, clk_get_rate(clk));
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
+                                           &div4_table);
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
 
-        clk_put(clk);
-
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-        return 0;
+        return ret;
 }
 
-arch_initcall(sh7757_clk_init);
-
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 1f1df48008cd..599630fc4d3b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -13,7 +13,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 #include <asm/io.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index 62d706350060..8894926479a6 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 #include <asm/io.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index c3e458aaa2b7..2d960247f3eb 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -14,7 +14,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/cpufreq.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 #include <cpu/sh7785.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index 597c9fbe49c6..42e403be9076 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -13,7 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index 236a6282d778..1afdb93b8ccb 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -5,7 +5,7 @@
  *
  *  Copyright (C) 2006-2007  Renesas Technology Corp.
  *  Copyright (C) 2006-2007  Renesas Solutions Corp.
- *  Copyright (C) 2006-2007  Paul Mundt
+ *  Copyright (C) 2006-2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -14,124 +14,183 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 
-static int ifc_divisors[] = { 1, 2, 4 ,6 };
-static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };
-static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18, 24, 32, 36, 48 };
-static int cfc_divisors[] = { 1, 1, 4, 6 };
-
-#define IFC_POS         28
-#define IFC_MSK         0x0003
-#define BFC_MSK         0x000f
-#define PFC_MSK         0x000f
-#define CFC_MSK         0x0003
-#define BFC_POS         16
-#define PFC_POS         0
-#define CFC_POS         20
-
-static void master_clk_init(struct clk *clk)
-{
-        clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK];
-}
-
-static struct clk_ops shx3_master_clk_ops = {
-        .init           = master_clk_init,
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+static struct clk extal_clk = {
+        .rate           = 16666666,
 };
 
-static unsigned long module_clk_recalc(struct clk *clk)
+static unsigned long pll_recalc(struct clk *clk)
 {
-        int idx = ((__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK);
-        return clk->parent->rate / pfc_divisors[idx];
+        /* PLL1 has a fixed x72 multiplier.  */
+        return clk->parent->rate * 72;
 }
 
-static struct clk_ops shx3_module_clk_ops = {
-        .recalc         = module_clk_recalc,
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
 };
 
-static unsigned long bus_clk_recalc(struct clk *clk)
-{
-        int idx = ((__raw_readl(FRQCR) >> BFC_POS) & BFC_MSK);
-        return clk->parent->rate / bfc_divisors[idx];
-}
+static struct clk pll_clk = {
+        .ops            = &pll_clk_ops,
+        .parent         = &extal_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
 
-static struct clk_ops shx3_bus_clk_ops = {
-        .recalc         = bus_clk_recalc,
+static struct clk *clks[] = {
+        &extal_clk,
+        &pll_clk,
 };
 
-static unsigned long cpu_clk_recalc(struct clk *clk)
-{
-        int idx = ((__raw_readl(FRQCR) >> IFC_POS) & IFC_MSK);
-        return clk->parent->rate / ifc_divisors[idx];
-}
+static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
+                               24, 32, 36, 48 };
 
-static struct clk_ops shx3_cpu_clk_ops = {
-        .recalc         = cpu_clk_recalc,
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = div2,
+        .nr_divisors = ARRAY_SIZE(div2),
 };
 
-static struct clk_ops *shx3_clk_ops[] = {
-        &shx3_master_clk_ops,
-        &shx3_module_clk_ops,
-        &shx3_bus_clk_ops,
-        &shx3_cpu_clk_ops,
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
-{
-        if (idx < ARRAY_SIZE(shx3_clk_ops))
-                *ops = shx3_clk_ops[idx];
-}
+enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR };
 
-static unsigned long shyway_clk_recalc(struct clk *clk)
-{
-        int idx = ((__raw_readl(FRQCR) >> CFC_POS) & CFC_MSK);
-        return clk->parent->rate / cfc_divisors[idx];
-}
+#define DIV4(_bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
 
-static struct clk_ops shx3_shyway_clk_ops = {
-        .recalc         = shyway_clk_recalc,
+struct clk div4_clks[DIV4_NR] = {
+        [DIV4_P] = DIV4(0, 0x0f80, 0),
+        [DIV4_SHA] = DIV4(4, 0x0ff0, 0),
+        [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
+        [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
 };
 
-static struct clk shx3_shyway_clk = {
-        .flags          = CLK_ENABLE_ON_INIT,
-        .ops            = &shx3_shyway_clk_ops,
-};
-
-/*
- * Additional SHx3-specific on-chip clocks that aren't already part of the
- * clock framework
- */
-static struct clk *shx3_onchip_clocks[] = {
-        &shx3_shyway_clk,
+#define MSTPCR0         0xffc00030
+#define MSTPCR1         0xffc00034
+
+enum { MSTP027, MSTP026, MSTP025, MSTP024,
+       MSTP009, MSTP008, MSTP003, MSTP002,
+       MSTP001, MSTP000, MSTP119, MSTP105,
+       MSTP104, MSTP_NR };
+
+static struct clk mstp_clks[MSTP_NR] = {
+        /* MSTPCR0 */
+        [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
+        [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
+        [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
+        [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
+        [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
+        [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
+        [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
+        [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
+        [MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
+        [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
+
+        /* MSTPCR1 */
+        [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
+        [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
+        [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
 };
 
 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 
 static struct clk_lookup lookups[] = {
         /* main clocks */
-        CLKDEV_CON_ID("shyway_clk", &shx3_shyway_clk),
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+        CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]),
+        CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
+        CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+
+        /* MSTP32 clocks */
+        {
+                /* SCIF3 */
+                .dev_id         = "sh-sci.3",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP027],
+        }, {
+                /* SCIF2 */
+                .dev_id         = "sh-sci.2",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP026],
+        }, {
+                /* SCIF1 */
+                .dev_id         = "sh-sci.1",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP025],
+        }, {
+                /* SCIF0 */
+                .dev_id         = "sh-sci.0",
+                .con_id         = "sci_fck",
+                .clk            = &mstp_clks[MSTP024],
+        },
+        CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),
+        CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),
+        CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]),
+        CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]),
+        {
+                /* TMU0 */
+                .dev_id         = "sh_tmu.0",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP008],
+        }, {
+                /* TMU1 */
+                .dev_id         = "sh_tmu.1",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP008],
+        }, {
+                /* TMU2 */
+                .dev_id         = "sh_tmu.2",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP008],
+        }, {
+                /* TMU3 */
+                .dev_id         = "sh_tmu.3",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP009],
+        }, {
+                /* TMU4 */
+                .dev_id         = "sh_tmu.4",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP009],
+        }, {
+                /* TMU5 */
+                .dev_id         = "sh_tmu.5",
+                .con_id         = "tmu_fck",
+                .clk            = &mstp_clks[MSTP009],
+        },
+        CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
+        CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
+        CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
 };
 
 int __init arch_clk_init(void)
 {
-        struct clk *clk;
         int i, ret = 0;
 
-        cpg_clk_init();
-
-        clk = clk_get(NULL, "master_clk");
-        for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) {
-                struct clk *clkp = shx3_onchip_clocks[i];
-
-                clkp->parent = clk;
-                ret |= clk_register(clkp);
-        }
-
-        clk_put(clk);
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                ret |= clk_register(clks[i]);
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
 
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
+                                           &div4_table);
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
 
         return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/intc-shx3.c b/arch/sh/kernel/cpu/sh4a/intc-shx3.c
new file mode 100644
index 000000000000..78c971486b4e
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/intc-shx3.c
@@ -0,0 +1,34 @@
+/*
+ * Shared support for SH-X3 interrupt controllers.
+ *
+ *  Copyright (C) 2009 - 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/init.h>
+
+#define INTACK          0xfe4100b8
+#define INTACKCLR       0xfe4100bc
+#define INTC_USERIMASK  0xfe411000
+
+#ifdef CONFIG_INTC_BALANCING
+unsigned int irq_lookup(unsigned int irq)
+{
+        return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
+}
+
+void irq_finish(unsigned int irq)
+{
+        __raw_writel(irq2evt(irq), INTACKCLR);
+}
+#endif
+
+static int __init shx3_irq_setup(void)
+{
+        return register_intc_userimask(INTC_USERIMASK);
+}
+arch_initcall(shx3_irq_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c
index eddc21973fa1..17e6bebfede0 100644
--- a/arch/sh/kernel/cpu/sh4a/perf_event.c
+++ b/arch/sh/kernel/cpu/sh4a/perf_event.c
@@ -1,7 +1,7 @@
 /*
  * Performance events support for SH-4A performance counters
  *
- *  Copyright (C) 2009  Paul Mundt
+ *  Copyright (C) 2009, 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -22,7 +22,25 @@
 #define CCBR_CMDS       (1 << 1)
 #define CCBR_PPCE       (1 << 0)
 
+#ifdef CONFIG_CPU_SHX3
+/*
+ * The PMCAT location for SH-X3 CPUs was quietly moved, while the CCBR
+ * and PMCTR locations remains tentatively constant. This change remains
+ * wholly undocumented, and was simply found through trial and error.
+ *
+ * Early cuts of SH-X3 still appear to use the SH-X/SH-X2 locations, and
+ * it's unclear when this ceased to be the case. For now we always use
+ * the new location (if future parts keep up with this trend then
+ * scanning for them at runtime also remains a viable option.)
+ *
+ * The gap in the register space also suggests that there are other
+ * undocumented counters, so this will need to be revisited at a later
+ * point in time.
+ */
+#define PPC_PMCAT       0xfc100240
+#else
 #define PPC_PMCAT       0xfc100080
+#endif
 
 #define PMCAT_OVF3      (1 << 27)
 #define PMCAT_CNN3      (1 << 26)
@@ -241,7 +259,7 @@ static void sh4a_pmu_enable_all(void)
 }
 
 static struct sh_pmu sh4a_pmu = {
-        .name           = "SH-4A",
+        .name           = "sh4a",
         .num_events     = 2,
         .event_map      = sh4a_event_map,
         .max_events     = ARRAY_SIZE(sh4a_general_events),
@@ -266,4 +284,4 @@ static int __init sh4a_pmu_init(void)
 
         return register_sh_pmu(&sh4a_pmu);
 }
-arch_initcall(sh4a_pmu_init);
+early_initcall(sh4a_pmu_init);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
index ed23b155c097..4c74bd04bba4 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
@@ -1,11 +1,11 @@
 /*
- * SH7757 (A0 step) Pinmux
+ * SH7757 (B0 step) Pinmux
  *
- *  Copyright (C) 2009  Renesas Solutions Corp.
+ *  Copyright (C) 2009-2010  Renesas Solutions Corp.
  *
  *  Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  *
- * Based on SH7757 Pinmux
+ * Based on SH7723 Pinmux
  *  Copyright (C) 2008  Magnus Damm
  *
  * This file is subject to the terms and conditions of the GNU General Public
@@ -40,27 +40,27 @@ enum {
         PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
         PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
         PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA,
-        PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
+                   PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
         PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
         PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
         PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
-        PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
+                   PTL6_DATA, PTL5_DATA, PTL4_DATA,
         PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
-        PTM6_DATA, PTM5_DATA, PTM4_DATA,
+        PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
         PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
-        PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
+                   PTN6_DATA, PTN5_DATA, PTN4_DATA,
         PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
         PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
         PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA,
-        PTP6_DATA, PTP5_DATA, PTP4_DATA,
+        PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
         PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA,
-        PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
+                   PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
         PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
         PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
         PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
         PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
         PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
-        PTT5_DATA, PTT4_DATA,
+        PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
         PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
         PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
         PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
@@ -95,27 +95,27 @@ enum {
         PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
         PTI7_IN, PTI6_IN, PTI5_IN, PTI4_IN,
         PTI3_IN, PTI2_IN, PTI1_IN, PTI0_IN,
-        PTJ7_IN, PTJ6_IN, PTJ5_IN, PTJ4_IN,
+                 PTJ6_IN, PTJ5_IN, PTJ4_IN,
         PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
         PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
         PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
-        PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
+                 PTL6_IN, PTL5_IN, PTL4_IN,
         PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
-        PTM6_IN, PTM5_IN, PTM4_IN,
+        PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
         PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
-        PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
+                 PTN6_IN, PTN5_IN, PTN4_IN,
         PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
         PTO7_IN, PTO6_IN, PTO5_IN, PTO4_IN,
         PTO3_IN, PTO2_IN, PTO1_IN, PTO0_IN,
-        PTP6_IN, PTP5_IN, PTP4_IN,
+        PTP7_IN, PTP6_IN, PTP5_IN, PTP4_IN,
         PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN,
-        PTQ6_IN, PTQ5_IN, PTQ4_IN,
+                 PTQ6_IN, PTQ5_IN, PTQ4_IN,
         PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
         PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
         PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
         PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN,
         PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
-        PTT5_IN, PTT4_IN,
+        PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN,
         PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
         PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
         PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
@@ -132,16 +132,43 @@ enum {
         PINMUX_INPUT_END,
 
         PINMUX_INPUT_PULLUP_BEGIN,
+        PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU,
+        PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
+        PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
+        PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU,
+        PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU,
+        PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU,
+        PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU,
+        PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU,
+        PTG7_IN_PU, PTG6_IN_PU,             PTG4_IN_PU,
+        PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU,
+        PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU,
+        PTI7_IN_PU, PTI6_IN_PU,             PTI4_IN_PU,
+        PTI3_IN_PU, PTI2_IN_PU, PTI1_IN_PU, PTI0_IN_PU,
+                    PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU,
+        PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU,
+        PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU,
+        PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU,
+                    PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU,
+        PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU,
+        PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU,
+                                            PTN4_IN_PU,
+        PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU,
+        PTO7_IN_PU, PTO6_IN_PU, PTO5_IN_PU, PTO4_IN_PU,
+        PTO3_IN_PU, PTO2_IN_PU, PTO1_IN_PU, PTO0_IN_PU,
+        PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU,
+        PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU,
         PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU,
         PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
         PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU,
-        PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU,
-        PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU,
-        PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU,
+        PTV3_IN_PU, PTV2_IN_PU,
+                                PTW1_IN_PU, PTW0_IN_PU,
         PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU,
         PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU,
         PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU,
         PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU,
+        PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU,
+        PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU,
         PINMUX_INPUT_PULLUP_END,
 
         PINMUX_OUTPUT_BEGIN,
@@ -163,27 +190,27 @@ enum {
         PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
         PTI7_OUT, PTI6_OUT, PTI5_OUT, PTI4_OUT,
         PTI3_OUT, PTI2_OUT, PTI1_OUT, PTI0_OUT,
-        PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ4_OUT,
+                  PTJ6_OUT, PTJ5_OUT, PTJ4_OUT,
         PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
         PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
         PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
-        PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
+                  PTL6_OUT, PTL5_OUT, PTL4_OUT,
         PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
-        PTM6_OUT, PTM5_OUT, PTM4_OUT,
+        PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
         PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
-        PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
+                  PTN6_OUT, PTN5_OUT, PTN4_OUT,
         PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
         PTO7_OUT, PTO6_OUT, PTO5_OUT, PTO4_OUT,
         PTO3_OUT, PTO2_OUT, PTO1_OUT, PTO0_OUT,
-        PTP6_OUT, PTP5_OUT, PTP4_OUT,
+        PTP7_OUT, PTP6_OUT, PTP5_OUT, PTP4_OUT,
         PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT,
-        PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
+                  PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
         PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
         PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
         PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT,
         PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT,
         PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
-        PTT5_OUT, PTT4_OUT,
+        PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT,
         PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
         PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
         PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
@@ -218,27 +245,27 @@ enum {
         PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
         PTI7_FN, PTI6_FN, PTI5_FN, PTI4_FN,
         PTI3_FN, PTI2_FN, PTI1_FN, PTI0_FN,
-        PTJ7_FN, PTJ6_FN, PTJ5_FN, PTJ4_FN,
+                 PTJ6_FN, PTJ5_FN, PTJ4_FN,
         PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
         PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
         PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
-        PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN,
+                 PTL6_FN, PTL5_FN, PTL4_FN,
         PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
-        PTM6_FN, PTM5_FN, PTM4_FN,
+        PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
         PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
-        PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN,
+                 PTN6_FN, PTN5_FN, PTN4_FN,
         PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
         PTO7_FN, PTO6_FN, PTO5_FN, PTO4_FN,
         PTO3_FN, PTO2_FN, PTO1_FN, PTO0_FN,
-        PTP6_FN, PTP5_FN, PTP4_FN,
+        PTP7_FN, PTP6_FN, PTP5_FN, PTP4_FN,
         PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN,
-        PTQ6_FN, PTQ5_FN, PTQ4_FN,
+                 PTQ6_FN, PTQ5_FN, PTQ4_FN,
         PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
         PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
         PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
         PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN,
         PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
-        PTT5_FN, PTT4_FN,
+        PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN,
         PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
         PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
         PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
@@ -253,181 +280,248 @@ enum {
         PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
         PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
 
-        PS0_15_FN1, PS0_15_FN3,
-        PS0_14_FN1, PS0_14_FN3,
-        PS0_13_FN1, PS0_13_FN3,
-        PS0_12_FN1, PS0_12_FN3,
+        PS0_15_FN1, PS0_15_FN2,
+        PS0_14_FN1, PS0_14_FN2,
+        PS0_13_FN1, PS0_13_FN2,
+        PS0_12_FN1, PS0_12_FN2,
+        PS0_11_FN1, PS0_11_FN2,
+        PS0_10_FN1, PS0_10_FN2,
+        PS0_9_FN1, PS0_9_FN2,
+        PS0_8_FN1, PS0_8_FN2,
         PS0_7_FN1, PS0_7_FN2,
         PS0_6_FN1, PS0_6_FN2,
         PS0_5_FN1, PS0_5_FN2,
         PS0_4_FN1, PS0_4_FN2,
         PS0_3_FN1, PS0_3_FN2,
         PS0_2_FN1, PS0_2_FN2,
-        PS0_1_FN1, PS0_1_FN2,
 
-        PS1_7_FN1, PS1_7_FN3,
-        PS1_6_FN1, PS1_6_FN3,
+        PS1_10_FN1, PS1_10_FN2,
+        PS1_9_FN1, PS1_9_FN2,
+        PS1_8_FN1, PS1_8_FN2,
+        PS1_2_FN1, PS1_2_FN2,
+
+        PS2_13_FN1, PS2_13_FN2,
+        PS2_12_FN1, PS2_12_FN2,
+        PS2_7_FN1, PS2_7_FN2,
+        PS2_6_FN1, PS2_6_FN2,
+        PS2_5_FN1, PS2_5_FN2,
+        PS2_4_FN1, PS2_4_FN2,
+        PS2_2_FN1, PS2_2_FN2,
+
+        PS3_15_FN1, PS3_15_FN2,
+        PS3_14_FN1, PS3_14_FN2,
+        PS3_13_FN1, PS3_13_FN2,
+        PS3_12_FN1, PS3_12_FN2,
+        PS3_11_FN1, PS3_11_FN2,
+        PS3_10_FN1, PS3_10_FN2,
+        PS3_9_FN1, PS3_9_FN2,
+        PS3_8_FN1, PS3_8_FN2,
+        PS3_7_FN1, PS3_7_FN2,
+        PS3_2_FN1, PS3_2_FN2,
+        PS3_1_FN1, PS3_1_FN2,
 
-        PS2_13_FN1, PS2_13_FN3,
-        PS2_12_FN1, PS2_12_FN3,
-        PS2_1_FN1, PS2_1_FN2,
-        PS2_0_FN1, PS2_0_FN2,
-
-        PS4_15_FN1, PS4_15_FN2,
         PS4_14_FN1, PS4_14_FN2,
         PS4_13_FN1, PS4_13_FN2,
         PS4_12_FN1, PS4_12_FN2,
-        PS4_11_FN1, PS4_11_FN2,
         PS4_10_FN1, PS4_10_FN2,
         PS4_9_FN1, PS4_9_FN2,
+        PS4_8_FN1, PS4_8_FN2,
+        PS4_4_FN1, PS4_4_FN2,
         PS4_3_FN1, PS4_3_FN2,
         PS4_2_FN1, PS4_2_FN2,
         PS4_1_FN1, PS4_1_FN2,
         PS4_0_FN1, PS4_0_FN2,
 
+        PS5_11_FN1, PS5_11_FN2,
+        PS5_10_FN1, PS5_10_FN2,
         PS5_9_FN1, PS5_9_FN2,
         PS5_8_FN1, PS5_8_FN2,
         PS5_7_FN1, PS5_7_FN2,
         PS5_6_FN1, PS5_6_FN2,
         PS5_5_FN1, PS5_5_FN2,
         PS5_4_FN1, PS5_4_FN2,
-
-        /* AN15 to 8 : EVENT15 to 8 */
-        PS6_7_FN_AN, PS6_7_FN_EV,
-        PS6_6_FN_AN, PS6_6_FN_EV,
-        PS6_5_FN_AN, PS6_5_FN_EV,
-        PS6_4_FN_AN, PS6_4_FN_EV,
-        PS6_3_FN_AN, PS6_3_FN_EV,
-        PS6_2_FN_AN, PS6_2_FN_EV,
-        PS6_1_FN_AN, PS6_1_FN_EV,
-        PS6_0_FN_AN, PS6_0_FN_EV,
-
+        PS5_3_FN1, PS5_3_FN2,
+        PS5_2_FN1, PS5_2_FN2,
+
+        PS6_15_FN1, PS6_15_FN2,
+        PS6_14_FN1, PS6_14_FN2,
+        PS6_13_FN1, PS6_13_FN2,
+        PS6_12_FN1, PS6_12_FN2,
+        PS6_11_FN1, PS6_11_FN2,
+        PS6_10_FN1, PS6_10_FN2,
+        PS6_9_FN1, PS6_9_FN2,
+        PS6_8_FN1, PS6_8_FN2,
+        PS6_7_FN1, PS6_7_FN2,
+        PS6_6_FN1, PS6_6_FN2,
+        PS6_5_FN1, PS6_5_FN2,
+        PS6_4_FN1, PS6_4_FN2,
+        PS6_3_FN1, PS6_3_FN2,
+        PS6_2_FN1, PS6_2_FN2,
+        PS6_1_FN1, PS6_1_FN2,
+        PS6_0_FN1, PS6_0_FN2,
+
+        PS7_15_FN1, PS7_15_FN2,
+        PS7_14_FN1, PS7_14_FN2,
+        PS7_13_FN1, PS7_13_FN2,
+        PS7_12_FN1, PS7_12_FN2,
+        PS7_11_FN1, PS7_11_FN2,
+        PS7_10_FN1, PS7_10_FN2,
+        PS7_9_FN1, PS7_9_FN2,
+        PS7_8_FN1, PS7_8_FN2,
+        PS7_7_FN1, PS7_7_FN2,
+        PS7_6_FN1, PS7_6_FN2,
+        PS7_5_FN1, PS7_5_FN2,
+        PS7_4_FN1, PS7_4_FN2,
+
+        PS8_15_FN1, PS8_15_FN2,
+        PS8_14_FN1, PS8_14_FN2,
+        PS8_13_FN1, PS8_13_FN2,
+        PS8_12_FN1, PS8_12_FN2,
+        PS8_11_FN1, PS8_11_FN2,
+        PS8_10_FN1, PS8_10_FN2,
+        PS8_9_FN1, PS8_9_FN2,
+        PS8_8_FN1, PS8_8_FN2,
         PINMUX_FUNCTION_END,
 
         PINMUX_MARK_BEGIN,
-        /* PTA (mobule: LBSC, CPG, LPC) */
+        /* PTA (mobule: LBSC, RGMII) */
         BS_MARK,        RDWR_MARK,      WE1_MARK,       RDY_MARK,
-        MD10_MARK,      MD9_MARK,       MD8_MARK,
-        LGPIO7_MARK,    LGPIO6_MARK,    LGPIO5_MARK,    LGPIO4_MARK,
-        LGPIO3_MARK,    LGPIO2_MARK,    LGPIO1_MARK,    LGPIO0_MARK,
-
-        /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
-        D15_MARK,       D14_MARK,       D13_MARK,       D12_MARK,
-        D11_MARK,       D10_MARK,       D9_MARK,        D8_MARK,
         ET0_MDC_MARK,   ET0_MDIO_MARK,  ET1_MDC_MARK,   ET1_MDIO_MARK,
-        SIM_D_MARK,     SIM_CLK_MARK,   SIM_RST_MARK,
-        WPSZ1_MARK,     WPSZ0_MARK,     FWID_MARK,      FLSHSZ_MARK,
-        LPC_SPIEN_MARK, BASEL_MARK,
 
-        /* PTC (mobule: SD) */
-        SD_WP_MARK,     SD_CD_MARK,     SD_CLK_MARK,    SD_CMD_MARK,
-        SD_D3_MARK,     SD_D2_MARK,     SD_D1_MARK,     SD_D0_MARK,
+        /* PTB (mobule: INTC, ONFI, TMU) */
+        IRQ15_MARK,     IRQ14_MARK,     IRQ13_MARK,     IRQ12_MARK,
+        IRQ11_MARK,     IRQ10_MARK,     IRQ9_MARK,      IRQ8_MARK,
+        ON_NRE_MARK,    ON_NWE_MARK,    ON_NWP_MARK,    ON_NCE0_MARK,
+        ON_R_B0_MARK,   ON_ALE_MARK,    ON_CLE_MARK,    TCLK_MARK,
 
-        /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
+        /* PTC (mobule: IRQ, PWMU) */
         IRQ7_MARK,      IRQ6_MARK,      IRQ5_MARK,      IRQ4_MARK,
         IRQ3_MARK,      IRQ2_MARK,      IRQ1_MARK,      IRQ0_MARK,
-        MD6_MARK,       MD5_MARK,       MD3_MARK,       MD2_MARK,
-        MD1_MARK,       MD0_MARK,       ADTRG1_MARK,    ADTRG0_MARK,
-
-        /* PTE (mobule: EtherC) */
-        ET0_CRS_DV_MARK,        ET0_TXD1_MARK,
-        ET0_TXD0_MARK,          ET0_TX_EN_MARK,
-        ET0_REF_CLK_MARK,       ET0_RXD1_MARK,
-        ET0_RXD0_MARK,          ET0_RX_ER_MARK,
-
-        /* PTF (mobule: EtherC) */
-        ET1_CRS_DV_MARK,        ET1_TXD1_MARK,
-        ET1_TXD0_MARK,          ET1_TX_EN_MARK,
-        ET1_REF_CLK_MARK,       ET1_RXD1_MARK,
-        ET1_RXD0_MARK,          ET1_RX_ER_MARK,
-
-        /* PTG (mobule: SYSTEM, PWMX, LPC) */
-        STATUS0_MARK,   STATUS1_MARK,
-        PWX0_MARK,      PWX1_MARK,      PWX2_MARK,      PWX3_MARK,
-        SERIRQ_MARK,    CLKRUN_MARK,    LPCPD_MARK,     LDRQ_MARK,
-
-        /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
-        TCLK_MARK,      RXD4_MARK,      TXD4_MARK,
+        PWMU0_MARK,     PWMU1_MARK,     PWMU2_MARK,     PWMU3_MARK,
+        PWMU4_MARK,     PWMU5_MARK,
+
+        /* PTD (mobule: SPI0, DMAC) */
+        SP0_MOSI_MARK,  SP0_MISO_MARK,  SP0_SCK_MARK,   SP0_SCK_FB_MARK,
+        SP0_SS0_MARK,   SP0_SS1_MARK,   SP0_SS2_MARK,   SP0_SS3_MARK,
+        DREQ0_MARK,     DACK0_MARK,     TEND0_MARK,
+
+        /* PTE (mobule: RMII) */
+        RMII0_CRS_DV_MARK,      RMII0_TXD1_MARK,
+        RMII0_TXD0_MARK,        RMII0_TXEN_MARK,
+        RMII0_REFCLK_MARK,      RMII0_RXD1_MARK,
+        RMII0_RXD0_MARK,        RMII0_RX_ER_MARK,
+
+        /* PTF (mobule: RMII, SerMux) */
+        RMII1_CRS_DV_MARK,      RMII1_TXD1_MARK,
+        RMII1_TXD0_MARK,        RMII1_TXEN_MARK,
+        RMII1_REFCLK_MARK,      RMII1_RXD1_MARK,
+        RMII1_RXD0_MARK,        RMII1_RX_ER_MARK,
+        RAC_RI_MARK,
+
+        /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
+        BOOTFMS_MARK,   BOOTWP_MARK,    A25_MARK,       A24_MARK,
+        SERIRQ_MARK,    WDTOVF_MARK,    LPCPD_MARK,     LDRQ_MARK,
+        MMCCLK_MARK,    MMCCMD_MARK,
+
+        /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
         SP1_MOSI_MARK,  SP1_MISO_MARK,  SP1_SCK_MARK,   SP1_SCK_FB_MARK,
-        SP1_SS0_MARK,   SP1_SS1_MARK,   SP0_SS1_MARK,
+        SP1_SS0_MARK,   SP1_SS1_MARK,   WP_MARK,        FMS0_MARK,
+        TEND1_MARK,     DREQ1_MARK,     DACK1_MARK,     ADTRG1_MARK,
+        ADTRG0_MARK,
 
-        /* PTI (mobule: INTC) */
-        IRQ15_MARK,     IRQ14_MARK,     IRQ13_MARK,     IRQ12_MARK,
-        IRQ11_MARK,     IRQ10_MARK,     IRQ9_MARK,      IRQ8_MARK,
+        /* PTI (mobule: LBSC, SDHI) */
+        D15_MARK,       D14_MARK,       D13_MARK,       D12_MARK,
+        D11_MARK,       D10_MARK,       D9_MARK,        D8_MARK,
+        SD_WP_MARK,     SD_CD_MARK,     SD_CLK_MARK,    SD_CMD_MARK,
+        SD_D3_MARK,     SD_D2_MARK,     SD_D1_MARK,     SD_D0_MARK,
 
-        /* PTJ (mobule: SCIF234, SERMUX) */
-        RXD3_MARK,      TXD3_MARK,      RXD2_MARK,      TXD2_MARK,
-        COM1_TXD_MARK,  COM1_RXD_MARK,  COM1_RTS_MARK,  COM1_CTS_MARK,
+        /* PTJ (mobule: SCIF234) */
+        RTS3_MARK,      CTS3_MARK,      TXD3_MARK,      RXD3_MARK,
+        RTS4_MARK,      RXD4_MARK,      TXD4_MARK,
 
-        /* PTK (mobule: SERMUX) */
+        /* PTK (mobule: SERMUX, LBSC, SCIF) */
         COM2_TXD_MARK,  COM2_RXD_MARK,  COM2_RTS_MARK,  COM2_CTS_MARK,
-        COM2_DTR_MARK,  COM2_DSR_MARK,  COM2_DCD_MARK,  COM2_RI_MARK,
+        COM2_DTR_MARK,  COM2_DSR_MARK,  COM2_DCD_MARK,  CLKOUT_MARK,
+        SCK2_MARK,      SCK4_MARK,      SCK3_MARK,
 
-        /* PTL (mobule: SERMUX) */
-        RAC_TXD_MARK,   RAC_RXD_MARK,   RAC_RTS_MARK,   RAC_CTS_MARK,
-        RAC_DTR_MARK,   RAC_DSR_MARK,   RAC_DCD_MARK,   RAC_RI_MARK,
+        /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
+        RAC_RXD_MARK,   RAC_RTS_MARK,   RAC_CTS_MARK,   RAC_DTR_MARK,
+        RAC_DSR_MARK,   RAC_DCD_MARK,   RAC_TXD_MARK,   RXD2_MARK,
+        CS5_MARK,       CS6_MARK,       AUDSYNC_MARK,   AUDCK_MARK,
+        TXD2_MARK,
 
-        /* PTM (mobule: IIC, LPC) */
+        /* PTM (mobule: LBSC, IIC) */
+        CS4_MARK,       RD_MARK,        WE0_MARK,       CS0_MARK,
         SDA6_MARK,      SCL6_MARK,      SDA7_MARK,      SCL7_MARK,
-        WP_MARK,        FMS0_MARK,      FMS1_MARK,
 
-        /* PTN (mobule: SCIF234, EVC) */
-        SCK2_MARK,      RTS4_MARK,      RTS3_MARK,      RTS2_MARK,
-        CTS4_MARK,      CTS3_MARK,      CTS2_MARK,
-        EVENT7_MARK,    EVENT6_MARK,    EVENT5_MARK,    EVENT4_MARK,
-        EVENT3_MARK,    EVENT2_MARK,    EVENT1_MARK,    EVENT0_MARK,
+        /* PTN (mobule: USB, JMC, SGPIO, WDT) */
+        VBUS_EN_MARK,   VBUS_OC_MARK,   JMCTCK_MARK,    JMCTMS_MARK,
+        JMCTDO_MARK,    JMCTDI_MARK,    JMCTRST_MARK,
+        SGPIO1_CLK_MARK,        SGPIO1_LOAD_MARK,       SGPIO1_DI_MARK,
+        SGPIO1_DO_MARK,         SUB_CLKIN_MARK,
 
-        /* PTO (mobule: SGPIO) */
-        SGPIO0_CLK_MARK,        SGPIO0_LOAD_MARK,
-        SGPIO0_DI_MARK,         SGPIO0_DO_MARK,
-        SGPIO1_CLK_MARK,        SGPIO1_LOAD_MARK,
-        SGPIO1_DI_MARK,         SGPIO1_DO_MARK,
-
-        /* PTP (mobule: JMC, SCIF234) */
-        JMCTCK_MARK,    JMCTMS_MARK,    JMCTDO_MARK,    JMCTDI_MARK,
-        JMCRST_MARK,    SCK4_MARK,      SCK3_MARK,
+        /* PTO (mobule: SGPIO, SerMux) */
+        SGPIO0_CLK_MARK,        SGPIO0_LOAD_MARK,       SGPIO0_DI_MARK,
+        SGPIO0_DO_MARK,         SGPIO2_CLK_MARK,        SGPIO2_LOAD_MARK,
+        SGPIO2_DI_MARK,         SGPIO2_DO_MARK,
+        COM1_TXD_MARK,  COM1_RXD_MARK,  COM1_RTS_MARK,  COM1_CTS_MARK,
 
         /* PTQ (mobule: LPC) */
         LAD3_MARK,      LAD2_MARK,      LAD1_MARK,      LAD0_MARK,
         LFRAME_MARK,    LRESET_MARK,    LCLK_MARK,
 
         /* PTR (mobule: GRA, IIC) */
-        DDC3_MARK,      DDC2_MARK,
-        SDA8_MARK,      SCL8_MARK,      SDA2_MARK,      SCL2_MARK,
+        DDC3_MARK,      DDC2_MARK,      SDA2_MARK,      SCL2_MARK,
         SDA1_MARK,      SCL1_MARK,      SDA0_MARK,      SCL0_MARK,
+        SDA8_MARK,      SCL8_MARK,
 
         /* PTS (mobule: GRA, IIC) */
-        DDC1_MARK,      DDC0_MARK,
-        SDA9_MARK,      SCL9_MARK,      SDA5_MARK,      SCL5_MARK,
+        DDC1_MARK,      DDC0_MARK,      SDA5_MARK,      SCL5_MARK,
         SDA4_MARK,      SCL4_MARK,      SDA3_MARK,      SCL3_MARK,
+        SDA9_MARK,      SCL9_MARK,
 
-        /* PTT (mobule: SYSTEM, PWMX) */
-        AUDSYNC_MARK,           AUDCK_MARK,
-        AUDATA3_MARK,           AUDATA2_MARK,
-        AUDATA1_MARK,           AUDATA0_MARK,
-        PWX7_MARK,      PWX6_MARK,      PWX5_MARK,      PWX4_MARK,
+        /* PTT (mobule: PWMX, AUD) */
+        PWMX7_MARK,     PWMX6_MARK,     PWMX5_MARK,     PWMX4_MARK,
+        PWMX3_MARK,     PWMX2_MARK,     PWMX1_MARK,     PWMX0_MARK,
+        AUDATA3_MARK,   AUDATA2_MARK,   AUDATA1_MARK,   AUDATA0_MARK,
+        STATUS1_MARK,   STATUS0_MARK,
 
-        /* PTU (mobule: LBSC, DMAC) */
-        CS6_MARK,       CS5_MARK,       CS4_MARK,       CS0_MARK,
-        RD_MARK,        WE0_MARK,       A25_MARK,       A24_MARK,
-        DREQ0_MARK,     DACK0_MARK,
+        /* PTU (mobule: LPC, APM) */
+        LGPIO7_MARK,    LGPIO6_MARK,    LGPIO5_MARK,    LGPIO4_MARK,
+        LGPIO3_MARK,    LGPIO2_MARK,    LGPIO1_MARK,    LGPIO0_MARK,
+        APMONCTL_O_MARK,        APMPWBTOUT_O_MARK,      APMSCI_O_MARK,
+        APMVDDON_MARK,  APMSLPBTN_MARK, APMPWRBTN_MARK, APMS5N_MARK,
+        APMS3N_MARK,
 
-        /* PTV (mobule: LBSC, DMAC) */
+        /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
         A23_MARK,       A22_MARK,       A21_MARK,       A20_MARK,
         A19_MARK,       A18_MARK,       A17_MARK,       A16_MARK,
-        TEND0_MARK,     DREQ1_MARK,     DACK1_MARK,     TEND1_MARK,
+        COM2_RI_MARK,           R_SPI_MOSI_MARK,        R_SPI_MISO_MARK,
+        R_SPI_RSPCK_MARK,       R_SPI_SSL0_MARK,        R_SPI_SSL1_MARK,
+        EVENT7_MARK,    EVENT6_MARK,    VBIOS_DI_MARK,  VBIOS_DO_MARK,
+        VBIOS_CLK_MARK, VBIOS_CS_MARK,
 
-        /* PTW (mobule: LBSC) */
+        /* PTW (mobule: LBSC, EVC, SCIF) */
         A15_MARK,       A14_MARK,       A13_MARK,       A12_MARK,
         A11_MARK,       A10_MARK,       A9_MARK,        A8_MARK,
+        EVENT5_MARK,    EVENT4_MARK,    EVENT3_MARK,    EVENT2_MARK,
+        EVENT1_MARK,    EVENT0_MARK,    CTS4_MARK,      CTS2_MARK,
 
-        /* PTX (mobule: LBSC) */
+        /* PTX (mobule: LBSC, SCIF, SIM) */
         A7_MARK,        A6_MARK,        A5_MARK,        A4_MARK,
         A3_MARK,        A2_MARK,        A1_MARK,        A0_MARK,
+        RTS2_MARK,      SIM_D_MARK,     SIM_CLK_MARK,   SIM_RST_MARK,
 
         /* PTY (mobule: LBSC) */
         D7_MARK,        D6_MARK,        D5_MARK,        D4_MARK,
         D3_MARK,        D2_MARK,        D1_MARK,        D0_MARK,
+
+        /* PTZ (mobule: eMMC, ONFI) */
+        MMCDAT7_MARK,   MMCDAT6_MARK,   MMCDAT5_MARK,   MMCDAT4_MARK,
+        MMCDAT3_MARK,   MMCDAT2_MARK,   MMCDAT1_MARK,   MMCDAT0_MARK,
+        ON_DQ7_MARK,    ON_DQ6_MARK,    ON_DQ5_MARK,    ON_DQ4_MARK,
+        ON_DQ3_MARK,    ON_DQ2_MARK,    ON_DQ1_MARK,    ON_DQ0_MARK,
+
         PINMUX_MARK_END,
 };
 
@@ -473,6 +567,8 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
 
         /* PTE GPIO */
+        PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT),
+        PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT),
         PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT),
         PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
         PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
@@ -521,7 +617,6 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(PTI0_DATA, PTI0_IN, PTI0_OUT),
 
         /* PTJ GPIO */
-        PINMUX_DATA(PTJ7_DATA, PTJ7_IN, PTJ7_OUT),
         PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT),
         PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT),
         PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT),
@@ -541,7 +636,6 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
 
         /* PTL GPIO */
-        PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT),
         PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
         PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
         PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
@@ -560,7 +654,6 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
 
         /* PTN GPIO */
-        PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT),
         PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT),
         PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT),
         PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT),
@@ -609,6 +702,8 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
 
         /* PTT GPIO */
+        PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT),
+        PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT),
         PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT),
         PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
         PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
@@ -677,186 +772,204 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT),
 
         /* PTA FN */
-        PINMUX_DATA(BS_MARK, PS0_15_FN1, PTA7_FN),
-        PINMUX_DATA(LGPIO7_MARK, PS0_15_FN3, PTA7_FN),
-        PINMUX_DATA(RDWR_MARK, PS0_14_FN1, PTA6_FN),
-        PINMUX_DATA(LGPIO6_MARK, PS0_14_FN3, PTA6_FN),
-        PINMUX_DATA(WE1_MARK, PS0_13_FN1, PTA5_FN),
-        PINMUX_DATA(LGPIO5_MARK, PS0_13_FN3, PTA5_FN),
-        PINMUX_DATA(RDY_MARK, PS0_12_FN1, PTA4_FN),
-        PINMUX_DATA(LGPIO4_MARK, PS0_12_FN3, PTA4_FN),
-        PINMUX_DATA(LGPIO3_MARK, PTA3_FN),
-        PINMUX_DATA(LGPIO2_MARK, PTA2_FN),
-        PINMUX_DATA(LGPIO1_MARK, PTA1_FN),
-        PINMUX_DATA(LGPIO0_MARK, PTA0_FN),
+        PINMUX_DATA(BS_MARK, PTA7_FN),
+        PINMUX_DATA(RDWR_MARK, PTA6_FN),
+        PINMUX_DATA(WE1_MARK, PTA5_FN),
+        PINMUX_DATA(RDY_MARK, PTA4_FN),
+        PINMUX_DATA(ET0_MDC_MARK, PTA3_FN),
+        PINMUX_DATA(ET0_MDIO_MARK, PTA2_FN),
+        PINMUX_DATA(ET1_MDC_MARK, PTA1_FN),
+        PINMUX_DATA(ET1_MDIO_MARK, PTA0_FN),
 
         /* PTB FN */
-        PINMUX_DATA(D15_MARK, PS0_7_FN1, PTB7_FN),
-        PINMUX_DATA(ET0_MDC_MARK, PS0_7_FN2, PTB7_FN),
-        PINMUX_DATA(D14_MARK, PS0_6_FN1, PTB6_FN),
-        PINMUX_DATA(ET0_MDIO_MARK, PS0_6_FN2, PTB6_FN),
-        PINMUX_DATA(D13_MARK, PS0_5_FN1, PTB5_FN),
-        PINMUX_DATA(ET1_MDC_MARK, PS0_5_FN2, PTB5_FN),
-        PINMUX_DATA(D12_MARK, PS0_4_FN1, PTB4_FN),
-        PINMUX_DATA(ET1_MDIO_MARK, PS0_4_FN2, PTB4_FN),
-        PINMUX_DATA(D11_MARK, PS0_3_FN1, PTB3_FN),
-        PINMUX_DATA(SIM_D_MARK, PS0_3_FN2, PTB3_FN),
-        PINMUX_DATA(D10_MARK, PS0_2_FN1, PTB2_FN),
-        PINMUX_DATA(SIM_CLK_MARK, PS0_2_FN2, PTB2_FN),
-        PINMUX_DATA(D9_MARK, PS0_1_FN1, PTB1_FN),
-        PINMUX_DATA(SIM_RST_MARK, PS0_1_FN2, PTB1_FN),
-        PINMUX_DATA(D8_MARK, PTB0_FN),
+        PINMUX_DATA(IRQ15_MARK, PS0_15_FN1, PTB7_FN),
+        PINMUX_DATA(ON_NRE_MARK, PS0_15_FN2, PTB7_FN),
+        PINMUX_DATA(IRQ14_MARK, PS0_14_FN1, PTB6_FN),
+        PINMUX_DATA(ON_NWE_MARK, PS0_14_FN2, PTB6_FN),
+        PINMUX_DATA(IRQ13_MARK, PS0_13_FN1, PTB5_FN),
+        PINMUX_DATA(ON_NWP_MARK, PS0_13_FN2, PTB5_FN),
+        PINMUX_DATA(IRQ12_MARK, PS0_12_FN1, PTB4_FN),
+        PINMUX_DATA(ON_NCE0_MARK, PS0_12_FN2, PTB4_FN),
+        PINMUX_DATA(IRQ11_MARK, PS0_11_FN1, PTB3_FN),
+        PINMUX_DATA(ON_R_B0_MARK, PS0_11_FN2, PTB3_FN),
+        PINMUX_DATA(IRQ10_MARK, PS0_10_FN1, PTB2_FN),
+        PINMUX_DATA(ON_ALE_MARK, PS0_10_FN2, PTB2_FN),
+        PINMUX_DATA(IRQ9_MARK, PS0_9_FN1, PTB1_FN),
+        PINMUX_DATA(ON_CLE_MARK, PS0_9_FN2, PTB1_FN),
+        PINMUX_DATA(IRQ8_MARK, PS0_8_FN1, PTB0_FN),
+        PINMUX_DATA(TCLK_MARK, PS0_8_FN2, PTB0_FN),
 
         /* PTC FN */
-        PINMUX_DATA(SD_WP_MARK, PTC7_FN),
-        PINMUX_DATA(SD_CD_MARK, PTC6_FN),
-        PINMUX_DATA(SD_CLK_MARK, PTC5_FN),
-        PINMUX_DATA(SD_CMD_MARK, PTC4_FN),
-        PINMUX_DATA(SD_D3_MARK, PTC3_FN),
-        PINMUX_DATA(SD_D2_MARK, PTC2_FN),
-        PINMUX_DATA(SD_D1_MARK, PTC1_FN),
-        PINMUX_DATA(SD_D0_MARK, PTC0_FN),
+        PINMUX_DATA(IRQ7_MARK, PS0_7_FN1, PTC7_FN),
+        PINMUX_DATA(PWMU0_MARK, PS0_7_FN2, PTC7_FN),
+        PINMUX_DATA(IRQ6_MARK, PS0_6_FN1, PTC6_FN),
+        PINMUX_DATA(PWMU1_MARK, PS0_6_FN2, PTC6_FN),
+        PINMUX_DATA(IRQ5_MARK, PS0_5_FN1, PTC5_FN),
+        PINMUX_DATA(PWMU2_MARK, PS0_5_FN2, PTC5_FN),
+        PINMUX_DATA(IRQ4_MARK, PS0_4_FN1, PTC5_FN),
+        PINMUX_DATA(PWMU3_MARK, PS0_4_FN2, PTC4_FN),
+        PINMUX_DATA(IRQ3_MARK, PS0_3_FN1, PTC3_FN),
+        PINMUX_DATA(PWMU4_MARK, PS0_3_FN2, PTC3_FN),
+        PINMUX_DATA(IRQ2_MARK, PS0_2_FN1, PTC2_FN),
+        PINMUX_DATA(PWMU5_MARK, PS0_2_FN2, PTC2_FN),
+        PINMUX_DATA(IRQ1_MARK, PTC1_FN),
+        PINMUX_DATA(IRQ0_MARK, PTC0_FN),
 
         /* PTD FN */
-        PINMUX_DATA(IRQ7_MARK, PS1_7_FN1, PTD7_FN),
-        PINMUX_DATA(ADTRG1_MARK, PS1_7_FN3, PTD7_FN),
-        PINMUX_DATA(IRQ6_MARK, PS1_6_FN1, PTD6_FN),
-        PINMUX_DATA(ADTRG0_MARK, PS1_6_FN3, PTD6_FN),
-        PINMUX_DATA(IRQ5_MARK, PTD5_FN),
-        PINMUX_DATA(IRQ4_MARK, PTD4_FN),
-        PINMUX_DATA(IRQ3_MARK, PTD3_FN),
-        PINMUX_DATA(IRQ2_MARK, PTD2_FN),
-        PINMUX_DATA(IRQ1_MARK, PTD1_FN),
-        PINMUX_DATA(IRQ0_MARK, PTD0_FN),
+        PINMUX_DATA(SP0_MOSI_MARK, PTD7_FN),
+        PINMUX_DATA(SP0_MISO_MARK, PTD6_FN),
+        PINMUX_DATA(SP0_SCK_MARK, PTD5_FN),
+        PINMUX_DATA(SP0_SCK_FB_MARK, PTD4_FN),
+        PINMUX_DATA(SP0_SS0_MARK, PTD3_FN),
+        PINMUX_DATA(SP0_SS1_MARK, PS1_10_FN1, PTD2_FN),
+        PINMUX_DATA(DREQ0_MARK, PS1_10_FN2, PTD2_FN),
+        PINMUX_DATA(SP0_SS2_MARK, PS1_9_FN1, PTD1_FN),
+        PINMUX_DATA(DACK0_MARK, PS1_9_FN2, PTD1_FN),
+        PINMUX_DATA(SP0_SS3_MARK, PS1_8_FN1, PTD0_FN),
+        PINMUX_DATA(TEND0_MARK, PS1_8_FN2, PTD0_FN),
 
         /* PTE FN */
-        PINMUX_DATA(ET0_CRS_DV_MARK, PTE7_FN),
-        PINMUX_DATA(ET0_TXD1_MARK, PTE6_FN),
-        PINMUX_DATA(ET0_TXD0_MARK, PTE5_FN),
-        PINMUX_DATA(ET0_TX_EN_MARK, PTE4_FN),
-        PINMUX_DATA(ET0_REF_CLK_MARK, PTE3_FN),
-        PINMUX_DATA(ET0_RXD1_MARK, PTE2_FN),
-        PINMUX_DATA(ET0_RXD0_MARK, PTE1_FN),
-        PINMUX_DATA(ET0_RX_ER_MARK, PTE0_FN),
+        PINMUX_DATA(RMII0_CRS_DV_MARK, PTE7_FN),
+        PINMUX_DATA(RMII0_TXD1_MARK, PTE6_FN),
+        PINMUX_DATA(RMII0_TXD0_MARK, PTE5_FN),
+        PINMUX_DATA(RMII0_TXEN_MARK, PTE4_FN),
+        PINMUX_DATA(RMII0_REFCLK_MARK, PTE3_FN),
+        PINMUX_DATA(RMII0_RXD1_MARK, PTE2_FN),
+        PINMUX_DATA(RMII0_RXD0_MARK, PTE1_FN),
+        PINMUX_DATA(RMII0_RX_ER_MARK, PTE0_FN),
 
         /* PTF FN */
-        PINMUX_DATA(ET1_CRS_DV_MARK, PTF7_FN),
-        PINMUX_DATA(ET1_TXD1_MARK, PTF6_FN),
-        PINMUX_DATA(ET1_TXD0_MARK, PTF5_FN),
-        PINMUX_DATA(ET1_TX_EN_MARK, PTF4_FN),
-        PINMUX_DATA(ET1_REF_CLK_MARK, PTF3_FN),
-        PINMUX_DATA(ET1_RXD1_MARK, PTF2_FN),
-        PINMUX_DATA(ET1_RXD0_MARK, PTF1_FN),
-        PINMUX_DATA(ET1_RX_ER_MARK, PTF0_FN),
+        PINMUX_DATA(RMII1_CRS_DV_MARK, PTF7_FN),
+        PINMUX_DATA(RMII1_TXD1_MARK, PTF6_FN),
+        PINMUX_DATA(RMII1_TXD0_MARK, PTF5_FN),
+        PINMUX_DATA(RMII1_TXEN_MARK, PTF4_FN),
+        PINMUX_DATA(RMII1_REFCLK_MARK, PTF3_FN),
+        PINMUX_DATA(RMII1_RXD1_MARK, PS1_2_FN1, PTF2_FN),
+        PINMUX_DATA(RAC_RI_MARK, PS1_2_FN2, PTF2_FN),
+        PINMUX_DATA(RMII1_RXD0_MARK, PTF1_FN),
+        PINMUX_DATA(RMII1_RX_ER_MARK, PTF0_FN),
 
         /* PTG FN */
-        PINMUX_DATA(PWX0_MARK, PTG7_FN),
-        PINMUX_DATA(PWX1_MARK, PTG6_FN),
-        PINMUX_DATA(STATUS0_MARK, PS2_13_FN1, PTG5_FN),
-        PINMUX_DATA(PWX2_MARK, PS2_13_FN3, PTG5_FN),
-        PINMUX_DATA(STATUS1_MARK, PS2_12_FN1, PTG4_FN),
-        PINMUX_DATA(PWX3_MARK, PS2_12_FN3, PTG4_FN),
+        PINMUX_DATA(BOOTFMS_MARK, PTG7_FN),
+        PINMUX_DATA(BOOTWP_MARK, PTG6_FN),
+        PINMUX_DATA(A25_MARK, PS2_13_FN1, PTG5_FN),
+        PINMUX_DATA(MMCCLK_MARK, PS2_13_FN2, PTG5_FN),
+        PINMUX_DATA(A24_MARK, PS2_12_FN1, PTG4_FN),
+        PINMUX_DATA(MMCCMD_MARK, PS2_12_FN2, PTG4_FN),
         PINMUX_DATA(SERIRQ_MARK, PTG3_FN),
-        PINMUX_DATA(CLKRUN_MARK, PTG2_FN),
+        PINMUX_DATA(WDTOVF_MARK, PTG2_FN),
         PINMUX_DATA(LPCPD_MARK, PTG1_FN),
         PINMUX_DATA(LDRQ_MARK, PTG0_FN),
 
         /* PTH FN */
-        PINMUX_DATA(SP1_MOSI_MARK, PTH7_FN),
-        PINMUX_DATA(SP1_MISO_MARK, PTH6_FN),
-        PINMUX_DATA(SP1_SCK_MARK, PTH5_FN),
-        PINMUX_DATA(SP1_SCK_FB_MARK, PTH4_FN),
+        PINMUX_DATA(SP1_MOSI_MARK, PS2_7_FN1, PTH7_FN),
+        PINMUX_DATA(TEND1_MARK, PS2_7_FN2, PTH7_FN),
+        PINMUX_DATA(SP1_MISO_MARK, PS2_6_FN1, PTH6_FN),
+        PINMUX_DATA(DREQ1_MARK, PS2_6_FN2, PTH6_FN),
+        PINMUX_DATA(SP1_SCK_MARK, PS2_5_FN1, PTH5_FN),
+        PINMUX_DATA(DACK1_MARK, PS2_5_FN2, PTH5_FN),
+        PINMUX_DATA(SP1_SCK_FB_MARK, PS2_4_FN1, PTH4_FN),
+        PINMUX_DATA(ADTRG1_MARK, PS2_4_FN2, PTH4_FN),
         PINMUX_DATA(SP1_SS0_MARK, PTH3_FN),
-        PINMUX_DATA(TCLK_MARK, PTH2_FN),
-        PINMUX_DATA(RXD4_MARK, PS2_1_FN1, PTH1_FN),
-        PINMUX_DATA(SP1_SS1_MARK, PS2_1_FN2, PTH1_FN),
-        PINMUX_DATA(TXD4_MARK, PS2_0_FN1, PTH0_FN),
-        PINMUX_DATA(SP0_SS1_MARK, PS2_0_FN2, PTH0_FN),
+        PINMUX_DATA(SP1_SS1_MARK, PS2_2_FN1, PTH2_FN),
+        PINMUX_DATA(ADTRG0_MARK, PS2_2_FN2, PTH2_FN),
+        PINMUX_DATA(WP_MARK, PTH1_FN),
+        PINMUX_DATA(FMS0_MARK, PTH0_FN),
 
         /* PTI FN */
-        PINMUX_DATA(IRQ15_MARK, PTI7_FN),
-        PINMUX_DATA(IRQ14_MARK, PTI6_FN),
-        PINMUX_DATA(IRQ13_MARK, PTI5_FN),
-        PINMUX_DATA(IRQ12_MARK, PTI4_FN),
-        PINMUX_DATA(IRQ11_MARK, PTI3_FN),
-        PINMUX_DATA(IRQ10_MARK, PTI2_FN),
-        PINMUX_DATA(IRQ9_MARK, PTI1_FN),
-        PINMUX_DATA(IRQ8_MARK, PTI0_FN),
+        PINMUX_DATA(D15_MARK, PS3_15_FN1, PTI7_FN),
+        PINMUX_DATA(SD_WP_MARK, PS3_15_FN2, PTI7_FN),
+        PINMUX_DATA(D14_MARK, PS3_14_FN1, PTI6_FN),
+        PINMUX_DATA(SD_CD_MARK, PS3_14_FN2, PTI6_FN),
+        PINMUX_DATA(D13_MARK, PS3_13_FN1, PTI5_FN),
+        PINMUX_DATA(SD_CLK_MARK, PS3_13_FN2, PTI5_FN),
+        PINMUX_DATA(D12_MARK, PS3_12_FN1, PTI4_FN),
+        PINMUX_DATA(SD_CMD_MARK, PS3_12_FN2, PTI4_FN),
+        PINMUX_DATA(D11_MARK, PS3_11_FN1, PTI3_FN),
+        PINMUX_DATA(SD_D3_MARK, PS3_11_FN2, PTI3_FN),
+        PINMUX_DATA(D10_MARK, PS3_10_FN1, PTI2_FN),
+        PINMUX_DATA(SD_D2_MARK, PS3_10_FN2, PTI2_FN),
+        PINMUX_DATA(D9_MARK, PS3_9_FN1, PTI1_FN),
+        PINMUX_DATA(SD_D1_MARK, PS3_9_FN2, PTI1_FN),
+        PINMUX_DATA(D8_MARK, PS3_8_FN1, PTI0_FN),
+        PINMUX_DATA(SD_D0_MARK, PS3_8_FN2, PTI0_FN),
 
         /* PTJ FN */
-        PINMUX_DATA(RXD3_MARK, PTJ7_FN),
-        PINMUX_DATA(TXD3_MARK, PTJ6_FN),
-        PINMUX_DATA(RXD2_MARK, PTJ5_FN),
-        PINMUX_DATA(TXD2_MARK, PTJ4_FN),
-        PINMUX_DATA(COM1_TXD_MARK, PTJ3_FN),
-        PINMUX_DATA(COM1_RXD_MARK, PTJ2_FN),
-        PINMUX_DATA(COM1_RTS_MARK, PTJ1_FN),
-        PINMUX_DATA(COM1_CTS_MARK, PTJ0_FN),
+        PINMUX_DATA(RTS3_MARK, PTJ6_FN),
+        PINMUX_DATA(CTS3_MARK, PTJ5_FN),
+        PINMUX_DATA(TXD3_MARK, PTJ4_FN),
+        PINMUX_DATA(RXD3_MARK, PTJ3_FN),
+        PINMUX_DATA(RTS4_MARK, PTJ2_FN),
+        PINMUX_DATA(RXD4_MARK, PTJ1_FN),
+        PINMUX_DATA(TXD4_MARK, PTJ0_FN),
 
         /* PTK FN */
-        PINMUX_DATA(COM2_TXD_MARK, PTK7_FN),
+        PINMUX_DATA(COM2_TXD_MARK, PS3_7_FN1, PTK7_FN),
+        PINMUX_DATA(SCK2_MARK, PS3_7_FN2, PTK7_FN),
         PINMUX_DATA(COM2_RXD_MARK, PTK6_FN),
         PINMUX_DATA(COM2_RTS_MARK, PTK5_FN),
         PINMUX_DATA(COM2_CTS_MARK, PTK4_FN),
         PINMUX_DATA(COM2_DTR_MARK, PTK3_FN),
-        PINMUX_DATA(COM2_DSR_MARK, PTK2_FN),
-        PINMUX_DATA(COM2_DCD_MARK, PTK1_FN),
-        PINMUX_DATA(COM2_RI_MARK, PTK0_FN),
+        PINMUX_DATA(COM2_DSR_MARK, PS3_2_FN1, PTK2_FN),
+        PINMUX_DATA(SCK4_MARK, PS3_2_FN2, PTK2_FN),
+        PINMUX_DATA(COM2_DCD_MARK, PS3_1_FN1, PTK1_FN),
+        PINMUX_DATA(SCK3_MARK, PS3_1_FN2, PTK1_FN),
+        PINMUX_DATA(CLKOUT_MARK, PTK0_FN),
 
         /* PTL FN */
-        PINMUX_DATA(RAC_TXD_MARK, PTL7_FN),
-        PINMUX_DATA(RAC_RXD_MARK, PTL6_FN),
-        PINMUX_DATA(RAC_RTS_MARK, PTL5_FN),
-        PINMUX_DATA(RAC_CTS_MARK, PTL4_FN),
+        PINMUX_DATA(RAC_RXD_MARK, PS4_14_FN1, PTL6_FN),
+        PINMUX_DATA(RXD2_MARK, PS4_14_FN2, PTL6_FN),
+        PINMUX_DATA(RAC_RTS_MARK, PS4_13_FN1, PTL5_FN),
+        PINMUX_DATA(CS5_MARK, PS4_13_FN2, PTL5_FN),
+        PINMUX_DATA(RAC_CTS_MARK, PS4_12_FN1, PTL4_FN),
+        PINMUX_DATA(CS6_MARK, PS4_12_FN2, PTL4_FN),
         PINMUX_DATA(RAC_DTR_MARK, PTL3_FN),
-        PINMUX_DATA(RAC_DSR_MARK, PTL2_FN),
-        PINMUX_DATA(RAC_DCD_MARK, PTL1_FN),
-        PINMUX_DATA(RAC_RI_MARK, PTL0_FN),
+        PINMUX_DATA(RAC_DSR_MARK, PS4_10_FN1, PTL2_FN),
+        PINMUX_DATA(AUDSYNC_MARK, PS4_10_FN2, PTL2_FN),
+        PINMUX_DATA(RAC_DCD_MARK, PS4_9_FN1, PTL1_FN),
+        PINMUX_DATA(AUDCK_MARK, PS4_9_FN2, PTL1_FN),
+        PINMUX_DATA(RAC_TXD_MARK, PS4_8_FN1, PTL0_FN),
+        PINMUX_DATA(TXD2_MARK, PS4_8_FN1, PTL0_FN),
 
         /* PTM FN */
-        PINMUX_DATA(WP_MARK, PTM6_FN),
-        PINMUX_DATA(FMS0_MARK, PTM5_FN),
-        PINMUX_DATA(FMS1_MARK, PTM4_FN),
+        PINMUX_DATA(CS4_MARK, PTM7_FN),
+        PINMUX_DATA(RD_MARK, PTM6_FN),
+        PINMUX_DATA(WE0_MARK, PTM7_FN),
+        PINMUX_DATA(CS0_MARK, PTM4_FN),
         PINMUX_DATA(SDA6_MARK, PTM3_FN),
         PINMUX_DATA(SCL6_MARK, PTM2_FN),
         PINMUX_DATA(SDA7_MARK, PTM1_FN),
         PINMUX_DATA(SCL7_MARK, PTM0_FN),
 
         /* PTN FN */
-        PINMUX_DATA(SCK2_MARK, PS4_15_FN1, PTN7_FN),
-        PINMUX_DATA(EVENT7_MARK, PS4_15_FN2, PTN7_FN),
-        PINMUX_DATA(RTS4_MARK, PS4_14_FN1, PTN6_FN),
-        PINMUX_DATA(EVENT6_MARK, PS4_14_FN2, PTN6_FN),
-        PINMUX_DATA(RTS3_MARK, PS4_13_FN1, PTN5_FN),
-        PINMUX_DATA(EVENT5_MARK, PS4_13_FN2, PTN5_FN),
-        PINMUX_DATA(RTS2_MARK, PS4_12_FN1, PTN4_FN),
-        PINMUX_DATA(EVENT4_MARK, PS4_12_FN2, PTN4_FN),
-        PINMUX_DATA(CTS4_MARK, PS4_11_FN1, PTN3_FN),
-        PINMUX_DATA(EVENT3_MARK, PS4_11_FN2, PTN3_FN),
-        PINMUX_DATA(CTS3_MARK, PS4_10_FN1, PTN2_FN),
-        PINMUX_DATA(EVENT2_MARK, PS4_10_FN2, PTN2_FN),
-        PINMUX_DATA(CTS2_MARK, PS4_9_FN1, PTN1_FN),
-        PINMUX_DATA(EVENT1_MARK, PS4_9_FN2, PTN1_FN),
-        PINMUX_DATA(EVENT0_MARK, PTN0_FN),
+        PINMUX_DATA(VBUS_EN_MARK, PTN6_FN),
+        PINMUX_DATA(VBUS_OC_MARK, PTN5_FN),
+        PINMUX_DATA(JMCTCK_MARK, PS4_4_FN1, PTN4_FN),
+        PINMUX_DATA(SGPIO1_CLK_MARK, PS4_4_FN2, PTN4_FN),
+        PINMUX_DATA(JMCTMS_MARK, PS4_3_FN1, PTN5_FN),
+        PINMUX_DATA(SGPIO1_LOAD_MARK, PS4_3_FN2, PTN5_FN),
+        PINMUX_DATA(JMCTDO_MARK, PS4_2_FN1, PTN2_FN),
+        PINMUX_DATA(SGPIO1_DO_MARK, PS4_2_FN2, PTN2_FN),
+        PINMUX_DATA(JMCTDI_MARK, PS4_1_FN1, PTN1_FN),
+        PINMUX_DATA(SGPIO1_DI_MARK, PS4_1_FN2, PTN1_FN),
+        PINMUX_DATA(JMCTRST_MARK, PS4_0_FN1, PTN0_FN),
+        PINMUX_DATA(SUB_CLKIN_MARK, PS4_0_FN2, PTN0_FN),
 
         /* PTO FN */
         PINMUX_DATA(SGPIO0_CLK_MARK, PTO7_FN),
         PINMUX_DATA(SGPIO0_LOAD_MARK, PTO6_FN),
         PINMUX_DATA(SGPIO0_DI_MARK, PTO5_FN),
         PINMUX_DATA(SGPIO0_DO_MARK, PTO4_FN),
-        PINMUX_DATA(SGPIO1_CLK_MARK, PTO3_FN),
-        PINMUX_DATA(SGPIO1_LOAD_MARK, PTO2_FN),
-        PINMUX_DATA(SGPIO1_DI_MARK, PTO1_FN),
-        PINMUX_DATA(SGPIO1_DO_MARK, PTO0_FN),
+        PINMUX_DATA(SGPIO2_CLK_MARK, PS5_11_FN1, PTO3_FN),
+        PINMUX_DATA(COM1_TXD_MARK, PS5_11_FN2, PTO3_FN),
+        PINMUX_DATA(SGPIO2_LOAD_MARK, PS5_10_FN1, PTO2_FN),
+        PINMUX_DATA(COM1_RXD_MARK, PS5_10_FN2, PTO2_FN),
+        PINMUX_DATA(SGPIO2_DI_MARK, PS5_9_FN1, PTO1_FN),
+        PINMUX_DATA(COM1_RTS_MARK, PS5_9_FN2, PTO1_FN),
+        PINMUX_DATA(SGPIO2_DO_MARK, PS5_8_FN1, PTO0_FN),
+        PINMUX_DATA(COM1_CTS_MARK, PS5_8_FN2, PTO0_FN),
 
         /* PTP FN */
-        PINMUX_DATA(JMCTCK_MARK, PTP6_FN),
-        PINMUX_DATA(JMCTMS_MARK, PTP5_FN),
-        PINMUX_DATA(JMCTDO_MARK, PTP4_FN),
-        PINMUX_DATA(JMCTDI_MARK, PTP3_FN),
-        PINMUX_DATA(JMCRST_MARK, PTP2_FN),
-        PINMUX_DATA(SCK4_MARK, PTP1_FN),
-        PINMUX_DATA(SCK3_MARK, PTP0_FN),
 
         /* PTQ FN */
         PINMUX_DATA(LAD3_MARK, PTQ6_FN),
@@ -864,8 +977,8 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(LAD1_MARK, PTQ4_FN),
         PINMUX_DATA(LAD0_MARK, PTQ3_FN),
         PINMUX_DATA(LFRAME_MARK, PTQ2_FN),
-        PINMUX_DATA(SCK4_MARK, PTQ1_FN),
-        PINMUX_DATA(SCK3_MARK, PTQ0_FN),
+        PINMUX_DATA(LRESET_MARK, PTQ1_FN),
+        PINMUX_DATA(LCLK_MARK, PTQ0_FN),
 
         /* PTR FN */
         PINMUX_DATA(SDA8_MARK, PTR7_FN),        /* DDC3? */
@@ -888,58 +1001,84 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(SCL3_MARK, PTS0_FN),
 
         /* PTT FN */
-        PINMUX_DATA(AUDSYNC_MARK, PTS5_FN),
-        PINMUX_DATA(AUDCK_MARK, PTS4_FN),
-        PINMUX_DATA(AUDATA3_MARK, PS4_3_FN1, PTS3_FN),
-        PINMUX_DATA(PWX7_MARK, PS4_3_FN2, PTS3_FN),
-        PINMUX_DATA(AUDATA2_MARK, PS4_2_FN1, PTS2_FN),
-        PINMUX_DATA(PWX6_MARK, PS4_2_FN2, PTS2_FN),
-        PINMUX_DATA(AUDATA1_MARK, PS4_1_FN1, PTS1_FN),
-        PINMUX_DATA(PWX5_MARK, PS4_1_FN2, PTS1_FN),
-        PINMUX_DATA(AUDATA0_MARK, PS4_0_FN1, PTS0_FN),
-        PINMUX_DATA(PWX4_MARK, PS4_0_FN2, PTS0_FN),
+        PINMUX_DATA(PWMX7_MARK, PS5_7_FN1, PTT7_FN),
+        PINMUX_DATA(AUDATA3_MARK, PS5_7_FN2, PTT7_FN),
+        PINMUX_DATA(PWMX6_MARK, PS5_6_FN1, PTT6_FN),
+        PINMUX_DATA(AUDATA2_MARK, PS5_6_FN2, PTT6_FN),
+        PINMUX_DATA(PWMX5_MARK, PS5_5_FN1, PTT5_FN),
+        PINMUX_DATA(AUDATA1_MARK, PS5_5_FN2, PTT5_FN),
+        PINMUX_DATA(PWMX4_MARK, PS5_4_FN1, PTT4_FN),
+        PINMUX_DATA(AUDATA0_MARK, PS5_4_FN2, PTT4_FN),
+        PINMUX_DATA(PWMX3_MARK, PS5_3_FN1, PTT3_FN),
+        PINMUX_DATA(STATUS1_MARK, PS5_3_FN2, PTT3_FN),
+        PINMUX_DATA(PWMX2_MARK, PS5_2_FN1, PTT2_FN),
+        PINMUX_DATA(STATUS0_MARK, PS5_2_FN2, PTT2_FN),
+        PINMUX_DATA(PWMX1_MARK, PTT1_FN),
+        PINMUX_DATA(PWMX0_MARK, PTT0_FN),
 
         /* PTU FN */
-        PINMUX_DATA(CS6_MARK, PTU7_FN),
-        PINMUX_DATA(CS5_MARK, PTU6_FN),
-        PINMUX_DATA(CS4_MARK, PTU5_FN),
-        PINMUX_DATA(CS0_MARK, PTU4_FN),
-        PINMUX_DATA(RD_MARK, PTU3_FN),
-        PINMUX_DATA(WE0_MARK, PTU2_FN),
-        PINMUX_DATA(A25_MARK, PS5_9_FN1, PTU1_FN),
-        PINMUX_DATA(DREQ0_MARK, PS5_9_FN2, PTU1_FN),
-        PINMUX_DATA(A24_MARK, PS5_8_FN1, PTU0_FN),
-        PINMUX_DATA(DACK0_MARK, PS5_8_FN2, PTU0_FN),
+        PINMUX_DATA(LGPIO7_MARK, PS6_15_FN1, PTU7_FN),
+        PINMUX_DATA(APMONCTL_O_MARK, PS6_15_FN2, PTU7_FN),
+        PINMUX_DATA(LGPIO6_MARK, PS6_14_FN1, PTU6_FN),
+        PINMUX_DATA(APMPWBTOUT_O_MARK, PS6_14_FN2, PTU6_FN),
+        PINMUX_DATA(LGPIO5_MARK, PS6_13_FN1, PTU5_FN),
+        PINMUX_DATA(APMSCI_O_MARK, PS6_13_FN2, PTU5_FN),
+        PINMUX_DATA(LGPIO4_MARK, PS6_12_FN1, PTU4_FN),
+        PINMUX_DATA(APMVDDON_MARK, PS6_12_FN2, PTU4_FN),
+        PINMUX_DATA(LGPIO3_MARK, PS6_11_FN1, PTU3_FN),
+        PINMUX_DATA(APMSLPBTN_MARK, PS6_11_FN2, PTU3_FN),
+        PINMUX_DATA(LGPIO2_MARK, PS6_10_FN1, PTU2_FN),
+        PINMUX_DATA(APMPWRBTN_MARK, PS6_10_FN2, PTU2_FN),
+        PINMUX_DATA(LGPIO1_MARK, PS6_9_FN1, PTU1_FN),
+        PINMUX_DATA(APMS5N_MARK, PS6_9_FN2, PTU1_FN),
+        PINMUX_DATA(LGPIO0_MARK, PS6_8_FN1, PTU0_FN),
+        PINMUX_DATA(APMS3N_MARK, PS6_8_FN2, PTU0_FN),
 
         /* PTV FN */
-        PINMUX_DATA(A23_MARK, PS5_7_FN1, PTV7_FN),
-        PINMUX_DATA(TEND0_MARK, PS5_7_FN2, PTV7_FN),
-        PINMUX_DATA(A22_MARK, PS5_6_FN1, PTV6_FN),
-        PINMUX_DATA(DREQ1_MARK, PS5_6_FN2, PTV6_FN),
-        PINMUX_DATA(A21_MARK, PS5_5_FN1, PTV5_FN),
-        PINMUX_DATA(DACK1_MARK, PS5_5_FN2, PTV5_FN),
-        PINMUX_DATA(A20_MARK, PS5_4_FN1, PTV4_FN),
-        PINMUX_DATA(TEND1_MARK, PS5_4_FN2, PTV4_FN),
-        PINMUX_DATA(A19_MARK, PTV3_FN),
-        PINMUX_DATA(A18_MARK, PTV2_FN),
-        PINMUX_DATA(A17_MARK, PTV1_FN),
-        PINMUX_DATA(A16_MARK, PTV0_FN),
+        PINMUX_DATA(A23_MARK, PS6_7_FN1, PTV7_FN),
+        PINMUX_DATA(COM2_RI_MARK, PS6_7_FN2, PTV7_FN),
+        PINMUX_DATA(A22_MARK, PS6_6_FN1, PTV6_FN),
+        PINMUX_DATA(R_SPI_MOSI_MARK, PS6_6_FN2, PTV6_FN),
+        PINMUX_DATA(A21_MARK, PS6_5_FN1, PTV5_FN),
+        PINMUX_DATA(R_SPI_MISO_MARK, PS6_5_FN2, PTV5_FN),
+        PINMUX_DATA(A20_MARK, PS6_4_FN1, PTV4_FN),
+        PINMUX_DATA(R_SPI_RSPCK_MARK, PS6_4_FN2, PTV4_FN),
+        PINMUX_DATA(A19_MARK, PS6_3_FN1, PTV3_FN),
+        PINMUX_DATA(R_SPI_SSL0_MARK, PS6_3_FN2, PTV3_FN),
+        PINMUX_DATA(A18_MARK, PS6_2_FN1, PTV2_FN),
+        PINMUX_DATA(R_SPI_SSL1_MARK, PS6_2_FN2, PTV2_FN),
+        PINMUX_DATA(A17_MARK, PS6_1_FN1, PTV1_FN),
+        PINMUX_DATA(EVENT7_MARK, PS6_1_FN2, PTV1_FN),
+        PINMUX_DATA(A16_MARK, PS6_0_FN1, PTV0_FN),
+        PINMUX_DATA(EVENT6_MARK, PS6_0_FN1, PTV0_FN),
 
         /* PTW FN */
-        PINMUX_DATA(A15_MARK, PTW7_FN),
-        PINMUX_DATA(A14_MARK, PTW6_FN),
-        PINMUX_DATA(A13_MARK, PTW5_FN),
-        PINMUX_DATA(A12_MARK, PTW4_FN),
-        PINMUX_DATA(A11_MARK, PTW3_FN),
-        PINMUX_DATA(A10_MARK, PTW2_FN),
-        PINMUX_DATA(A9_MARK, PTW1_FN),
-        PINMUX_DATA(A8_MARK, PTW0_FN),
+        PINMUX_DATA(A15_MARK, PS7_15_FN1, PTW7_FN),
+        PINMUX_DATA(EVENT5_MARK, PS7_15_FN2, PTW7_FN),
+        PINMUX_DATA(A14_MARK, PS7_14_FN1, PTW6_FN),
+        PINMUX_DATA(EVENT4_MARK, PS7_14_FN2, PTW6_FN),
+        PINMUX_DATA(A13_MARK, PS7_13_FN1, PTW5_FN),
+        PINMUX_DATA(EVENT3_MARK, PS7_13_FN2, PTW5_FN),
+        PINMUX_DATA(A12_MARK, PS7_12_FN1, PTW4_FN),
+        PINMUX_DATA(EVENT2_MARK, PS7_12_FN2, PTW4_FN),
+        PINMUX_DATA(A11_MARK, PS7_11_FN1, PTW3_FN),
+        PINMUX_DATA(EVENT1_MARK, PS7_11_FN2, PTW3_FN),
+        PINMUX_DATA(A10_MARK, PS7_10_FN1, PTW2_FN),
+        PINMUX_DATA(EVENT0_MARK, PS7_10_FN2, PTW2_FN),
+        PINMUX_DATA(A9_MARK, PS7_9_FN1, PTW1_FN),
+        PINMUX_DATA(CTS4_MARK, PS7_9_FN2, PTW1_FN),
+        PINMUX_DATA(A8_MARK, PS7_8_FN1, PTW0_FN),
+        PINMUX_DATA(CTS2_MARK, PS7_8_FN2, PTW0_FN),
 
         /* PTX FN */
-        PINMUX_DATA(A7_MARK, PTX7_FN),
-        PINMUX_DATA(A6_MARK, PTX6_FN),
-        PINMUX_DATA(A5_MARK, PTX5_FN),
-        PINMUX_DATA(A4_MARK, PTX4_FN),
+        PINMUX_DATA(A7_MARK, PS7_7_FN1, PTX7_FN),
+        PINMUX_DATA(RTS2_MARK, PS7_7_FN2, PTX7_FN),
+        PINMUX_DATA(A6_MARK, PS7_6_FN1, PTX6_FN),
+        PINMUX_DATA(SIM_D_MARK, PS7_6_FN2, PTX6_FN),
+        PINMUX_DATA(A5_MARK, PS7_5_FN1, PTX5_FN),
+        PINMUX_DATA(SIM_CLK_MARK, PS7_5_FN2, PTX5_FN),
+        PINMUX_DATA(A4_MARK, PS7_4_FN1, PTX4_FN),
+        PINMUX_DATA(SIM_RST_MARK, PS7_4_FN2, PTX4_FN),
         PINMUX_DATA(A3_MARK, PTX3_FN),
         PINMUX_DATA(A2_MARK, PTX2_FN),
         PINMUX_DATA(A1_MARK, PTX1_FN),
@@ -954,6 +1093,24 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(D2_MARK, PTY2_FN),
         PINMUX_DATA(D1_MARK, PTY1_FN),
         PINMUX_DATA(D0_MARK, PTY0_FN),
+
+        /* PTZ FN */
+        PINMUX_DATA(MMCDAT7_MARK, PS8_15_FN1, PTZ7_FN),
+        PINMUX_DATA(ON_DQ7_MARK, PS8_15_FN2, PTZ7_FN),
+        PINMUX_DATA(MMCDAT6_MARK, PS8_14_FN1, PTZ6_FN),
+        PINMUX_DATA(ON_DQ6_MARK, PS8_14_FN2, PTZ6_FN),
+        PINMUX_DATA(MMCDAT5_MARK, PS8_13_FN1, PTZ5_FN),
+        PINMUX_DATA(ON_DQ5_MARK, PS8_13_FN2, PTZ5_FN),
+        PINMUX_DATA(MMCDAT4_MARK, PS8_12_FN1, PTZ4_FN),
+        PINMUX_DATA(ON_DQ4_MARK, PS8_12_FN2, PTZ4_FN),
+        PINMUX_DATA(MMCDAT3_MARK, PS8_11_FN1, PTZ3_FN),
+        PINMUX_DATA(ON_DQ3_MARK, PS8_11_FN2, PTZ3_FN),
+        PINMUX_DATA(MMCDAT2_MARK, PS8_10_FN1, PTZ2_FN),
+        PINMUX_DATA(ON_DQ2_MARK, PS8_10_FN2, PTZ2_FN),
+        PINMUX_DATA(MMCDAT1_MARK, PS8_9_FN1, PTZ1_FN),
+        PINMUX_DATA(ON_DQ1_MARK, PS8_9_FN2, PTZ1_FN),
+        PINMUX_DATA(MMCDAT0_MARK, PS8_8_FN1, PTZ0_FN),
+        PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN),
 };
 
 static struct pinmux_gpio pinmux_gpios[] = {
@@ -1048,7 +1205,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PTI0, PTI0_DATA),
 
         /* PTJ */
-        PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
         PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
         PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
         PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA),
@@ -1068,7 +1224,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
 
         /* PTL */
-        PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
         PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
         PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
         PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
@@ -1078,6 +1233,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
 
         /* PTM */
+        PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
         PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
         PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
         PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
@@ -1087,7 +1243,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
 
         /* PTN */
-        PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
         PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
         PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
         PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
@@ -1107,6 +1262,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PTO0, PTO0_DATA),
 
         /* PTP */
+        PINMUX_GPIO(GPIO_PTP7, PTP7_DATA),
         PINMUX_GPIO(GPIO_PTP6, PTP6_DATA),
         PINMUX_GPIO(GPIO_PTP5, PTP5_DATA),
         PINMUX_GPIO(GPIO_PTP4, PTP4_DATA),
@@ -1145,6 +1301,8 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
 
         /* PTT */
+        PINMUX_GPIO(GPIO_PTT7, PTT7_DATA),
+        PINMUX_GPIO(GPIO_PTT6, PTT6_DATA),
         PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
         PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
         PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
@@ -1212,54 +1370,35 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
         PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
 
-        /* PTA (mobule: LBSC, CPG, LPC) */
+        /* PTA (mobule: LBSC, RGMII) */
         PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
         PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
         PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK),
         PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK),
-        PINMUX_GPIO(GPIO_FN_MD10, MD10_MARK),
-        PINMUX_GPIO(GPIO_FN_MD9, MD9_MARK),
-        PINMUX_GPIO(GPIO_FN_MD8, MD8_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK),
-        PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK),
-
-        /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
-        PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
-        PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
-        PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
-        PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
-        PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
-        PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
-        PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
-        PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
         PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK),
-        PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK),
+        PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDC_MARK),
         PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK),
-        PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK),
-        PINMUX_GPIO(GPIO_FN_WPSZ1, WPSZ1_MARK),
-        PINMUX_GPIO(GPIO_FN_WPSZ0, WPSZ0_MARK),
-        PINMUX_GPIO(GPIO_FN_FWID, FWID_MARK),
-        PINMUX_GPIO(GPIO_FN_FLSHSZ, FLSHSZ_MARK),
-        PINMUX_GPIO(GPIO_FN_LPC_SPIEN, LPC_SPIEN_MARK),
-        PINMUX_GPIO(GPIO_FN_BASEL, BASEL_MARK),
-
-        /* PTC (mobule: SD) */
-        PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK),
-        PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK),
+        PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDC_MARK),
 
-        /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
+        /* PTB (mobule: INTC, ONFI, TMU) */
+        PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_NRE, ON_NRE_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_NWE, ON_NWE_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_NWP, ON_NWP_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_NCE0, ON_NCE0_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_R_B0, ON_R_B0_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_ALE, ON_ALE_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_CLE, ON_CLE_MARK),
+        PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
+
+        /* PTC (mobule: IRQ, PWMU) */
         PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
         PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
         PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
@@ -1268,80 +1407,102 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
         PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
         PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
-        PINMUX_GPIO(GPIO_FN_MD6, MD6_MARK),
-        PINMUX_GPIO(GPIO_FN_MD5, MD5_MARK),
-        PINMUX_GPIO(GPIO_FN_MD3, MD3_MARK),
-        PINMUX_GPIO(GPIO_FN_MD2, MD2_MARK),
-        PINMUX_GPIO(GPIO_FN_MD1, MD1_MARK),
-        PINMUX_GPIO(GPIO_FN_MD0, MD0_MARK),
-        PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK),
-        PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMU0, PWMU0_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMU1, PWMU1_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMU2, PWMU2_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMU3, PWMU3_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMU4, PWMU4_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMU5, PWMU5_MARK),
+
+        /* PTD (mobule: SPI0, DMAC) */
+        PINMUX_GPIO(GPIO_FN_SP0_MOSI, SP0_MOSI_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_MISO, SP0_MISO_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_SCK, SP0_SCK_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_SCK_FB, SP0_SCK_FB_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_SS0, SP0_SS0_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_SS2, SP0_SS2_MARK),
+        PINMUX_GPIO(GPIO_FN_SP0_SS3, SP0_SS3_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
+        PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
 
-        /* PTE (mobule: EtherC) */
-        PINMUX_GPIO(GPIO_FN_ET0_CRS_DV, ET0_CRS_DV_MARK),
-        PINMUX_GPIO(GPIO_FN_ET0_TXD1, ET0_TXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_ET0_TXD0, ET0_TXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_ET0_TX_EN, ET0_TX_EN_MARK),
-        PINMUX_GPIO(GPIO_FN_ET0_REF_CLK, ET0_REF_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_ET0_RXD1, ET0_RXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_ET0_RXD0, ET0_RXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_ET0_RX_ER, ET0_RX_ER_MARK),
-
-        /* PTF (mobule: EtherC) */
-        PINMUX_GPIO(GPIO_FN_ET1_CRS_DV, ET1_CRS_DV_MARK),
-        PINMUX_GPIO(GPIO_FN_ET1_TXD1, ET1_TXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_ET1_TXD0, ET1_TXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_ET1_TX_EN, ET1_TX_EN_MARK),
-        PINMUX_GPIO(GPIO_FN_ET1_REF_CLK, ET1_REF_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_ET1_RXD1, ET1_RXD1_MARK),
-        PINMUX_GPIO(GPIO_FN_ET1_RXD0, ET1_RXD0_MARK),
-        PINMUX_GPIO(GPIO_FN_ET1_RX_ER, ET1_RX_ER_MARK),
-
-        /* PTG (mobule: SYSTEM, PWMX, LPC) */
-        PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
-        PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
-        PINMUX_GPIO(GPIO_FN_PWX0, PWX0_MARK),
-        PINMUX_GPIO(GPIO_FN_PWX1, PWX1_MARK),
-        PINMUX_GPIO(GPIO_FN_PWX2, PWX2_MARK),
-        PINMUX_GPIO(GPIO_FN_PWX3, PWX3_MARK),
+        /* PTE (mobule: RMII) */
+        PINMUX_GPIO(GPIO_FN_RMII0_CRS_DV, RMII0_CRS_DV_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII0_TXD1, RMII0_TXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII0_TXD0, RMII0_TXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII0_TXEN, RMII0_TXEN_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII0_REFCLK, RMII0_REFCLK_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII0_RXD1, RMII0_RXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII0_RXD0, RMII0_RXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII0_RX_ER, RMII0_RX_ER_MARK),
+
+        /* PTF (mobule: RMII, SerMux) */
+        PINMUX_GPIO(GPIO_FN_RMII1_CRS_DV, RMII1_CRS_DV_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII1_TXD1, RMII1_TXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII1_TXD0, RMII1_TXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII1_TXEN, RMII1_TXEN_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII1_REFCLK, RMII1_REFCLK_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII1_RXD1, RMII1_RXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII1_RXD0, RMII1_RXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RMII1_RX_ER, RMII1_RX_ER_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK),
+
+        /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
+        PINMUX_GPIO(GPIO_FN_BOOTFMS, BOOTFMS_MARK),
+        PINMUX_GPIO(GPIO_FN_BOOTWP, BOOTWP_MARK),
+        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
+        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
         PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK),
-        PINMUX_GPIO(GPIO_FN_CLKRUN, CLKRUN_MARK),
+        PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
         PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK),
         PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK),
 
-        /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
-        PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
+        /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
         PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK),
         PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK),
         PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK),
         PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK),
         PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK),
         PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK),
-        PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK),
+        PINMUX_GPIO(GPIO_FN_WP, WP_MARK),
+        PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK),
+        PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
+        PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK),
+        PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK),
 
-        /* PTI (mobule: INTC) */
-        PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK),
-        PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK),
+        /* PTI (mobule: LBSC, SDHI) */
+        PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
+        PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
+        PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
+        PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
+        PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
+        PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
+        PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
+        PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK),
+        PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK),
 
         /* PTJ (mobule: SCIF234, SERMUX) */
-        PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
+        PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
+        PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
         PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
-        PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
-        PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
-        PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK),
-        PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK),
-        PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK),
-        PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
+        PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
 
-        /* PTK (mobule: SERMUX) */
+        /* PTK (mobule: SERMUX, LBSC, SCIF) */
         PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK),
         PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK),
         PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK),
@@ -1349,62 +1510,65 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK),
         PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK),
         PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK),
-        PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK),
+        PINMUX_GPIO(GPIO_FN_CLKOUT, CLKOUT_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
 
-        /* PTL (mobule: SERMUX) */
-        PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK),
+        /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
         PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK),
         PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK),
         PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK),
         PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK),
         PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK),
         PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK),
-        PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK),
+        PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
+        PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
 
-        /* PTM (mobule: IIC, LPC) */
+        /* PTM (mobule: LBSC, IIC) */
+        PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
+        PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
+        PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK),
+        PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
         PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK),
         PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK),
         PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK),
         PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK),
-        PINMUX_GPIO(GPIO_FN_WP, WP_MARK),
-        PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK),
-        PINMUX_GPIO(GPIO_FN_FMS1, FMS1_MARK),
 
-        /* PTN (mobule: SCIF234, EVC) */
-        PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
-        PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK),
-        PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
-        PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK),
-        PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK),
-        PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
-        PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK),
-        PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK),
+        /* PTN (mobule: USB, JMC, SGPIO, WDT) */
+        PINMUX_GPIO(GPIO_FN_VBUS_EN, VBUS_EN_MARK),
+        PINMUX_GPIO(GPIO_FN_VBUS_OC, VBUS_OC_MARK),
+        PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK),
+        PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK),
+        PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK),
+        PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK),
+        PINMUX_GPIO(GPIO_FN_JMCTRST, JMCTRST_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK),
+        PINMUX_GPIO(GPIO_FN_SUB_CLKIN, SUB_CLKIN_MARK),
 
-        /* PTO (mobule: SGPIO) */
+        /* PTO (mobule: SGPIO, SerMux) */
         PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK),
         PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK),
         PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK),
         PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK),
-        PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO2_CLK, SGPIO2_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO2_LOAD, SGPIO2_LOAD_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO2_DI, SGPIO2_DI_MARK),
+        PINMUX_GPIO(GPIO_FN_SGPIO2_DO, SGPIO2_DO_MARK),
+        PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK),
+        PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK),
+        PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK),
+        PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK),
 
-        /* PTP (mobule: JMC, SCIF234) */
-        PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK),
-        PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK),
-        PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK),
-        PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK),
-        PINMUX_GPIO(GPIO_FN_JMCRST, JMCRST_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
-        PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
+        /* PTP (mobule: EVC, ADC) */
 
         /* PTQ (mobule: LPC) */
         PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK),
@@ -1439,31 +1603,41 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
         PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
 
-        /* PTT (mobule: SYSTEM, PWMX) */
-        PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
-        PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
+        /* PTT (mobule: PWMX, AUD) */
+        PINMUX_GPIO(GPIO_FN_PWMX7, PWMX7_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMX6, PWMX6_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMX5, PWMX5_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMX4, PWMX4_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMX3, PWMX3_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMX2, PWMX2_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMX1, PWMX1_MARK),
+        PINMUX_GPIO(GPIO_FN_PWMX0, PWMX0_MARK),
         PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
         PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
         PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
         PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
-        PINMUX_GPIO(GPIO_FN_PWX7, PWX7_MARK),
-        PINMUX_GPIO(GPIO_FN_PWX6, PWX6_MARK),
-        PINMUX_GPIO(GPIO_FN_PWX5, PWX5_MARK),
-        PINMUX_GPIO(GPIO_FN_PWX4, PWX4_MARK),
-
-        /* PTU (mobule: LBSC, DMAC) */
-        PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
-        PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
-        PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
-        PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
-        PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
-        PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK),
-        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
-        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
+        PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
+        PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
 
-        /* PTV (mobule: LBSC, DMAC) */
+        /* PTU (mobule: LPC, APM) */
+        PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK),
+        PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK),
+        PINMUX_GPIO(GPIO_FN_APMONCTL_O, APMONCTL_O_MARK),
+        PINMUX_GPIO(GPIO_FN_APMPWBTOUT_O, APMPWBTOUT_O_MARK),
+        PINMUX_GPIO(GPIO_FN_APMSCI_O, APMSCI_O_MARK),
+        PINMUX_GPIO(GPIO_FN_APMVDDON, APMVDDON_MARK),
+        PINMUX_GPIO(GPIO_FN_APMSLPBTN, APMSLPBTN_MARK),
+        PINMUX_GPIO(GPIO_FN_APMPWRBTN, APMPWRBTN_MARK),
+        PINMUX_GPIO(GPIO_FN_APMS5N, APMS5N_MARK),
+        PINMUX_GPIO(GPIO_FN_APMS3N, APMS3N_MARK),
+
+        /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
         PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
         PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
         PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
@@ -1472,12 +1646,20 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
         PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
         PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
-        PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
-        PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
-        PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
-        PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
+        PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK),
+        PINMUX_GPIO(GPIO_FN_R_SPI_MOSI, R_SPI_MOSI_MARK),
+        PINMUX_GPIO(GPIO_FN_R_SPI_MISO, R_SPI_MISO_MARK),
+        PINMUX_GPIO(GPIO_FN_R_SPI_RSPCK, R_SPI_RSPCK_MARK),
+        PINMUX_GPIO(GPIO_FN_R_SPI_SSL0, R_SPI_SSL0_MARK),
+        PINMUX_GPIO(GPIO_FN_R_SPI_SSL1, R_SPI_SSL1_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK),
+        PINMUX_GPIO(GPIO_FN_VBIOS_DI, VBIOS_DI_MARK),
+        PINMUX_GPIO(GPIO_FN_VBIOS_DO, VBIOS_DO_MARK),
+        PINMUX_GPIO(GPIO_FN_VBIOS_CLK, VBIOS_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_VBIOS_CS, VBIOS_CS_MARK),
 
-        /* PTW (mobule: LBSC) */
+        /* PTW (mobule: LBSC, EVC, SCIF) */
         PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
         PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
         PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
@@ -1487,6 +1669,14 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
         PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
         PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK),
+        PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK),
+        PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK),
+        PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK),
 
         /* PTX (mobule: LBSC) */
         PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
@@ -1497,6 +1687,10 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
         PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
         PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
+        PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK),
+        PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
+        PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
 
         /* PTY (mobule: LBSC) */
         PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
@@ -1507,18 +1701,36 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
         PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
         PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
+
+        /* PTZ (mobule: eMMC, ONFI) */
+        PINMUX_GPIO(GPIO_FN_MMCDAT7, MMCDAT7_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCDAT6, MMCDAT6_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCDAT5, MMCDAT5_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCDAT4, MMCDAT4_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCDAT3, MMCDAT3_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCDAT2, MMCDAT2_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCDAT1, MMCDAT1_MARK),
+        PINMUX_GPIO(GPIO_FN_MMCDAT0, MMCDAT0_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ7, ON_DQ7_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ6, ON_DQ6_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ5, ON_DQ5_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ4, ON_DQ4_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ3, ON_DQ3_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ2, ON_DQ2_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ1, ON_DQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_ON_DQ0, ON_DQ0_MARK),
  };
 
 static struct pinmux_cfg_reg pinmux_config_regs[] = {
         { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
-                PTA7_FN, PTA7_OUT, PTA7_IN, 0,
-                PTA6_FN, PTA6_OUT, PTA6_IN, 0,
-                PTA5_FN, PTA5_OUT, PTA5_IN, 0,
-                PTA4_FN, PTA4_OUT, PTA4_IN, 0,
-                PTA3_FN, PTA3_OUT, PTA3_IN, 0,
-                PTA2_FN, PTA2_OUT, PTA2_IN, 0,
-                PTA1_FN, PTA1_OUT, PTA1_IN, 0,
-                PTA0_FN, PTA0_OUT, PTA0_IN, 0 }
+                PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU,
+                PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU,
+                PTA5_FN, PTA5_OUT, PTA5_IN, PTA5_IN_PU,
+                PTA4_FN, PTA4_OUT, PTA4_IN, PTA4_IN_PU,
+                PTA3_FN, PTA3_OUT, PTA3_IN, PTA3_IN_PU,
+                PTA2_FN, PTA2_OUT, PTA2_IN, PTA2_IN_PU,
+                PTA1_FN, PTA1_OUT, PTA1_IN, PTA1_IN_PU,
+                PTA0_FN, PTA0_OUT, PTA0_IN, PTA0_IN_PU }
         },
         { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) {
                 PTB7_FN, PTB7_OUT, PTB7_IN, 0,
@@ -1541,125 +1753,126 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                 PTC0_FN, PTC0_OUT, PTC0_IN, 0 }
         },
         { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) {
-                PTD7_FN, PTD7_OUT, PTD7_IN, 0,
-                PTD6_FN, PTD6_OUT, PTD6_IN, 0,
-                PTD5_FN, PTD5_OUT, PTD5_IN, 0,
-                PTD4_FN, PTD4_OUT, PTD4_IN, 0,
-                PTD3_FN, PTD3_OUT, PTD3_IN, 0,
-                PTD2_FN, PTD2_OUT, PTD2_IN, 0,
-                PTD1_FN, PTD1_OUT, PTD1_IN, 0,
-                PTD0_FN, PTD0_OUT, PTD0_IN, 0 }
+                PTD7_FN, PTD7_OUT, PTD7_IN, PTD7_IN_PU,
+                PTD6_FN, PTD6_OUT, PTD6_IN, PTD6_IN_PU,
+                PTD5_FN, PTD5_OUT, PTD5_IN, PTD5_IN_PU,
+                PTD4_FN, PTD4_OUT, PTD4_IN, PTD4_IN_PU,
+                PTD3_FN, PTD3_OUT, PTD3_IN, PTD3_IN_PU,
+                PTD2_FN, PTD2_OUT, PTD2_IN, PTD2_IN_PU,
+                PTD1_FN, PTD1_OUT, PTD1_IN, PTD1_IN_PU,
+                PTD0_FN, PTD0_OUT, PTD0_IN, PTD0_IN_PU }
         },
         { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) {
-                PTE7_FN, PTE7_OUT, PTE7_IN, 0,
-                PTE6_FN, PTE6_OUT, PTE6_IN, 0,
-                PTE5_FN, PTE5_OUT, PTE5_IN, 0,
-                PTE4_FN, PTE4_OUT, PTE4_IN, 0,
-                PTE3_FN, PTE3_OUT, PTE3_IN, 0,
-                PTE2_FN, PTE2_OUT, PTE2_IN, 0,
-                PTE1_FN, PTE1_OUT, PTE1_IN, 0,
-                PTE0_FN, PTE0_OUT, PTE0_IN, 0 }
+                PTE7_FN, PTE7_OUT, PTE7_IN, PTE7_IN_PU,
+                PTE6_FN, PTE6_OUT, PTE6_IN, PTE6_IN_PU,
+                PTE5_FN, PTE5_OUT, PTE5_IN, PTE5_IN_PU,
+                PTE4_FN, PTE4_OUT, PTE4_IN, PTE4_IN_PU,
+                PTE3_FN, PTE3_OUT, PTE3_IN, PTE3_IN_PU,
+                PTE2_FN, PTE2_OUT, PTE2_IN, PTE2_IN_PU,
+                PTE1_FN, PTE1_OUT, PTE1_IN, PTE1_IN_PU,
+                PTE0_FN, PTE0_OUT, PTE0_IN, PTE0_IN_PU }
         },
         { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) {
-                PTF7_FN, PTF7_OUT, PTF7_IN, 0,
-                PTF6_FN, PTF6_OUT, PTF6_IN, 0,
-                PTF5_FN, PTF5_OUT, PTF5_IN, 0,
-                PTF4_FN, PTF4_OUT, PTF4_IN, 0,
-                PTF3_FN, PTF3_OUT, PTF3_IN, 0,
-                PTF2_FN, PTF2_OUT, PTF2_IN, 0,
-                PTF1_FN, PTF1_OUT, PTF1_IN, 0,
-                PTF0_FN, PTF0_OUT, PTF0_IN, 0 }
+                PTF7_FN, PTF7_OUT, PTF7_IN, PTF7_IN_PU,
+                PTF6_FN, PTF6_OUT, PTF6_IN, PTF6_IN_PU,
+                PTF5_FN, PTF5_OUT, PTF5_IN, PTF5_IN_PU,
+                PTF4_FN, PTF4_OUT, PTF4_IN, PTF4_IN_PU,
+                PTF3_FN, PTF3_OUT, PTF3_IN, PTF3_IN_PU,
+                PTF2_FN, PTF2_OUT, PTF2_IN, PTF2_IN_PU,
+                PTF1_FN, PTF1_OUT, PTF1_IN, PTF1_IN_PU,
+                PTF0_FN, PTF0_OUT, PTF0_IN, PTF0_IN_PU }
         },
         { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) {
-                PTG7_FN, PTG7_OUT, PTG7_IN, 0,
-                PTG6_FN, PTG6_OUT, PTG6_IN, 0,
+                PTG7_FN, PTG7_OUT, PTG7_IN, PTG7_IN_PU ,
+                PTG6_FN, PTG6_OUT, PTG6_IN, PTG6_IN_PU ,
                 PTG5_FN, PTG5_OUT, PTG5_IN, 0,
-                PTG4_FN, PTG4_OUT, PTG4_IN, 0,
+                PTG4_FN, PTG4_OUT, PTG4_IN, PTG4_IN_PU ,
                 PTG3_FN, PTG3_OUT, PTG3_IN, 0,
                 PTG2_FN, PTG2_OUT, PTG2_IN, 0,
                 PTG1_FN, PTG1_OUT, PTG1_IN, 0,
                 PTG0_FN, PTG0_OUT, PTG0_IN, 0 }
         },
         { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) {
-                PTH7_FN, PTH7_OUT, PTH7_IN, 0,
-                PTH6_FN, PTH6_OUT, PTH6_IN, 0,
-                PTH5_FN, PTH5_OUT, PTH5_IN, 0,
-                PTH4_FN, PTH4_OUT, PTH4_IN, 0,
-                PTH3_FN, PTH3_OUT, PTH3_IN, 0,
-                PTH2_FN, PTH2_OUT, PTH2_IN, 0,
-                PTH1_FN, PTH1_OUT, PTH1_IN, 0,
-                PTH0_FN, PTH0_OUT, PTH0_IN, 0 }
+                PTH7_FN, PTH7_OUT, PTH7_IN, PTH7_IN_PU,
+                PTH6_FN, PTH6_OUT, PTH6_IN, PTH6_IN_PU,
+                PTH5_FN, PTH5_OUT, PTH5_IN, PTH5_IN_PU,
+                PTH4_FN, PTH4_OUT, PTH4_IN, PTH4_IN_PU,
+                PTH3_FN, PTH3_OUT, PTH3_IN, PTH3_IN_PU,
+                PTH2_FN, PTH2_OUT, PTH2_IN, PTH2_IN_PU,
+                PTH1_FN, PTH1_OUT, PTH1_IN, PTH1_IN_PU,
+                PTH0_FN, PTH0_OUT, PTH0_IN, PTH0_IN_PU }
         },
         { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) {
-                PTI7_FN, PTI7_OUT, PTI7_IN, 0,
-                PTI6_FN, PTI6_OUT, PTI6_IN, 0,
+                PTI7_FN, PTI7_OUT, PTI7_IN, PTI7_IN_PU,
+                PTI6_FN, PTI6_OUT, PTI6_IN, PTI6_IN_PU,
                 PTI5_FN, PTI5_OUT, PTI5_IN, 0,
-                PTI4_FN, PTI4_OUT, PTI4_IN, 0,
-                PTI3_FN, PTI3_OUT, PTI3_IN, 0,
-                PTI2_FN, PTI2_OUT, PTI2_IN, 0,
-                PTI1_FN, PTI1_OUT, PTI1_IN, 0,
-                PTI0_FN, PTI0_OUT, PTI0_IN, 0 }
+                PTI4_FN, PTI4_OUT, PTI4_IN, PTI4_IN_PU,
+                PTI3_FN, PTI3_OUT, PTI3_IN, PTI3_IN_PU,
+                PTI2_FN, PTI2_OUT, PTI2_IN, PTI2_IN_PU,
+                PTI1_FN, PTI1_OUT, PTI1_IN, PTI1_IN_PU,
+                PTI0_FN, PTI0_OUT, PTI0_IN, PTI0_IN_PU }
         },
         { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) {
-                PTJ7_FN, PTJ7_OUT, PTJ7_IN, 0,
-                PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0,
-                PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0,
-                PTJ4_FN, PTJ4_OUT, PTJ4_IN, 0,
-                PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0,
-                PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0,
-                PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0,
-                PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 }
+                0, 0, 0, 0,     /* reserved: always set 1 */
+                PTJ6_FN, PTJ6_OUT, PTJ6_IN, PTJ6_IN_PU,
+                PTJ5_FN, PTJ5_OUT, PTJ5_IN, PTJ5_IN_PU,
+                PTJ4_FN, PTJ4_OUT, PTJ4_IN, PTJ4_IN_PU,
+                PTJ3_FN, PTJ3_OUT, PTJ3_IN, PTJ3_IN_PU,
+                PTJ2_FN, PTJ2_OUT, PTJ2_IN, PTJ2_IN_PU,
+                PTJ1_FN, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU,
+                PTJ0_FN, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU }
         },
         { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) {
-                PTK7_FN, PTK7_OUT, PTK7_IN, 0,
-                PTK6_FN, PTK6_OUT, PTK6_IN, 0,
-                PTK5_FN, PTK5_OUT, PTK5_IN, 0,
-                PTK4_FN, PTK4_OUT, PTK4_IN, 0,
-                PTK3_FN, PTK3_OUT, PTK3_IN, 0,
-                PTK2_FN, PTK2_OUT, PTK2_IN, 0,
-                PTK1_FN, PTK1_OUT, PTK1_IN, 0,
-                PTK0_FN, PTK0_OUT, PTK0_IN, 0 }
+                PTK7_FN, PTK7_OUT, PTK7_IN, PTK7_IN_PU,
+                PTK6_FN, PTK6_OUT, PTK6_IN, PTK6_IN_PU,
+                PTK5_FN, PTK5_OUT, PTK5_IN, PTK5_IN_PU,
+                PTK4_FN, PTK4_OUT, PTK4_IN, PTK4_IN_PU,
+                PTK3_FN, PTK3_OUT, PTK3_IN, PTK3_IN_PU,
+                PTK2_FN, PTK2_OUT, PTK2_IN, PTK2_IN_PU,
+                PTK1_FN, PTK1_OUT, PTK1_IN, PTK1_IN_PU,
+                PTK0_FN, PTK0_OUT, PTK0_IN, PTK0_IN_PU }
         },
         { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) {
-                PTL7_FN, PTL7_OUT, PTL7_IN, 0,
-                PTL6_FN, PTL6_OUT, PTL6_IN, 0,
-                PTL5_FN, PTL5_OUT, PTL5_IN, 0,
-                PTL4_FN, PTL4_OUT, PTL4_IN, 0,
-                PTL3_FN, PTL3_OUT, PTL3_IN, 0,
-                PTL2_FN, PTL2_OUT, PTL2_IN, 0,
-                PTL1_FN, PTL1_OUT, PTL1_IN, 0,
-                PTL0_FN, PTL0_OUT, PTL0_IN, 0 }
+                0, 0, 0, 0,     /* reserved: always set 1 */
+                PTL6_FN, PTL6_OUT, PTL6_IN, PTL6_IN_PU,
+                PTL5_FN, PTL5_OUT, PTL5_IN, PTL5_IN_PU,
+                PTL4_FN, PTL4_OUT, PTL4_IN, PTL4_IN_PU,
+                PTL3_FN, PTL3_OUT, PTL3_IN, PTL3_IN_PU,
+                PTL2_FN, PTL2_OUT, PTL2_IN, PTL2_IN_PU,
+                PTL1_FN, PTL1_OUT, PTL1_IN, PTL1_IN_PU,
+                PTL0_FN, PTL0_OUT, PTL0_IN, PTL0_IN_PU }
         },
         { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) {
-                0, 0, 0, 0,     /* reserved: always set 1 */
-                PTM6_FN, PTM6_OUT, PTM6_IN, 0,
-                PTM5_FN, PTM5_OUT, PTM5_IN, 0,
-                PTM4_FN, PTM4_OUT, PTM4_IN, 0,
+                PTM7_FN, PTM7_OUT, PTM7_IN, PTM7_IN_PU,
+                PTM6_FN, PTM6_OUT, PTM6_IN, PTM6_IN_PU,
+                PTM5_FN, PTM5_OUT, PTM5_IN, PTM5_IN_PU,
+                PTM4_FN, PTM4_OUT, PTM4_IN, PTM4_IN_PU,
                 PTM3_FN, PTM3_OUT, PTM3_IN, 0,
                 PTM2_FN, PTM2_OUT, PTM2_IN, 0,
                 PTM1_FN, PTM1_OUT, PTM1_IN, 0,
                 PTM0_FN, PTM0_OUT, PTM0_IN, 0 }
         },
         { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) {
-                PTN7_FN, PTN7_OUT, PTN7_IN, 0,
+                0, 0, 0, 0,     /* reserved: always set 1 */
                 PTN6_FN, PTN6_OUT, PTN6_IN, 0,
                 PTN5_FN, PTN5_OUT, PTN5_IN, 0,
-                PTN4_FN, PTN4_OUT, PTN4_IN, 0,
-                PTN3_FN, PTN3_OUT, PTN3_IN, 0,
-                PTN2_FN, PTN2_OUT, PTN2_IN, 0,
-                PTN1_FN, PTN1_OUT, PTN1_IN, 0,
-                PTN0_FN, PTN0_OUT, PTN0_IN, 0 }
+                PTN4_FN, PTN4_OUT, PTN4_IN, PTN4_IN_PU,
+                PTN3_FN, PTN3_OUT, PTN3_IN, PTN3_IN_PU,
+                PTN2_FN, PTN2_OUT, PTN2_IN, PTN2_IN_PU,
+                PTN1_FN, PTN1_OUT, PTN1_IN, PTN1_IN_PU,
+                PTN0_FN, PTN0_OUT, PTN0_IN, PTN0_IN_PU }
         },
         { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) {
-                PTO7_FN, PTO7_OUT, PTO7_IN, 0,
-                PTO6_FN, PTO6_OUT, PTO6_IN, 0,
-                PTO5_FN, PTO5_OUT, PTO5_IN, 0,
-                PTO4_FN, PTO4_OUT, PTO4_IN, 0,
-                PTO3_FN, PTO3_OUT, PTO3_IN, 0,
-                PTO2_FN, PTO2_OUT, PTO2_IN, 0,
-                PTO1_FN, PTO1_OUT, PTO1_IN, 0,
-                PTO0_FN, PTO0_OUT, PTO0_IN, 0 }
+                PTO7_FN, PTO7_OUT, PTO7_IN, PTO7_IN_PU,
+                PTO6_FN, PTO6_OUT, PTO6_IN, PTO6_IN_PU,
+                PTO5_FN, PTO5_OUT, PTO5_IN, PTO5_IN_PU,
+                PTO4_FN, PTO4_OUT, PTO4_IN, PTO4_IN_PU,
+                PTO3_FN, PTO3_OUT, PTO3_IN, PTO3_IN_PU,
+                PTO2_FN, PTO2_OUT, PTO2_IN, PTO2_IN_PU,
+                PTO1_FN, PTO1_OUT, PTO1_IN, PTO1_IN_PU,
+                PTO0_FN, PTO0_OUT, PTO0_IN, PTO0_IN_PU }
         },
+#if 0   /* FIXME: Remove it? */
         { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) {
                 0, 0, 0, 0,     /* reserved: always set 1 */
                 PTP6_FN, PTP6_OUT, PTP6_IN, 0,
@@ -1670,6 +1883,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                 PTP1_FN, PTP1_OUT, PTP1_IN, 0,
                 PTP0_FN, PTP0_OUT, PTP0_IN, 0 }
         },
+#endif
         { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) {
                 0, 0, 0, 0,     /* reserved: always set 1 */
                 PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0,
@@ -1701,14 +1915,14 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                 PTS0_FN, PTS0_OUT, PTS0_IN, 0 }
         },
         { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) {
-                0, 0, 0, 0,     /* reserved: always set 1 */
-                0, 0, 0, 0,     /* reserved: always set 1 */
-                PTT5_FN, PTT5_OUT, PTT5_IN, 0,
-                PTT4_FN, PTT4_OUT, PTT4_IN, 0,
-                PTT3_FN, PTT3_OUT, PTT3_IN, 0,
-                PTT2_FN, PTT2_OUT, PTT2_IN, 0,
-                PTT1_FN, PTT1_OUT, PTT1_IN, 0,
-                PTT0_FN, PTT0_OUT, PTT0_IN, 0 }
+                PTT7_FN, PTT7_OUT, PTT7_IN, PTO7_IN_PU,
+                PTT6_FN, PTT6_OUT, PTT6_IN, PTO6_IN_PU,
+                PTT5_FN, PTT5_OUT, PTT5_IN, PTO5_IN_PU,
+                PTT4_FN, PTT4_OUT, PTT4_IN, PTO4_IN_PU,
+                PTT3_FN, PTT3_OUT, PTT3_IN, PTO3_IN_PU,
+                PTT2_FN, PTT2_OUT, PTT2_IN, PTO2_IN_PU,
+                PTT1_FN, PTT1_OUT, PTT1_IN, PTO1_IN_PU,
+                PTT0_FN, PTT0_OUT, PTT0_IN, PTO0_IN_PU }
         },
         { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) {
                 PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU,
@@ -1727,16 +1941,16 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                 PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU,
                 PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU,
                 PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU,
-                PTV1_FN, PTV1_OUT, PTV1_IN, PTV1_IN_PU,
-                PTV0_FN, PTV0_OUT, PTV0_IN, PTV0_IN_PU }
+                PTV1_FN, PTV1_OUT, PTV1_IN, 0,
+                PTV0_FN, PTV0_OUT, PTV0_IN, 0 }
         },
         { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) {
-                PTW7_FN, PTW7_OUT, PTW7_IN, PTW7_IN_PU,
-                PTW6_FN, PTW6_OUT, PTW6_IN, PTW6_IN_PU,
-                PTW5_FN, PTW5_OUT, PTW5_IN, PTW5_IN_PU,
-                PTW4_FN, PTW4_OUT, PTW4_IN, PTW4_IN_PU,
-                PTW3_FN, PTW3_OUT, PTW3_IN, PTW3_IN_PU,
-                PTW2_FN, PTW2_OUT, PTW2_IN, PTW2_IN_PU,
+                PTW7_FN, PTW7_OUT, PTW7_IN, 0,
+                PTW6_FN, PTW6_OUT, PTW6_IN, 0,
+                PTW5_FN, PTW5_OUT, PTW5_IN, 0,
+                PTW4_FN, PTW4_OUT, PTW4_IN, 0,
+                PTW3_FN, PTW3_OUT, PTW3_IN, 0,
+                PTW2_FN, PTW2_OUT, PTW2_IN, 0,
                 PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU,
                 PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU }
         },
@@ -1761,32 +1975,32 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                 PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU }
         },
         { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) {
-                0, PTZ7_OUT, PTZ7_IN, 0,
-                0, PTZ6_OUT, PTZ6_IN, 0,
-                0, PTZ5_OUT, PTZ5_IN, 0,
-                0, PTZ4_OUT, PTZ4_IN, 0,
-                0, PTZ3_OUT, PTZ3_IN, 0,
-                0, PTZ2_OUT, PTZ2_IN, 0,
-                0, PTZ1_OUT, PTZ1_IN, 0,
-                0, PTZ0_OUT, PTZ0_IN, 0 }
+                PTZ7_FN, PTZ7_OUT, PTZ7_IN, 0,
+                PTZ6_FN, PTZ6_OUT, PTZ6_IN, 0,
+                PTZ5_FN, PTZ5_OUT, PTZ5_IN, 0,
+                PTZ4_FN, PTZ4_OUT, PTZ4_IN, 0,
+                PTZ3_FN, PTZ3_OUT, PTZ3_IN, 0,
+                PTZ2_FN, PTZ2_OUT, PTZ2_IN, 0,
+                PTZ1_FN, PTZ1_OUT, PTZ1_IN, 0,
+                PTZ0_FN, PTZ0_OUT, PTZ0_IN, 0 }
         },
 
         { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) {
-                PS0_15_FN3, PS0_15_FN1,
-                PS0_14_FN3, PS0_14_FN1,
-                PS0_13_FN3, PS0_13_FN1,
-                PS0_12_FN3, PS0_12_FN1,
-                0, 0,
-                0, 0,
+                PS0_15_FN1, PS0_15_FN2,
+                PS0_14_FN1, PS0_14_FN2,
+                PS0_13_FN1, PS0_13_FN2,
+                PS0_12_FN1, PS0_12_FN2,
+                PS0_11_FN1, PS0_11_FN2,
+                PS0_10_FN1, PS0_10_FN2,
+                PS0_9_FN1, PS0_9_FN2,
+                PS0_8_FN1, PS0_8_FN2,
+                PS0_7_FN1, PS0_7_FN2,
+                PS0_6_FN1, PS0_6_FN2,
+                PS0_5_FN1, PS0_5_FN2,
+                PS0_4_FN1, PS0_4_FN2,
+                PS0_3_FN1, PS0_3_FN2,
+                PS0_2_FN1, PS0_2_FN2,
                 0, 0,
-                0, 0,
-                PS0_7_FN2, PS0_7_FN1,
-                PS0_6_FN2, PS0_6_FN1,
-                PS0_5_FN2, PS0_5_FN1,
-                PS0_4_FN2, PS0_4_FN1,
-                PS0_3_FN2, PS0_3_FN1,
-                PS0_2_FN2, PS0_2_FN1,
-                PS0_1_FN2, PS0_1_FN1,
                 0, 0, }
         },
         { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) {
@@ -1795,73 +2009,136 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                 0, 0,
                 0, 0,
                 0, 0,
+                PS1_10_FN1, PS1_10_FN2,
+                PS1_9_FN1, PS1_9_FN2,
+                PS1_8_FN1, PS1_8_FN2,
                 0, 0,
                 0, 0,
                 0, 0,
-                PS1_7_FN1, PS1_7_FN3,
-                PS1_6_FN1, PS1_6_FN3,
-                0, 0,
-                0, 0,
                 0, 0,
                 0, 0,
+                PS1_2_FN1, PS1_2_FN2,
                 0, 0,
                 0, 0, }
         },
         { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) {
                 0, 0,
                 0, 0,
-                PS2_13_FN3, PS2_13_FN1,
-                PS2_12_FN3, PS2_12_FN1,
+                PS2_13_FN1, PS2_13_FN2,
+                PS2_12_FN1, PS2_12_FN2,
                 0, 0,
                 0, 0,
                 0, 0,
                 0, 0,
+                PS2_7_FN1, PS2_7_FN2,
+                PS2_6_FN1, PS2_6_FN2,
+                PS2_5_FN1, PS2_5_FN2,
+                PS2_4_FN1, PS2_4_FN2,
                 0, 0,
+                PS2_2_FN1, PS2_2_FN2,
                 0, 0,
+                0, 0, }
+        },
+        { PINMUX_CFG_REG("PSEL3", 0xffec0076, 16, 1) {
+                PS3_15_FN1, PS3_15_FN2,
+                PS3_14_FN1, PS3_14_FN2,
+                PS3_13_FN1, PS3_13_FN2,
+                PS3_12_FN1, PS3_12_FN2,
+                PS3_11_FN1, PS3_11_FN2,
+                PS3_10_FN1, PS3_10_FN2,
+                PS3_9_FN1, PS3_9_FN2,
+                PS3_8_FN1, PS3_8_FN2,
+                PS3_7_FN1, PS3_7_FN2,
                 0, 0,
                 0, 0,
                 0, 0,
                 0, 0,
-                PS2_1_FN1, PS2_1_FN2,
-                PS2_0_FN1, PS2_0_FN2, }
+                PS3_2_FN1, PS3_2_FN2,
+                PS3_1_FN1, PS3_1_FN2,
+                0, 0, }
         },
+
         { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) {
-                PS4_15_FN2, PS4_15_FN1,
-                PS4_14_FN2, PS4_14_FN1,
-                PS4_13_FN2, PS4_13_FN1,
-                PS4_12_FN2, PS4_12_FN1,
-                PS4_11_FN2, PS4_11_FN1,
-                PS4_10_FN2, PS4_10_FN1,
-                PS4_9_FN2, PS4_9_FN1,
                 0, 0,
+                PS4_14_FN1, PS4_14_FN2,
+                PS4_13_FN1, PS4_13_FN2,
+                PS4_12_FN1, PS4_12_FN2,
                 0, 0,
+                PS4_10_FN1, PS4_10_FN2,
+                PS4_9_FN1, PS4_9_FN2,
+                PS4_8_FN1, PS4_8_FN2,
                 0, 0,
                 0, 0,
                 0, 0,
-                PS4_3_FN2, PS4_3_FN1,
-                PS4_2_FN2, PS4_2_FN1,
-                PS4_1_FN2, PS4_1_FN1,
-                PS4_0_FN2, PS4_0_FN1, }
+                PS4_4_FN1, PS4_4_FN2,
+                PS4_3_FN1, PS4_3_FN2,
+                PS4_2_FN1, PS4_2_FN2,
+                PS4_1_FN1, PS4_1_FN2,
+                PS4_0_FN1, PS4_0_FN2, }
         },
         { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) {
                 0, 0,
                 0, 0,
                 0, 0,
                 0, 0,
-                0, 0,
-                0, 0,
+                PS5_11_FN1, PS5_11_FN2,
+                PS5_10_FN1, PS5_10_FN2,
                 PS5_9_FN1, PS5_9_FN2,
                 PS5_8_FN1, PS5_8_FN2,
                 PS5_7_FN1, PS5_7_FN2,
                 PS5_6_FN1, PS5_6_FN2,
                 PS5_5_FN1, PS5_5_FN2,
+                PS5_4_FN1, PS5_4_FN2,
+                PS5_3_FN1, PS5_3_FN2,
+                PS5_2_FN1, PS5_2_FN2,
+                0, 0,
+                0, 0, }
+        },
+        { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) {
+                PS6_15_FN1, PS6_15_FN2,
+                PS6_14_FN1, PS6_14_FN2,
+                PS6_13_FN1, PS6_13_FN2,
+                PS6_12_FN1, PS6_12_FN2,
+                PS6_11_FN1, PS6_11_FN2,
+                PS6_10_FN1, PS6_10_FN2,
+                PS6_9_FN1, PS6_9_FN2,
+                PS6_8_FN1, PS6_8_FN2,
+                PS6_7_FN1, PS6_7_FN2,
+                PS6_6_FN1, PS6_6_FN2,
+                PS6_5_FN1, PS6_5_FN2,
+                PS6_4_FN1, PS6_4_FN2,
+                PS6_3_FN1, PS6_3_FN2,
+                PS6_2_FN1, PS6_2_FN2,
+                PS6_1_FN1, PS6_1_FN2,
+                PS6_0_FN1, PS6_0_FN2, }
+        },
+        { PINMUX_CFG_REG("PSEL7", 0xffec0082, 16, 1) {
+                PS7_15_FN1, PS7_15_FN2,
+                PS7_14_FN1, PS7_14_FN2,
+                PS7_13_FN1, PS7_13_FN2,
+                PS7_12_FN1, PS7_12_FN2,
+                PS7_11_FN1, PS7_11_FN2,
+                PS7_10_FN1, PS7_10_FN2,
+                PS7_9_FN1, PS7_9_FN2,
+                PS7_8_FN1, PS7_8_FN2,
+                PS7_7_FN1, PS7_7_FN2,
+                PS7_6_FN1, PS7_6_FN2,
+                PS7_5_FN1, PS7_5_FN2,
                 0, 0,
                 0, 0,
                 0, 0,
                 0, 0,
                 0, 0, }
         },
-        { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) {
+        { PINMUX_CFG_REG("PSEL8", 0xffec0084, 16, 1) {
+                PS8_15_FN1, PS8_15_FN2,
+                PS8_14_FN1, PS8_14_FN2,
+                PS8_13_FN1, PS8_13_FN2,
+                PS8_12_FN1, PS8_12_FN2,
+                PS8_11_FN1, PS8_11_FN2,
+                PS8_10_FN1, PS8_10_FN2,
+                PS8_9_FN1, PS8_9_FN2,
+                PS8_8_FN1, PS8_8_FN2,
                 0, 0,
                 0, 0,
                 0, 0,
@@ -1869,15 +2146,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                 0, 0,
                 0, 0,
                 0, 0,
-                0, 0,
-                PS6_7_FN_AN, PS6_7_FN_EV,
-                PS6_6_FN_AN, PS6_6_FN_EV,
-                PS6_5_FN_AN, PS6_5_FN_EV,
-                PS6_4_FN_AN, PS6_4_FN_EV,
-                PS6_3_FN_AN, PS6_3_FN_EV,
-                PS6_2_FN_AN, PS6_2_FN_EV,
-                PS6_1_FN_AN, PS6_1_FN_EV,
-                PS6_0_FN_AN, PS6_0_FN_EV, }
+                0, 0, }
         },
         {}
 };
@@ -1920,7 +2189,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
                 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA }
         },
         { PINMUX_DATA_REG("PJDR", 0xffec0046, 8) {
-                PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
+                0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
                 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
         },
         { PINMUX_DATA_REG("PKDR", 0xffec0048, 8) {
@@ -1928,15 +2197,15 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
                 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
         },
         { PINMUX_DATA_REG("PLDR", 0xffec004a, 8) {
-                PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
+                0, PTL6_DATA, PTL5_DATA, PTL4_DATA,
                 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
         },
         { PINMUX_DATA_REG("PMDR", 0xffec004c, 8) {
-                0, PTM6_DATA, PTM5_DATA, PTM4_DATA,
+                PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
                 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
         },
         { PINMUX_DATA_REG("PNDR", 0xffec004e, 8) {
-                PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
+                0, PTN6_DATA, PTN5_DATA, PTN4_DATA,
                 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
         },
         { PINMUX_DATA_REG("PODR", 0xffec0050, 8) {
@@ -1944,7 +2213,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
                 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA }
         },
         { PINMUX_DATA_REG("PPDR", 0xffec0052, 8) {
-                0, PTP6_DATA, PTP5_DATA, PTP4_DATA,
+                PTP7_DATA, PTP6_DATA, PTP5_DATA, PTP4_DATA,
                 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA }
         },
         { PINMUX_DATA_REG("PQDR", 0xffec0054, 8) {
@@ -1960,7 +2229,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
                 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
         },
         { PINMUX_DATA_REG("PTDR", 0xffec005a, 8) {
-                0, 0, PTT5_DATA, PTT4_DATA,
+                PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
                 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
         },
         { PINMUX_DATA_REG("PUDR", 0xffec005c, 8) {
@@ -2000,8 +2269,8 @@ static struct pinmux_info sh7757_pinmux_info = {
         .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
-        .first_gpio = GPIO_PTA7,
-        .last_gpio = GPIO_FN_D0,
+        .first_gpio = GPIO_PTA0,
+        .last_gpio = GPIO_FN_ON_DQ0,
 
         .gpios = pinmux_gpios,
         .cfg_regs = pinmux_config_regs,
@@ -2015,5 +2284,4 @@ static int __init plat_pinmux_setup(void)
 {
         return register_pinmux(&sh7757_pinmux_info);
 }
-
 arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
new file mode 100644
index 000000000000..aaa5338abbff
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
@@ -0,0 +1,587 @@
+/*
+ * SH-X3 prototype CPU pinmux
+ *
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <cpu/shx3.h>
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
+        PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
+        PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
+        PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
+        PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
+        PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
+        PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
+        PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
+        PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
+        PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
+        PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
+        PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
+        PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
+        PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
+
+        PH5_DATA, PH4_DATA,
+        PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        PA7_IN, PA6_IN, PA5_IN, PA4_IN,
+        PA3_IN, PA2_IN, PA1_IN, PA0_IN,
+        PB7_IN, PB6_IN, PB5_IN, PB4_IN,
+        PB3_IN, PB2_IN, PB1_IN, PB0_IN,
+        PC7_IN, PC6_IN, PC5_IN, PC4_IN,
+        PC3_IN, PC2_IN, PC1_IN, PC0_IN,
+        PD7_IN, PD6_IN, PD5_IN, PD4_IN,
+        PD3_IN, PD2_IN, PD1_IN, PD0_IN,
+        PE7_IN, PE6_IN, PE5_IN, PE4_IN,
+        PE3_IN, PE2_IN, PE1_IN, PE0_IN,
+        PF7_IN, PF6_IN, PF5_IN, PF4_IN,
+        PF3_IN, PF2_IN, PF1_IN, PF0_IN,
+        PG7_IN, PG6_IN, PG5_IN, PG4_IN,
+        PG3_IN, PG2_IN, PG1_IN, PG0_IN,
+
+        PH5_IN, PH4_IN,
+        PH3_IN, PH2_IN, PH1_IN, PH0_IN,
+        PINMUX_INPUT_END,
+
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
+        PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
+        PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
+        PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
+        PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
+        PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
+        PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
+        PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
+        PE7_IN_PU, PE6_IN_PU, PE5_IN_PU, PE4_IN_PU,
+        PE3_IN_PU, PE2_IN_PU, PE1_IN_PU, PE0_IN_PU,
+        PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
+        PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
+        PG7_IN_PU, PG6_IN_PU, PG5_IN_PU, PG4_IN_PU,
+        PG3_IN_PU, PG2_IN_PU, PG1_IN_PU, PG0_IN_PU,
+
+        PH5_IN_PU, PH4_IN_PU,
+        PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
+        PINMUX_INPUT_PULLUP_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
+        PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
+        PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
+        PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
+        PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
+        PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
+        PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
+        PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
+        PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
+        PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
+        PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
+        PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
+        PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
+        PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
+
+        PH5_OUT, PH4_OUT,
+        PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        PA7_FN, PA6_FN, PA5_FN, PA4_FN,
+        PA3_FN, PA2_FN, PA1_FN, PA0_FN,
+        PB7_FN, PB6_FN, PB5_FN, PB4_FN,
+        PB3_FN, PB2_FN, PB1_FN, PB0_FN,
+        PC7_FN, PC6_FN, PC5_FN, PC4_FN,
+        PC3_FN, PC2_FN, PC1_FN, PC0_FN,
+        PD7_FN, PD6_FN, PD5_FN, PD4_FN,
+        PD3_FN, PD2_FN, PD1_FN, PD0_FN,
+        PE7_FN, PE6_FN, PE5_FN, PE4_FN,
+        PE3_FN, PE2_FN, PE1_FN, PE0_FN,
+        PF7_FN, PF6_FN, PF5_FN, PF4_FN,
+        PF3_FN, PF2_FN, PF1_FN, PF0_FN,
+        PG7_FN, PG6_FN, PG5_FN, PG4_FN,
+        PG3_FN, PG2_FN, PG1_FN, PG0_FN,
+
+        PH5_FN, PH4_FN,
+        PH3_FN, PH2_FN, PH1_FN, PH0_FN,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+
+        D31_MARK, D30_MARK, D29_MARK, D28_MARK, D27_MARK, D26_MARK,
+        D25_MARK, D24_MARK, D23_MARK, D22_MARK, D21_MARK, D20_MARK,
+        D19_MARK, D18_MARK, D17_MARK, D16_MARK,
+
+        BACK_MARK, BREQ_MARK,
+        WE3_MARK, WE2_MARK,
+        CS6_MARK, CS5_MARK, CS4_MARK,
+        CLKOUTENB_MARK,
+
+        DACK3_MARK, DACK2_MARK, DACK1_MARK, DACK0_MARK,
+        DREQ3_MARK, DREQ2_MARK, DREQ1_MARK, DREQ0_MARK,
+
+        IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
+
+        DRAK3_MARK, DRAK2_MARK, DRAK1_MARK, DRAK0_MARK,
+
+        SCK3_MARK, SCK2_MARK, SCK1_MARK, SCK0_MARK,
+        IRL3_MARK, IRL2_MARK, IRL1_MARK, IRL0_MARK,
+        TXD3_MARK, TXD2_MARK, TXD1_MARK, TXD0_MARK,
+        RXD3_MARK, RXD2_MARK, RXD1_MARK, RXD0_MARK,
+
+        CE2B_MARK, CE2A_MARK, IOIS16_MARK,
+        STATUS1_MARK, STATUS0_MARK,
+
+        IRQOUT_MARK,
+
+        PINMUX_MARK_END,
+};
+
+static pinmux_enum_t shx3_pinmux_data[] = {
+
+        /* PA GPIO */
+        PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
+        PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
+        PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
+        PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
+        PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
+        PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
+        PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
+        PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
+
+        /* PB GPIO */
+        PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
+        PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
+        PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
+        PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
+        PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
+        PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
+        PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
+        PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
+
+        /* PC GPIO */
+        PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
+        PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
+        PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
+        PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
+        PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
+        PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
+        PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
+        PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
+
+        /* PD GPIO */
+        PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
+        PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
+        PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
+        PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
+        PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
+        PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
+        PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
+        PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
+
+        /* PE GPIO */
+        PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
+        PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
+        PINMUX_DATA(PE5_DATA, PE5_IN, PE5_OUT, PE5_IN_PU),
+        PINMUX_DATA(PE4_DATA, PE4_IN, PE4_OUT, PE4_IN_PU),
+        PINMUX_DATA(PE3_DATA, PE3_IN, PE3_OUT, PE3_IN_PU),
+        PINMUX_DATA(PE2_DATA, PE2_IN, PE2_OUT, PE2_IN_PU),
+        PINMUX_DATA(PE1_DATA, PE1_IN, PE1_OUT, PE1_IN_PU),
+        PINMUX_DATA(PE0_DATA, PE0_IN, PE0_OUT, PE0_IN_PU),
+
+        /* PF GPIO */
+        PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
+        PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
+        PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
+        PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
+        PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
+        PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
+        PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
+        PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
+
+        /* PG GPIO */
+        PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
+        PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
+        PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
+        PINMUX_DATA(PG4_DATA, PG4_IN, PG4_OUT, PG4_IN_PU),
+        PINMUX_DATA(PG3_DATA, PG3_IN, PG3_OUT, PG3_IN_PU),
+        PINMUX_DATA(PG2_DATA, PG2_IN, PG2_OUT, PG2_IN_PU),
+        PINMUX_DATA(PG1_DATA, PG1_IN, PG1_OUT, PG1_IN_PU),
+        PINMUX_DATA(PG0_DATA, PG0_IN, PG0_OUT, PG0_IN_PU),
+
+        /* PH GPIO */
+        PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
+        PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
+        PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
+        PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
+        PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
+        PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
+
+        /* PA FN */
+        PINMUX_DATA(D31_MARK, PA7_FN),
+        PINMUX_DATA(D30_MARK, PA6_FN),
+        PINMUX_DATA(D29_MARK, PA5_FN),
+        PINMUX_DATA(D28_MARK, PA4_FN),
+        PINMUX_DATA(D27_MARK, PA3_FN),
+        PINMUX_DATA(D26_MARK, PA2_FN),
+        PINMUX_DATA(D25_MARK, PA1_FN),
+        PINMUX_DATA(D24_MARK, PA0_FN),
+
+        /* PB FN */
+        PINMUX_DATA(D23_MARK, PB7_FN),
+        PINMUX_DATA(D22_MARK, PB6_FN),
+        PINMUX_DATA(D21_MARK, PB5_FN),
+        PINMUX_DATA(D20_MARK, PB4_FN),
+        PINMUX_DATA(D19_MARK, PB3_FN),
+        PINMUX_DATA(D18_MARK, PB2_FN),
+        PINMUX_DATA(D17_MARK, PB1_FN),
+        PINMUX_DATA(D16_MARK, PB0_FN),
+
+        /* PC FN */
+        PINMUX_DATA(BACK_MARK,          PC7_FN),
+        PINMUX_DATA(BREQ_MARK,          PC6_FN),
+        PINMUX_DATA(WE3_MARK,           PC5_FN),
+        PINMUX_DATA(WE2_MARK,           PC4_FN),
+        PINMUX_DATA(CS6_MARK,           PC3_FN),
+        PINMUX_DATA(CS5_MARK,           PC2_FN),
+        PINMUX_DATA(CS4_MARK,           PC1_FN),
+        PINMUX_DATA(CLKOUTENB_MARK,     PC0_FN),
+
+        /* PD FN */
+        PINMUX_DATA(DACK3_MARK, PD7_FN),
+        PINMUX_DATA(DACK2_MARK, PD6_FN),
+        PINMUX_DATA(DACK1_MARK, PD5_FN),
+        PINMUX_DATA(DACK0_MARK, PD4_FN),
+        PINMUX_DATA(DREQ3_MARK, PD3_FN),
+        PINMUX_DATA(DREQ2_MARK, PD2_FN),
+        PINMUX_DATA(DREQ1_MARK, PD1_FN),
+        PINMUX_DATA(DREQ0_MARK, PD0_FN),
+
+        /* PE FN */
+        PINMUX_DATA(IRQ3_MARK,  PE7_FN),
+        PINMUX_DATA(IRQ2_MARK,  PE6_FN),
+        PINMUX_DATA(IRQ1_MARK,  PE5_FN),
+        PINMUX_DATA(IRQ0_MARK,  PE4_FN),
+        PINMUX_DATA(DRAK3_MARK, PE3_FN),
+        PINMUX_DATA(DRAK2_MARK, PE2_FN),
+        PINMUX_DATA(DRAK1_MARK, PE1_FN),
+        PINMUX_DATA(DRAK0_MARK, PE0_FN),
+
+        /* PF FN */
+        PINMUX_DATA(SCK3_MARK, PF7_FN),
+        PINMUX_DATA(SCK2_MARK, PF6_FN),
+        PINMUX_DATA(SCK1_MARK, PF5_FN),
+        PINMUX_DATA(SCK0_MARK, PF4_FN),
+        PINMUX_DATA(IRL3_MARK, PF3_FN),
+        PINMUX_DATA(IRL2_MARK, PF2_FN),
+        PINMUX_DATA(IRL1_MARK, PF1_FN),
+        PINMUX_DATA(IRL0_MARK, PF0_FN),
+
+        /* PG FN */
+        PINMUX_DATA(TXD3_MARK, PG7_FN),
+        PINMUX_DATA(TXD2_MARK, PG6_FN),
+        PINMUX_DATA(TXD1_MARK, PG5_FN),
+        PINMUX_DATA(TXD0_MARK, PG4_FN),
+        PINMUX_DATA(RXD3_MARK, PG3_FN),
+        PINMUX_DATA(RXD2_MARK, PG2_FN),
+        PINMUX_DATA(RXD1_MARK, PG1_FN),
+        PINMUX_DATA(RXD0_MARK, PG0_FN),
+
+        /* PH FN */
+        PINMUX_DATA(CE2B_MARK,          PH5_FN),
+        PINMUX_DATA(CE2A_MARK,          PH4_FN),
+        PINMUX_DATA(IOIS16_MARK,        PH3_FN),
+        PINMUX_DATA(STATUS1_MARK,       PH2_FN),
+        PINMUX_DATA(STATUS0_MARK,       PH1_FN),
+        PINMUX_DATA(IRQOUT_MARK,        PH0_FN),
+};
+
+static struct pinmux_gpio shx3_pinmux_gpios[] = {
+        /* PA */
+        PINMUX_GPIO(GPIO_PA7, PA7_DATA),
+        PINMUX_GPIO(GPIO_PA6, PA6_DATA),
+        PINMUX_GPIO(GPIO_PA5, PA5_DATA),
+        PINMUX_GPIO(GPIO_PA4, PA4_DATA),
+        PINMUX_GPIO(GPIO_PA3, PA3_DATA),
+        PINMUX_GPIO(GPIO_PA2, PA2_DATA),
+        PINMUX_GPIO(GPIO_PA1, PA1_DATA),
+        PINMUX_GPIO(GPIO_PA0, PA0_DATA),
+
+        /* PB */
+        PINMUX_GPIO(GPIO_PB7, PB7_DATA),
+        PINMUX_GPIO(GPIO_PB6, PB6_DATA),
+        PINMUX_GPIO(GPIO_PB5, PB5_DATA),
+        PINMUX_GPIO(GPIO_PB4, PB4_DATA),
+        PINMUX_GPIO(GPIO_PB3, PB3_DATA),
+        PINMUX_GPIO(GPIO_PB2, PB2_DATA),
+        PINMUX_GPIO(GPIO_PB1, PB1_DATA),
+        PINMUX_GPIO(GPIO_PB0, PB0_DATA),
+
+        /* PC */
+        PINMUX_GPIO(GPIO_PC7, PC7_DATA),
+        PINMUX_GPIO(GPIO_PC6, PC6_DATA),
+        PINMUX_GPIO(GPIO_PC5, PC5_DATA),
+        PINMUX_GPIO(GPIO_PC4, PC4_DATA),
+        PINMUX_GPIO(GPIO_PC3, PC3_DATA),
+        PINMUX_GPIO(GPIO_PC2, PC2_DATA),
+        PINMUX_GPIO(GPIO_PC1, PC1_DATA),
+        PINMUX_GPIO(GPIO_PC0, PC0_DATA),
+
+        /* PD */
+        PINMUX_GPIO(GPIO_PD7, PD7_DATA),
+        PINMUX_GPIO(GPIO_PD6, PD6_DATA),
+        PINMUX_GPIO(GPIO_PD5, PD5_DATA),
+        PINMUX_GPIO(GPIO_PD4, PD4_DATA),
+        PINMUX_GPIO(GPIO_PD3, PD3_DATA),
+        PINMUX_GPIO(GPIO_PD2, PD2_DATA),
+        PINMUX_GPIO(GPIO_PD1, PD1_DATA),
+        PINMUX_GPIO(GPIO_PD0, PD0_DATA),
+
+        /* PE */
+        PINMUX_GPIO(GPIO_PE7, PE7_DATA),
+        PINMUX_GPIO(GPIO_PE6, PE6_DATA),
+        PINMUX_GPIO(GPIO_PE5, PE5_DATA),
+        PINMUX_GPIO(GPIO_PE4, PE4_DATA),
+        PINMUX_GPIO(GPIO_PE3, PE3_DATA),
+        PINMUX_GPIO(GPIO_PE2, PE2_DATA),
+        PINMUX_GPIO(GPIO_PE1, PE1_DATA),
+        PINMUX_GPIO(GPIO_PE0, PE0_DATA),
+
+        /* PF */
+        PINMUX_GPIO(GPIO_PF7, PF7_DATA),
+        PINMUX_GPIO(GPIO_PF6, PF6_DATA),
+        PINMUX_GPIO(GPIO_PF5, PF5_DATA),
+        PINMUX_GPIO(GPIO_PF4, PF4_DATA),
+        PINMUX_GPIO(GPIO_PF3, PF3_DATA),
+        PINMUX_GPIO(GPIO_PF2, PF2_DATA),
+        PINMUX_GPIO(GPIO_PF1, PF1_DATA),
+        PINMUX_GPIO(GPIO_PF0, PF0_DATA),
+
+        /* PG */
+        PINMUX_GPIO(GPIO_PG7, PG7_DATA),
+        PINMUX_GPIO(GPIO_PG6, PG6_DATA),
+        PINMUX_GPIO(GPIO_PG5, PG5_DATA),
+        PINMUX_GPIO(GPIO_PG4, PG4_DATA),
+        PINMUX_GPIO(GPIO_PG3, PG3_DATA),
+        PINMUX_GPIO(GPIO_PG2, PG2_DATA),
+        PINMUX_GPIO(GPIO_PG1, PG1_DATA),
+        PINMUX_GPIO(GPIO_PG0, PG0_DATA),
+
+        /* PH */
+        PINMUX_GPIO(GPIO_PH5, PH5_DATA),
+        PINMUX_GPIO(GPIO_PH4, PH4_DATA),
+        PINMUX_GPIO(GPIO_PH3, PH3_DATA),
+        PINMUX_GPIO(GPIO_PH2, PH2_DATA),
+        PINMUX_GPIO(GPIO_PH1, PH1_DATA),
+        PINMUX_GPIO(GPIO_PH0, PH0_DATA),
+
+        /* FN */
+        PINMUX_GPIO(GPIO_FN_D31,        D31_MARK),
+        PINMUX_GPIO(GPIO_FN_D30,        D30_MARK),
+        PINMUX_GPIO(GPIO_FN_D29,        D29_MARK),
+        PINMUX_GPIO(GPIO_FN_D28,        D28_MARK),
+        PINMUX_GPIO(GPIO_FN_D27,        D27_MARK),
+        PINMUX_GPIO(GPIO_FN_D26,        D26_MARK),
+        PINMUX_GPIO(GPIO_FN_D25,        D25_MARK),
+        PINMUX_GPIO(GPIO_FN_D24,        D24_MARK),
+        PINMUX_GPIO(GPIO_FN_D23,        D23_MARK),
+        PINMUX_GPIO(GPIO_FN_D22,        D22_MARK),
+        PINMUX_GPIO(GPIO_FN_D21,        D21_MARK),
+        PINMUX_GPIO(GPIO_FN_D20,        D20_MARK),
+        PINMUX_GPIO(GPIO_FN_D19,        D19_MARK),
+        PINMUX_GPIO(GPIO_FN_D18,        D18_MARK),
+        PINMUX_GPIO(GPIO_FN_D17,        D17_MARK),
+        PINMUX_GPIO(GPIO_FN_D16,        D16_MARK),
+        PINMUX_GPIO(GPIO_FN_BACK,       BACK_MARK),
+        PINMUX_GPIO(GPIO_FN_BREQ,       BREQ_MARK),
+        PINMUX_GPIO(GPIO_FN_WE3,        WE3_MARK),
+        PINMUX_GPIO(GPIO_FN_WE2,        WE2_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6,        CS6_MARK),
+        PINMUX_GPIO(GPIO_FN_CS5,        CS5_MARK),
+        PINMUX_GPIO(GPIO_FN_CS4,        CS4_MARK),
+        PINMUX_GPIO(GPIO_FN_CLKOUTENB,  CLKOUTENB_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK3,      DACK3_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK2,      DACK2_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK1,      DACK1_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK0,      DACK0_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ3,      DREQ3_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ2,      DREQ2_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ1,      DREQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ0,      DREQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ3,       IRQ3_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ2,       IRQ2_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ1,       IRQ1_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ0,       IRQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_DRAK3,      DRAK3_MARK),
+        PINMUX_GPIO(GPIO_FN_DRAK2,      DRAK2_MARK),
+        PINMUX_GPIO(GPIO_FN_DRAK1,      DRAK1_MARK),
+        PINMUX_GPIO(GPIO_FN_DRAK0,      DRAK0_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK3,       SCK3_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK2,       SCK2_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK1,       SCK1_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK0,       SCK0_MARK),
+        PINMUX_GPIO(GPIO_FN_IRL3,       IRL3_MARK),
+        PINMUX_GPIO(GPIO_FN_IRL2,       IRL2_MARK),
+        PINMUX_GPIO(GPIO_FN_IRL1,       IRL1_MARK),
+        PINMUX_GPIO(GPIO_FN_IRL0,       IRL0_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD3,       TXD3_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD2,       TXD2_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD1,       TXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD0,       TXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD3,       RXD3_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD2,       RXD2_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD1,       RXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD0,       RXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_CE2B,       CE2B_MARK),
+        PINMUX_GPIO(GPIO_FN_CE2A,       CE2A_MARK),
+        PINMUX_GPIO(GPIO_FN_IOIS16,     IOIS16_MARK),
+        PINMUX_GPIO(GPIO_FN_STATUS1,    STATUS1_MARK),
+        PINMUX_GPIO(GPIO_FN_STATUS0,    STATUS0_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQOUT,     IRQOUT_MARK),
+};
+
+static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
+                PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
+                PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
+                PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
+                PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
+                PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
+                PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
+                PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
+                PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU,
+                PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
+                PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
+                PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
+                PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
+                PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
+                PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
+                PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
+                PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU, },
+        },
+        { PINMUX_CFG_REG("PCDCR", 0xffc70004, 32, 2) {
+                PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
+                PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
+                PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
+                PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
+                PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
+                PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
+                PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
+                PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU,
+                PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
+                PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
+                PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
+                PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
+                PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
+                PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
+                PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
+                PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU, },
+        },
+        { PINMUX_CFG_REG("PEFCR", 0xffc70008, 32, 2) {
+                PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
+                PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
+                PE5_FN, PE5_OUT, PE5_IN, PE5_IN_PU,
+                PE4_FN, PE4_OUT, PE4_IN, PE4_IN_PU,
+                PE3_FN, PE3_OUT, PE3_IN, PE3_IN_PU,
+                PE2_FN, PE2_OUT, PE2_IN, PE2_IN_PU,
+                PE1_FN, PE1_OUT, PE1_IN, PE1_IN_PU,
+                PE0_FN, PE0_OUT, PE0_IN, PE0_IN_PU,
+                PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
+                PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
+                PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
+                PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
+                PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
+                PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
+                PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
+                PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU, },
+        },
+        { PINMUX_CFG_REG("PGHCR", 0xffc7000c, 32, 2) {
+                PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
+                PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
+                PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
+                PG4_FN, PG4_OUT, PG4_IN, PG4_IN_PU,
+                PG3_FN, PG3_OUT, PG3_IN, PG3_IN_PU,
+                PG2_FN, PG2_OUT, PG2_IN, PG2_IN_PU,
+                PG1_FN, PG1_OUT, PG1_IN, PG1_IN_PU,
+                PG0_FN, PG0_OUT, PG0_IN, PG0_IN_PU,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
+                PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
+                PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
+                PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
+                PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
+                PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU, },
+        },
+        { },
+};
+
+static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
+                PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
+                PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, },
+        },
+        { PINMUX_DATA_REG("PCDDR", 0xffc70014, 32) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
+                PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
+                PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, },
+        },
+        { PINMUX_DATA_REG("PEFDR", 0xffc70018, 32) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
+                PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
+                PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, },
+        },
+        { PINMUX_DATA_REG("PGHDR", 0xffc7001c, 32) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
+                PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, PH5_DATA, PH4_DATA,
+                PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, },
+        },
+        { },
+};
+
+static struct pinmux_info shx3_pinmux_info = {
+        .name           = "shx3_pfc",
+        .reserved_id    = PINMUX_RESERVED,
+        .data           = { PINMUX_DATA_BEGIN,     PINMUX_DATA_END },
+        .input          = { PINMUX_INPUT_BEGIN,    PINMUX_INPUT_END },
+        .input_pu       = { PINMUX_INPUT_PULLUP_BEGIN,
+                            PINMUX_INPUT_PULLUP_END },
+        .output         = { PINMUX_OUTPUT_BEGIN,   PINMUX_OUTPUT_END },
+        .mark           = { PINMUX_MARK_BEGIN,     PINMUX_MARK_END },
+        .function       = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+        .first_gpio     = GPIO_PA7,
+        .last_gpio      = GPIO_FN_IRQOUT,
+        .gpios          = shx3_pinmux_gpios,
+        .gpio_data      = shx3_pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
+        .cfg_regs       = shx3_pinmux_config_regs,
+        .data_regs      = shx3_pinmux_data_regs,
+};
+
+static int __init shx3_pinmux_setup(void)
+{
+        return register_pinmux(&shx3_pinmux_info);
+}
+arch_initcall(shx3_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 3681cafdb4af..1b8848317e9c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -19,6 +19,8 @@
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xffe00000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 80, 80, 80, 80 },
 };
@@ -34,6 +36,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xffe10000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 81, 81, 81, 81 },
 };
@@ -49,6 +53,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xffe20000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 82, 82, 82, 82 },
 };
@@ -64,6 +70,8 @@ static struct platform_device scif2_device = {
 static struct plat_sci_port scif3_platform_data = {
         .mapbase        = 0xffe30000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 83, 83, 83, 83 },
 };
@@ -360,6 +368,8 @@ void __init plat_early_device_setup(void)
 
 enum {
         UNUSED = 0,
+        ENABLED,
+        DISABLED,
 
         /* interrupt sources */
         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -375,15 +385,13 @@ enum {
         I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
         I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
         SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
-        IRDA,
-        SDHI0, SDHI1, SDHI2, SDHI3,
-        CMT, TSIF, SIU,
+        IRDA, SDHI, CMT, TSIF, SIU,
         TMU0, TMU1, TMU2,
         JPU, LCDC,
 
         /* interrupt groups */
 
-        DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, SDHI, USB,
+        DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, USB,
 };
 
 static struct intc_vect vectors[] __initdata = {
@@ -412,8 +420,8 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
         INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
         INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
-        INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
-        INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
+        INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
+        INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
         INTC_VECT(SIU, 0xf80),
         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
@@ -431,7 +439,6 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
         INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
         INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
-        INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
         INTC_GROUP(USB, USBI0, USBI1),
 };
 
@@ -452,7 +459,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-          { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
+          { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
           { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -488,9 +495,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC_ACK(intc_desc, "sh7343", vectors, groups,
-                             mask_registers, prio_registers, sense_registers,
-                             ack_registers);
+static struct intc_desc intc_desc __initdata = {
+        .name = "sh7343",
+        .force_enable = ENABLED,
+        .force_disable = DISABLED,
+        .hw = INTC_HW_DESC(vectors, groups, mask_registers,
+                           prio_registers, sense_registers, ack_registers),
+};
 
 void __init plat_irq_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 8dab9e1bbd89..82616af64d62 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -21,6 +21,8 @@
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xffe00000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 80, 80, 80, 80 },
 };
@@ -319,6 +321,8 @@ void __init plat_early_device_setup(void)
 
 enum {
         UNUSED=0,
+        ENABLED,
+        DISABLED,
 
         /* interrupt sources */
         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -332,14 +336,13 @@ enum {
         DENC, MSIOF,
         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
-        SDHI0, SDHI1, SDHI2, SDHI3,
-        CMT, TSIF, SIU,
+        SDHI, CMT, TSIF, SIU,
         TMU0, TMU1, TMU2,
         VEU2, LCDC,
 
         /* interrupt groups */
 
-        DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, SDHI,
+        DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C,
 };
 
 static struct intc_vect vectors[] __initdata = {
@@ -364,8 +367,8 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
-        INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
-        INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
+        INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
+        INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
         INTC_VECT(SIU, 0xf80),
         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
@@ -381,7 +384,6 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
-        INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
 };
 
 static struct intc_mask_reg mask_registers[] __initdata = {
@@ -403,7 +405,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-          { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
+          { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
           { 0, 0, 0, CMT, 0, USB, } },
         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -441,9 +443,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC_ACK(intc_desc, "sh7366", vectors, groups,
-                             mask_registers, prio_registers, sense_registers,
-                             ack_registers);
+static struct intc_desc intc_desc __initdata = {
+        .name = "sh7366",
+        .force_enable = ENABLED,
+        .force_disable = DISABLED,
+        .hw = INTC_HW_DESC(vectors, groups, mask_registers,
+                           prio_registers, sense_registers, ack_registers),
+};
 
 void __init plat_irq_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 156ccc960015..5813d8023619 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -181,6 +181,8 @@ struct platform_device dma_device = {
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xffe00000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 80, 80, 80, 80 },
 };
@@ -196,6 +198,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xffe10000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 81, 81, 81, 81 },
 };
@@ -211,6 +215,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xffe20000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 82, 82, 82, 82 },
 };
@@ -551,7 +557,7 @@ static struct resource siu_resources[] = {
 };
 
 static struct platform_device siu_device = {
-        .name           = "sh_siu",
+        .name           = "siu-pcm-audio",
         .id             = -1,
         .dev = {
                 .platform_data  = &siu_platform_data,
@@ -699,7 +705,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-          { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
+          { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
           { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 0eadefdbbba1..072382280f96 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -24,6 +24,8 @@
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xffe00000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 80, 80, 80, 80 },
 };
@@ -39,6 +41,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xffe10000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 81, 81, 81, 81 },
 };
@@ -54,6 +58,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xffe20000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 82, 82, 82, 82 },
 };
@@ -69,6 +75,8 @@ static struct platform_device scif2_device = {
 static struct plat_sci_port scif3_platform_data = {
         .mapbase        = 0xa4e30000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_3,
         .type           = PORT_SCIFA,
         .irqs           = { 56, 56, 56, 56 },
 };
@@ -84,6 +92,8 @@ static struct platform_device scif3_device = {
 static struct plat_sci_port scif4_platform_data = {
         .mapbase        = 0xa4e40000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_3,
         .type           = PORT_SCIFA,
         .irqs           = { 88, 88, 88, 88 },
 };
@@ -99,6 +109,8 @@ static struct platform_device scif4_device = {
 static struct plat_sci_port scif5_platform_data = {
         .mapbase        = 0xa4e50000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_3,
         .type           = PORT_SCIFA,
         .irqs           = { 109, 109, 109, 109 },
 };
@@ -719,7 +731,7 @@ static struct intc_group groups[] __initdata = {
 static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
           { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
-            0, DISABLED, ENABLED, ENABLED } },
+            0, ENABLED, ENABLED, ENABLED } },
         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
           { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
@@ -736,7 +748,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-          { 0, DISABLED, ENABLED, ENABLED,
+          { 0, ENABLED, ENABLED, ENABLED,
             0, 0, SCIFA_SCIFA2, SIU_SIUI } },
         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
           { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 79c556e56262..134a397b1918 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -93,6 +93,46 @@ static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
                 .mid_rid        = 0x36,
         }, {
+                .slave_id       = SHDMA_SLAVE_USB0D0_TX,
+                .addr           = 0xA4D80100,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0x73,
+        }, {
+                .slave_id       = SHDMA_SLAVE_USB0D0_RX,
+                .addr           = 0xA4D80100,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0x73,
+        }, {
+                .slave_id       = SHDMA_SLAVE_USB0D1_TX,
+                .addr           = 0xA4D80120,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0x77,
+        }, {
+                .slave_id       = SHDMA_SLAVE_USB0D1_RX,
+                .addr           = 0xA4D80120,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0x77,
+        }, {
+                .slave_id       = SHDMA_SLAVE_USB1D0_TX,
+                .addr           = 0xA4D90100,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xab,
+        }, {
+                .slave_id       = SHDMA_SLAVE_USB1D0_RX,
+                .addr           = 0xA4D90100,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xab,
+        }, {
+                .slave_id       = SHDMA_SLAVE_USB1D1_TX,
+                .addr           = 0xA4D90120,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xaf,
+        }, {
+                .slave_id       = SHDMA_SLAVE_USB1D1_RX,
+                .addr           = 0xA4D90120,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xaf,
+        }, {
                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
                 .addr           = 0x04ce0030,
                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
@@ -257,6 +297,8 @@ static struct platform_device dma1_device = {
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xffe00000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 80, 80, 80, 80 },
 };
@@ -272,6 +314,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xffe10000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 81, 81, 81, 81 },
 };
@@ -287,6 +331,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xffe20000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 82, 82, 82, 82 },
 };
@@ -302,6 +348,8 @@ static struct platform_device scif2_device = {
 static struct plat_sci_port scif3_platform_data = {
         .mapbase        = 0xa4e30000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_3,
         .type           = PORT_SCIFA,
         .irqs           = { 56, 56, 56, 56 },
 };
@@ -317,6 +365,8 @@ static struct platform_device scif3_device = {
 static struct plat_sci_port scif4_platform_data = {
         .mapbase        = 0xa4e40000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_3,
         .type           = PORT_SCIFA,
         .irqs           = { 88, 88, 88, 88 },
 };
@@ -332,6 +382,8 @@ static struct platform_device scif4_device = {
 static struct plat_sci_port scif5_platform_data = {
         .mapbase        = 0xa4e50000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE,
+        .scbrr_algo_id  = SCBRR_ALGO_3,
         .type           = PORT_SCIFA,
         .irqs           = { 109, 109, 109, 109 },
 };
@@ -524,6 +576,70 @@ static struct platform_device veu1_device = {
         },
 };
 
+/* BEU0 */
+static struct uio_info beu0_platform_data = {
+        .name = "BEU0",
+        .version = "0",
+        .irq = evt2irq(0x8A0),
+};
+
+static struct resource beu0_resources[] = {
+        [0] = {
+                .name   = "BEU0",
+                .start  = 0xfe930000,
+                .end    = 0xfe933400,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device beu0_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 6,
+        .dev = {
+                .platform_data  = &beu0_platform_data,
+        },
+        .resource       = beu0_resources,
+        .num_resources  = ARRAY_SIZE(beu0_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_BEU0,
+        },
+};
+
+/* BEU1 */
+static struct uio_info beu1_platform_data = {
+        .name = "BEU1",
+        .version = "0",
+        .irq = evt2irq(0xA00),
+};
+
+static struct resource beu1_resources[] = {
+        [0] = {
+                .name   = "BEU1",
+                .start  = 0xfe940000,
+                .end    = 0xfe943400,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device beu1_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 7,
+        .dev = {
+                .platform_data  = &beu1_platform_data,
+        },
+        .resource       = beu1_resources,
+        .num_resources  = ARRAY_SIZE(beu1_resources),
+        .archdata = {
+                .hwblk_id = HWBLK_BEU1,
+        },
+};
+
 static struct sh_timer_config cmt_platform_data = {
         .channel_offset = 0x60,
         .timer_bit = 5,
@@ -857,6 +973,8 @@ static struct platform_device *sh7724_devices[] __initdata = {
         &vpu_device,
         &veu0_device,
         &veu1_device,
+        &beu0_device,
+        &beu1_device,
         &jpu_device,
         &spu0_device,
         &spu1_device,
@@ -1078,7 +1196,7 @@ static struct intc_group groups[] __initdata = {
 static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
           { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
-            0, DISABLED, ENABLED, ENABLED } },
+            0, ENABLED, ENABLED, ENABLED } },
         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
           { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
             DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
@@ -1100,7 +1218,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
             I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-          { DISABLED, DISABLED, ENABLED, ENABLED,
+          { DISABLED, ENABLED, ENABLED, ENABLED,
             0, 0, SCIFA5, FSI } },
         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
           { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 444aca95b20d..e915deafac89 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -1,7 +1,7 @@
 /*
  * SH7757 Setup
  *
- * Copyright (C) 2009  Renesas Solutions Corp.
+ * Copyright (C) 2009, 2011  Renesas Solutions Corp.
  *
  *  based on setup-sh7785.c : Copyright (C) 2007  Paul Mundt
  *
@@ -16,17 +16,23 @@
 #include <linux/io.h>
 #include <linux/mm.h>
 #include <linux/sh_timer.h>
+#include <linux/sh_dma.h>
+
+#include <cpu/dma-register.h>
+#include <cpu/sh7757.h>
 
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xfe4b0000,           /* SCIF2 */
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 40, 40, 40, 40 },
 };
 
 static struct platform_device scif2_device = {
         .name           = "sh-sci",
-        .id             = 2,
+        .id             = 0,
         .dev            = {
                 .platform_data  = &scif2_platform_data,
         },
@@ -35,13 +41,15 @@ static struct platform_device scif2_device = {
 static struct plat_sci_port scif3_platform_data = {
         .mapbase        = 0xfe4c0000,           /* SCIF3 */
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 76, 76, 76, 76 },
 };
 
 static struct platform_device scif3_device = {
         .name           = "sh-sci",
-        .id             = 3,
+        .id             = 1,
         .dev            = {
                 .platform_data  = &scif3_platform_data,
         },
@@ -50,13 +58,15 @@ static struct platform_device scif3_device = {
 static struct plat_sci_port scif4_platform_data = {
         .mapbase        = 0xfe4d0000,           /* SCIF4 */
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 104, 104, 104, 104 },
 };
 
 static struct platform_device scif4_device = {
         .name           = "sh-sci",
-        .id             = 4,
+        .id             = 2,
         .dev            = {
                 .platform_data  = &scif4_platform_data,
         },
@@ -118,12 +128,598 @@ static struct platform_device tmu1_device = {
         .num_resources  = ARRAY_SIZE(tmu1_resources),
 };
 
+static struct resource spi0_resources[] = {
+        [0] = {
+                .start  = 0xfe002000,
+                .end    = 0xfe0020ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 86,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+/* DMA */
+static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_SDHI_TX,
+                .addr           = 0x1fe50030,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc5,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_SDHI_RX,
+                .addr           = 0x1fe50030,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc6,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+                .addr           = 0x1fcb0034,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd3,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+                .addr           = 0x1fcb0034,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd7,
+        },
+};
+
+static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF2_TX,
+                .addr           = 0x1f4b000c,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x21,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF2_RX,
+                .addr           = 0x1f4b0014,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x22,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF3_TX,
+                .addr           = 0x1f4c000c,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x29,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF3_RX,
+                .addr           = 0x1f4c0014,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2a,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF4_TX,
+                .addr           = 0x1f4d000c,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x41,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF4_RX,
+                .addr           = 0x1f4d0014,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x42,
+        },
+};
+
+static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC0_TX,
+                .addr           = 0x1e500012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x21,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC0_RX,
+                .addr           = 0x1e500013,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x22,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC1_TX,
+                .addr           = 0x1e510012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x29,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC1_RX,
+                .addr           = 0x1e510013,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2a,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC2_TX,
+                .addr           = 0x1e520012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0xa1,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC2_RX,
+                .addr           = 0x1e520013,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0xa2,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC3_TX,
+                .addr           = 0x1e530012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0xa9,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC3_RX,
+                .addr           = 0x1e530013,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0xaf,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC4_TX,
+                .addr           = 0x1e540012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0xc5,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC4_RX,
+                .addr           = 0x1e540013,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0xc6,
+        },
+};
+
+static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC5_TX,
+                .addr           = 0x1e550012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x21,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC5_RX,
+                .addr           = 0x1e550013,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x22,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC6_TX,
+                .addr           = 0x1e560012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x29,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC6_RX,
+                .addr           = 0x1e560013,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2a,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC7_TX,
+                .addr           = 0x1e570012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x41,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC7_RX,
+                .addr           = 0x1e570013,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x42,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC8_TX,
+                .addr           = 0x1e580012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x45,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC8_RX,
+                .addr           = 0x1e580013,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x46,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC9_TX,
+                .addr           = 0x1e590012,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x51,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RIIC9_RX,
+                .addr           = 0x1e590013,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .mid_rid        = 0x52,
+        },
+};
+
+static const struct sh_dmae_channel sh7757_dmae_channels[] = {
+        {
+                .offset = 0,
+                .dmars = 0,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x10,
+                .dmars = 0,
+                .dmars_bit = 8,
+        }, {
+                .offset = 0x20,
+                .dmars = 4,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x30,
+                .dmars = 4,
+                .dmars_bit = 8,
+        }, {
+                .offset = 0x50,
+                .dmars = 8,
+                .dmars_bit = 0,
+        }, {
+                .offset = 0x60,
+                .dmars = 8,
+                .dmars_bit = 8,
+        }
+};
+
+static const unsigned int ts_shift[] = TS_SHIFT;
+
+static struct sh_dmae_pdata dma0_platform_data = {
+        .slave          = sh7757_dmae0_slaves,
+        .slave_num      = ARRAY_SIZE(sh7757_dmae0_slaves),
+        .channel        = sh7757_dmae_channels,
+        .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+static struct sh_dmae_pdata dma1_platform_data = {
+        .slave          = sh7757_dmae1_slaves,
+        .slave_num      = ARRAY_SIZE(sh7757_dmae1_slaves),
+        .channel        = sh7757_dmae_channels,
+        .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+static struct sh_dmae_pdata dma2_platform_data = {
+        .slave          = sh7757_dmae2_slaves,
+        .slave_num      = ARRAY_SIZE(sh7757_dmae2_slaves),
+        .channel        = sh7757_dmae_channels,
+        .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+static struct sh_dmae_pdata dma3_platform_data = {
+        .slave          = sh7757_dmae3_slaves,
+        .slave_num      = ARRAY_SIZE(sh7757_dmae3_slaves),
+        .channel        = sh7757_dmae_channels,
+        .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
+        .ts_low_shift   = CHCR_TS_LOW_SHIFT,
+        .ts_low_mask    = CHCR_TS_LOW_MASK,
+        .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
+        .ts_high_mask   = CHCR_TS_HIGH_MASK,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_INIT,
+};
+
+/* channel 0 to 5 */
+static struct resource sh7757_dmae0_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xff608020,
+                .end    = 0xff60808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* DMARSx */
+                .start  = 0xff609000,
+                .end    = 0xff60900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = 34,
+                .end    = 34,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+};
+
+/* channel 6 to 11 */
+static struct resource sh7757_dmae1_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xff618020,
+                .end    = 0xff61808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* DMARSx */
+                .start  = 0xff619000,
+                .end    = 0xff61900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMA error */
+                .start  = 34,
+                .end    = 34,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 4 */
+                .start  = 46,
+                .end    = 46,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 5 */
+                .start  = 46,
+                .end    = 46,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 6 */
+                .start  = 88,
+                .end    = 88,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 7 */
+                .start  = 88,
+                .end    = 88,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 8 */
+                .start  = 88,
+                .end    = 88,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 9 */
+                .start  = 88,
+                .end    = 88,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 10 */
+                .start  = 88,
+                .end    = 88,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+        {
+                /* IRQ for channels 11 */
+                .start  = 88,
+                .end    = 88,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
+        },
+};
+
+/* channel 12 to 17 */
+static struct resource sh7757_dmae2_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xff708020,
+                .end    = 0xff70808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* DMARSx */
+                .start  = 0xff709000,
+                .end    = 0xff70900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMA error */
+                .start  = 323,
+                .end    = 323,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 12 to 16 */
+                .start  = 272,
+                .end    = 276,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channel 17 */
+                .start  = 279,
+                .end    = 279,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+/* channel 18 to 23 */
+static struct resource sh7757_dmae3_resources[] = {
+        [0] = {
+                /* Channel registers and DMAOR */
+                .start  = 0xff718020,
+                .end    = 0xff71808f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* DMARSx */
+                .start  = 0xff719000,
+                .end    = 0xff71900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMA error */
+                .start  = 324,
+                .end    = 324,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 18 to 22 */
+                .start  = 280,
+                .end    = 284,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channel 23 */
+                .start  = 288,
+                .end    = 288,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dma0_device = {
+        .name           = "sh-dma-engine",
+        .id             = 0,
+        .resource       = sh7757_dmae0_resources,
+        .num_resources  = ARRAY_SIZE(sh7757_dmae0_resources),
+        .dev            = {
+                .platform_data  = &dma0_platform_data,
+        },
+};
+
+static struct platform_device dma1_device = {
+        .name           = "sh-dma-engine",
+        .id             = 1,
+        .resource       = sh7757_dmae1_resources,
+        .num_resources  = ARRAY_SIZE(sh7757_dmae1_resources),
+        .dev            = {
+                .platform_data  = &dma1_platform_data,
+        },
+};
+
+static struct platform_device dma2_device = {
+        .name           = "sh-dma-engine",
+        .id             = 2,
+        .resource       = sh7757_dmae2_resources,
+        .num_resources  = ARRAY_SIZE(sh7757_dmae2_resources),
+        .dev            = {
+                .platform_data  = &dma2_platform_data,
+        },
+};
+
+static struct platform_device dma3_device = {
+        .name           = "sh-dma-engine",
+        .id             = 3,
+        .resource       = sh7757_dmae3_resources,
+        .num_resources  = ARRAY_SIZE(sh7757_dmae3_resources),
+        .dev            = {
+                .platform_data  = &dma3_platform_data,
+        },
+};
+
+static struct platform_device spi0_device = {
+        .name   = "sh_spi",
+        .id     = 0,
+        .dev    = {
+                .dma_mask               = NULL,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(spi0_resources),
+        .resource       = spi0_resources,
+};
+
+static struct resource usb_ehci_resources[] = {
+        [0] = {
+                .start  = 0xfe4f1000,
+                .end    = 0xfe4f10ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 57,
+                .end    = 57,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device usb_ehci_device = {
+        .name           = "sh_ehci",
+        .id             = -1,
+        .dev = {
+                .dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(usb_ehci_resources),
+        .resource       = usb_ehci_resources,
+};
+
+static struct resource usb_ohci_resources[] = {
+        [0] = {
+                .start  = 0xfe4f1800,
+                .end    = 0xfe4f18ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 57,
+                .end    = 57,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device usb_ohci_device = {
+        .name           = "sh_ohci",
+        .id             = -1,
+        .dev = {
+                .dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(usb_ohci_resources),
+        .resource       = usb_ohci_resources,
+};
+
 static struct platform_device *sh7757_devices[] __initdata = {
         &scif2_device,
         &scif3_device,
         &scif4_device,
         &tmu0_device,
         &tmu1_device,
+        &dma0_device,
+        &dma1_device,
+        &dma2_device,
+        &dma3_device,
+        &spi0_device,
+        &usb_ehci_device,
+        &usb_ohci_device,
 };
 
 static int __init sh7757_devices_setup(void)
@@ -163,39 +759,23 @@ enum {
         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 
-        SDHI,
-        DVC,
-        IRQ8, IRQ9, IRQ10,
-        WDT0,
-        TMU0, TMU1, TMU2, TMU2_TICPI,
+        SDHI, DVC,
+        IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
+        TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
         HUDI,
-
         ARC4,
-        DMAC0,
-        IRQ11,
-        SCIF2,
-        DMAC1_6,
-        USB0,
-        IRQ12,
+        DMAC0_5, DMAC6_7, DMAC8_11,
+        SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
+        USB0, USB1,
         JMC,
-        SPI1,
-        IRQ13, IRQ14,
-        USB1,
+        SPI0, SPI1,
         TMR01, TMR23, TMR45,
-        WDT1,
         FRT,
-        LPC,
-        SCIF0, SCIF1, SCIF3,
-        PECI0I, PECI1I, PECI2I,
-        IRQ15,
+        LPC, LPC5, LPC6, LPC7, LPC8,
+        PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
         ETHERC,
-        SPI0,
-        ADC1,
-        DMAC1_8,
+        ADC0, ADC1,
         SIM,
-        TMU3, TMU4, TMU5,
-        ADC0,
-        SCIF4,
         IIC0_0, IIC0_1, IIC0_2, IIC0_3,
         IIC1_0, IIC1_1, IIC1_2, IIC1_3,
         IIC2_0, IIC2_1, IIC2_2, IIC2_3,
@@ -206,9 +786,23 @@ enum {
         IIC7_0, IIC7_1, IIC7_2, IIC7_3,
         IIC8_0, IIC8_1, IIC8_2, IIC8_3,
         IIC9_0, IIC9_1, IIC9_2, IIC9_3,
-        PCIINTA,
-        PCIE,
+        ONFICTL,
+        MMC1, MMC2,
+        ECCU,
+        PCIC,
+        G200,
+        RSPI,
         SGPIO,
+        DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
+        DMINT20, DMINT21, DMINT22, DMINT23,
+        DDRECC,
+        TSIP,
+        PCIE_BRIDGE,
+        WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
+        GETHER0, GETHER1, GETHER2,
+        PBIA, PBIB, PBIC,
+        DMAE2, DMAE3,
+        SERMUX2, SERMUX3,
 
         /* interrupt groups */
 
@@ -221,19 +815,18 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(DVC, 0x4e0),
         INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
         INTC_VECT(IRQ10, 0x540),
-        INTC_VECT(WDT0, 0x560),
         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
         INTC_VECT(HUDI, 0x600),
         INTC_VECT(ARC4, 0x620),
-        INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
-        INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
-        INTC_VECT(DMAC0, 0x6c0),
+        INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
+        INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
+        INTC_VECT(DMAC0_5, 0x6c0),
         INTC_VECT(IRQ11, 0x6e0),
         INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
         INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
-        INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
-        INTC_VECT(DMAC1_6, 0x7c0), INTC_VECT(DMAC1_6, 0x7e0),
+        INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
+        INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
         INTC_VECT(USB0, 0x840),
         INTC_VECT(IRQ12, 0x880),
         INTC_VECT(JMC, 0x8a0),
@@ -242,7 +835,6 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(USB1, 0x920),
         INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
         INTC_VECT(TMR45, 0xa40),
-        INTC_VECT(WDT1, 0xa60),
         INTC_VECT(FRT, 0xa80),
         INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
         INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
@@ -250,14 +842,14 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
         INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
         INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
-        INTC_VECT(PECI0I, 0xc00), INTC_VECT(PECI1I, 0xc20),
-        INTC_VECT(PECI2I, 0xc40),
+        INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
+        INTC_VECT(PECI2, 0xc40),
         INTC_VECT(IRQ15, 0xc60),
         INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
         INTC_VECT(SPI0, 0xcc0),
         INTC_VECT(ADC1, 0xce0),
-        INTC_VECT(DMAC1_8, 0xd00), INTC_VECT(DMAC1_8, 0xd20),
-        INTC_VECT(DMAC1_8, 0xd40), INTC_VECT(DMAC1_8, 0xd60),
+        INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
+        INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
@@ -278,17 +870,47 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
         INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
         INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
-        INTC_VECT(IIC6_2, 0x1920), INTC_VECT(IIC6_3, 0x1980),
+        INTC_VECT(IIC6_2, 0x1920),
+        INTC_VECT(ONFICTL, 0x1960),
+        INTC_VECT(IIC6_3, 0x1980),
         INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
         INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
         INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
         INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
         INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
         INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
-        INTC_VECT(PCIINTA, 0x1ce0),
-        INTC_VECT(PCIE, 0x1e00),
-        INTC_VECT(SGPIO, 0x1f80),
-        INTC_VECT(SGPIO, 0x1fa0),
+        INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
+        INTC_VECT(ECCU, 0x1cc0),
+        INTC_VECT(PCIC, 0x1ce0),
+        INTC_VECT(G200, 0x1d00),
+        INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
+        INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
+        INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
+        INTC_VECT(PECI5, 0x1f00),
+        INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
+        INTC_VECT(SGPIO, 0x1fc0),
+        INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
+        INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
+        INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
+        INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
+        INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
+        INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
+        INTC_VECT(DDRECC, 0x2620),
+        INTC_VECT(TSIP, 0x2640),
+        INTC_VECT(PCIE_BRIDGE, 0x27c0),
+        INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
+        INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
+        INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
+        INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
+        INTC_VECT(WDT8B, 0x2900),
+        INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
+        INTC_VECT(GETHER2, 0x29a0),
+        INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
+        INTC_VECT(PBIC, 0x2a40),
+        INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
+        INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
+        INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
+        INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
 };
 
 static struct intc_group groups[] __initdata = {
@@ -312,31 +934,45 @@ static struct intc_mask_reg mask_registers[] __initdata = {
 
         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
           { 0, 0, 0, 0, 0, 0, 0, 0,
-            0, DMAC1_8, 0, PECI0I, LPC, FRT, WDT1, TMR45,
-            TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0,
-            HUDI, 0, WDT0, SCIF3, SCIF2, SDHI, TMU345, TMU012
+            0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
+            TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
+            HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
              } },
 
         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
           { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
             IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
-            ADC1, 0, DMAC1_6, ADC0, SPI0, SIM, PECI2I, PECI1I,
+            ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
             ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
              } },
 
         { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
-          { IIC4_1, IIC4_2, IIC5_0, 0, 0, 0, SGPIO, 0,
-            0, 0, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
+          { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
+            0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
             IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
-            IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, PCIE, IIC2_2
+            IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
              } },
 
-        { 0xffd100d0, 0xff1400d4, 32, /* INT2MSKR3 / INT2MSKCR4 */
-          { 0, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, 0, 0,
+        { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
+          { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
             IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
-            PCIINTA, 0, IIC4_0, 0, 0, 0, 0, IIC9_3,
+            PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
             IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
              } },
+
+        { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
+          { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
+            0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
+            PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
+            DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
+             } },
+
+        { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
+          { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
+            DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
+            0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
+            DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
+             } },
 };
 
 #define INTPRI          0xffd00010
@@ -372,6 +1008,22 @@ static struct intc_mask_reg mask_registers[] __initdata = {
 #define INT2PRI29       0xffd100b4
 #define INT2PRI30       0xffd100b8
 #define INT2PRI31       0xffd100bc
+#define INT2PRI32       0xffd20000
+#define INT2PRI33       0xffd20004
+#define INT2PRI34       0xffd20008
+#define INT2PRI35       0xffd2000c
+#define INT2PRI36       0xffd20010
+#define INT2PRI37       0xffd20014
+#define INT2PRI38       0xffd20018
+#define INT2PRI39       0xffd2001c
+#define INT2PRI40       0xffd200a0
+#define INT2PRI41       0xffd200a4
+#define INT2PRI42       0xffd200a8
+#define INT2PRI43       0xffd200ac
+#define INT2PRI44       0xffd200b0
+#define INT2PRI45       0xffd200b4
+#define INT2PRI46       0xffd200b8
+#define INT2PRI47       0xffd200bc
 
 static struct intc_prio_reg prio_registers[] __initdata = {
         { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
@@ -379,49 +1031,71 @@ static struct intc_prio_reg prio_registers[] __initdata = {
 
         { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
         { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
-        { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, WDT0, IRQ8 } },
-        { INT2PRI3, 0, 32, 8, { HUDI, DMAC0, ADC0, IRQ9 } },
+        { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
+        { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
         { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
-        { INT2PRI5, 0, 32, 8, { TMR45, WDT1, FRT, LPC } },
-        { INT2PRI6, 0, 32, 8, { PECI0I, ETHERC, DMAC1_8, 0 } },
+        { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
+        { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
         { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
         { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
         { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
-        { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2I, PECI1I } },
-        { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC1_6, IRQ14 } },
+        { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
+        { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
         { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
         { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
 
         { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
-        { INT2PRI17, 0, 32, 8, { PCIE, 0, 0, IIC1_0 } },
+        { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
         { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
         { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
         { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
         { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
-        { INT2PRI22, 0, 32, 8, { IIC9_2, 0, 0, 0 } },
-        { INT2PRI23, 0, 32, 8, { 0, SGPIO, IIC3_2, IIC5_1 } },
-        { INT2PRI24, 0, 32, 8, { 0, 0, 0, IIC1_1 } },
+        { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
+        { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
+        { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
         { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
-        { INT2PRI26, 0, 32, 8, { 0, 0, 0, IIC9_3 } },
-        { INT2PRI27, 0, 32, 8, { PCIINTA, IIC6_0, IIC4_0, IIC6_1 } },
-        { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, 0, IIC6_2 } },
+        { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
+        { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
+        { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
         { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
-        { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, 0 } },
+        { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
         { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
+        { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
+        { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
+        { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
+        { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
+        { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
+        { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
+        { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
+        { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
+        { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
+        { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
+        { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
+        { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
+        { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
+        { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
+        { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
+        { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
+};
+
+static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
+        { 0xffd100f8, 32, 2, /* ICR2 */   { IRQ15, IRQ14, IRQ13, IRQ12,
+                                            IRQ11, IRQ10, IRQ9, IRQ8 } },
 };
 
 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
-                         mask_registers, prio_registers, NULL);
+                         mask_registers, prio_registers,
+                         sense_registers_irq8to15);
 
 /* Support for external interrupt pins in IRQ mode */
 static struct intc_vect vectors_irq0123[] __initdata = {
-        INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
-        INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
+        INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
+        INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
 };
 
 static struct intc_vect vectors_irq4567[] __initdata = {
-        INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
-        INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
+        INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
+        INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
 };
 
 static struct intc_sense_reg sense_registers[] __initdata = {
@@ -455,14 +1129,14 @@ static struct intc_vect vectors_irl0123[] __initdata = {
 };
 
 static struct intc_vect vectors_irl4567[] __initdata = {
-        INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
-        INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
-        INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
-        INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
-        INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
-        INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
-        INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
-        INTC_VECT(IRL4_HHHL, 0xcc0),
+        INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220),
+        INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260),
+        INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0),
+        INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0),
+        INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320),
+        INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360),
+        INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0),
+        INTC_VECT(IRL4_HHHL, 0x3c0),
 };
 
 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 5b5f6b005fc5..593eca6509b5 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -19,6 +19,8 @@
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xffe00000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 40, 40, 40, 40 },
 };
@@ -34,6 +36,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xffe08000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 76, 76, 76, 76 },
 };
@@ -49,6 +53,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xffe10000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 104, 104, 104, 104 },
 };
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 7270d7fd6761..2c6aa22cf5f6 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -17,6 +17,8 @@
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xff923000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 61, 61, 61, 61 },
 };
@@ -32,6 +34,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xff924000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 62, 62, 62, 62 },
 };
@@ -47,6 +51,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xff925000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 63, 63, 63, 63 },
 };
@@ -62,6 +68,8 @@ static struct platform_device scif2_device = {
 static struct plat_sci_port scif3_platform_data = {
         .mapbase        = 0xff926000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 64, 64, 64, 64 },
 };
@@ -77,6 +85,8 @@ static struct platform_device scif3_device = {
 static struct plat_sci_port scif4_platform_data = {
         .mapbase        = 0xff927000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 65, 65, 65, 65 },
 };
@@ -92,6 +102,8 @@ static struct platform_device scif4_device = {
 static struct plat_sci_port scif5_platform_data = {
         .mapbase        = 0xff928000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 66, 66, 66, 66 },
 };
@@ -107,6 +119,8 @@ static struct platform_device scif5_device = {
 static struct plat_sci_port scif6_platform_data = {
         .mapbase        = 0xff929000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 67, 67, 67, 67 },
 };
@@ -122,6 +136,8 @@ static struct platform_device scif6_device = {
 static struct plat_sci_port scif7_platform_data = {
         .mapbase        = 0xff92a000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 68, 68, 68, 68 },
 };
@@ -137,6 +153,8 @@ static struct platform_device scif7_device = {
 static struct plat_sci_port scif8_platform_data = {
         .mapbase        = 0xff92b000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 69, 69, 69, 69 },
 };
@@ -152,6 +170,8 @@ static struct platform_device scif8_device = {
 static struct plat_sci_port scif9_platform_data = {
         .mapbase        = 0xff92c000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 70, 70, 70, 70 },
 };
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 0f414864f76b..08add7fa6849 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -20,6 +20,8 @@
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xffe00000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
         .irqs           = { 40, 40, 40, 40 },
 };
@@ -35,6 +37,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xffe10000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
         .irqs           = { 76, 76, 76, 76 },
 };
@@ -379,6 +383,7 @@ static int __init sh7780_devices_setup(void)
                                     ARRAY_SIZE(sh7780_devices));
 }
 arch_initcall(sh7780_devices_setup);
+
 static struct platform_device *sh7780_early_devices[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -392,6 +397,13 @@ static struct platform_device *sh7780_early_devices[] __initdata = {
 
 void __init plat_early_device_setup(void)
 {
+        if (mach_is_sh2007()) {
+                scif0_platform_data.scscr &= ~SCSCR_CKE1;
+                scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
+                scif1_platform_data.scscr &= ~SCSCR_CKE1;
+                scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
+        }
+
         early_platform_add_devices(sh7780_early_devices,
                                    ARRAY_SIZE(sh7780_early_devices));
 }
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index c9a572bc6dc8..18d8fc136fb2 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -23,6 +23,8 @@
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xffea0000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
         .irqs           = { 40, 40, 40, 40 },
 };
@@ -38,6 +40,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xffeb0000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
         .irqs           = { 44, 44, 44, 44 },
 };
@@ -53,6 +57,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xffec0000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
         .irqs           = { 60, 60, 60, 60 },
 };
@@ -68,6 +74,8 @@ static struct platform_device scif2_device = {
 static struct plat_sci_port scif3_platform_data = {
         .mapbase        = 0xffed0000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
         .irqs           = { 61, 61, 61, 61 },
 };
@@ -83,6 +91,8 @@ static struct platform_device scif3_device = {
 static struct plat_sci_port scif4_platform_data = {
         .mapbase        = 0xffee0000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
         .irqs           = { 62, 62, 62, 62 },
 };
@@ -98,6 +108,8 @@ static struct platform_device scif4_device = {
 static struct plat_sci_port scif5_platform_data = {
         .mapbase        = 0xffef0000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
         .irqs           = { 63, 63, 63, 63 },
 };
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 8797723231ea..beba32beb6d9 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -29,6 +29,8 @@
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xffea0000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
         .irqs           = { 40, 41, 43, 42 },
 };
@@ -47,6 +49,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xffeb0000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
         .irqs           = { 44, 44, 44, 44 },
 };
@@ -62,6 +66,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xffec0000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
         .irqs           = { 50, 50, 50, 50 },
 };
@@ -77,6 +83,8 @@ static struct platform_device scif2_device = {
 static struct plat_sci_port scif3_platform_data = {
         .mapbase        = 0xffed0000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
         .irqs           = { 51, 51, 51, 51 },
 };
@@ -92,6 +100,8 @@ static struct platform_device scif3_device = {
 static struct plat_sci_port scif4_platform_data = {
         .mapbase        = 0xffee0000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
         .irqs           = { 52, 52, 52, 52 },
 };
@@ -107,6 +117,8 @@ static struct platform_device scif4_device = {
 static struct plat_sci_port scif5_platform_data = {
         .mapbase        = 0xffef0000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
+        .scbrr_algo_id  = SCBRR_ALGO_1,
         .type           = PORT_SCIF,
         .irqs           = { 53, 53, 53, 53 },
 };
@@ -522,10 +534,37 @@ static struct platform_device dma0_device = {
         },
 };
 
+#define USB_EHCI_START 0xffe70000
+#define USB_OHCI_START 0xffe70400
+
+static struct resource usb_ehci_resources[] = {
+        [0] = {
+                .start  = USB_EHCI_START,
+                .end    = USB_EHCI_START + 0x3ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 77,
+                .end    = 77,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device usb_ehci_device = {
+        .name           = "sh_ehci",
+        .id             = -1,
+        .dev = {
+                .dma_mask               = &usb_ehci_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(usb_ehci_resources),
+        .resource       = usb_ehci_resources,
+};
+
 static struct resource usb_ohci_resources[] = {
         [0] = {
-                .start  = 0xffe70400,
-                .end    = 0xffe704ff,
+                .start  = USB_OHCI_START,
+                .end    = USB_OHCI_START + 0x3ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -535,12 +574,11 @@ static struct resource usb_ohci_resources[] = {
         },
 };
 
-static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
 static struct platform_device usb_ohci_device = {
         .name           = "sh_ohci",
         .id             = -1,
         .dev = {
-                .dma_mask               = &usb_ohci_dma_mask,
+                .dma_mask               = &usb_ohci_device.dev.coherent_dma_mask,
                 .coherent_dma_mask      = DMA_BIT_MASK(32),
         },
         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
@@ -570,6 +608,7 @@ static struct platform_device *sh7786_early_devices[] __initdata = {
 
 static struct platform_device *sh7786_devices[] __initdata = {
         &dma0_device,
+        &usb_ehci_device,
         &usb_ohci_device,
 };
 
@@ -609,7 +648,7 @@ static void __init sh7786_usb_setup(void)
          * The following settings are necessary
          * for using the USB modules.
          *
-         * see "USB Inital Settings" for detail
+         * see "USB Initial Settings" for detail
          */
         __raw_writel(USBINITVAL1, USBINITREG1);
         __raw_writel(USBINITVAL2, USBINITREG2);
@@ -629,33 +668,10 @@ static void __init sh7786_usb_setup(void)
         }
 }
 
-static int __init sh7786_devices_setup(void)
-{
-        int ret;
-
-        sh7786_usb_setup();
-
-        ret = platform_add_devices(sh7786_early_devices,
-                                   ARRAY_SIZE(sh7786_early_devices));
-        if (unlikely(ret != 0))
-                return ret;
-
-        return platform_add_devices(sh7786_devices,
-                                    ARRAY_SIZE(sh7786_devices));
-}
-arch_initcall(sh7786_devices_setup);
-
-void __init plat_early_device_setup(void)
-{
-        early_platform_add_devices(sh7786_early_devices,
-                                   ARRAY_SIZE(sh7786_early_devices));
-}
-
 enum {
         UNUSED = 0,
 
         /* interrupt sources */
-
         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
@@ -693,9 +709,12 @@ enum {
         Thermal,
         INTICI0, INTICI1, INTICI2, INTICI3,
         INTICI4, INTICI5, INTICI6, INTICI7,
+
+        /* Muxed sub-events */
+        TXI1, BRI1, RXI1, ERI1,
 };
 
-static struct intc_vect vectors[] __initdata = {
+static struct intc_vect sh7786_vectors[] __initdata = {
         INTC_VECT(WDT, 0x3e0),
         INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
         INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
@@ -756,14 +775,12 @@ static struct intc_vect vectors[] __initdata = {
 
 #define INTDISTCR0      0xfe4100b0
 #define INTDISTCR1      0xfe4100b4
-#define INTACK          0xfe4100b8
-#define INTACKCLR       0xfe4100bc
 #define INT2DISTCR0     0xfe410900
 #define INT2DISTCR1     0xfe410904
 #define INT2DISTCR2     0xfe410908
 #define INT2DISTCR3     0xfe41090c
 
-static struct intc_mask_reg mask_registers[] __initdata = {
+static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
         { CnINTMSK0, CnINTMSKCLR0, 32,
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
             INTC_SMP_BALANCING(INTDISTCR0) },
@@ -807,7 +824,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
             0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
 };
 
-static struct intc_prio_reg prio_registers[] __initdata = {
+static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
         { 0xfe410010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
         { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
@@ -851,11 +868,27 @@ static struct intc_prio_reg prio_registers[] __initdata = {
             INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
 };
 
-static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
-                         mask_registers, prio_registers, NULL);
+static struct intc_subgroup sh7786_subgroups[] __initdata = {
+        { 0xfe410c20, 32, SCIF1,
+          { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+            0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
+};
+
+static struct intc_desc sh7786_intc_desc __initdata = {
+        .name           = "sh7786",
+        .hw             = {
+                .vectors        = sh7786_vectors,
+                .nr_vectors     = ARRAY_SIZE(sh7786_vectors),
+                .mask_regs      = sh7786_mask_registers,
+                .nr_mask_regs   = ARRAY_SIZE(sh7786_mask_registers),
+                .subgroups      = sh7786_subgroups,
+                .nr_subgroups   = ARRAY_SIZE(sh7786_subgroups),
+                .prio_regs      = sh7786_prio_registers,
+                .nr_prio_regs   = ARRAY_SIZE(sh7786_prio_registers),
+        },
+};
 
 /* Support for external interrupt pins in IRQ mode */
-
 static struct intc_vect vectors_irq0123[] __initdata = {
         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
@@ -866,23 +899,25 @@ static struct intc_vect vectors_irq4567[] __initdata = {
         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
 };
 
-static struct intc_sense_reg sense_registers[] __initdata = {
+static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
         { 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static struct intc_mask_reg ack_registers[] __initdata = {
+static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
         { 0xfe410024, 0, 32, /* INTREQ */
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
-                             vectors_irq0123, NULL, mask_registers,
-                             prio_registers, sense_registers, ack_registers);
+                             vectors_irq0123, NULL, sh7786_mask_registers,
+                             sh7786_prio_registers, sh7786_sense_registers,
+                             sh7786_ack_registers);
 
 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
-                             vectors_irq4567, NULL, mask_registers,
-                             prio_registers, sense_registers, ack_registers);
+                             vectors_irq4567, NULL, sh7786_mask_registers,
+                             sh7786_prio_registers, sh7786_sense_registers,
+                             sh7786_ack_registers);
 
 /* External interrupt pins in IRL mode */
 
@@ -909,10 +944,10 @@ static struct intc_vect vectors_irl4567[] __initdata = {
 };
 
 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
-                         NULL, mask_registers, NULL, NULL);
+                         NULL, sh7786_mask_registers, NULL, NULL);
 
 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
-                         NULL, mask_registers, NULL, NULL);
+                         NULL, sh7786_mask_registers, NULL, NULL);
 
 #define INTC_ICR0       0xfe410000
 #define INTC_INTMSK0    CnINTMSK0
@@ -920,19 +955,6 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
 #define INTC_INTMSK2    INTMSK2
 #define INTC_INTMSKCLR1 CnINTMSKCLR1
 #define INTC_INTMSKCLR2 INTMSKCLR2
-#define INTC_USERIMASK  0xfe411000
-
-#ifdef CONFIG_INTC_BALANCING
-unsigned int irq_lookup(unsigned int irq)
-{
-        return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
-}
-
-void irq_finish(unsigned int irq)
-{
-        __raw_writel(irq2evt(irq), INTACKCLR);
-}
-#endif
 
 void __init plat_irq_setup(void)
 {
@@ -946,8 +968,7 @@ void __init plat_irq_setup(void)
         /* select IRL mode for IRL3-0 + IRL7-4 */
         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
-        register_intc_controller(&intc_desc);
-        register_intc_userimask(INTC_USERIMASK);
+        register_intc_controller(&sh7786_intc_desc);
 }
 
 void __init plat_irq_setup_pins(int mode)
@@ -991,3 +1012,39 @@ void __init plat_irq_setup_pins(int mode)
 void __init plat_mem_setup(void)
 {
 }
+
+static int __init sh7786_devices_setup(void)
+{
+        int ret, irq;
+
+        sh7786_usb_setup();
+
+        /*
+         * De-mux SCIF1 IRQs if possible
+         */
+        irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
+        if (irq > 0) {
+                scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq;
+                scif1_platform_data.irqs[SCIx_ERI_IRQ] =
+                        intc_irq_lookup(sh7786_intc_desc.name, ERI1);
+                scif1_platform_data.irqs[SCIx_BRI_IRQ] =
+                        intc_irq_lookup(sh7786_intc_desc.name, BRI1);
+                scif1_platform_data.irqs[SCIx_RXI_IRQ] =
+                        intc_irq_lookup(sh7786_intc_desc.name, RXI1);
+        }
+
+        ret = platform_add_devices(sh7786_early_devices,
+                                   ARRAY_SIZE(sh7786_early_devices));
+        if (unlikely(ret != 0))
+                return ret;
+
+        return platform_add_devices(sh7786_devices,
+                                    ARRAY_SIZE(sh7786_devices));
+}
+arch_initcall(sh7786_devices_setup);
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7786_early_devices,
+                                   ARRAY_SIZE(sh7786_early_devices));
+}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 9158bc5ea38b..bb208806dc1a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -1,7 +1,7 @@
 /*
  * SH-X3 Prototype Setup
  *
- *  Copyright (C) 2007 - 2009  Paul Mundt
+ *  Copyright (C) 2007 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -12,7 +12,9 @@
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 #include <linux/sh_timer.h>
+#include <cpu/shx3.h>
 #include <asm/mmzone.h>
 
 /*
@@ -27,6 +29,8 @@
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = 0xffc30000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 40, 41, 43, 42 },
 };
@@ -42,6 +46,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
         .mapbase        = 0xffc40000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 44, 45, 47, 46 },
 };
@@ -57,6 +63,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
         .mapbase        = 0xffc60000,
         .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 52, 53, 55, 54 },
 };
@@ -354,6 +362,10 @@ static struct intc_group groups[] __initdata = {
                    DMAC1_DMINT9, DMAC1_DMINT10, DMAC1_DMINT11),
 };
 
+#define INT2DISTCR0     0xfe4108a0
+#define INT2DISTCR1     0xfe4108a4
+#define INT2DISTCR2     0xfe4108a8
+
 static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */
           { IRQ0, IRQ1, IRQ2, IRQ3 } },
@@ -363,20 +375,23 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { FE1, FE0, 0, ATAPI, VCORE0, VIN1, VIN0, IIC,
             DU, GPIO3, GPIO2, GPIO1, GPIO0, PAM, 0, 0,
             0, 0, 0, 0, 0, 0, 0, 0, /* HUDI bits ignored */
-            0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, } },
+            0, TMU5, TMU4, TMU3, TMU2, TMU1, TMU0, 0, },
+            INTC_SMP_BALANCING(INT2DISTCR0) },
         { 0xfe410830, 0xfe410860, 32, /* CnINT2MSK1 / CnINT2MSKCLR1 */
           { 0, 0, 0, 0, DTU3, DTU2, DTU1, DTU0, /* IRM bits ignored */
             PCII9, PCII8, PCII7, PCII6, PCII5, PCII4, PCII3, PCII2,
             PCII1, PCII0, DMAC1_DMAE, DMAC1_DMINT11,
             DMAC1_DMINT10, DMAC1_DMINT9, DMAC1_DMINT8, DMAC1_DMINT7,
             DMAC1_DMINT6, DMAC0_DMAE, DMAC0_DMINT5, DMAC0_DMINT4,
-            DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 } },
+            DMAC0_DMINT3, DMAC0_DMINT2, DMAC0_DMINT1, DMAC0_DMINT0 },
+            INTC_SMP_BALANCING(INT2DISTCR1) },
         { 0xfe410840, 0xfe410870, 32, /* CnINT2MSK2 / CnINT2MSKCLR2 */
           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
             SCIF3_TXI, SCIF3_BRI, SCIF3_RXI, SCIF3_ERI,
             SCIF2_TXI, SCIF2_BRI, SCIF2_RXI, SCIF2_ERI,
             SCIF1_TXI, SCIF1_BRI, SCIF1_RXI, SCIF1_ERI,
-            SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } },
+            SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI },
+            INTC_SMP_BALANCING(INT2DISTCR2) },
 };
 
 static struct intc_prio_reg prio_registers[] __initdata = {
@@ -433,11 +448,33 @@ static DECLARE_INTC_DESC(intc_desc_irl, "shx3-irl", vectors_irl, groups,
 
 void __init plat_irq_setup_pins(int mode)
 {
+        int ret = 0;
+
         switch (mode) {
         case IRQ_MODE_IRQ:
+                ret |= gpio_request(GPIO_FN_IRQ3, intc_desc_irq.name);
+                ret |= gpio_request(GPIO_FN_IRQ2, intc_desc_irq.name);
+                ret |= gpio_request(GPIO_FN_IRQ1, intc_desc_irq.name);
+                ret |= gpio_request(GPIO_FN_IRQ0, intc_desc_irq.name);
+
+                if (unlikely(ret)) {
+                        pr_err("Failed to set IRQ mode\n");
+                        return;
+                }
+
                 register_intc_controller(&intc_desc_irq);
                 break;
         case IRQ_MODE_IRL3210:
+                ret |= gpio_request(GPIO_FN_IRL3, intc_desc_irl.name);
+                ret |= gpio_request(GPIO_FN_IRL2, intc_desc_irl.name);
+                ret |= gpio_request(GPIO_FN_IRL1, intc_desc_irl.name);
+                ret |= gpio_request(GPIO_FN_IRL0, intc_desc_irl.name);
+
+                if (unlikely(ret)) {
+                        pr_err("Failed to set IRL mode\n");
+                        return;
+                }
+
                 register_intc_controller(&intc_desc_irl);
                 break;
         default:
@@ -447,6 +484,9 @@ void __init plat_irq_setup_pins(int mode)
 
 void __init plat_irq_setup(void)
 {
+        reserve_intc_vectors(vectors_irq, ARRAY_SIZE(vectors_irq));
+        reserve_intc_vectors(vectors_irl, ARRAY_SIZE(vectors_irl));
+
         register_intc_controller(&intc_desc);
 }
 
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index d910666142b1..18419f1de963 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -19,6 +19,8 @@
 static struct plat_sci_port scif0_platform_data = {
         .mapbase        = PHYS_PERIPHERAL_BLOCK + 0x01030000,
         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
+        .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
         .type           = PORT_SCIF,
         .irqs           = { 39, 40, 42, 0 },
 };
diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c
index 83972aa319c2..e4469e7233cb 100644
--- a/arch/sh/kernel/cpu/shmobile/cpuidle.c
+++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c
@@ -75,13 +75,12 @@ void sh_mobile_setup_cpuidle(void)
         i = CPUIDLE_DRIVER_STATE_START;
 
         state = &dev->states[i++];
-        snprintf(state->name, CPUIDLE_NAME_LEN, "C0");
+        snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
         strncpy(state->desc, "SuperH Sleep Mode", CPUIDLE_DESC_LEN);
         state->exit_latency = 1;
         state->target_residency = 1 * 2;
         state->power_usage = 3;
         state->flags = 0;
-        state->flags |= CPUIDLE_FLAG_SHALLOW;
         state->flags |= CPUIDLE_FLAG_TIME_VALID;
         state->enter = cpuidle_sleep_enter;
 
@@ -89,7 +88,7 @@ void sh_mobile_setup_cpuidle(void)
 
         if (sh_mobile_sleep_supported & SUSP_SH_SF) {
                 state = &dev->states[i++];
-                snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
+                snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
                 strncpy(state->desc, "SuperH Sleep Mode [SF]",
                         CPUIDLE_DESC_LEN);
                 state->exit_latency = 100;
@@ -102,7 +101,7 @@ void sh_mobile_setup_cpuidle(void)
 
         if (sh_mobile_sleep_supported & SUSP_SH_STANDBY) {
                 state = &dev->states[i++];
-                snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
+                snprintf(state->name, CPUIDLE_NAME_LEN, "C3");
                 strncpy(state->desc, "SuperH Mobile Standby Mode [SF]",
                         CPUIDLE_DESC_LEN);
                 state->exit_latency = 2300;
diff --git a/arch/sh/kernel/cpu/shmobile/pm.c b/arch/sh/kernel/cpu/shmobile/pm.c
index e55968712706..a6f95ae4aae7 100644
--- a/arch/sh/kernel/cpu/shmobile/pm.c
+++ b/arch/sh/kernel/cpu/shmobile/pm.c
@@ -141,7 +141,7 @@ static int sh_pm_enter(suspend_state_t state)
         return 0;
 }
 
-static struct platform_suspend_ops sh_pm_ops = {
+static const struct platform_suspend_ops sh_pm_ops = {
         .enter          = sh_pm_enter,
         .valid          = suspend_valid_only_mem,
 };
diff --git a/arch/sh/kernel/cpu/shmobile/pm_runtime.c b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
index 6dcb8166a64d..64c807c39208 100644
--- a/arch/sh/kernel/cpu/shmobile/pm_runtime.c
+++ b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
@@ -139,7 +139,7 @@ void platform_pm_runtime_suspend_idle(void)
         queue_work(pm_wq, &hwblk_work);
 }
 
-int platform_pm_runtime_suspend(struct device *dev)
+static int default_platform_runtime_suspend(struct device *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
         struct pdev_archdata *ad = &pdev->archdata;
@@ -147,7 +147,7 @@ int platform_pm_runtime_suspend(struct device *dev)
         int hwblk = ad->hwblk_id;
         int ret = 0;
 
-        dev_dbg(dev, "platform_pm_runtime_suspend() [%d]\n", hwblk);
+        dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
 
         /* ignore off-chip platform devices */
         if (!hwblk)
@@ -157,7 +157,7 @@ int platform_pm_runtime_suspend(struct device *dev)
         might_sleep();
 
         /* catch misconfigured drivers not starting with resume */
-        if (test_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags)) {
+        if (test_bit(PDEV_ARCHDATA_FLAG_INIT, &ad->flags)) {
                 ret = -EINVAL;
                 goto out;
         }
@@ -170,8 +170,8 @@ int platform_pm_runtime_suspend(struct device *dev)
 
         /* put device on idle list */
         spin_lock_irqsave(&hwblk_lock, flags);
-        list_add_tail(&pdev->archdata.entry, &hwblk_idle_list);
-        __set_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags);
+        list_add_tail(&ad->entry, &hwblk_idle_list);
+        __set_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags);
         spin_unlock_irqrestore(&hwblk_lock, flags);
 
         /* increase idle count */
@@ -183,20 +183,20 @@ int platform_pm_runtime_suspend(struct device *dev)
         mutex_unlock(&ad->mutex);
 
 out:
-        dev_dbg(dev, "platform_pm_runtime_suspend() [%d] returns %d\n",
-                hwblk, ret);
+        dev_dbg(dev, "%s() [%d] returns %d\n",
+                 __func__, hwblk, ret);
 
         return ret;
 }
 
-int platform_pm_runtime_resume(struct device *dev)
+static int default_platform_runtime_resume(struct device *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
         struct pdev_archdata *ad = &pdev->archdata;
         int hwblk = ad->hwblk_id;
         int ret = 0;
 
-        dev_dbg(dev, "platform_pm_runtime_resume() [%d]\n", hwblk);
+        dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
 
         /* ignore off-chip platform devices */
         if (!hwblk)
@@ -228,19 +228,19 @@ int platform_pm_runtime_resume(struct device *dev)
          */
         mutex_unlock(&ad->mutex);
 out:
-        dev_dbg(dev, "platform_pm_runtime_resume() [%d] returns %d\n",
-                hwblk, ret);
+        dev_dbg(dev, "%s() [%d] returns %d\n",
+                __func__, hwblk, ret);
 
         return ret;
 }
 
-int platform_pm_runtime_idle(struct device *dev)
+static int default_platform_runtime_idle(struct device *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
         int hwblk = pdev->archdata.hwblk_id;
         int ret = 0;
 
-        dev_dbg(dev, "platform_pm_runtime_idle() [%d]\n", hwblk);
+        dev_dbg(dev, "%s() [%d]\n", __func__, hwblk);
 
         /* ignore off-chip platform devices */
         if (!hwblk)
@@ -252,10 +252,19 @@ int platform_pm_runtime_idle(struct device *dev)
         /* suspend synchronously to disable clocks immediately */
         ret = pm_runtime_suspend(dev);
 out:
-        dev_dbg(dev, "platform_pm_runtime_idle() [%d] done!\n", hwblk);
+        dev_dbg(dev, "%s() [%d] done!\n", __func__, hwblk);
         return ret;
 }
 
+static struct dev_power_domain default_power_domain = {
+        .ops = {
+                .runtime_suspend = default_platform_runtime_suspend,
+                .runtime_resume = default_platform_runtime_resume,
+                .runtime_idle = default_platform_runtime_idle,
+                USE_PLATFORM_PM_SLEEP_OPS
+        },
+};
+
 static int platform_bus_notify(struct notifier_block *nb,
                                unsigned long action, void *data)
 {
@@ -276,6 +285,7 @@ static int platform_bus_notify(struct notifier_block *nb,
                 hwblk_disable(hwblk_info, hwblk);
                 /* make sure driver re-inits itself once */
                 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
+                dev->pwr_domain = &default_power_domain;
                 break;
         /* TODO: add BUS_NOTIFY_BIND_DRIVER and increase idle count */
         case BUS_NOTIFY_BOUND_DRIVER:
@@ -289,6 +299,7 @@ static int platform_bus_notify(struct notifier_block *nb,
                 __set_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags);
                 break;
         case BUS_NOTIFY_DEL_DEVICE:
+                dev->pwr_domain = NULL;
                 break;
         }
         return 0;
diff --git a/arch/sh/kernel/crash_dump.c b/arch/sh/kernel/crash_dump.c
index 37c97d444576..569e7b171c01 100644
--- a/arch/sh/kernel/crash_dump.c
+++ b/arch/sh/kernel/crash_dump.c
@@ -9,28 +9,6 @@
 #include <linux/io.h>
 #include <asm/uaccess.h>
 
-/* Stores the physical address of elf header of crash image. */
-unsigned long long elfcorehdr_addr = ELFCORE_ADDR_MAX;
-
-/*
- * Note: elfcorehdr_addr is not just limited to vmcore. It is also used by
- * is_kdump_kernel() to determine if we are booting after a panic. Hence
- * ifdef it under CONFIG_CRASH_DUMP and not CONFIG_PROC_VMCORE.
- *
- * elfcorehdr= specifies the location of elf core header
- * stored by the crashed kernel.
- */
-static int __init parse_elfcorehdr(char *arg)
-{
-        if (!arg)
-                return -EINVAL;
-
-        elfcorehdr_addr = memparse(arg, &arg);
-
-        return 0;
-}
-early_param("elfcorehdr", parse_elfcorehdr);
-
 /**
  * copy_oldmem_page - copy one page from "oldmem"
  * @pfn: page frame number to be copied
diff --git a/arch/sh/kernel/dumpstack.c b/arch/sh/kernel/dumpstack.c
index 6f5ad1513409..694158b9a50f 100644
--- a/arch/sh/kernel/dumpstack.c
+++ b/arch/sh/kernel/dumpstack.c
@@ -69,19 +69,6 @@ stack_reader_dump(struct task_struct *task, struct pt_regs *regs,
         }
 }
 
-static void
-print_trace_warning_symbol(void *data, char *msg, unsigned long symbol)
-{
-        printk(data);
-        print_symbol(msg, symbol);
-        printk("\n");
-}
-
-static void print_trace_warning(void *data, char *msg)
-{
-        printk("%s%s\n", (char *)data, msg);
-}
-
 static int print_trace_stack(void *data, char *name)
 {
         printk("%s <%s> ", (char *)data, name);
@@ -98,8 +85,6 @@ static void print_trace_address(void *data, unsigned long addr, int reliable)
 }
 
 static const struct stacktrace_ops print_trace_ops = {
-        .warning = print_trace_warning,
-        .warning_symbol = print_trace_warning_symbol,
         .stack = print_trace_stack,
         .address = print_trace_address,
 };
diff --git a/arch/sh/kernel/head_32.S b/arch/sh/kernel/head_32.S
index 6e35f012cc03..7db248936b60 100644
--- a/arch/sh/kernel/head_32.S
+++ b/arch/sh/kernel/head_32.S
@@ -330,7 +330,7 @@ ENTRY(_stext)
 #if defined(CONFIG_CPU_SH2)
 1:      .long   0x000000F0              ! IMASK=0xF
 #else
-1:      .long   0x400080F0              ! MD=1, RB=0, BL=0, FD=1, IMASK=0xF
+1:      .long   0x500080F0              ! MD=1, RB=0, BL=1, FD=1, IMASK=0xF
 #endif
 ENTRY(stack_start)
 2:      .long   init_thread_union+THREAD_SIZE
diff --git a/arch/sh/kernel/io_generic.c b/arch/sh/kernel/io_generic.c
deleted file mode 100644
index 447d78f666f9..000000000000
--- a/arch/sh/kernel/io_generic.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * arch/sh/kernel/io_generic.c
- *
- * Copyright (C) 2000  Niibe Yutaka
- * Copyright (C) 2005 - 2007 Paul Mundt
- *
- * Generic I/O routine. These can be used where a machine specific version
- * is not required.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/module.h>
-#include <linux/io.h>
-#include <asm/machvec.h>
-
-#ifdef CONFIG_CPU_SH3
-/* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a
- * workaround. */
-/* I'm not sure SH7709 has this kind of bug */
-#define dummy_read()    __raw_readb(0xba000000)
-#else
-#define dummy_read()
-#endif
-
-unsigned long generic_io_base = 0;
-
-u8 generic_inb(unsigned long port)
-{
-        return __raw_readb(__ioport_map(port, 1));
-}
-
-u16 generic_inw(unsigned long port)
-{
-        return __raw_readw(__ioport_map(port, 2));
-}
-
-u32 generic_inl(unsigned long port)
-{
-        return __raw_readl(__ioport_map(port, 4));
-}
-
-u8 generic_inb_p(unsigned long port)
-{
-        unsigned long v = generic_inb(port);
-
-        ctrl_delay();
-        return v;
-}
-
-u16 generic_inw_p(unsigned long port)
-{
-        unsigned long v = generic_inw(port);
-
-        ctrl_delay();
-        return v;
-}
-
-u32 generic_inl_p(unsigned long port)
-{
-        unsigned long v = generic_inl(port);
-
-        ctrl_delay();
-        return v;
-}
-
-/*
- * insb/w/l all read a series of bytes/words/longs from a fixed port
- * address. However as the port address doesn't change we only need to
- * convert the port address to real address once.
- */
-
-void generic_insb(unsigned long port, void *dst, unsigned long count)
-{
-        __raw_readsb(__ioport_map(port, 1), dst, count);
-        dummy_read();
-}
-
-void generic_insw(unsigned long port, void *dst, unsigned long count)
-{
-        __raw_readsw(__ioport_map(port, 2), dst, count);
-        dummy_read();
-}
-
-void generic_insl(unsigned long port, void *dst, unsigned long count)
-{
-        __raw_readsl(__ioport_map(port, 4), dst, count);
-        dummy_read();
-}
-
-void generic_outb(u8 b, unsigned long port)
-{
-        __raw_writeb(b, __ioport_map(port, 1));
-}
-
-void generic_outw(u16 b, unsigned long port)
-{
-        __raw_writew(b, __ioport_map(port, 2));
-}
-
-void generic_outl(u32 b, unsigned long port)
-{
-        __raw_writel(b, __ioport_map(port, 4));
-}
-
-void generic_outb_p(u8 b, unsigned long port)
-{
-        generic_outb(b, port);
-        ctrl_delay();
-}
-
-void generic_outw_p(u16 b, unsigned long port)
-{
-        generic_outw(b, port);
-        ctrl_delay();
-}
-
-void generic_outl_p(u32 b, unsigned long port)
-{
-        generic_outl(b, port);
-        ctrl_delay();
-}
-
-/*
- * outsb/w/l all write a series of bytes/words/longs to a fixed port
- * address. However as the port address doesn't change we only need to
- * convert the port address to real address once.
- */
-void generic_outsb(unsigned long port, const void *src, unsigned long count)
-{
-        __raw_writesb(__ioport_map(port, 1), src, count);
-        dummy_read();
-}
-
-void generic_outsw(unsigned long port, const void *src, unsigned long count)
-{
-        __raw_writesw(__ioport_map(port, 2), src, count);
-        dummy_read();
-}
-
-void generic_outsl(unsigned long port, const void *src, unsigned long count)
-{
-        __raw_writesl(__ioport_map(port, 4), src, count);
-        dummy_read();
-}
-
-void __iomem *generic_ioport_map(unsigned long addr, unsigned int size)
-{
-#ifdef P1SEG
-        if (PXSEG(addr) >= P1SEG)
-                return (void __iomem *)addr;
-#endif
-
-        return (void __iomem *)(addr + generic_io_base);
-}
-
-void generic_ioport_unmap(void __iomem *addr)
-{
-}
-
-#ifndef CONFIG_GENERIC_IOMAP
-void __iomem *ioport_map(unsigned long port, unsigned int nr)
-{
-        void __iomem *ret;
-
-        ret = __ioport_map_trapped(port, nr);
-        if (ret)
-                return ret;
-
-        return __ioport_map(port, nr);
-}
-EXPORT_SYMBOL(ioport_map);
-
-void ioport_unmap(void __iomem *addr)
-{
-        sh_mv.mv_ioport_unmap(addr);
-}
-EXPORT_SYMBOL(ioport_unmap);
-#endif /* CONFIG_GENERIC_IOMAP */
diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c
index 2947d2bd1291..32c385ef1011 100644
--- a/arch/sh/kernel/io_trapped.c
+++ b/arch/sh/kernel/io_trapped.c
@@ -291,7 +291,7 @@ int handle_trapped_io(struct pt_regs *regs, unsigned long address)
         }
 
         tmp = handle_unaligned_access(instruction, regs,
-                                      &trapped_io_access, 1);
+                                      &trapped_io_access, 1, address);
         set_fs(oldfs);
         return tmp == 0;
 }
diff --git a/arch/sh/kernel/iomap.c b/arch/sh/kernel/iomap.c
new file mode 100644
index 000000000000..2e8e8b9b9cef
--- /dev/null
+++ b/arch/sh/kernel/iomap.c
@@ -0,0 +1,165 @@
+/*
+ * arch/sh/kernel/iomap.c
+ *
+ * Copyright (C) 2000  Niibe Yutaka
+ * Copyright (C) 2005 - 2007 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/module.h>
+#include <linux/io.h>
+
+unsigned int ioread8(void __iomem *addr)
+{
+        return readb(addr);
+}
+EXPORT_SYMBOL(ioread8);
+
+unsigned int ioread16(void __iomem *addr)
+{
+        return readw(addr);
+}
+EXPORT_SYMBOL(ioread16);
+
+unsigned int ioread16be(void __iomem *addr)
+{
+        return be16_to_cpu(__raw_readw(addr));
+}
+EXPORT_SYMBOL(ioread16be);
+
+unsigned int ioread32(void __iomem *addr)
+{
+        return readl(addr);
+}
+EXPORT_SYMBOL(ioread32);
+
+unsigned int ioread32be(void __iomem *addr)
+{
+        return be32_to_cpu(__raw_readl(addr));
+}
+EXPORT_SYMBOL(ioread32be);
+
+void iowrite8(u8 val, void __iomem *addr)
+{
+        writeb(val, addr);
+}
+EXPORT_SYMBOL(iowrite8);
+
+void iowrite16(u16 val, void __iomem *addr)
+{
+        writew(val, addr);
+}
+EXPORT_SYMBOL(iowrite16);
+
+void iowrite16be(u16 val, void __iomem *addr)
+{
+        __raw_writew(cpu_to_be16(val), addr);
+}
+EXPORT_SYMBOL(iowrite16be);
+
+void iowrite32(u32 val, void __iomem *addr)
+{
+        writel(val, addr);
+}
+EXPORT_SYMBOL(iowrite32);
+
+void iowrite32be(u32 val, void __iomem *addr)
+{
+        __raw_writel(cpu_to_be32(val), addr);
+}
+EXPORT_SYMBOL(iowrite32be);
+
+/*
+ * These are the "repeat MMIO read/write" functions.
+ * Note the "__raw" accesses, since we don't want to
+ * convert to CPU byte order. We write in "IO byte
+ * order" (we also don't have IO barriers).
+ */
+static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
+{
+        while (--count >= 0) {
+                u8 data = __raw_readb(addr);
+                *dst = data;
+                dst++;
+        }
+}
+
+static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
+{
+        while (--count >= 0) {
+                u16 data = __raw_readw(addr);
+                *dst = data;
+                dst++;
+        }
+}
+
+static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
+{
+        while (--count >= 0) {
+                u32 data = __raw_readl(addr);
+                *dst = data;
+                dst++;
+        }
+}
+
+static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
+{
+        while (--count >= 0) {
+                __raw_writeb(*src, addr);
+                src++;
+        }
+}
+
+static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
+{
+        while (--count >= 0) {
+                __raw_writew(*src, addr);
+                src++;
+        }
+}
+
+static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
+{
+        while (--count >= 0) {
+                __raw_writel(*src, addr);
+                src++;
+        }
+}
+
+void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+        mmio_insb(addr, dst, count);
+}
+EXPORT_SYMBOL(ioread8_rep);
+
+void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+        mmio_insw(addr, dst, count);
+}
+EXPORT_SYMBOL(ioread16_rep);
+
+void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+        mmio_insl(addr, dst, count);
+}
+EXPORT_SYMBOL(ioread32_rep);
+
+void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+        mmio_outsb(addr, src, count);
+}
+EXPORT_SYMBOL(iowrite8_rep);
+
+void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+        mmio_outsw(addr, src, count);
+}
+EXPORT_SYMBOL(iowrite16_rep);
+
+void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+        mmio_outsl(addr, src, count);
+}
+EXPORT_SYMBOL(iowrite32_rep);
diff --git a/arch/sh/kernel/ioport.c b/arch/sh/kernel/ioport.c
new file mode 100644
index 000000000000..e3ad6103e7c1
--- /dev/null
+++ b/arch/sh/kernel/ioport.c
@@ -0,0 +1,43 @@
+/*
+ * arch/sh/kernel/ioport.c
+ *
+ * Copyright (C) 2000  Niibe Yutaka
+ * Copyright (C) 2005 - 2007 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/module.h>
+#include <linux/io.h>
+
+const unsigned long sh_io_port_base __read_mostly = -1;
+EXPORT_SYMBOL(sh_io_port_base);
+
+void __iomem *__ioport_map(unsigned long addr, unsigned int size)
+{
+        if (sh_mv.mv_ioport_map)
+                return sh_mv.mv_ioport_map(addr, size);
+
+        return (void __iomem *)(addr + sh_io_port_base);
+}
+EXPORT_SYMBOL(__ioport_map);
+
+void __iomem *ioport_map(unsigned long port, unsigned int nr)
+{
+        void __iomem *ret;
+
+        ret = __ioport_map_trapped(port, nr);
+        if (ret)
+                return ret;
+
+        return __ioport_map(port, nr);
+}
+EXPORT_SYMBOL(ioport_map);
+
+void ioport_unmap(void __iomem *addr)
+{
+        if (sh_mv.mv_ioport_unmap)
+                sh_mv.mv_ioport_unmap(addr);
+}
+EXPORT_SYMBOL(ioport_unmap);
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index 257de1f0692b..a3ee91971129 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -13,6 +13,7 @@
 #include <linux/seq_file.h>
 #include <linux/ftrace.h>
 #include <linux/delay.h>
+#include <linux/ratelimit.h>
 #include <asm/processor.h>
 #include <asm/machvec.h>
 #include <asm/uaccess.h>
@@ -34,9 +35,9 @@ void ack_bad_irq(unsigned int irq)
 
 #if defined(CONFIG_PROC_FS)
 /*
- * /proc/interrupts printing:
+ * /proc/interrupts printing for arch specific interrupts
  */
-static int show_other_interrupts(struct seq_file *p, int prec)
+int arch_show_interrupts(struct seq_file *p, int prec)
 {
         int j;
 
@@ -49,58 +50,6 @@ static int show_other_interrupts(struct seq_file *p, int prec)
 
         return 0;
 }
-
-int show_interrupts(struct seq_file *p, void *v)
-{
-        unsigned long flags, any_count = 0;
-        int i = *(loff_t *)v, j, prec;
-        struct irqaction *action;
-        struct irq_desc *desc;
-
-        if (i > nr_irqs)
-                return 0;
-
-        for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
-                j *= 10;
-
-        if (i == nr_irqs)
-                return show_other_interrupts(p, prec);
-
-        if (i == 0) {
-                seq_printf(p, "%*s", prec + 8, "");
-                for_each_online_cpu(j)
-                        seq_printf(p, "CPU%-8d", j);
-                seq_putc(p, '\n');
-        }
-
-        desc = irq_to_desc(i);
-        if (!desc)
-                return 0;
-
-        raw_spin_lock_irqsave(&desc->lock, flags);
-        for_each_online_cpu(j)
-                any_count |= kstat_irqs_cpu(i, j);
-        action = desc->action;
-        if (!action && !any_count)
-                goto out;
-
-        seq_printf(p, "%*d: ", prec, i);
-        for_each_online_cpu(j)
-                seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
-        seq_printf(p, " %14s", desc->chip->name);
-        seq_printf(p, "-%-8s", desc->name);
-
-        if (action) {
-                seq_printf(p, "  %s", action->name);
-                while ((action = action->next) != NULL)
-                        seq_printf(p, ", %s", action->name);
-        }
-
-        seq_putc(p, '\n');
-out:
-        raw_spin_unlock_irqrestore(&desc->lock, flags);
-        return 0;
-}
 #endif
 
 #ifdef CONFIG_IRQSTACKS
@@ -235,7 +184,7 @@ asmlinkage void do_softirq(void)
                 );
 
                 /*
-                 * Shouldnt happen, we returned above if in_interrupt():
+                 * Shouldn't happen, we returned above if in_interrupt():
                  */
                 WARN_ON_ONCE(softirq_count());
         }
@@ -273,16 +222,12 @@ void __init init_IRQ(void)
 {
         plat_irq_setup();
 
-        /*
-         * Pin any of the legacy IRQ vectors that haven't already been
-         * grabbed by the platform
-         */
-        reserve_irq_legacy();
-
         /* Perform the machine specific initialisation */
         if (sh_mv.mv_init_irq)
                 sh_mv.mv_init_irq();
 
+        intc_finalize();
+
         irq_ctx_init(smp_processor_id());
 }
 
@@ -290,18 +235,21 @@ void __init init_IRQ(void)
 int __init arch_probe_nr_irqs(void)
 {
         nr_irqs = sh_mv.mv_nr_irqs;
-        return 0;
+        return NR_IRQS_LEGACY;
 }
 #endif
 
 #ifdef CONFIG_HOTPLUG_CPU
-static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
+static void route_irq(struct irq_data *data, unsigned int irq, unsigned int cpu)
 {
+        struct irq_desc *desc = irq_to_desc(irq);
+        struct irq_chip *chip = irq_data_get_irq_chip(data);
+
         printk(KERN_INFO "IRQ%u: moving from cpu%u to cpu%u\n",
-               irq, desc->node, cpu);
+               irq, data->node, cpu);
 
         raw_spin_lock_irq(&desc->lock);
-        desc->chip->set_affinity(irq, cpumask_of(cpu));
+        chip->irq_set_affinity(data, cpumask_of(cpu), false);
         raw_spin_unlock_irq(&desc->lock);
 }
 
@@ -312,24 +260,24 @@ static void route_irq(struct irq_desc *desc, unsigned int irq, unsigned int cpu)
  */
 void migrate_irqs(void)
 {
-        struct irq_desc *desc;
         unsigned int irq, cpu = smp_processor_id();
 
-        for_each_irq_desc(irq, desc) {
-                if (desc->node == cpu) {
-                        unsigned int newcpu = cpumask_any_and(desc->affinity,
+        for_each_active_irq(irq) {
+                struct irq_data *data = irq_get_irq_data(irq);
+
+                if (data->node == cpu) {
+                        unsigned int newcpu = cpumask_any_and(data->affinity,
                                                               cpu_online_mask);
                         if (newcpu >= nr_cpu_ids) {
-                                if (printk_ratelimit())
-                                        printk(KERN_INFO "IRQ%u no longer affine to CPU%u\n",
-                                               irq, cpu);
+                                pr_info_ratelimited("IRQ%u no longer affine to CPU%u\n",
+                                                    irq, cpu);
 
-                                cpumask_setall(desc->affinity);
-                                newcpu = cpumask_any_and(desc->affinity,
+                                cpumask_setall(data->affinity);
+                                newcpu = cpumask_any_and(data->affinity,
                                                          cpu_online_mask);
                         }
 
-                        route_irq(desc, irq, newcpu);
+                        route_irq(data, irq, newcpu);
                 }
         }
 }
diff --git a/arch/sh/kernel/irq_32.c b/arch/sh/kernel/irq_32.c
index e33ab15831f9..e5a755be9129 100644
--- a/arch/sh/kernel/irq_32.c
+++ b/arch/sh/kernel/irq_32.c
@@ -10,11 +10,11 @@
 #include <linux/irqflags.h>
 #include <linux/module.h>
 
-void notrace raw_local_irq_restore(unsigned long flags)
+void notrace arch_local_irq_restore(unsigned long flags)
 {
         unsigned long __dummy0, __dummy1;
 
-        if (flags == RAW_IRQ_DISABLED) {
+        if (flags == ARCH_IRQ_DISABLED) {
                 __asm__ __volatile__ (
                         "stc    sr, %0\n\t"
                         "or     #0xf0, %0\n\t"
@@ -33,14 +33,14 @@ void notrace raw_local_irq_restore(unsigned long flags)
 #endif
                         "ldc    %0, sr\n\t"
                         : "=&r" (__dummy0), "=r" (__dummy1)
-                        : "1" (~RAW_IRQ_DISABLED)
+                        : "1" (~ARCH_IRQ_DISABLED)
                         : "memory"
                 );
         }
 }
-EXPORT_SYMBOL(raw_local_irq_restore);
+EXPORT_SYMBOL(arch_local_irq_restore);
 
-unsigned long notrace __raw_local_save_flags(void)
+unsigned long notrace arch_local_save_flags(void)
 {
         unsigned long flags;
 
@@ -54,4 +54,4 @@ unsigned long notrace __raw_local_save_flags(void)
 
         return flags;
 }
-EXPORT_SYMBOL(__raw_local_save_flags);
+EXPORT_SYMBOL(arch_local_save_flags);
diff --git a/arch/sh/kernel/irq_64.c b/arch/sh/kernel/irq_64.c
index 32365ba0e039..8fc05b997b6d 100644
--- a/arch/sh/kernel/irq_64.c
+++ b/arch/sh/kernel/irq_64.c
@@ -11,17 +11,17 @@
 #include <linux/module.h>
 #include <cpu/registers.h>
 
-void notrace raw_local_irq_restore(unsigned long flags)
+void notrace arch_local_irq_restore(unsigned long flags)
 {
         unsigned long long __dummy;
 
-        if (flags == RAW_IRQ_DISABLED) {
+        if (flags == ARCH_IRQ_DISABLED) {
                 __asm__ __volatile__ (
                         "getcon " __SR ", %0\n\t"
                         "or     %0, %1, %0\n\t"
                         "putcon %0, " __SR "\n\t"
                         : "=&r" (__dummy)
-                        : "r" (RAW_IRQ_DISABLED)
+                        : "r" (ARCH_IRQ_DISABLED)
                 );
         } else {
                 __asm__ __volatile__ (
@@ -29,13 +29,13 @@ void notrace raw_local_irq_restore(unsigned long flags)
                         "and    %0, %1, %0\n\t"
                         "putcon %0, " __SR "\n\t"
                         : "=&r" (__dummy)
-                        : "r" (~RAW_IRQ_DISABLED)
+                        : "r" (~ARCH_IRQ_DISABLED)
                 );
         }
 }
-EXPORT_SYMBOL(raw_local_irq_restore);
+EXPORT_SYMBOL(arch_local_irq_restore);
 
-unsigned long notrace __raw_local_save_flags(void)
+unsigned long notrace arch_local_save_flags(void)
 {
         unsigned long flags;
 
@@ -43,9 +43,9 @@ unsigned long notrace __raw_local_save_flags(void)
                 "getcon " __SR ", %0\n\t"
                 "and    %0, %1, %0"
                 : "=&r" (flags)
-                : "r" (RAW_IRQ_DISABLED)
+                : "r" (ARCH_IRQ_DISABLED)
         );
 
         return flags;
 }
-EXPORT_SYMBOL(__raw_local_save_flags);
+EXPORT_SYMBOL(arch_local_save_flags);
diff --git a/arch/sh/kernel/kdebugfs.c b/arch/sh/kernel/kdebugfs.c
new file mode 100644
index 000000000000..e11c30bb100c
--- /dev/null
+++ b/arch/sh/kernel/kdebugfs.c
@@ -0,0 +1,16 @@
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/debugfs.h>
+
+struct dentry *arch_debugfs_dir;
+EXPORT_SYMBOL(arch_debugfs_dir);
+
+static int __init arch_kdebugfs_init(void)
+{
+        arch_debugfs_dir = debugfs_create_dir("sh", NULL);
+        if (!arch_debugfs_dir)
+                return -ENOMEM;
+
+        return 0;
+}
+arch_initcall(arch_kdebugfs_init);
diff --git a/arch/sh/kernel/kprobes.c b/arch/sh/kernel/kprobes.c
index 4049d99f76e1..1208b09e95c3 100644
--- a/arch/sh/kernel/kprobes.c
+++ b/arch/sh/kernel/kprobes.c
@@ -20,9 +20,9 @@
 DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL;
 DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
 
-static struct kprobe saved_current_opcode;
-static struct kprobe saved_next_opcode;
-static struct kprobe saved_next_opcode2;
+static DEFINE_PER_CPU(struct kprobe, saved_current_opcode);
+static DEFINE_PER_CPU(struct kprobe, saved_next_opcode);
+static DEFINE_PER_CPU(struct kprobe, saved_next_opcode2);
 
 #define OPCODE_JMP(x)   (((x) & 0xF0FF) == 0x402b)
 #define OPCODE_JSR(x)   (((x) & 0xF0FF) == 0x400b)
@@ -102,16 +102,21 @@ int __kprobes kprobe_handle_illslot(unsigned long pc)
 
 void __kprobes arch_remove_kprobe(struct kprobe *p)
 {
-        if (saved_next_opcode.addr != 0x0) {
+        struct kprobe *saved = &__get_cpu_var(saved_next_opcode);
+
+        if (saved->addr) {
                 arch_disarm_kprobe(p);
-                arch_disarm_kprobe(&saved_next_opcode);
-                saved_next_opcode.addr = 0x0;
-                saved_next_opcode.opcode = 0x0;
-
-                if (saved_next_opcode2.addr != 0x0) {
-                        arch_disarm_kprobe(&saved_next_opcode2);
-                        saved_next_opcode2.addr = 0x0;
-                        saved_next_opcode2.opcode = 0x0;
+                arch_disarm_kprobe(saved);
+
+                saved->addr = NULL;
+                saved->opcode = 0;
+
+                saved = &__get_cpu_var(saved_next_opcode2);
+                if (saved->addr) {
+                        arch_disarm_kprobe(saved);
+
+                        saved->addr = NULL;
+                        saved->opcode = 0;
                 }
         }
 }
@@ -141,57 +146,59 @@ static void __kprobes set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
  */
 static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
 {
-        kprobe_opcode_t *addr = NULL;
-        saved_current_opcode.addr = (kprobe_opcode_t *) (regs->pc);
-        addr = saved_current_opcode.addr;
+        __get_cpu_var(saved_current_opcode).addr = (kprobe_opcode_t *)regs->pc;
 
         if (p != NULL) {
+                struct kprobe *op1, *op2;
+
                 arch_disarm_kprobe(p);
 
+                op1 = &__get_cpu_var(saved_next_opcode);
+                op2 = &__get_cpu_var(saved_next_opcode2);
+
                 if (OPCODE_JSR(p->opcode) || OPCODE_JMP(p->opcode)) {
                         unsigned int reg_nr = ((p->opcode >> 8) & 0x000F);
-                        saved_next_opcode.addr =
-                            (kprobe_opcode_t *) regs->regs[reg_nr];
+                        op1->addr = (kprobe_opcode_t *) regs->regs[reg_nr];
                 } else if (OPCODE_BRA(p->opcode) || OPCODE_BSR(p->opcode)) {
                         unsigned long disp = (p->opcode & 0x0FFF);
-                        saved_next_opcode.addr =
+                        op1->addr =
                             (kprobe_opcode_t *) (regs->pc + 4 + disp * 2);
 
                 } else if (OPCODE_BRAF(p->opcode) || OPCODE_BSRF(p->opcode)) {
                         unsigned int reg_nr = ((p->opcode >> 8) & 0x000F);
-                        saved_next_opcode.addr =
+                        op1->addr =
                             (kprobe_opcode_t *) (regs->pc + 4 +
                                                  regs->regs[reg_nr]);
 
                 } else if (OPCODE_RTS(p->opcode)) {
-                        saved_next_opcode.addr = (kprobe_opcode_t *) regs->pr;
+                        op1->addr = (kprobe_opcode_t *) regs->pr;
 
                 } else if (OPCODE_BF(p->opcode) || OPCODE_BT(p->opcode)) {
                         unsigned long disp = (p->opcode & 0x00FF);
                         /* case 1 */
-                        saved_next_opcode.addr = p->addr + 1;
+                        op1->addr = p->addr + 1;
                         /* case 2 */
-                        saved_next_opcode2.addr =
+                        op2->addr =
                             (kprobe_opcode_t *) (regs->pc + 4 + disp * 2);
-                        saved_next_opcode2.opcode = *(saved_next_opcode2.addr);
-                        arch_arm_kprobe(&saved_next_opcode2);
+                        op2->opcode = *(op2->addr);
+                        arch_arm_kprobe(op2);
 
                 } else if (OPCODE_BF_S(p->opcode) || OPCODE_BT_S(p->opcode)) {
                         unsigned long disp = (p->opcode & 0x00FF);
                         /* case 1 */
-                        saved_next_opcode.addr = p->addr + 2;
+                        op1->addr = p->addr + 2;
                         /* case 2 */
-                        saved_next_opcode2.addr =
+                        op2->addr =
                             (kprobe_opcode_t *) (regs->pc + 4 + disp * 2);
-                        saved_next_opcode2.opcode = *(saved_next_opcode2.addr);
-                        arch_arm_kprobe(&saved_next_opcode2);
+                        op2->opcode = *(op2->addr);
+                        arch_arm_kprobe(op2);
 
                 } else {
-                        saved_next_opcode.addr = p->addr + 1;
+                        op1->addr = p->addr + 1;
                 }
 
-                saved_next_opcode.opcode = *(saved_next_opcode.addr);
-                arch_arm_kprobe(&saved_next_opcode);
+                op1->opcode = *(op1->addr);
+                arch_arm_kprobe(op1);
         }
 }
 
@@ -376,21 +383,23 @@ static int __kprobes post_kprobe_handler(struct pt_regs *regs)
                 cur->post_handler(cur, regs, 0);
         }
 
-        if (saved_next_opcode.addr != 0x0) {
-                arch_disarm_kprobe(&saved_next_opcode);
-                saved_next_opcode.addr = 0x0;
-                saved_next_opcode.opcode = 0x0;
+        p = &__get_cpu_var(saved_next_opcode);
+        if (p->addr) {
+                arch_disarm_kprobe(p);
+                p->addr = NULL;
+                p->opcode = 0;
 
-                addr = saved_current_opcode.addr;
-                saved_current_opcode.addr = 0x0;
+                addr = __get_cpu_var(saved_current_opcode).addr;
+                __get_cpu_var(saved_current_opcode).addr = NULL;
 
                 p = get_kprobe(addr);
                 arch_arm_kprobe(p);
 
-                if (saved_next_opcode2.addr != 0x0) {
-                        arch_disarm_kprobe(&saved_next_opcode2);
-                        saved_next_opcode2.addr = 0x0;
-                        saved_next_opcode2.opcode = 0x0;
+                p = &__get_cpu_var(saved_next_opcode2);
+                if (p->addr) {
+                        arch_disarm_kprobe(p);
+                        p->addr = NULL;
+                        p->opcode = 0;
                 }
         }
 
@@ -572,14 +581,5 @@ static struct kprobe trampoline_p = {
 
 int __init arch_init_kprobes(void)
 {
-        saved_next_opcode.addr = 0x0;
-        saved_next_opcode.opcode = 0x0;
-
-        saved_current_opcode.addr = 0x0;
-        saved_current_opcode.opcode = 0x0;
-
-        saved_next_opcode2.addr = 0x0;
-        saved_next_opcode2.opcode = 0x0;
-
         return register_kprobe(&trampoline_p);
 }
diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c
index 9f9bb63616ad..3d722e49db08 100644
--- a/arch/sh/kernel/machvec.c
+++ b/arch/sh/kernel/machvec.c
@@ -118,28 +118,6 @@ void __init sh_mv_setup(void)
                 sh_mv.mv_##elem = generic_##elem; \
 } while (0)
 
-#ifdef CONFIG_HAS_IOPORT
-
-#ifdef P2SEG
-        __set_io_port_base(P2SEG);
-#else
-        __set_io_port_base(0);
-#endif
-
-        mv_set(inb);    mv_set(inw);    mv_set(inl);
-        mv_set(outb);   mv_set(outw);   mv_set(outl);
-
-        mv_set(inb_p);  mv_set(inw_p);  mv_set(inl_p);
-        mv_set(outb_p); mv_set(outw_p); mv_set(outl_p);
-
-        mv_set(insb);   mv_set(insw);   mv_set(insl);
-        mv_set(outsb);  mv_set(outsw);  mv_set(outsl);
-
-        mv_set(ioport_map);
-        mv_set(ioport_unmap);
-
-#endif
-
         mv_set(irq_demux);
         mv_set(mode_pins);
         mv_set(mem_init);
diff --git a/arch/sh/kernel/module.c b/arch/sh/kernel/module.c
index ae0be697a89e..19b1f8826aef 100644
--- a/arch/sh/kernel/module.c
+++ b/arch/sh/kernel/module.c
@@ -93,6 +93,8 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
 #endif
 
                 switch (ELF32_R_TYPE(rel[i].r_info)) {
+                case R_SH_NONE:
+                        break;
                 case R_SH_DIR32:
                         value = get_unaligned(location);
                         value += relocation;
diff --git a/arch/sh/kernel/perf_callchain.c b/arch/sh/kernel/perf_callchain.c
index a9dd3abde28e..cc80b614b5fa 100644
--- a/arch/sh/kernel/perf_callchain.c
+++ b/arch/sh/kernel/perf_callchain.c
@@ -14,21 +14,6 @@
 #include <asm/unwinder.h>
 #include <asm/ptrace.h>
 
-static inline void callchain_store(struct perf_callchain_entry *entry, u64 ip)
-{
-        if (entry->nr < PERF_MAX_STACK_DEPTH)
-                entry->ip[entry->nr++] = ip;
-}
-
-static void callchain_warning(void *data, char *msg)
-{
-}
-
-static void
-callchain_warning_symbol(void *data, char *msg, unsigned long symbol)
-{
-}
-
 static int callchain_stack(void *data, char *name)
 {
         return 0;
@@ -39,57 +24,18 @@ static void callchain_address(void *data, unsigned long addr, int reliable)
         struct perf_callchain_entry *entry = data;
 
         if (reliable)
-                callchain_store(entry, addr);
+                perf_callchain_store(entry, addr);
 }
 
 static const struct stacktrace_ops callchain_ops = {
-        .warning        = callchain_warning,
-        .warning_symbol = callchain_warning_symbol,
         .stack          = callchain_stack,
         .address        = callchain_address,
 };
 
-static void
-perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
+void
+perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
 {
-        callchain_store(entry, PERF_CONTEXT_KERNEL);
-        callchain_store(entry, regs->pc);
+        perf_callchain_store(entry, regs->pc);
 
         unwind_stack(NULL, regs, NULL, &callchain_ops, entry);
 }
-
-static void
-perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
-{
-        int is_user;
-
-        if (!regs)
-                return;
-
-        is_user = user_mode(regs);
-
-        if (is_user && current->state != TASK_RUNNING)
-                return;
-
-        /*
-         * Only the kernel side is implemented for now.
-         */
-        if (!is_user)
-                perf_callchain_kernel(regs, entry);
-}
-
-/*
- * No need for separate IRQ and NMI entries.
- */
-static DEFINE_PER_CPU(struct perf_callchain_entry, callchain);
-
-struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
-{
-        struct perf_callchain_entry *entry = &__get_cpu_var(callchain);
-
-        entry->nr = 0;
-
-        perf_do_callchain(regs, entry);
-
-        return entry;
-}
diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c
index 7a3dc3567258..2ee21a47b5af 100644
--- a/arch/sh/kernel/perf_event.c
+++ b/arch/sh/kernel/perf_event.c
@@ -59,6 +59,24 @@ static inline int sh_pmu_initialized(void)
         return !!sh_pmu;
 }
 
+const char *perf_pmu_name(void)
+{
+        if (!sh_pmu)
+                return NULL;
+
+        return sh_pmu->name;
+}
+EXPORT_SYMBOL_GPL(perf_pmu_name);
+
+int perf_num_counters(void)
+{
+        if (!sh_pmu)
+                return 0;
+
+        return sh_pmu->num_events;
+}
+EXPORT_SYMBOL_GPL(perf_num_counters);
+
 /*
  * Release the PMU if this is the last perf_event.
  */
@@ -206,50 +224,80 @@ again:
         local64_add(delta, &event->count);
 }
 
-static void sh_pmu_disable(struct perf_event *event)
+static void sh_pmu_stop(struct perf_event *event, int flags)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
         struct hw_perf_event *hwc = &event->hw;
         int idx = hwc->idx;
 
-        clear_bit(idx, cpuc->active_mask);
-        sh_pmu->disable(hwc, idx);
+        if (!(event->hw.state & PERF_HES_STOPPED)) {
+                sh_pmu->disable(hwc, idx);
+                cpuc->events[idx] = NULL;
+                event->hw.state |= PERF_HES_STOPPED;
+        }
+
+        if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
+                sh_perf_event_update(event, &event->hw, idx);
+                event->hw.state |= PERF_HES_UPTODATE;
+        }
+}
+
+static void sh_pmu_start(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+
+        if (WARN_ON_ONCE(idx == -1))
+                return;
+
+        if (flags & PERF_EF_RELOAD)
+                WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
 
-        barrier();
+        cpuc->events[idx] = event;
+        event->hw.state = 0;
+        sh_pmu->enable(hwc, idx);
+}
 
-        sh_perf_event_update(event, &event->hw, idx);
+static void sh_pmu_del(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 
-        cpuc->events[idx] = NULL;
-        clear_bit(idx, cpuc->used_mask);
+        sh_pmu_stop(event, PERF_EF_UPDATE);
+        __clear_bit(event->hw.idx, cpuc->used_mask);
 
         perf_event_update_userpage(event);
 }
 
-static int sh_pmu_enable(struct perf_event *event)
+static int sh_pmu_add(struct perf_event *event, int flags)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
         struct hw_perf_event *hwc = &event->hw;
         int idx = hwc->idx;
+        int ret = -EAGAIN;
+
+        perf_pmu_disable(event->pmu);
 
-        if (test_and_set_bit(idx, cpuc->used_mask)) {
+        if (__test_and_set_bit(idx, cpuc->used_mask)) {
                 idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events);
                 if (idx == sh_pmu->num_events)
-                        return -EAGAIN;
+                        goto out;
 
-                set_bit(idx, cpuc->used_mask);
+                __set_bit(idx, cpuc->used_mask);
                 hwc->idx = idx;
         }
 
         sh_pmu->disable(hwc, idx);
 
-        cpuc->events[idx] = event;
-        set_bit(idx, cpuc->active_mask);
-
-        sh_pmu->enable(hwc, idx);
+        event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+        if (flags & PERF_EF_START)
+                sh_pmu_start(event, PERF_EF_RELOAD);
 
         perf_event_update_userpage(event);
-
-        return 0;
+        ret = 0;
+out:
+        perf_pmu_enable(event->pmu);
+        return ret;
 }
 
 static void sh_pmu_read(struct perf_event *event)
@@ -257,24 +305,56 @@ static void sh_pmu_read(struct perf_event *event)
         sh_perf_event_update(event, &event->hw, event->hw.idx);
 }
 
-static const struct pmu pmu = {
-        .enable         = sh_pmu_enable,
-        .disable        = sh_pmu_disable,
-        .read           = sh_pmu_read,
-};
-
-const struct pmu *hw_perf_event_init(struct perf_event *event)
+static int sh_pmu_event_init(struct perf_event *event)
 {
-        int err = __hw_perf_event_init(event);
+        int err;
+
+        switch (event->attr.type) {
+        case PERF_TYPE_RAW:
+        case PERF_TYPE_HW_CACHE:
+        case PERF_TYPE_HARDWARE:
+                err = __hw_perf_event_init(event);
+                break;
+
+        default:
+                return -ENOENT;
+        }
+
         if (unlikely(err)) {
                 if (event->destroy)
                         event->destroy(event);
-                return ERR_PTR(err);
         }
 
-        return &pmu;
+        return err;
+}
+
+static void sh_pmu_enable(struct pmu *pmu)
+{
+        if (!sh_pmu_initialized())
+                return;
+
+        sh_pmu->enable_all();
+}
+
+static void sh_pmu_disable(struct pmu *pmu)
+{
+        if (!sh_pmu_initialized())
+                return;
+
+        sh_pmu->disable_all();
 }
 
+static struct pmu pmu = {
+        .pmu_enable     = sh_pmu_enable,
+        .pmu_disable    = sh_pmu_disable,
+        .event_init     = sh_pmu_event_init,
+        .add            = sh_pmu_add,
+        .del            = sh_pmu_del,
+        .start          = sh_pmu_start,
+        .stop           = sh_pmu_stop,
+        .read           = sh_pmu_read,
+};
+
 static void sh_pmu_setup(int cpu)
 {
         struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
@@ -299,32 +379,17 @@ sh_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
         return NOTIFY_OK;
 }
 
-void hw_perf_enable(void)
-{
-        if (!sh_pmu_initialized())
-                return;
-
-        sh_pmu->enable_all();
-}
-
-void hw_perf_disable(void)
-{
-        if (!sh_pmu_initialized())
-                return;
-
-        sh_pmu->disable_all();
-}
-
-int __cpuinit register_sh_pmu(struct sh_pmu *pmu)
+int __cpuinit register_sh_pmu(struct sh_pmu *_pmu)
 {
         if (sh_pmu)
                 return -EBUSY;
-        sh_pmu = pmu;
+        sh_pmu = _pmu;
 
-        pr_info("Performance Events: %s support registered\n", pmu->name);
+        pr_info("Performance Events: %s support registered\n", _pmu->name);
 
-        WARN_ON(pmu->num_events > MAX_HWEVENTS);
+        WARN_ON(_pmu->num_events > MAX_HWEVENTS);
 
+        perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
         perf_cpu_notifier(sh_pmu_notifier);
         return 0;
 }
diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c
index dcb126dc76fd..325f98b1736d 100644
--- a/arch/sh/kernel/process.c
+++ b/arch/sh/kernel/process.c
@@ -32,16 +32,16 @@ void free_thread_xstate(struct task_struct *tsk)
 #if THREAD_SHIFT < PAGE_SHIFT
 static struct kmem_cache *thread_info_cache;
 
-struct thread_info *alloc_thread_info(struct task_struct *tsk)
+struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
 {
         struct thread_info *ti;
-
-        ti = kmem_cache_alloc(thread_info_cache, GFP_KERNEL);
-        if (unlikely(ti == NULL))
-                return NULL;
 #ifdef CONFIG_DEBUG_STACK_USAGE
-        memset(ti, 0, THREAD_SIZE);
+        gfp_t mask = GFP_KERNEL | __GFP_ZERO;
+#else
+        gfp_t mask = GFP_KERNEL;
 #endif
+
+        ti = kmem_cache_alloc_node(thread_info_cache, mask, node);
         return ti;
 }
 
@@ -57,14 +57,16 @@ void thread_info_cache_init(void)
                                               THREAD_SIZE, SLAB_PANIC, NULL);
 }
 #else
-struct thread_info *alloc_thread_info(struct task_struct *tsk)
+struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
 {
 #ifdef CONFIG_DEBUG_STACK_USAGE
         gfp_t mask = GFP_KERNEL | __GFP_ZERO;
 #else
         gfp_t mask = GFP_KERNEL;
 #endif
-        return (struct thread_info *)__get_free_pages(mask, THREAD_SIZE_ORDER);
+        struct page *page = alloc_pages_node(node, mask, THREAD_SIZE_ORDER);
+
+        return page ? page_address(page) : NULL;
 }
 
 void free_thread_info(struct thread_info *ti)
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index 762a13984bbd..aaf6d59c2012 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -21,6 +21,7 @@
 #include <linux/fs.h>
 #include <linux/ftrace.h>
 #include <linux/hw_breakpoint.h>
+#include <linux/prefetch.h>
 #include <asm/uaccess.h>
 #include <asm/mmu_context.h>
 #include <asm/system.h>
@@ -101,8 +102,6 @@ EXPORT_SYMBOL(kernel_thread);
 void start_thread(struct pt_regs *regs, unsigned long new_pc,
                   unsigned long new_sp)
 {
-        set_fs(USER_DS);
-
         regs->pr = 0;
         regs->sr = SR_FD;
         regs->pc = new_pc;
diff --git a/arch/sh/kernel/ptrace.c b/arch/sh/kernel/ptrace.c
new file mode 100644
index 000000000000..0a05983633ca
--- /dev/null
+++ b/arch/sh/kernel/ptrace.c
@@ -0,0 +1,33 @@
+#include <linux/ptrace.h>
+
+/**
+ * regs_query_register_offset() - query register offset from its name
+ * @name:       the name of a register
+ *
+ * regs_query_register_offset() returns the offset of a register in struct
+ * pt_regs from its name. If the name is invalid, this returns -EINVAL;
+ */
+int regs_query_register_offset(const char *name)
+{
+        const struct pt_regs_offset *roff;
+        for (roff = regoffset_table; roff->name != NULL; roff++)
+                if (!strcmp(roff->name, name))
+                        return roff->offset;
+        return -EINVAL;
+}
+
+/**
+ * regs_query_register_name() - query register name from its offset
+ * @offset:     the offset of a register in struct pt_regs.
+ *
+ * regs_query_register_name() returns the name of a register from its
+ * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
+ */
+const char *regs_query_register_name(unsigned int offset)
+{
+        const struct pt_regs_offset *roff;
+        for (roff = regoffset_table; roff->name != NULL; roff++)
+                if (roff->offset == offset)
+                        return roff->name;
+        return NULL;
+}
diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c
index 6c4bbba2a675..3d7b209b2178 100644
--- a/arch/sh/kernel/ptrace_32.c
+++ b/arch/sh/kernel/ptrace_32.c
@@ -101,6 +101,8 @@ static int set_single_step(struct task_struct *tsk, unsigned long addr)
 
                 attr = bp->attr;
                 attr.bp_addr = addr;
+                /* reenable breakpoint */
+                attr.disabled = false;
                 err = modify_user_hw_breakpoint(bp, &attr);
                 if (unlikely(err))
                         return err;
@@ -115,7 +117,11 @@ void user_enable_single_step(struct task_struct *child)
 
         set_tsk_thread_flag(child, TIF_SINGLESTEP);
 
+        if (ptrace_get_breakpoints(child) < 0)
+                return;
+
         set_single_step(child, pc);
+        ptrace_put_breakpoints(child);
 }
 
 void user_disable_single_step(struct task_struct *child)
@@ -274,6 +280,33 @@ static int dspregs_active(struct task_struct *target,
 }
 #endif
 
+const struct pt_regs_offset regoffset_table[] = {
+        REGS_OFFSET_NAME(0),
+        REGS_OFFSET_NAME(1),
+        REGS_OFFSET_NAME(2),
+        REGS_OFFSET_NAME(3),
+        REGS_OFFSET_NAME(4),
+        REGS_OFFSET_NAME(5),
+        REGS_OFFSET_NAME(6),
+        REGS_OFFSET_NAME(7),
+        REGS_OFFSET_NAME(8),
+        REGS_OFFSET_NAME(9),
+        REGS_OFFSET_NAME(10),
+        REGS_OFFSET_NAME(11),
+        REGS_OFFSET_NAME(12),
+        REGS_OFFSET_NAME(13),
+        REGS_OFFSET_NAME(14),
+        REGS_OFFSET_NAME(15),
+        REG_OFFSET_NAME(pc),
+        REG_OFFSET_NAME(pr),
+        REG_OFFSET_NAME(sr),
+        REG_OFFSET_NAME(gbr),
+        REG_OFFSET_NAME(mach),
+        REG_OFFSET_NAME(macl),
+        REG_OFFSET_NAME(tra),
+        REG_OFFSET_END,
+};
+
 /*
  * These are our native regset flavours.
  */
@@ -338,9 +371,9 @@ const struct user_regset_view *task_user_regset_view(struct task_struct *task)
         return &user_sh_native_view;
 }
 
-long arch_ptrace(struct task_struct *child, long request, long addr, long data)
+long arch_ptrace(struct task_struct *child, long request,
+                 unsigned long addr, unsigned long data)
 {
-        struct user * dummy = NULL;
         unsigned long __user *datap = (unsigned long __user *)data;
         int ret;
 
@@ -356,17 +389,23 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 
                 if (addr < sizeof(struct pt_regs))
                         tmp = get_stack_long(child, addr);
-                else if (addr >= (long) &dummy->fpu &&
-                         addr < (long) &dummy->u_fpvalid) {
+                else if (addr >= offsetof(struct user, fpu) &&
+                         addr < offsetof(struct user, u_fpvalid)) {
                         if (!tsk_used_math(child)) {
-                                if (addr == (long)&dummy->fpu.fpscr)
+                                if (addr == offsetof(struct user, fpu.fpscr))
                                         tmp = FPSCR_INIT;
                                 else
                                         tmp = 0;
-                        } else
-                                tmp = ((long *)child->thread.xstate)
-                                        [(addr - (long)&dummy->fpu) >> 2];
-                } else if (addr == (long) &dummy->u_fpvalid)
+                        } else {
+                                unsigned long index;
+                                ret = init_fpu(child);
+                                if (ret)
+                                        break;
+                                index = addr - offsetof(struct user, fpu);
+                                tmp = ((unsigned long *)child->thread.xstate)
+                                        [index >> 2];
+                        }
+                } else if (addr == offsetof(struct user, u_fpvalid))
                         tmp = !!tsk_used_math(child);
                 else if (addr == PT_TEXT_ADDR)
                         tmp = child->mm->start_code;
@@ -390,13 +429,18 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 
                 if (addr < sizeof(struct pt_regs))
                         ret = put_stack_long(child, addr, data);
-                else if (addr >= (long) &dummy->fpu &&
-                         addr < (long) &dummy->u_fpvalid) {
+                else if (addr >= offsetof(struct user, fpu) &&
+                         addr < offsetof(struct user, u_fpvalid)) {
+                        unsigned long index;
+                        ret = init_fpu(child);
+                        if (ret)
+                                break;
+                        index = addr - offsetof(struct user, fpu);
                         set_stopped_child_used_math(child);
-                        ((long *)child->thread.xstate)
-                                [(addr - (long)&dummy->fpu) >> 2] = data;
+                        ((unsigned long *)child->thread.xstate)
+                                [index >> 2] = data;
                         ret = 0;
-                } else if (addr == (long) &dummy->u_fpvalid) {
+                } else if (addr == offsetof(struct user, u_fpvalid)) {
                         conditional_stopped_child_used_math(data, child);
                         ret = 0;
                 }
@@ -406,35 +450,35 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 return copy_regset_to_user(child, &user_sh_native_view,
                                            REGSET_GENERAL,
                                            0, sizeof(struct pt_regs),
-                                           (void __user *)data);
+                                           datap);
         case PTRACE_SETREGS:
                 return copy_regset_from_user(child, &user_sh_native_view,
                                              REGSET_GENERAL,
                                              0, sizeof(struct pt_regs),
-                                             (const void __user *)data);
+                                             datap);
 #ifdef CONFIG_SH_FPU
         case PTRACE_GETFPREGS:
                 return copy_regset_to_user(child, &user_sh_native_view,
                                            REGSET_FPU,
                                            0, sizeof(struct user_fpu_struct),
-                                           (void __user *)data);
+                                           datap);
         case PTRACE_SETFPREGS:
                 return copy_regset_from_user(child, &user_sh_native_view,
                                              REGSET_FPU,
                                              0, sizeof(struct user_fpu_struct),
-                                             (const void __user *)data);
+                                             datap);
 #endif
 #ifdef CONFIG_SH_DSP
         case PTRACE_GETDSPREGS:
                 return copy_regset_to_user(child, &user_sh_native_view,
                                            REGSET_DSP,
                                            0, sizeof(struct pt_dspregs),
-                                           (void __user *)data);
+                                           datap);
         case PTRACE_SETDSPREGS:
                 return copy_regset_from_user(child, &user_sh_native_view,
                                              REGSET_DSP,
                                              0, sizeof(struct pt_dspregs),
-                                             (const void __user *)data);
+                                             datap);
 #endif
         default:
                 ret = ptrace_request(child, request, addr, data);
diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c
index 5fd644da7f02..c8f97649f354 100644
--- a/arch/sh/kernel/ptrace_64.c
+++ b/arch/sh/kernel/ptrace_64.c
@@ -20,7 +20,7 @@
 #include <linux/sched.h>
 #include <linux/mm.h>
 #include <linux/smp.h>
-#include <linux/smp_lock.h>
+#include <linux/bitops.h>
 #include <linux/errno.h>
 #include <linux/ptrace.h>
 #include <linux/user.h>
@@ -252,6 +252,85 @@ static int fpregs_active(struct task_struct *target,
 }
 #endif
 
+const struct pt_regs_offset regoffset_table[] = {
+        REG_OFFSET_NAME(pc),
+        REG_OFFSET_NAME(sr),
+        REG_OFFSET_NAME(syscall_nr),
+        REGS_OFFSET_NAME(0),
+        REGS_OFFSET_NAME(1),
+        REGS_OFFSET_NAME(2),
+        REGS_OFFSET_NAME(3),
+        REGS_OFFSET_NAME(4),
+        REGS_OFFSET_NAME(5),
+        REGS_OFFSET_NAME(6),
+        REGS_OFFSET_NAME(7),
+        REGS_OFFSET_NAME(8),
+        REGS_OFFSET_NAME(9),
+        REGS_OFFSET_NAME(10),
+        REGS_OFFSET_NAME(11),
+        REGS_OFFSET_NAME(12),
+        REGS_OFFSET_NAME(13),
+        REGS_OFFSET_NAME(14),
+        REGS_OFFSET_NAME(15),
+        REGS_OFFSET_NAME(16),
+        REGS_OFFSET_NAME(17),
+        REGS_OFFSET_NAME(18),
+        REGS_OFFSET_NAME(19),
+        REGS_OFFSET_NAME(20),
+        REGS_OFFSET_NAME(21),
+        REGS_OFFSET_NAME(22),
+        REGS_OFFSET_NAME(23),
+        REGS_OFFSET_NAME(24),
+        REGS_OFFSET_NAME(25),
+        REGS_OFFSET_NAME(26),
+        REGS_OFFSET_NAME(27),
+        REGS_OFFSET_NAME(28),
+        REGS_OFFSET_NAME(29),
+        REGS_OFFSET_NAME(30),
+        REGS_OFFSET_NAME(31),
+        REGS_OFFSET_NAME(32),
+        REGS_OFFSET_NAME(33),
+        REGS_OFFSET_NAME(34),
+        REGS_OFFSET_NAME(35),
+        REGS_OFFSET_NAME(36),
+        REGS_OFFSET_NAME(37),
+        REGS_OFFSET_NAME(38),
+        REGS_OFFSET_NAME(39),
+        REGS_OFFSET_NAME(40),
+        REGS_OFFSET_NAME(41),
+        REGS_OFFSET_NAME(42),
+        REGS_OFFSET_NAME(43),
+        REGS_OFFSET_NAME(44),
+        REGS_OFFSET_NAME(45),
+        REGS_OFFSET_NAME(46),
+        REGS_OFFSET_NAME(47),
+        REGS_OFFSET_NAME(48),
+        REGS_OFFSET_NAME(49),
+        REGS_OFFSET_NAME(50),
+        REGS_OFFSET_NAME(51),
+        REGS_OFFSET_NAME(52),
+        REGS_OFFSET_NAME(53),
+        REGS_OFFSET_NAME(54),
+        REGS_OFFSET_NAME(55),
+        REGS_OFFSET_NAME(56),
+        REGS_OFFSET_NAME(57),
+        REGS_OFFSET_NAME(58),
+        REGS_OFFSET_NAME(59),
+        REGS_OFFSET_NAME(60),
+        REGS_OFFSET_NAME(61),
+        REGS_OFFSET_NAME(62),
+        REGS_OFFSET_NAME(63),
+        TREGS_OFFSET_NAME(0),
+        TREGS_OFFSET_NAME(1),
+        TREGS_OFFSET_NAME(2),
+        TREGS_OFFSET_NAME(3),
+        TREGS_OFFSET_NAME(4),
+        TREGS_OFFSET_NAME(5),
+        TREGS_OFFSET_NAME(6),
+        TREGS_OFFSET_NAME(7),
+        REG_OFFSET_END,
+};
+
 /*
  * These are our native regset flavours.
  */
@@ -304,9 +383,11 @@ const struct user_regset_view *task_user_regset_view(struct task_struct *task)
         return &user_sh64_native_view;
 }
 
-long arch_ptrace(struct task_struct *child, long request, long addr, long data)
+long arch_ptrace(struct task_struct *child, long request,
+                 unsigned long addr, unsigned long data)
 {
         int ret;
+        unsigned long __user *datap = (unsigned long __user *) data;
 
         switch (request) {
         /* read the word at location addr in the USER area. */
@@ -321,13 +402,18 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                         tmp = get_stack_long(child, addr);
                 else if ((addr >= offsetof(struct user, fpu)) &&
                          (addr <  offsetof(struct user, u_fpvalid))) {
-                        tmp = get_fpu_long(child, addr - offsetof(struct user, fpu));
+                        unsigned long index;
+                        ret = init_fpu(child);
+                        if (ret)
+                                break;
+                        index = addr - offsetof(struct user, fpu);
+                        tmp = get_fpu_long(child, index);
                 } else if (addr == offsetof(struct user, u_fpvalid)) {
                         tmp = !!tsk_used_math(child);
                 } else {
                         break;
                 }
-                ret = put_user(tmp, (unsigned long *)data);
+                ret = put_user(tmp, datap);
                 break;
         }
 
@@ -358,7 +444,12 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 }
                 else if ((addr >= offsetof(struct user, fpu)) &&
                          (addr <  offsetof(struct user, u_fpvalid))) {
-                        ret = put_fpu_long(child, addr - offsetof(struct user, fpu), data);
+                        unsigned long index;
+                        ret = init_fpu(child);
+                        if (ret)
+                                break;
+                        index = addr - offsetof(struct user, fpu);
+                        ret = put_fpu_long(child, index, data);
                 }
                 break;
 
@@ -366,23 +457,23 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 return copy_regset_to_user(child, &user_sh64_native_view,
                                            REGSET_GENERAL,
                                            0, sizeof(struct pt_regs),
-                                           (void __user *)data);
+                                           datap);
         case PTRACE_SETREGS:
                 return copy_regset_from_user(child, &user_sh64_native_view,
                                              REGSET_GENERAL,
                                              0, sizeof(struct pt_regs),
-                                             (const void __user *)data);
+                                             datap);
 #ifdef CONFIG_SH_FPU
         case PTRACE_GETFPREGS:
                 return copy_regset_to_user(child, &user_sh64_native_view,
                                            REGSET_FPU,
                                            0, sizeof(struct user_fpu_struct),
-                                           (void __user *)data);
+                                           datap);
         case PTRACE_SETFPREGS:
                 return copy_regset_from_user(child, &user_sh64_native_view,
                                              REGSET_FPU,
                                              0, sizeof(struct user_fpu_struct),
-                                             (const void __user *)data);
+                                             datap);
 #endif
         default:
                 ret = ptrace_request(child, request, addr, data);
@@ -392,13 +483,13 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
         return ret;
 }
 
-asmlinkage int sh64_ptrace(long request, long pid, long addr, long data)
+asmlinkage int sh64_ptrace(long request, long pid,
+                           unsigned long addr, unsigned long data)
 {
 #define WPC_DBRMODE 0x0d104008
-        static int first_call = 1;
+        static unsigned long first_call;
 
-        lock_kernel();
-        if (first_call) {
+        if (!test_and_set_bit(0, &first_call)) {
                 /* Set WPC.DBRMODE to 0.  This makes all debug events get
                  * delivered through RESVEC, i.e. into the handlers in entry.S.
                  * (If the kernel was downloaded using a remote gdb, WPC.DBRMODE
@@ -408,9 +499,7 @@ asmlinkage int sh64_ptrace(long request, long pid, long addr, long data)
                  * the remote gdb.) */
                 printk("DBRMODE set to 0 to permit native debugging\n");
                 poke_real_address_q(WPC_DBRMODE, 0);
-                first_call = 0;
         }
-        unlock_kernel();
 
         return sys_ptrace(request, pid, addr, data);
 }
diff --git a/arch/sh/kernel/reboot.c b/arch/sh/kernel/reboot.c
index b1fca66bb92e..ca6a5ca64015 100644
--- a/arch/sh/kernel/reboot.c
+++ b/arch/sh/kernel/reboot.c
@@ -9,6 +9,7 @@
 #include <asm/addrspace.h>
 #include <asm/reboot.h>
 #include <asm/system.h>
+#include <asm/tlbflush.h>
 
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
@@ -25,6 +26,9 @@ static void native_machine_restart(char * __unused)
 {
         local_irq_disable();
 
+        /* Destroy all of the TLBs in preparation for reset by MMU */
+        __flush_tlb_global();
+
         /* Address error with SR.BL=1 first. */
         trigger_address_error();
 
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index e769401a78ba..58bff45d1156 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -12,7 +12,6 @@
 #include <linux/initrd.h>
 #include <linux/bootmem.h>
 #include <linux/console.h>
-#include <linux/seq_file.h>
 #include <linux/root_dev.h>
 #include <linux/utsname.h>
 #include <linux/nodemask.h>
@@ -24,7 +23,6 @@
 #include <linux/module.h>
 #include <linux/smp.h>
 #include <linux/err.h>
-#include <linux/debugfs.h>
 #include <linux/crash_dump.h>
 #include <linux/mmzone.h>
 #include <linux/clk.h>
@@ -42,6 +40,7 @@
 #include <asm/smp.h>
 #include <asm/mmu_context.h>
 #include <asm/mmzone.h>
+#include <asm/sparsemem.h>
 
 /*
  * Initialize loops_per_jiffy as 10000000 (1000MIPS).
@@ -53,6 +52,7 @@ struct sh_cpuinfo cpu_data[NR_CPUS] __read_mostly = {
                 .type                   = CPU_SH_NONE,
                 .family                 = CPU_FAMILY_UNKNOWN,
                 .loops_per_jiffy        = 10000000,
+                .phys_bits              = MAX_PHYSMEM_BITS,
         },
 };
 EXPORT_SYMBOL(cpu_data);
@@ -136,8 +136,9 @@ void __init check_for_initrd(void)
                 goto disable;
         }
 
-        if (unlikely(start < PAGE_OFFSET)) {
-                pr_err("initrd start < PAGE_OFFSET\n");
+        if (unlikely(start < __MEMORY_START)) {
+                pr_err("initrd start (%08lx) < __MEMORY_START(%x)\n",
+                        start, __MEMORY_START);
                 goto disable;
         }
 
@@ -149,7 +150,7 @@ void __init check_for_initrd(void)
         }
 
         /*
-         * If we got this far inspite of the boot loader's best efforts
+         * If we got this far in spite of the boot loader's best efforts
          * to the contrary, assume we actually have a valid initrd and
          * fix up the root dev.
          */
@@ -158,7 +159,7 @@ void __init check_for_initrd(void)
         /*
          * Address sanitization
          */
-        initrd_start = (unsigned long)__va(__pa(start));
+        initrd_start = (unsigned long)__va(start);
         initrd_end = initrd_start + INITRD_SIZE;
 
         memblock_reserve(__pa(initrd_start), INITRD_SIZE);
@@ -317,158 +318,3 @@ int test_mode_pin(int pin)
 {
         return sh_mv.mv_mode_pins() & pin;
 }
-
-static const char *cpu_name[] = {
-        [CPU_SH7201]    = "SH7201",
-        [CPU_SH7203]    = "SH7203",     [CPU_SH7263]    = "SH7263",
-        [CPU_SH7206]    = "SH7206",     [CPU_SH7619]    = "SH7619",
-        [CPU_SH7705]    = "SH7705",     [CPU_SH7706]    = "SH7706",
-        [CPU_SH7707]    = "SH7707",     [CPU_SH7708]    = "SH7708",
-        [CPU_SH7709]    = "SH7709",     [CPU_SH7710]    = "SH7710",
-        [CPU_SH7712]    = "SH7712",     [CPU_SH7720]    = "SH7720",
-        [CPU_SH7721]    = "SH7721",     [CPU_SH7729]    = "SH7729",
-        [CPU_SH7750]    = "SH7750",     [CPU_SH7750S]   = "SH7750S",
-        [CPU_SH7750R]   = "SH7750R",    [CPU_SH7751]    = "SH7751",
-        [CPU_SH7751R]   = "SH7751R",    [CPU_SH7760]    = "SH7760",
-        [CPU_SH4_202]   = "SH4-202",    [CPU_SH4_501]   = "SH4-501",
-        [CPU_SH7763]    = "SH7763",     [CPU_SH7770]    = "SH7770",
-        [CPU_SH7780]    = "SH7780",     [CPU_SH7781]    = "SH7781",
-        [CPU_SH7343]    = "SH7343",     [CPU_SH7785]    = "SH7785",
-        [CPU_SH7786]    = "SH7786",     [CPU_SH7757]    = "SH7757",
-        [CPU_SH7722]    = "SH7722",     [CPU_SHX3]      = "SH-X3",
-        [CPU_SH5_101]   = "SH5-101",    [CPU_SH5_103]   = "SH5-103",
-        [CPU_MXG]       = "MX-G",       [CPU_SH7723]    = "SH7723",
-        [CPU_SH7366]    = "SH7366",     [CPU_SH7724]    = "SH7724",
-        [CPU_SH_NONE]   = "Unknown"
-};
-
-const char *get_cpu_subtype(struct sh_cpuinfo *c)
-{
-        return cpu_name[c->type];
-}
-EXPORT_SYMBOL(get_cpu_subtype);
-
-#ifdef CONFIG_PROC_FS
-/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
-static const char *cpu_flags[] = {
-        "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
-        "ptea", "llsc", "l2", "op32", "pteaex", NULL
-};
-
-static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
-{
-        unsigned long i;
-
-        seq_printf(m, "cpu flags\t:");
-
-        if (!c->flags) {
-                seq_printf(m, " %s\n", cpu_flags[0]);
-                return;
-        }
-
-        for (i = 0; cpu_flags[i]; i++)
-                if ((c->flags & (1 << i)))
-                        seq_printf(m, " %s", cpu_flags[i+1]);
-
-        seq_printf(m, "\n");
-}
-
-static void show_cacheinfo(struct seq_file *m, const char *type,
-                           struct cache_info info)
-{
-        unsigned int cache_size;
-
-        cache_size = info.ways * info.sets * info.linesz;
-
-        seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",
-                   type, cache_size >> 10, info.ways);
-}
-
-/*
- *      Get CPU information for use by the procfs.
- */
-static int show_cpuinfo(struct seq_file *m, void *v)
-{
-        struct sh_cpuinfo *c = v;
-        unsigned int cpu = c - cpu_data;
-
-        if (!cpu_online(cpu))
-                return 0;
-
-        if (cpu == 0)
-                seq_printf(m, "machine\t\t: %s\n", get_system_type());
-        else
-                seq_printf(m, "\n");
-
-        seq_printf(m, "processor\t: %d\n", cpu);
-        seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
-        seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
-        if (c->cut_major == -1)
-                seq_printf(m, "cut\t\t: unknown\n");
-        else if (c->cut_minor == -1)
-                seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
-        else
-                seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
-
-        show_cpuflags(m, c);
-
-        seq_printf(m, "cache type\t: ");
-
-        /*
-         * Check for what type of cache we have, we support both the
-         * unified cache on the SH-2 and SH-3, as well as the harvard
-         * style cache on the SH-4.
-         */
-        if (c->icache.flags & SH_CACHE_COMBINED) {
-                seq_printf(m, "unified\n");
-                show_cacheinfo(m, "cache", c->icache);
-        } else {
-                seq_printf(m, "split (harvard)\n");
-                show_cacheinfo(m, "icache", c->icache);
-                show_cacheinfo(m, "dcache", c->dcache);
-        }
-
-        /* Optional secondary cache */
-        if (c->flags & CPU_HAS_L2_CACHE)
-                show_cacheinfo(m, "scache", c->scache);
-
-        seq_printf(m, "bogomips\t: %lu.%02lu\n",
-                     c->loops_per_jiffy/(500000/HZ),
-                     (c->loops_per_jiffy/(5000/HZ)) % 100);
-
-        return 0;
-}
-
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
-        return *pos < NR_CPUS ? cpu_data + *pos : NULL;
-}
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
-        ++*pos;
-        return c_start(m, pos);
-}
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-const struct seq_operations cpuinfo_op = {
-        .start  = c_start,
-        .next   = c_next,
-        .stop   = c_stop,
-        .show   = show_cpuinfo,
-};
-#endif /* CONFIG_PROC_FS */
-
-struct dentry *sh_debugfs_root;
-
-static int __init sh_debugfs_init(void)
-{
-        sh_debugfs_root = debugfs_create_dir("sh", NULL);
-        if (!sh_debugfs_root)
-                return -ENOMEM;
-        if (IS_ERR(sh_debugfs_root))
-                return PTR_ERR(sh_debugfs_root);
-
-        return 0;
-}
-arch_initcall(sh_debugfs_init);
diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c
index 509b36b45115..6207561ea34a 100644
--- a/arch/sh/kernel/smp.c
+++ b/arch/sh/kernel/smp.c
@@ -20,6 +20,7 @@
 #include <linux/module.h>
 #include <linux/cpu.h>
 #include <linux/interrupt.h>
+#include <linux/sched.h>
 #include <asm/atomic.h>
 #include <asm/processor.h>
 #include <asm/system.h>
@@ -323,6 +324,7 @@ void smp_message_recv(unsigned int msg)
                 generic_smp_call_function_interrupt();
                 break;
         case SMP_MSG_RESCHEDULE:
+                scheduler_ipi();
                 break;
         case SMP_MSG_FUNCTION_SINGLE:
                 generic_smp_call_function_single_interrupt();
diff --git a/arch/sh/kernel/stacktrace.c b/arch/sh/kernel/stacktrace.c
index c2e45c48409c..bf989e063a0c 100644
--- a/arch/sh/kernel/stacktrace.c
+++ b/arch/sh/kernel/stacktrace.c
@@ -17,15 +17,6 @@
 #include <asm/ptrace.h>
 #include <asm/stacktrace.h>
 
-static void save_stack_warning(void *data, char *msg)
-{
-}
-
-static void
-save_stack_warning_symbol(void *data, char *msg, unsigned long symbol)
-{
-}
-
 static int save_stack_stack(void *data, char *name)
 {
         return 0;
@@ -51,8 +42,6 @@ static void save_stack_address(void *data, unsigned long addr, int reliable)
 }
 
 static const struct stacktrace_ops save_stack_ops = {
-        .warning = save_stack_warning,
-        .warning_symbol = save_stack_warning_symbol,
         .stack = save_stack_stack,
         .address = save_stack_address,
 };
@@ -88,8 +77,6 @@ save_stack_address_nosched(void *data, unsigned long addr, int reliable)
 }
 
 static const struct stacktrace_ops save_stack_ops_nosched = {
-        .warning = save_stack_warning,
-        .warning_symbol = save_stack_warning_symbol,
         .stack = save_stack_stack,
         .address = save_stack_address_nosched,
 };
diff --git a/arch/sh/kernel/sys_sh.c b/arch/sh/kernel/sys_sh.c
index 81f58371613d..8c6a350df751 100644
--- a/arch/sh/kernel/sys_sh.c
+++ b/arch/sh/kernel/sys_sh.c
@@ -88,7 +88,7 @@ asmlinkage int sys_cacheflush(unsigned long addr, unsigned long len, int op)
         }
 
         if (op & CACHEFLUSH_I)
-                flush_cache_all();
+                flush_icache_range(addr, addr+len);
 
         up_read(&current->mm->mmap_sem);
         return 0;
diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S
index 19fd11dd9871..39b051de4c7c 100644
--- a/arch/sh/kernel/syscalls_32.S
+++ b/arch/sh/kernel/syscalls_32.S
@@ -353,3 +353,32 @@ ENTRY(sys_call_table)
         .long sys_pwritev
         .long sys_rt_tgsigqueueinfo     /* 335 */
         .long sys_perf_event_open
+        .long sys_fanotify_init
+        .long sys_fanotify_mark
+        .long sys_prlimit64
+        /* Broken-out socket family */
+        .long sys_socket                /* 340 */
+        .long sys_bind
+        .long sys_connect
+        .long sys_listen
+        .long sys_accept
+        .long sys_getsockname   /* 345 */
+        .long sys_getpeername
+        .long sys_socketpair
+        .long sys_send
+        .long sys_sendto
+        .long sys_recv                  /* 350 */
+        .long sys_recvfrom
+        .long sys_shutdown
+        .long sys_setsockopt
+        .long sys_getsockopt
+        .long sys_sendmsg               /* 355 */
+        .long sys_recvmsg
+        .long sys_recvmmsg
+        .long sys_accept4
+        .long sys_name_to_handle_at
+        .long sys_open_by_handle_at     /* 360 */
+        .long sys_clock_adjtime
+        .long sys_syncfs
+        .long sys_sendmmsg
+        .long sys_setns
diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S
index 2048a20d7c80..089c4d825d08 100644
--- a/arch/sh/kernel/syscalls_64.S
+++ b/arch/sh/kernel/syscalls_64.S
@@ -393,3 +393,12 @@ sys_call_table:
         .long sys_perf_event_open
         .long sys_recvmmsg              /* 365 */
         .long sys_accept4
+        .long sys_fanotify_init
+        .long sys_fanotify_mark
+        .long sys_prlimit64
+        .long sys_name_to_handle_at     /* 370 */
+        .long sys_open_by_handle_at
+        .long sys_clock_adjtime
+        .long sys_syncfs
+        .long sys_sendmmsg
+        .long sys_setns                 /* 375 */
diff --git a/arch/sh/kernel/topology.c b/arch/sh/kernel/topology.c
index 948fdb656933..38e862852dd0 100644
--- a/arch/sh/kernel/topology.c
+++ b/arch/sh/kernel/topology.c
@@ -17,6 +17,7 @@
 static DEFINE_PER_CPU(struct cpu, cpu_devices);
 
 cpumask_t cpu_core_map[NR_CPUS];
+EXPORT_SYMBOL(cpu_core_map);
 
 static cpumask_t cpu_coregroup_map(unsigned int cpu)
 {
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index c3d86fa71ddf..b51a17104b5f 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -5,7 +5,7 @@
  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
  *                  Copyright (C) 2000 Philipp Rumpf
  *                  Copyright (C) 2000 David Howells
- *                  Copyright (C) 2002 - 2007 Paul Mundt
+ *                  Copyright (C) 2002 - 2010 Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -26,6 +26,7 @@
 #include <linux/limits.h>
 #include <linux/sysfs.h>
 #include <linux/uaccess.h>
+#include <linux/perf_event.h>
 #include <asm/system.h>
 #include <asm/alignment.h>
 #include <asm/fpu.h>
@@ -86,7 +87,6 @@ void die(const char * str, struct pt_regs * regs, long err)
         bust_spinlocks(1);
 
         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
-        sysfs_printk_last_file();
         print_modules();
         show_regs(regs);
 
@@ -369,7 +369,8 @@ static inline int handle_delayslot(struct pt_regs *regs,
 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
 
 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
-                            struct mem_access *ma, int expected)
+                            struct mem_access *ma, int expected,
+                            unsigned long address)
 {
         u_int rm;
         int ret, index;
@@ -383,9 +384,18 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
         index = (instruction>>8)&15;    /* 0x0F00 */
         rm = regs->regs[index];
 
-        /* shout about fixups */
-        if (!expected)
+        /*
+         * Log the unexpected fixups, and then pass them on to perf.
+         *
+         * We intentionally don't report the expected cases to perf as
+         * otherwise the trapped I/O case will skew the results too much
+         * to be useful.
+         */
+        if (!expected) {
                 unaligned_fixups_notify(current, instruction, regs);
+                perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0,
+                              regs, address);
+        }
 
         ret = -EFAULT;
         switch (instruction&0xF000) {
@@ -574,7 +584,8 @@ fixup:
 
                 set_fs(USER_DS);
                 tmp = handle_unaligned_access(instruction, regs,
-                                              &user_mem_access, 0);
+                                              &user_mem_access, 0,
+                                              address);
                 set_fs(oldfs);
 
                 if (tmp == 0)
@@ -607,8 +618,8 @@ uspace_segv:
 
                 unaligned_fixups_notify(current, instruction, regs);
 
-                handle_unaligned_access(instruction, regs,
-                                        &user_mem_access, 0);
+                handle_unaligned_access(instruction, regs, &user_mem_access,
+                                        0, address);
                 set_fs(oldfs);
         }
 }
@@ -802,6 +813,9 @@ void __cpuinit per_cpu_trap_init(void)
                      : /* no output */
                      : "r" (&vbr_base)
                      : "memory");
+
+        /* disable exception blocking now when the vbr has been setup */
+        clear_bl_bit();
 }
 
 void *set_exception_table_vec(unsigned int vec, void *handler)
diff --git a/arch/sh/kernel/traps_64.c b/arch/sh/kernel/traps_64.c
index e67e140bf1f6..6713ca97e553 100644
--- a/arch/sh/kernel/traps_64.c
+++ b/arch/sh/kernel/traps_64.c
@@ -24,6 +24,7 @@
 #include <linux/interrupt.h>
 #include <linux/sysctl.h>
 #include <linux/module.h>
+#include <linux/perf_event.h>
 #include <asm/system.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
@@ -50,7 +51,7 @@ asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
         do_unhandled_exception(trapnr, signr, str, __stringify(name), error_code, regs, current); \
 }
 
-spinlock_t die_lock;
+static DEFINE_SPINLOCK(die_lock);
 
 void die(const char * str, struct pt_regs * regs, long err)
 {
@@ -433,6 +434,8 @@ static int misaligned_load(struct pt_regs *regs,
                 return error;
         }
 
+        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, address);
+
         destreg = (opcode >> 4) & 0x3f;
         if (user_mode(regs)) {
                 __u64 buffer;
@@ -509,6 +512,8 @@ static int misaligned_store(struct pt_regs *regs,
                 return error;
         }
 
+        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, 0, regs, address);
+
         srcreg = (opcode >> 4) & 0x3f;
         if (user_mode(regs)) {
                 __u64 buffer;
@@ -583,6 +588,8 @@ static int misaligned_fpu_load(struct pt_regs *regs,
                 return error;
         }
 
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, address);
+
         destreg = (opcode >> 4) & 0x3f;
         if (user_mode(regs)) {
                 __u64 buffer;
@@ -658,6 +665,8 @@ static int misaligned_fpu_store(struct pt_regs *regs,
                 return error;
         }
 
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, address);
+
         srcreg = (opcode >> 4) & 0x3f;
         if (user_mode(regs)) {
                 __u64 buffer;
diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S
index 7f8a709c3ada..731c10ce67b5 100644
--- a/arch/sh/kernel/vmlinux.lds.S
+++ b/arch/sh/kernel/vmlinux.lds.S
@@ -66,7 +66,7 @@ SECTIONS
                 __machvec_end = .;
         }
 
-        PERCPU(PAGE_SIZE)
+        PERCPU_SECTION(L1_CACHE_BYTES)
 
         /*
          * .exit.text is discarded at runtime, not link time, to deal with
diff --git a/arch/sh/kernel/vsyscall/vsyscall-trapa.S b/arch/sh/kernel/vsyscall/vsyscall-trapa.S
index 3b6eb34c43fa..3e70f851cdc6 100644
--- a/arch/sh/kernel/vsyscall/vsyscall-trapa.S
+++ b/arch/sh/kernel/vsyscall/vsyscall-trapa.S
@@ -8,9 +8,9 @@ __kernel_vsyscall:
          * fill out .eh_frame -- PFM. */
 .LEND_vsyscall:
         .size __kernel_vsyscall,.-.LSTART_vsyscall
-        .previous
 
         .section .eh_frame,"a",@progbits
+        .previous
 .LCIE:
         .ualong .LCIE_end - .LCIE_start
 .LCIE_start:
diff --git a/arch/sh/kernel/vsyscall/vsyscall.c b/arch/sh/kernel/vsyscall/vsyscall.c
index 242117cbad67..1d6d51a1ce79 100644
--- a/arch/sh/kernel/vsyscall/vsyscall.c
+++ b/arch/sh/kernel/vsyscall/vsyscall.c
@@ -94,17 +94,17 @@ const char *arch_vma_name(struct vm_area_struct *vma)
         return NULL;
 }
 
-struct vm_area_struct *get_gate_vma(struct task_struct *task)
+struct vm_area_struct *get_gate_vma(struct mm_struct *mm)
 {
         return NULL;
 }
 
-int in_gate_area(struct task_struct *task, unsigned long address)
+int in_gate_area(struct mm_struct *mm, unsigned long address)
 {
         return 0;
 }
 
-int in_gate_area_no_task(unsigned long address)
+int in_gate_area_no_mm(unsigned long address)
 {
         return 0;
 }
diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile
index dab4d2129812..7b95f29e3174 100644
--- a/arch/sh/lib/Makefile
+++ b/arch/sh/lib/Makefile
@@ -30,4 +30,4 @@ lib-$(CONFIG_MMU)		+= copy_page.o __clear_user.o
 lib-$(CONFIG_MCOUNT)            += mcount.o
 lib-y                           += $(memcpy-y) $(memset-y) $(udivsi3-y)
 
-EXTRA_CFLAGS += -Werror
+ccflags-y := -Werror
diff --git a/arch/sh/lib/delay.c b/arch/sh/lib/delay.c
index faa8f86c0db4..0901b2f14e15 100644
--- a/arch/sh/lib/delay.c
+++ b/arch/sh/lib/delay.c
@@ -10,6 +10,16 @@
 void __delay(unsigned long loops)
 {
         __asm__ __volatile__(
+                /*
+                 * ST40-300 appears to have an issue with this code,
+                 * normally taking two cycles each loop, as with all
+                 * other SH variants. If however the branch and the
+                 * delay slot straddle an 8 byte boundary, this increases
+                 * to 3 cycles.
+                 * This align directive ensures this doesn't occur.
+                 */
+                ".balign 8\n\t"
+
                 "tst    %0, %0\n\t"
                 "1:\t"
                 "bf/s   1b\n\t"
diff --git a/arch/sh/lib64/copy_user_memcpy.S b/arch/sh/lib64/copy_user_memcpy.S
index 2a62816d2ddd..49aeabeba2c2 100644
--- a/arch/sh/lib64/copy_user_memcpy.S
+++ b/arch/sh/lib64/copy_user_memcpy.S
@@ -27,7 +27,7 @@
 ! 2.: When there are two or three bytes in the last word of an 11-or-more
 !     bytes memory chunk to b copied, the rest of the word can be read
 !     without side effects.
-!     This could be easily changed by increasing the minumum size of
+!     This could be easily changed by increasing the minimum size of
 !     a fast memcpy and the amount subtracted from r7 before L_2l_loop be 2,
 !     however, this would cost a few extra cyles on average.
 !     For SHmedia, the assumption is that any quadword can be read in its
diff --git a/arch/sh/lib64/memcpy.S b/arch/sh/lib64/memcpy.S
index dd300c372ce1..5d682e0ee24f 100644
--- a/arch/sh/lib64/memcpy.S
+++ b/arch/sh/lib64/memcpy.S
@@ -29,7 +29,7 @@
 ! 2.: When there are two or three bytes in the last word of an 11-or-more
 !     bytes memory chunk to b copied, the rest of the word can be read
 !     without side effects.
-!     This could be easily changed by increasing the minumum size of
+!     This could be easily changed by increasing the minimum size of
 !     a fast memcpy and the amount subtracted from r7 before L_2l_loop be 2,
 !     however, this would cost a few extra cyles on average.
 !     For SHmedia, the assumption is that any quadword can be read in its
diff --git a/arch/sh/math-emu/math.c b/arch/sh/math-emu/math.c
index 1fcdb1220975..f76a5090d5d1 100644
--- a/arch/sh/math-emu/math.c
+++ b/arch/sh/math-emu/math.c
@@ -12,6 +12,7 @@
 #include <linux/types.h>
 #include <linux/sched.h>
 #include <linux/signal.h>
+#include <linux/perf_event.h>
 
 #include <asm/system.h>
 #include <asm/uaccess.h>
@@ -619,6 +620,8 @@ int do_fpu_inst(unsigned short inst, struct pt_regs *regs)
         struct task_struct *tsk = current;
         struct sh_fpu_soft_struct *fpu = &(tsk->thread.xstate->softfpu);
 
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, 0);
+
         if (!(task_thread_info(tsk)->status & TS_USEDFPU)) {
                 /* initialize once. */
                 fpu_init(fpu);
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 1445ca6257df..c3e61b366493 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -79,7 +79,7 @@ config 29BIT
 
 config 32BIT
         bool
-        default y if CPU_SH5
+        default y if CPU_SH5 || !MMU
 
 config PMB
         bool "Support 32-bit physical addressing through PMB"
@@ -168,6 +168,10 @@ config IOREMAP_FIXED
 config UNCACHED_MAPPING
         bool
 
+config HAVE_SRAM_POOL
+        bool
+        select GENERIC_ALLOCATOR
+
 choice
         prompt "Kernel page size"
         default PAGE_SIZE_4KB
diff --git a/arch/sh/mm/Makefile b/arch/sh/mm/Makefile
index 53f7c684afb2..2228c8cee4d6 100644
--- a/arch/sh/mm/Makefile
+++ b/arch/sh/mm/Makefile
@@ -15,7 +15,7 @@ cacheops-$(CONFIG_CPU_SHX3)		+= cache-shx3.o
 obj-y                   += $(cacheops-y)
 
 mmu-y                   := nommu.o extable_32.o
-mmu-$(CONFIG_MMU)       := extable_$(BITS).o fault_$(BITS).o \
+mmu-$(CONFIG_MMU)       := extable_$(BITS).o fault_$(BITS).o gup.o \
                            ioremap.o kmap.o pgtable.o tlbflush_$(BITS).o
 
 obj-y                   += $(mmu-y)
@@ -40,6 +40,9 @@ obj-$(CONFIG_PMB)		+= pmb.o
 obj-$(CONFIG_NUMA)              += numa.o
 obj-$(CONFIG_IOREMAP_FIXED)     += ioremap_fixed.o
 obj-$(CONFIG_UNCACHED_MAPPING)  += uncached.o
+obj-$(CONFIG_HAVE_SRAM_POOL)    += sram.o
+
+GCOV_PROFILE_pmb.o := n
 
 # Special flags for fault_64.o.  This puts restrictions on the number of
 # caller-save registers that the compiler can target when building this file.
@@ -66,4 +69,4 @@ CFLAGS_fault_64.o += -ffixed-r7 \
         -ffixed-r60 -ffixed-r61 -ffixed-r62 \
         -fomit-frame-pointer
 
-EXTRA_CFLAGS += -Werror
+ccflags-y := -Werror
diff --git a/arch/sh/mm/alignment.c b/arch/sh/mm/alignment.c
index b2595b8548ee..620fa7ff9eec 100644
--- a/arch/sh/mm/alignment.c
+++ b/arch/sh/mm/alignment.c
@@ -13,6 +13,7 @@
 #include <linux/seq_file.h>
 #include <linux/proc_fs.h>
 #include <linux/uaccess.h>
+#include <linux/ratelimit.h>
 #include <asm/alignment.h>
 #include <asm/processor.h>
 
@@ -95,13 +96,13 @@ int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
 void unaligned_fixups_notify(struct task_struct *tsk, insn_size_t insn,
                              struct pt_regs *regs)
 {
-        if (user_mode(regs) && (se_usermode & UM_WARN) && printk_ratelimit())
-                pr_notice("Fixing up unaligned userspace access "
+        if (user_mode(regs) && (se_usermode & UM_WARN))
+                pr_notice_ratelimited("Fixing up unaligned userspace access "
                           "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
                           tsk->comm, task_pid_nr(tsk),
                           (void *)instruction_pointer(regs), insn);
-        else if (se_kernmode_warn && printk_ratelimit())
-                pr_notice("Fixing up unaligned kernel access "
+        else if (se_kernmode_warn)
+                pr_notice_ratelimited("Fixing up unaligned kernel access "
                           "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
                           tsk->comm, task_pid_nr(tsk),
                           (void *)instruction_pointer(regs), insn);
diff --git a/arch/sh/mm/asids-debugfs.c b/arch/sh/mm/asids-debugfs.c
index cd8c3bf39b5a..74c03ecc4871 100644
--- a/arch/sh/mm/asids-debugfs.c
+++ b/arch/sh/mm/asids-debugfs.c
@@ -63,7 +63,7 @@ static int __init asids_debugfs_init(void)
 {
         struct dentry *asids_dentry;
 
-        asids_dentry = debugfs_create_file("asids", S_IRUSR, sh_debugfs_root,
+        asids_dentry = debugfs_create_file("asids", S_IRUSR, arch_debugfs_dir,
                                            NULL, &asids_debugfs_fops);
         if (!asids_dentry)
                 return -ENOMEM;
diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c
index 690ed010d002..115725198038 100644
--- a/arch/sh/mm/cache-debugfs.c
+++ b/arch/sh/mm/cache-debugfs.c
@@ -26,9 +26,9 @@ static int cache_seq_show(struct seq_file *file, void *iter)
 {
         unsigned int cache_type = (unsigned int)file->private;
         struct cache_info *cache;
-        unsigned int waysize, way, cache_size;
-        unsigned long ccr, base;
-        static unsigned long addrstart = 0;
+        unsigned int waysize, way;
+        unsigned long ccr;
+        unsigned long addrstart = 0;
 
         /*
          * Go uncached immediately so we don't skew the results any
@@ -45,28 +45,13 @@ static int cache_seq_show(struct seq_file *file, void *iter)
         }
 
         if (cache_type == CACHE_TYPE_DCACHE) {
-                base = CACHE_OC_ADDRESS_ARRAY;
+                addrstart = CACHE_OC_ADDRESS_ARRAY;
                 cache = &current_cpu_data.dcache;
         } else {
-                base = CACHE_IC_ADDRESS_ARRAY;
+                addrstart = CACHE_IC_ADDRESS_ARRAY;
                 cache = &current_cpu_data.icache;
         }
 
-        /*
-         * Due to the amount of data written out (depending on the cache size),
-         * we may be iterated over multiple times. In this case, keep track of
-         * the entry position in addrstart, and rewind it when we've hit the
-         * end of the cache.
-         *
-         * Likewise, the same code is used for multiple caches, so care must
-         * be taken for bouncing addrstart back and forth so the appropriate
-         * cache is hit.
-         */
-        cache_size = cache->ways * cache->sets * cache->linesz;
-        if (((addrstart & 0xff000000) != base) ||
-             (addrstart & 0x00ffffff) > cache_size)
-                addrstart = base;
-
         waysize = cache->sets;
 
         /*
@@ -126,25 +111,19 @@ static int __init cache_debugfs_init(void)
 {
         struct dentry *dcache_dentry, *icache_dentry;
 
-        dcache_dentry = debugfs_create_file("dcache", S_IRUSR, sh_debugfs_root,
+        dcache_dentry = debugfs_create_file("dcache", S_IRUSR, arch_debugfs_dir,
                                             (unsigned int *)CACHE_TYPE_DCACHE,
                                             &cache_debugfs_fops);
         if (!dcache_dentry)
                 return -ENOMEM;
-        if (IS_ERR(dcache_dentry))
-                return PTR_ERR(dcache_dentry);
 
-        icache_dentry = debugfs_create_file("icache", S_IRUSR, sh_debugfs_root,
+        icache_dentry = debugfs_create_file("icache", S_IRUSR, arch_debugfs_dir,
                                             (unsigned int *)CACHE_TYPE_ICACHE,
                                             &cache_debugfs_fops);
         if (!icache_dentry) {
                 debugfs_remove(dcache_dentry);
                 return -ENOMEM;
         }
-        if (IS_ERR(icache_dentry)) {
-                debugfs_remove(dcache_dentry);
-                return PTR_ERR(icache_dentry);
-        }
 
         return 0;
 }
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 2cfae81914aa..92eb98633ab0 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -114,7 +114,7 @@ static void sh4_flush_dcache_page(void *arg)
         struct address_space *mapping = page_mapping(page);
 
         if (mapping && !mapping_mapped(mapping))
-                set_bit(PG_dcache_dirty, &page->flags);
+                clear_bit(PG_dcache_clean, &page->flags);
         else
 #endif
                 flush_cache_one(CACHE_OC_ADDRESS_ARRAY |
@@ -239,7 +239,7 @@ static void sh4_flush_cache_page(void *args)
                  * another ASID than the current one.
                  */
                 map_coherent = (current_cpu_data.dcache.n_aliases &&
-                        !test_bit(PG_dcache_dirty, &page->flags) &&
+                        test_bit(PG_dcache_clean, &page->flags) &&
                         page_mapped(page));
                 if (map_coherent)
                         vaddr = kmap_coherent(page, address);
diff --git a/arch/sh/mm/cache-sh5.c b/arch/sh/mm/cache-sh5.c
index eb4cc4ec7952..d1bffbcd9d52 100644
--- a/arch/sh/mm/cache-sh5.c
+++ b/arch/sh/mm/cache-sh5.c
@@ -568,7 +568,7 @@ static void sh5_flush_dcache_page(void *page)
 }
 
 /*
- * Flush the range [start,end] of kernel virtual adddress space from
+ * Flush the range [start,end] of kernel virtual address space from
  * the I-cache.  The corresponding range must be purged from the
  * D-cache also because the SH-5 doesn't have cache snooping between
  * the caches.  The addresses will be visible through the superpage
diff --git a/arch/sh/mm/cache-sh7705.c b/arch/sh/mm/cache-sh7705.c
index f498da1cce7a..7729cca727eb 100644
--- a/arch/sh/mm/cache-sh7705.c
+++ b/arch/sh/mm/cache-sh7705.c
@@ -139,7 +139,7 @@ static void sh7705_flush_dcache_page(void *arg)
         struct address_space *mapping = page_mapping(page);
 
         if (mapping && !mapping_mapped(mapping))
-                set_bit(PG_dcache_dirty, &page->flags);
+                clear_bit(PG_dcache_clean, &page->flags);
         else
                 __flush_dcache_page(__pa(page_address(page)));
 }
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c
index ba401d137bb9..5a580ea04429 100644
--- a/arch/sh/mm/cache.c
+++ b/arch/sh/mm/cache.c
@@ -60,14 +60,14 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
                        unsigned long len)
 {
         if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
-            !test_bit(PG_dcache_dirty, &page->flags)) {
+            test_bit(PG_dcache_clean, &page->flags)) {
                 void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
                 memcpy(vto, src, len);
                 kunmap_coherent(vto);
         } else {
                 memcpy(dst, src, len);
                 if (boot_cpu_data.dcache.n_aliases)
-                        set_bit(PG_dcache_dirty, &page->flags);
+                        clear_bit(PG_dcache_clean, &page->flags);
         }
 
         if (vma->vm_flags & VM_EXEC)
@@ -79,14 +79,14 @@ void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
                          unsigned long len)
 {
         if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
-            !test_bit(PG_dcache_dirty, &page->flags)) {
+            test_bit(PG_dcache_clean, &page->flags)) {
                 void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
                 memcpy(dst, vfrom, len);
                 kunmap_coherent(vfrom);
         } else {
                 memcpy(dst, src, len);
                 if (boot_cpu_data.dcache.n_aliases)
-                        set_bit(PG_dcache_dirty, &page->flags);
+                        clear_bit(PG_dcache_clean, &page->flags);
         }
 }
 
@@ -98,7 +98,7 @@ void copy_user_highpage(struct page *to, struct page *from,
         vto = kmap_atomic(to, KM_USER1);
 
         if (boot_cpu_data.dcache.n_aliases && page_mapped(from) &&
-            !test_bit(PG_dcache_dirty, &from->flags)) {
+            test_bit(PG_dcache_clean, &from->flags)) {
                 vfrom = kmap_coherent(from, vaddr);
                 copy_page(vto, vfrom);
                 kunmap_coherent(vfrom);
@@ -108,7 +108,8 @@ void copy_user_highpage(struct page *to, struct page *from,
                 kunmap_atomic(vfrom, KM_USER0);
         }
 
-        if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
+        if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK) ||
+            (vma->vm_flags & VM_EXEC))
                 __flush_purge_region(vto, PAGE_SIZE);
 
         kunmap_atomic(vto, KM_USER1);
@@ -141,7 +142,7 @@ void __update_cache(struct vm_area_struct *vma,
 
         page = pfn_to_page(pfn);
         if (pfn_valid(pfn)) {
-                int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
+                int dirty = !test_and_set_bit(PG_dcache_clean, &page->flags);
                 if (dirty)
                         __flush_purge_region(page_address(page), PAGE_SIZE);
         }
@@ -153,7 +154,7 @@ void __flush_anon_page(struct page *page, unsigned long vmaddr)
 
         if (pages_do_alias(addr, vmaddr)) {
                 if (boot_cpu_data.dcache.n_aliases && page_mapped(page) &&
-                    !test_bit(PG_dcache_dirty, &page->flags)) {
+                    test_bit(PG_dcache_clean, &page->flags)) {
                         void *kaddr;
 
                         kaddr = kmap_coherent(page, vmaddr);
diff --git a/arch/sh/mm/consistent.c b/arch/sh/mm/consistent.c
index c86a08540258..f251b5f27652 100644
--- a/arch/sh/mm/consistent.c
+++ b/arch/sh/mm/consistent.c
@@ -38,11 +38,12 @@ void *dma_generic_alloc_coherent(struct device *dev, size_t size,
         void *ret, *ret_nocache;
         int order = get_order(size);
 
+        gfp |= __GFP_ZERO;
+
         ret = (void *)__get_free_pages(gfp, order);
         if (!ret)
                 return NULL;
 
-        memset(ret, 0, size);
         /*
          * Pages from the page allocator may have data present in
          * cache. So flush the cache before using uncached memory.
@@ -78,21 +79,20 @@ void dma_generic_free_coherent(struct device *dev, size_t size,
 void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
                     enum dma_data_direction direction)
 {
-#if defined(CONFIG_CPU_SH5) || defined(CONFIG_PMB)
-        void *p1addr = vaddr;
-#else
-        void *p1addr = (void*) P1SEGADDR((unsigned long)vaddr);
-#endif
+        void *addr;
+
+        addr = __in_29bit_mode() ?
+               (void *)CAC_ADDR((unsigned long)vaddr) : vaddr;
 
         switch (direction) {
         case DMA_FROM_DEVICE:           /* invalidate only */
-                __flush_invalidate_region(p1addr, size);
+                __flush_invalidate_region(addr, size);
                 break;
         case DMA_TO_DEVICE:             /* writeback only */
-                __flush_wback_region(p1addr, size);
+                __flush_wback_region(addr, size);
                 break;
         case DMA_BIDIRECTIONAL:         /* writeback and invalidate */
-                __flush_purge_region(p1addr, size);
+                __flush_purge_region(addr, size);
                 break;
         default:
                 BUG();
diff --git a/arch/sh/mm/gup.c b/arch/sh/mm/gup.c
new file mode 100644
index 000000000000..bf8daf9d9c9b
--- /dev/null
+++ b/arch/sh/mm/gup.c
@@ -0,0 +1,273 @@
+/*
+ * Lockless get_user_pages_fast for SuperH
+ *
+ * Copyright (C) 2009 - 2010  Paul Mundt
+ *
+ * Cloned from the x86 and PowerPC versions, by:
+ *
+ *      Copyright (C) 2008 Nick Piggin
+ *      Copyright (C) 2008 Novell Inc.
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/vmstat.h>
+#include <linux/highmem.h>
+#include <asm/pgtable.h>
+
+static inline pte_t gup_get_pte(pte_t *ptep)
+{
+#ifndef CONFIG_X2TLB
+        return ACCESS_ONCE(*ptep);
+#else
+        /*
+         * With get_user_pages_fast, we walk down the pagetables without
+         * taking any locks.  For this we would like to load the pointers
+         * atomically, but that is not possible with 64-bit PTEs.  What
+         * we do have is the guarantee that a pte will only either go
+         * from not present to present, or present to not present or both
+         * -- it will not switch to a completely different present page
+         * without a TLB flush in between; something that we are blocking
+         * by holding interrupts off.
+         *
+         * Setting ptes from not present to present goes:
+         * ptep->pte_high = h;
+         * smp_wmb();
+         * ptep->pte_low = l;
+         *
+         * And present to not present goes:
+         * ptep->pte_low = 0;
+         * smp_wmb();
+         * ptep->pte_high = 0;
+         *
+         * We must ensure here that the load of pte_low sees l iff pte_high
+         * sees h. We load pte_high *after* loading pte_low, which ensures we
+         * don't see an older value of pte_high.  *Then* we recheck pte_low,
+         * which ensures that we haven't picked up a changed pte high. We might
+         * have got rubbish values from pte_low and pte_high, but we are
+         * guaranteed that pte_low will not have the present bit set *unless*
+         * it is 'l'. And get_user_pages_fast only operates on present ptes, so
+         * we're safe.
+         *
+         * gup_get_pte should not be used or copied outside gup.c without being
+         * very careful -- it does not atomically load the pte or anything that
+         * is likely to be useful for you.
+         */
+        pte_t pte;
+
+retry:
+        pte.pte_low = ptep->pte_low;
+        smp_rmb();
+        pte.pte_high = ptep->pte_high;
+        smp_rmb();
+        if (unlikely(pte.pte_low != ptep->pte_low))
+                goto retry;
+
+        return pte;
+#endif
+}
+
+/*
+ * The performance critical leaf functions are made noinline otherwise gcc
+ * inlines everything into a single function which results in too much
+ * register pressure.
+ */
+static noinline int gup_pte_range(pmd_t pmd, unsigned long addr,
+                unsigned long end, int write, struct page **pages, int *nr)
+{
+        u64 mask, result;
+        pte_t *ptep;
+
+#ifdef CONFIG_X2TLB
+        result = _PAGE_PRESENT | _PAGE_EXT(_PAGE_EXT_KERN_READ | _PAGE_EXT_USER_READ);
+        if (write)
+                result |= _PAGE_EXT(_PAGE_EXT_KERN_WRITE | _PAGE_EXT_USER_WRITE);
+#elif defined(CONFIG_SUPERH64)
+        result = _PAGE_PRESENT | _PAGE_USER | _PAGE_READ;
+        if (write)
+                result |= _PAGE_WRITE;
+#else
+        result = _PAGE_PRESENT | _PAGE_USER;
+        if (write)
+                result |= _PAGE_RW;
+#endif
+
+        mask = result | _PAGE_SPECIAL;
+
+        ptep = pte_offset_map(&pmd, addr);
+        do {
+                pte_t pte = gup_get_pte(ptep);
+                struct page *page;
+
+                if ((pte_val(pte) & mask) != result) {
+                        pte_unmap(ptep);
+                        return 0;
+                }
+                VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
+                page = pte_page(pte);
+                get_page(page);
+                pages[*nr] = page;
+                (*nr)++;
+
+        } while (ptep++, addr += PAGE_SIZE, addr != end);
+        pte_unmap(ptep - 1);
+
+        return 1;
+}
+
+static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
+                int write, struct page **pages, int *nr)
+{
+        unsigned long next;
+        pmd_t *pmdp;
+
+        pmdp = pmd_offset(&pud, addr);
+        do {
+                pmd_t pmd = *pmdp;
+
+                next = pmd_addr_end(addr, end);
+                if (pmd_none(pmd))
+                        return 0;
+                if (!gup_pte_range(pmd, addr, next, write, pages, nr))
+                        return 0;
+        } while (pmdp++, addr = next, addr != end);
+
+        return 1;
+}
+
+static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end,
+                        int write, struct page **pages, int *nr)
+{
+        unsigned long next;
+        pud_t *pudp;
+
+        pudp = pud_offset(&pgd, addr);
+        do {
+                pud_t pud = *pudp;
+
+                next = pud_addr_end(addr, end);
+                if (pud_none(pud))
+                        return 0;
+                if (!gup_pmd_range(pud, addr, next, write, pages, nr))
+                        return 0;
+        } while (pudp++, addr = next, addr != end);
+
+        return 1;
+}
+
+/*
+ * Like get_user_pages_fast() except its IRQ-safe in that it won't fall
+ * back to the regular GUP.
+ */
+int __get_user_pages_fast(unsigned long start, int nr_pages, int write,
+                          struct page **pages)
+{
+        struct mm_struct *mm = current->mm;
+        unsigned long addr, len, end;
+        unsigned long next;
+        unsigned long flags;
+        pgd_t *pgdp;
+        int nr = 0;
+
+        start &= PAGE_MASK;
+        addr = start;
+        len = (unsigned long) nr_pages << PAGE_SHIFT;
+        end = start + len;
+        if (unlikely(!access_ok(write ? VERIFY_WRITE : VERIFY_READ,
+                                        (void __user *)start, len)))
+                return 0;
+
+        /*
+         * This doesn't prevent pagetable teardown, but does prevent
+         * the pagetables and pages from being freed.
+         */
+        local_irq_save(flags);
+        pgdp = pgd_offset(mm, addr);
+        do {
+                pgd_t pgd = *pgdp;
+
+                next = pgd_addr_end(addr, end);
+                if (pgd_none(pgd))
+                        break;
+                if (!gup_pud_range(pgd, addr, next, write, pages, &nr))
+                        break;
+        } while (pgdp++, addr = next, addr != end);
+        local_irq_restore(flags);
+
+        return nr;
+}
+
+/**
+ * get_user_pages_fast() - pin user pages in memory
+ * @start:      starting user address
+ * @nr_pages:   number of pages from start to pin
+ * @write:      whether pages will be written to
+ * @pages:      array that receives pointers to the pages pinned.
+ *              Should be at least nr_pages long.
+ *
+ * Attempt to pin user pages in memory without taking mm->mmap_sem.
+ * If not successful, it will fall back to taking the lock and
+ * calling get_user_pages().
+ *
+ * Returns number of pages pinned. This may be fewer than the number
+ * requested. If nr_pages is 0 or negative, returns 0. If no pages
+ * were pinned, returns -errno.
+ */
+int get_user_pages_fast(unsigned long start, int nr_pages, int write,
+                        struct page **pages)
+{
+        struct mm_struct *mm = current->mm;
+        unsigned long addr, len, end;
+        unsigned long next;
+        pgd_t *pgdp;
+        int nr = 0;
+
+        start &= PAGE_MASK;
+        addr = start;
+        len = (unsigned long) nr_pages << PAGE_SHIFT;
+
+        end = start + len;
+        if (end < start)
+                goto slow_irqon;
+
+        local_irq_disable();
+        pgdp = pgd_offset(mm, addr);
+        do {
+                pgd_t pgd = *pgdp;
+
+                next = pgd_addr_end(addr, end);
+                if (pgd_none(pgd))
+                        goto slow;
+                if (!gup_pud_range(pgd, addr, next, write, pages, &nr))
+                        goto slow;
+        } while (pgdp++, addr = next, addr != end);
+        local_irq_enable();
+
+        VM_BUG_ON(nr != (end - start) >> PAGE_SHIFT);
+        return nr;
+
+        {
+                int ret;
+
+slow:
+                local_irq_enable();
+slow_irqon:
+                /* Try to get the remaining pages with get_user_pages */
+                start += nr << PAGE_SHIFT;
+                pages += nr;
+
+                down_read(&mm->mmap_sem);
+                ret = get_user_pages(current, mm, start,
+                        (end - start) >> PAGE_SHIFT, write, 0, pages, NULL);
+                up_read(&mm->mmap_sem);
+
+                /* Have to be a bit careful with return values */
+                if (nr > 0) {
+                        if (ret < 0)
+                                ret = nr;
+                        else
+                                ret += nr;
+                }
+
+                return ret;
+        }
+}
diff --git a/arch/sh/mm/hugetlbpage.c b/arch/sh/mm/hugetlbpage.c
index 9163db3e8d15..d7762349ea48 100644
--- a/arch/sh/mm/hugetlbpage.c
+++ b/arch/sh/mm/hugetlbpage.c
@@ -35,7 +35,7 @@ pte_t *huge_pte_alloc(struct mm_struct *mm,
                 if (pud) {
                         pmd = pmd_alloc(mm, pud, addr);
                         if (pmd)
-                                pte = pte_alloc_map(mm, pmd, addr);
+                                pte = pte_alloc_map(mm, NULL, pmd, addr);
                 }
         }
 
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index d0e249100e98..58a93fb3d965 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -2,7 +2,7 @@
  * linux/arch/sh/mm/init.c
  *
  *  Copyright (C) 1999  Niibe Yutaka
- *  Copyright (C) 2002 - 2010  Paul Mundt
+ *  Copyright (C) 2002 - 2011  Paul Mundt
  *
  *  Based on linux/arch/i386/mm/init.c:
  *   Copyright (C) 1995  Linus Torvalds
@@ -28,7 +28,6 @@
 #include <asm/cache.h>
 #include <asm/sizes.h>
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
 pgd_t swapper_pg_dir[PTRS_PER_PGD];
 
 void __init generic_mem_init(void)
@@ -47,7 +46,6 @@ static pte_t *__get_pte_phys(unsigned long addr)
         pgd_t *pgd;
         pud_t *pud;
         pmd_t *pmd;
-        pte_t *pte;
 
         pgd = pgd_offset_k(addr);
         if (pgd_none(*pgd)) {
@@ -67,8 +65,7 @@ static pte_t *__get_pte_phys(unsigned long addr)
                 return NULL;
         }
 
-        pte = pte_offset_kernel(pmd, addr);
-        return pte;
+        return pte_offset_kernel(pmd, addr);
 }
 
 static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot)
@@ -125,13 +122,45 @@ void __clear_fixmap(enum fixed_addresses idx, pgprot_t prot)
         clear_pte_phys(address, prot);
 }
 
+static pmd_t * __init one_md_table_init(pud_t *pud)
+{
+        if (pud_none(*pud)) {
+                pmd_t *pmd;
+
+                pmd = alloc_bootmem_pages(PAGE_SIZE);
+                pud_populate(&init_mm, pud, pmd);
+                BUG_ON(pmd != pmd_offset(pud, 0));
+        }
+
+        return pmd_offset(pud, 0);
+}
+
+static pte_t * __init one_page_table_init(pmd_t *pmd)
+{
+        if (pmd_none(*pmd)) {
+                pte_t *pte;
+
+                pte = alloc_bootmem_pages(PAGE_SIZE);
+                pmd_populate_kernel(&init_mm, pmd, pte);
+                BUG_ON(pte != pte_offset_kernel(pmd, 0));
+        }
+
+        return pte_offset_kernel(pmd, 0);
+}
+
+static pte_t * __init page_table_kmap_check(pte_t *pte, pmd_t *pmd,
+                                            unsigned long vaddr, pte_t *lastpte)
+{
+        return pte;
+}
+
 void __init page_table_range_init(unsigned long start, unsigned long end,
                                          pgd_t *pgd_base)
 {
         pgd_t *pgd;
         pud_t *pud;
         pmd_t *pmd;
-        pte_t *pte;
+        pte_t *pte = NULL;
         int i, j, k;
         unsigned long vaddr;
 
@@ -144,19 +173,13 @@ void __init page_table_range_init(unsigned long start, unsigned long end,
         for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) {
                 pud = (pud_t *)pgd;
                 for ( ; (j < PTRS_PER_PUD) && (vaddr != end); pud++, j++) {
-#ifdef __PAGETABLE_PMD_FOLDED
-                        pmd = (pmd_t *)pud;
-#else
-                        pmd = (pmd_t *)alloc_bootmem_low_pages(PAGE_SIZE);
-                        pud_populate(&init_mm, pud, pmd);
+                        pmd = one_md_table_init(pud);
+#ifndef __PAGETABLE_PMD_FOLDED
                         pmd += k;
 #endif
                         for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) {
-                                if (pmd_none(*pmd)) {
-                                        pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
-                                        pmd_populate_kernel(&init_mm, pmd, pte);
-                                        BUG_ON(pte != pte_offset_kernel(pmd, 0));
-                                }
+                                pte = page_table_kmap_check(one_page_table_init(pmd),
+                                                            pmd, vaddr, pte);
                                 vaddr += PMD_SIZE;
                         }
                         k = 0;
@@ -200,7 +223,6 @@ static void __init bootmem_init_one_node(unsigned int nid)
         unsigned long total_pages, paddr;
         unsigned long end_pfn;
         struct pglist_data *p;
-        int i;
 
         p = NODE_DATA(nid);
 
@@ -226,11 +248,12 @@ static void __init bootmem_init_one_node(unsigned int nid)
          * reservations in other nodes.
          */
         if (nid == 0) {
+                struct memblock_region *reg;
+
                 /* Reserve the sections we're already using. */
-                for (i = 0; i < memblock.reserved.cnt; i++)
-                        reserve_bootmem(memblock.reserved.region[i].base,
-                                        memblock_size_bytes(&memblock.reserved, i),
-                                        BOOTMEM_DEFAULT);
+                for_each_memblock(reserved, reg) {
+                        reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT);
+                }
         }
 
         sparse_memory_present_with_active_regions(nid);
@@ -238,13 +261,14 @@ static void __init bootmem_init_one_node(unsigned int nid)
 
 static void __init do_init_bootmem(void)
 {
+        struct memblock_region *reg;
         int i;
 
         /* Add active regions with valid PFNs. */
-        for (i = 0; i < memblock.memory.cnt; i++) {
+        for_each_memblock(memory, reg) {
                 unsigned long start_pfn, end_pfn;
-                start_pfn = memblock.memory.region[i].base >> PAGE_SHIFT;
-                end_pfn = start_pfn + memblock_size_pages(&memblock.memory, i);
+                start_pfn = memblock_region_memory_base_pfn(reg);
+                end_pfn = memblock_region_memory_end_pfn(reg);
                 __add_active_range(0, start_pfn, end_pfn);
         }
 
@@ -300,11 +324,17 @@ void __init paging_init(void)
         int nid;
 
         memblock_init();
-
         sh_mv.mv_mem_init();
 
         early_reserve_mem();
 
+        /*
+         * Once the early reservations are out of the way, give the
+         * platforms a chance to kick out some memory.
+         */
+        if (sh_mv.mv_mem_reserve)
+                sh_mv.mv_mem_reserve();
+
         memblock_enforce_memory_limit(memory_limit);
         memblock_analyze();
 
diff --git a/arch/sh/mm/kmap.c b/arch/sh/mm/kmap.c
index 15d74ea42094..ec29e14ec5a8 100644
--- a/arch/sh/mm/kmap.c
+++ b/arch/sh/mm/kmap.c
@@ -34,7 +34,7 @@ void *kmap_coherent(struct page *page, unsigned long addr)
         enum fixed_addresses idx;
         unsigned long vaddr;
 
-        BUG_ON(test_bit(PG_dcache_dirty, &page->flags));
+        BUG_ON(!test_bit(PG_dcache_clean, &page->flags));
 
         pagefault_disable();
 
diff --git a/arch/sh/mm/nommu.c b/arch/sh/mm/nommu.c
index 7694f50c9034..36312d254faf 100644
--- a/arch/sh/mm/nommu.c
+++ b/arch/sh/mm/nommu.c
@@ -67,6 +67,10 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
         BUG();
 }
 
+void __flush_tlb_global(void)
+{
+}
+
 void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 {
 }
diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index 6379091a1647..fad52f1f6812 100644
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -3,7 +3,7 @@
  *
  * Privileged Space Mapping Buffer (PMB) Support.
  *
- * Copyright (C) 2005 - 2010  Paul Mundt
+ * Copyright (C) 2005 - 2011  Paul Mundt
  * Copyright (C) 2010  Matt Fleming
  *
  * This file is subject to the terms and conditions of the GNU General Public
@@ -12,7 +12,7 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/sysdev.h>
+#include <linux/syscore_ops.h>
 #include <linux/cpu.h>
 #include <linux/module.h>
 #include <linux/bitops.h>
@@ -40,7 +40,7 @@ struct pmb_entry {
         unsigned long flags;
         unsigned long size;
 
-        spinlock_t lock;
+        raw_spinlock_t lock;
 
         /*
          * 0 .. NR_PMB_ENTRIES for specific entry selection, or
@@ -265,7 +265,7 @@ static struct pmb_entry *pmb_alloc(unsigned long vpn, unsigned long ppn,
 
         memset(pmbe, 0, sizeof(struct pmb_entry));
 
-        spin_lock_init(&pmbe->lock);
+        raw_spin_lock_init(&pmbe->lock);
 
         pmbe->vpn       = vpn;
         pmbe->ppn       = ppn;
@@ -327,9 +327,9 @@ static void set_pmb_entry(struct pmb_entry *pmbe)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&pmbe->lock, flags);
+        raw_spin_lock_irqsave(&pmbe->lock, flags);
         __set_pmb_entry(pmbe);
-        spin_unlock_irqrestore(&pmbe->lock, flags);
+        raw_spin_unlock_irqrestore(&pmbe->lock, flags);
 }
 #endif /* CONFIG_PM */
 
@@ -368,7 +368,7 @@ int pmb_bolt_mapping(unsigned long vaddr, phys_addr_t phys,
                                 return PTR_ERR(pmbe);
                         }
 
-                        spin_lock_irqsave(&pmbe->lock, flags);
+                        raw_spin_lock_irqsave(&pmbe->lock, flags);
 
                         pmbe->size = pmb_sizes[i].size;
 
@@ -383,9 +383,10 @@ int pmb_bolt_mapping(unsigned long vaddr, phys_addr_t phys,
                          * entries for easier tear-down.
                          */
                         if (likely(pmbp)) {
-                                spin_lock(&pmbp->lock);
+                                raw_spin_lock_nested(&pmbp->lock,
+                                                     SINGLE_DEPTH_NESTING);
                                 pmbp->link = pmbe;
-                                spin_unlock(&pmbp->lock);
+                                raw_spin_unlock(&pmbp->lock);
                         }
 
                         pmbp = pmbe;
@@ -398,7 +399,7 @@ int pmb_bolt_mapping(unsigned long vaddr, phys_addr_t phys,
                         i--;
                         mapped++;
 
-                        spin_unlock_irqrestore(&pmbe->lock, flags);
+                        raw_spin_unlock_irqrestore(&pmbe->lock, flags);
                 }
         } while (size >= SZ_16M);
 
@@ -627,15 +628,14 @@ static void __init pmb_synchronize(void)
                         continue;
                 }
 
-                spin_lock_irqsave(&pmbe->lock, irqflags);
+                raw_spin_lock_irqsave(&pmbe->lock, irqflags);
 
                 for (j = 0; j < ARRAY_SIZE(pmb_sizes); j++)
                         if (pmb_sizes[j].flag == size)
                                 pmbe->size = pmb_sizes[j].size;
 
                 if (pmbp) {
-                        spin_lock(&pmbp->lock);
-
+                        raw_spin_lock_nested(&pmbp->lock, SINGLE_DEPTH_NESTING);
                         /*
                          * Compare the previous entry against the current one to
                          * see if the entries span a contiguous mapping. If so,
@@ -644,13 +644,12 @@ static void __init pmb_synchronize(void)
                          */
                         if (pmb_can_merge(pmbp, pmbe))
                                 pmbp->link = pmbe;
-
-                        spin_unlock(&pmbp->lock);
+                        raw_spin_unlock(&pmbp->lock);
                 }
 
                 pmbp = pmbe;
 
-                spin_unlock_irqrestore(&pmbe->lock, irqflags);
+                raw_spin_unlock_irqrestore(&pmbe->lock, irqflags);
         }
 }
 
@@ -757,7 +756,7 @@ static void __init pmb_resize(void)
                 /*
                  * Found it, now resize it.
                  */
-                spin_lock_irqsave(&pmbe->lock, flags);
+                raw_spin_lock_irqsave(&pmbe->lock, flags);
 
                 pmbe->size = SZ_16M;
                 pmbe->flags &= ~PMB_SZ_MASK;
@@ -767,7 +766,7 @@ static void __init pmb_resize(void)
 
                 __set_pmb_entry(pmbe);
 
-                spin_unlock_irqrestore(&pmbe->lock, flags);
+                raw_spin_unlock_irqrestore(&pmbe->lock, flags);
         }
 
         read_unlock(&pmb_rwlock);
@@ -866,57 +865,40 @@ static int __init pmb_debugfs_init(void)
         struct dentry *dentry;
 
         dentry = debugfs_create_file("pmb", S_IFREG | S_IRUGO,
-                                     sh_debugfs_root, NULL, &pmb_debugfs_fops);
+                                     arch_debugfs_dir, NULL, &pmb_debugfs_fops);
         if (!dentry)
                 return -ENOMEM;
-        if (IS_ERR(dentry))
-                return PTR_ERR(dentry);
 
         return 0;
 }
 subsys_initcall(pmb_debugfs_init);
 
 #ifdef CONFIG_PM
-static int pmb_sysdev_suspend(struct sys_device *dev, pm_message_t state)
+static void pmb_syscore_resume(void)
 {
-        static pm_message_t prev_state;
+        struct pmb_entry *pmbe;
         int i;
 
-        /* Restore the PMB after a resume from hibernation */
-        if (state.event == PM_EVENT_ON &&
-            prev_state.event == PM_EVENT_FREEZE) {
-                struct pmb_entry *pmbe;
-
-                read_lock(&pmb_rwlock);
+        read_lock(&pmb_rwlock);
 
-                for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
-                        if (test_bit(i, pmb_map)) {
-                                pmbe = &pmb_entry_list[i];
-                                set_pmb_entry(pmbe);
-                        }
+        for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
+                if (test_bit(i, pmb_map)) {
+                        pmbe = &pmb_entry_list[i];
+                        set_pmb_entry(pmbe);
                 }
-
-                read_unlock(&pmb_rwlock);
         }
 
-        prev_state = state;
-
-        return 0;
-}
-
-static int pmb_sysdev_resume(struct sys_device *dev)
-{
-        return pmb_sysdev_suspend(dev, PMSG_ON);
+        read_unlock(&pmb_rwlock);
 }
 
-static struct sysdev_driver pmb_sysdev_driver = {
-        .suspend = pmb_sysdev_suspend,
-        .resume = pmb_sysdev_resume,
+static struct syscore_ops pmb_syscore_ops = {
+        .resume = pmb_syscore_resume,
 };
 
 static int __init pmb_sysdev_init(void)
 {
-        return sysdev_driver_register(&cpu_sysdev_class, &pmb_sysdev_driver);
+        register_syscore_ops(&pmb_syscore_ops);
+        return 0;
 }
 subsys_initcall(pmb_sysdev_init);
 #endif
diff --git a/arch/sh/mm/sram.c b/arch/sh/mm/sram.c
new file mode 100644
index 000000000000..bc156ec4545e
--- /dev/null
+++ b/arch/sh/mm/sram.c
@@ -0,0 +1,34 @@
+/*
+ * SRAM pool for tiny memories not otherwise managed.
+ *
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <asm/sram.h>
+
+/*
+ * This provides a standard SRAM pool for tiny memories that can be
+ * added either by the CPU or the platform code. Typical SRAM sizes
+ * to be inserted in to the pool will generally be less than the page
+ * size, with anything more reasonably sized handled as a NUMA memory
+ * node.
+ */
+struct gen_pool *sram_pool;
+
+static int __init sram_pool_init(void)
+{
+        /*
+         * This is a global pool, we don't care about node locality.
+         */
+        sram_pool = gen_pool_create(1, -1);
+        if (unlikely(!sram_pool))
+                return -ENOMEM;
+
+        return 0;
+}
+core_initcall(sram_pool_init);
diff --git a/arch/sh/mm/tlb-debugfs.c b/arch/sh/mm/tlb-debugfs.c
index 229bf75f28df..dea637a09246 100644
--- a/arch/sh/mm/tlb-debugfs.c
+++ b/arch/sh/mm/tlb-debugfs.c
@@ -151,15 +151,13 @@ static int __init tlb_debugfs_init(void)
 {
         struct dentry *itlb, *utlb;
 
-        itlb = debugfs_create_file("itlb", S_IRUSR, sh_debugfs_root,
+        itlb = debugfs_create_file("itlb", S_IRUSR, arch_debugfs_dir,
                                    (unsigned int *)TLB_TYPE_ITLB,
                                    &tlb_debugfs_fops);
         if (unlikely(!itlb))
                 return -ENOMEM;
-        if (IS_ERR(itlb))
-                return PTR_ERR(itlb);
 
-        utlb = debugfs_create_file("utlb", S_IRUSR, sh_debugfs_root,
+        utlb = debugfs_create_file("utlb", S_IRUSR, arch_debugfs_dir,
                                    (unsigned int *)TLB_TYPE_UTLB,
                                    &tlb_debugfs_fops);
         if (unlikely(!utlb)) {
@@ -167,11 +165,6 @@ static int __init tlb_debugfs_init(void)
                 return -ENOMEM;
         }
 
-        if (IS_ERR(utlb)) {
-                debugfs_remove(itlb);
-                return PTR_ERR(utlb);
-        }
-
         return 0;
 }
 module_init(tlb_debugfs_init);
diff --git a/arch/sh/mm/tlbflush_32.c b/arch/sh/mm/tlbflush_32.c
index 3fbe03ce8fe3..a6a20d6de4c0 100644
--- a/arch/sh/mm/tlbflush_32.c
+++ b/arch/sh/mm/tlbflush_32.c
@@ -119,3 +119,19 @@ void local_flush_tlb_mm(struct mm_struct *mm)
                 local_irq_restore(flags);
         }
 }
+
+void __flush_tlb_global(void)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        /*
+         * This is the most destructive of the TLB flushing options,
+         * and will tear down all of the UTLB/ITLB mappings, including
+         * wired entries.
+         */
+        __raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR);
+
+        local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c
index 03db41cc1268..7f5810f5dfdc 100644
--- a/arch/sh/mm/tlbflush_64.c
+++ b/arch/sh/mm/tlbflush_64.c
@@ -455,6 +455,11 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
         flush_tlb_all();
 }
 
+void __flush_tlb_global(void)
+{
+        flush_tlb_all();
+}
+
 void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 {
 }
diff --git a/arch/sh/mm/uncached.c b/arch/sh/mm/uncached.c
index 8a4eca551fc0..a7767da815e9 100644
--- a/arch/sh/mm/uncached.c
+++ b/arch/sh/mm/uncached.c
@@ -28,7 +28,7 @@ EXPORT_SYMBOL(virt_addr_uncached);
 
 void __init uncached_init(void)
 {
-#ifdef CONFIG_29BIT
+#if defined(CONFIG_29BIT) || !defined(CONFIG_MMU)
         uncached_start = P2SEG;
 #else
         uncached_start = memory_end;
diff --git a/arch/sh/oprofile/Makefile b/arch/sh/oprofile/Makefile
index 4886c5c1786c..ce3b119021e7 100644
--- a/arch/sh/oprofile/Makefile
+++ b/arch/sh/oprofile/Makefile
@@ -1,9 +1,15 @@
 obj-$(CONFIG_OPROFILE) += oprofile.o
 
+CFLAGS_common.o += -DUTS_MACHINE='"$(UTS_MACHINE)"'
+
 DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \
                 oprof.o cpu_buffer.o buffer_sync.o \
                 event_buffer.o oprofile_files.o \
                 oprofilefs.o oprofile_stats.o \
                 timer_int.o )
 
+ifeq ($(CONFIG_HW_PERF_EVENTS),y)
+DRIVER_OBJS += $(addprefix ../../../drivers/oprofile/, oprofile_perf.o)
+endif
+
 oprofile-y      := $(DRIVER_OBJS) common.o backtrace.o
diff --git a/arch/sh/oprofile/backtrace.c b/arch/sh/oprofile/backtrace.c
index 2bc74de23f08..9c88dcd56e86 100644
--- a/arch/sh/oprofile/backtrace.c
+++ b/arch/sh/oprofile/backtrace.c
@@ -23,17 +23,6 @@
 #include <asm/sections.h>
 #include <asm/stacktrace.h>
 
-static void backtrace_warning_symbol(void *data, char *msg,
-                                     unsigned long symbol)
-{
-        /* Ignore warnings */
-}
-
-static void backtrace_warning(void *data, char *msg)
-{
-        /* Ignore warnings */
-}
-
 static int backtrace_stack(void *data, char *name)
 {
         /* Yes, we want all stacks */
@@ -49,8 +38,6 @@ static void backtrace_address(void *data, unsigned long addr, int reliable)
 }
 
 static struct stacktrace_ops backtrace_ops = {
-        .warning = backtrace_warning,
-        .warning_symbol = backtrace_warning_symbol,
         .stack = backtrace_stack,
         .address = backtrace_address,
 };
@@ -91,7 +78,7 @@ void sh_backtrace(struct pt_regs * const regs, unsigned int depth)
         if (depth > backtrace_limit)
                 depth = backtrace_limit;
 
-        stackaddr = (unsigned long *)regs->regs[15];
+        stackaddr = (unsigned long *)kernel_stack_pointer(regs);
         if (!user_mode(regs)) {
                 if (depth)
                         unwind_stack(NULL, regs, stackaddr,
diff --git a/arch/sh/oprofile/common.c b/arch/sh/oprofile/common.c
index ac604937f3ee..b4c2d2b946dd 100644
--- a/arch/sh/oprofile/common.c
+++ b/arch/sh/oprofile/common.c
@@ -1,7 +1,7 @@
 /*
  * arch/sh/oprofile/init.c
  *
- * Copyright (C) 2003 - 2008  Paul Mundt
+ * Copyright (C) 2003 - 2010  Paul Mundt
  *
  * Based on arch/mips/oprofile/common.c:
  *
@@ -17,114 +17,48 @@
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
+#include <linux/perf_event.h>
+#include <linux/slab.h>
 #include <asm/processor.h>
-#include "op_impl.h"
-
-static struct op_sh_model *model;
-
-static struct op_counter_config ctr[20];
 
 extern void sh_backtrace(struct pt_regs * const regs, unsigned int depth);
 
-static int op_sh_setup(void)
-{
-        /* Pre-compute the values to stuff in the hardware registers.  */
-        model->reg_setup(ctr);
-
-        /* Configure the registers on all cpus.  */
-        on_each_cpu(model->cpu_setup, NULL, 1);
-
-        return 0;
-}
-
-static int op_sh_create_files(struct super_block *sb, struct dentry *root)
-{
-        int i, ret = 0;
-
-        for (i = 0; i < model->num_counters; i++) {
-                struct dentry *dir;
-                char buf[4];
-
-                snprintf(buf, sizeof(buf), "%d", i);
-                dir = oprofilefs_mkdir(sb, root, buf);
-
-                ret |= oprofilefs_create_ulong(sb, dir, "enabled", &ctr[i].enabled);
-                ret |= oprofilefs_create_ulong(sb, dir, "event", &ctr[i].event);
-                ret |= oprofilefs_create_ulong(sb, dir, "kernel", &ctr[i].kernel);
-                ret |= oprofilefs_create_ulong(sb, dir, "user", &ctr[i].user);
-
-                if (model->create_files)
-                        ret |= model->create_files(sb, dir);
-                else
-                        ret |= oprofilefs_create_ulong(sb, dir, "count", &ctr[i].count);
-
-                /* Dummy entries */
-                ret |= oprofilefs_create_ulong(sb, dir, "unit_mask", &ctr[i].unit_mask);
-        }
-
-        return ret;
-}
-
-static int op_sh_start(void)
-{
-        /* Enable performance monitoring for all counters.  */
-        on_each_cpu(model->cpu_start, NULL, 1);
-
-        return 0;
-}
+#ifdef CONFIG_HW_PERF_EVENTS
+/*
+ * This will need to be reworked when multiple PMUs are supported.
+ */
+static char *sh_pmu_op_name;
 
-static void op_sh_stop(void)
+char *op_name_from_perf_id(void)
 {
-        /* Disable performance monitoring for all counters.  */
-        on_each_cpu(model->cpu_stop, NULL, 1);
+        return sh_pmu_op_name;
 }
 
 int __init oprofile_arch_init(struct oprofile_operations *ops)
 {
-        struct op_sh_model *lmodel = NULL;
-        int ret;
-
-        /*
-         * Always assign the backtrace op. If the counter initialization
-         * fails, we fall back to the timer which will still make use of
-         * this.
-         */
         ops->backtrace = sh_backtrace;
 
-        /*
-         * XXX
-         *
-         * All of the SH7750/SH-4A counters have been converted to perf,
-         * this infrastructure hook is left for other users until they've
-         * had a chance to convert over, at which point all of this
-         * will be deleted.
-         */
-
-        if (!lmodel)
-                return -ENODEV;
-        if (!(current_cpu_data.flags & CPU_HAS_PERF_COUNTER))
+        if (perf_num_counters() == 0)
                 return -ENODEV;
 
-        ret = lmodel->init();
-        if (unlikely(ret != 0))
-                return ret;
+        sh_pmu_op_name = kasprintf(GFP_KERNEL, "%s/%s",
+                                   UTS_MACHINE, perf_pmu_name());
+        if (unlikely(!sh_pmu_op_name))
+                return -ENOMEM;
 
-        model = lmodel;
-
-        ops->setup              = op_sh_setup;
-        ops->create_files       = op_sh_create_files;
-        ops->start              = op_sh_start;
-        ops->stop               = op_sh_stop;
-        ops->cpu_type           = lmodel->cpu_type;
-
-        printk(KERN_INFO "oprofile: using %s performance monitoring.\n",
-               lmodel->cpu_type);
-
-        return 0;
+        return oprofile_perf_init(ops);
 }
 
-void oprofile_arch_exit(void)
+void __exit oprofile_arch_exit(void)
 {
-        if (model && model->exit)
-                model->exit();
+        oprofile_perf_exit();
+        kfree(sh_pmu_op_name);
+}
+#else
+int __init oprofile_arch_init(struct oprofile_operations *ops)
+{
+        ops->backtrace = sh_backtrace;
+        return -ENODEV;
 }
+void __exit oprofile_arch_exit(void) {}
+#endif /* CONFIG_HW_PERF_EVENTS */
diff --git a/arch/sh/oprofile/op_impl.h b/arch/sh/oprofile/op_impl.h
deleted file mode 100644
index 1244479ceb29..000000000000
--- a/arch/sh/oprofile/op_impl.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __OP_IMPL_H
-#define __OP_IMPL_H
-
-/* Per-counter configuration as set via oprofilefs.  */
-struct op_counter_config {
-        unsigned long enabled;
-        unsigned long event;
-
-        unsigned long count;
-
-        /* Dummy values for userspace tool compliance */
-        unsigned long kernel;
-        unsigned long user;
-        unsigned long unit_mask;
-};
-
-/* Per-architecture configury and hooks.  */
-struct op_sh_model {
-        void (*reg_setup)(struct op_counter_config *);
-        int (*create_files)(struct super_block *sb, struct dentry *dir);
-        void (*cpu_setup)(void *dummy);
-        int (*init)(void);
-        void (*exit)(void);
-        void (*cpu_start)(void *args);
-        void (*cpu_stop)(void *args);
-        char *cpu_type;
-        unsigned char num_counters;
-};
-
-/* arch/sh/oprofile/common.c */
-extern void sh_backtrace(struct pt_regs * const regs, unsigned int depth);
-
-#endif /* __OP_IMPL_H */
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index b25aa554ee5e..6dd56c4d0054 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -9,6 +9,7 @@ SE			SH_SOLUTION_ENGINE
 HIGHLANDER              SH_HIGHLANDER
 RTS7751R2D              SH_RTS7751R2D
 RSK                     SH_RSK
+ALPHA_BOARD             SH_ALPHA_BOARD
 
 #
 # List of companion chips / MFDs.
@@ -26,7 +27,6 @@ HD64461			HD64461
 7724SE                  SH_7724_SOLUTION_ENGINE
 7751SE                  SH_7751_SOLUTION_ENGINE
 7780SE                  SH_7780_SOLUTION_ENGINE
-7751SYSTEMH             SH_7751_SYSTEMH
 HP6XX                   SH_HP6XX
 DREAMCAST               SH_DREAMCAST
 SNAPGEAR                SH_SECUREEDGE5410
@@ -52,6 +52,8 @@ MIGOR			SH_MIGOR
 RSK7201                 SH_RSK7201
 RSK7203                 SH_RSK7203
 AP325RXA                SH_AP325RXA
+SH2007                  SH_SH2007
+SH7757LCR               SH_SH7757LCR
 SH7763RDP               SH_SH7763RDP
 SH7785LCR               SH_SH7785LCR
 SH7785LCR_PT            SH_SH7785LCR_PT
@@ -60,3 +62,5 @@ ESPT			SH_ESPT
 POLARIS                 SH_POLARIS
 KFR2R09                 SH_KFR2R09
 ECOVEC                  SH_ECOVEC
+APSH4A3A                SH_APSH4A3A
+APSH4AD0A               SH_APSH4AD0A