diff options
author | Paul Mundt <lethal@linux-sh.org> | 2010-04-04 23:21:09 -0400 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2010-04-04 23:21:09 -0400 |
commit | 94a46d3cde81fc82eef2105fcb5c9e6e31bac0f7 (patch) | |
tree | 445ff43779938b539e0799e81c90b85bbee552cd /arch/sh/mm | |
parent | 720fcb36ac1aa2df2c54c170253b6b29600cbefc (diff) | |
parent | db217dece3003df0841bacf9556b5c06aa097dae (diff) |
Merge branch 'sh/stable-updates'
Diffstat (limited to 'arch/sh/mm')
-rw-r--r-- | arch/sh/mm/tlb-pteaex.c | 28 | ||||
-rw-r--r-- | arch/sh/mm/tlb-sh3.c | 19 | ||||
-rw-r--r-- | arch/sh/mm/tlb-sh4.c | 28 | ||||
-rw-r--r-- | arch/sh/mm/tlbflush_32.c | 28 |
4 files changed, 75 insertions, 28 deletions
diff --git a/arch/sh/mm/tlb-pteaex.c b/arch/sh/mm/tlb-pteaex.c index bdd0982b56ee..b71db6af8060 100644 --- a/arch/sh/mm/tlb-pteaex.c +++ b/arch/sh/mm/tlb-pteaex.c | |||
@@ -77,3 +77,31 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page) | |||
77 | __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); | 77 | __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); |
78 | back_to_cached(); | 78 | back_to_cached(); |
79 | } | 79 | } |
80 | |||
81 | void local_flush_tlb_all(void) | ||
82 | { | ||
83 | unsigned long flags, status; | ||
84 | int i; | ||
85 | |||
86 | /* | ||
87 | * Flush all the TLB. | ||
88 | */ | ||
89 | local_irq_save(flags); | ||
90 | jump_to_uncached(); | ||
91 | |||
92 | status = __raw_readl(MMUCR); | ||
93 | status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT); | ||
94 | |||
95 | if (status == 0) | ||
96 | status = MMUCR_URB_NENTRIES; | ||
97 | |||
98 | for (i = 0; i < status; i++) | ||
99 | __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); | ||
100 | |||
101 | for (i = 0; i < 4; i++) | ||
102 | __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); | ||
103 | |||
104 | back_to_cached(); | ||
105 | ctrl_barrier(); | ||
106 | local_irq_restore(flags); | ||
107 | } | ||
diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c index 4f5f7cbdd508..7a940dbfc2e9 100644 --- a/arch/sh/mm/tlb-sh3.c +++ b/arch/sh/mm/tlb-sh3.c | |||
@@ -77,3 +77,22 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page) | |||
77 | for (i = 0; i < ways; i++) | 77 | for (i = 0; i < ways; i++) |
78 | __raw_writel(data, addr + (i << 8)); | 78 | __raw_writel(data, addr + (i << 8)); |
79 | } | 79 | } |
80 | |||
81 | void local_flush_tlb_all(void) | ||
82 | { | ||
83 | unsigned long flags, status; | ||
84 | |||
85 | /* | ||
86 | * Flush all the TLB. | ||
87 | * | ||
88 | * Write to the MMU control register's bit: | ||
89 | * TF-bit for SH-3, TI-bit for SH-4. | ||
90 | * It's same position, bit #2. | ||
91 | */ | ||
92 | local_irq_save(flags); | ||
93 | status = __raw_readl(MMUCR); | ||
94 | status |= 0x04; | ||
95 | __raw_writel(status, MMUCR); | ||
96 | ctrl_barrier(); | ||
97 | local_irq_restore(flags); | ||
98 | } | ||
diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c index ccac77f504a8..cfdf7930d294 100644 --- a/arch/sh/mm/tlb-sh4.c +++ b/arch/sh/mm/tlb-sh4.c | |||
@@ -80,3 +80,31 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page) | |||
80 | __raw_writel(data, addr); | 80 | __raw_writel(data, addr); |
81 | back_to_cached(); | 81 | back_to_cached(); |
82 | } | 82 | } |
83 | |||
84 | void local_flush_tlb_all(void) | ||
85 | { | ||
86 | unsigned long flags, status; | ||
87 | int i; | ||
88 | |||
89 | /* | ||
90 | * Flush all the TLB. | ||
91 | */ | ||
92 | local_irq_save(flags); | ||
93 | jump_to_uncached(); | ||
94 | |||
95 | status = __raw_readl(MMUCR); | ||
96 | status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT); | ||
97 | |||
98 | if (status == 0) | ||
99 | status = MMUCR_URB_NENTRIES; | ||
100 | |||
101 | for (i = 0; i < status; i++) | ||
102 | __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); | ||
103 | |||
104 | for (i = 0; i < 4; i++) | ||
105 | __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); | ||
106 | |||
107 | back_to_cached(); | ||
108 | ctrl_barrier(); | ||
109 | local_irq_restore(flags); | ||
110 | } | ||
diff --git a/arch/sh/mm/tlbflush_32.c b/arch/sh/mm/tlbflush_32.c index 77dc5efa7127..3fbe03ce8fe3 100644 --- a/arch/sh/mm/tlbflush_32.c +++ b/arch/sh/mm/tlbflush_32.c | |||
@@ -119,31 +119,3 @@ void local_flush_tlb_mm(struct mm_struct *mm) | |||
119 | local_irq_restore(flags); | 119 | local_irq_restore(flags); |
120 | } | 120 | } |
121 | } | 121 | } |
122 | |||
123 | void local_flush_tlb_all(void) | ||
124 | { | ||
125 | unsigned long flags, status; | ||
126 | int i; | ||
127 | |||
128 | /* | ||
129 | * Flush all the TLB. | ||
130 | */ | ||
131 | local_irq_save(flags); | ||
132 | jump_to_uncached(); | ||
133 | |||
134 | status = __raw_readl(MMUCR); | ||
135 | status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT); | ||
136 | |||
137 | if (status == 0) | ||
138 | status = MMUCR_URB_NENTRIES; | ||
139 | |||
140 | for (i = 0; i < status; i++) | ||
141 | __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); | ||
142 | |||
143 | for (i = 0; i < 4; i++) | ||
144 | __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); | ||
145 | |||
146 | back_to_cached(); | ||
147 | ctrl_barrier(); | ||
148 | local_irq_restore(flags); | ||
149 | } | ||