diff options
author | Paul Mundt <lethal@linux-sh.org> | 2011-01-13 01:06:28 -0500 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2011-01-13 01:06:28 -0500 |
commit | f43dc23d5ea91fca257be02138a255f02d98e806 (patch) | |
tree | b29722f6e965316e90ac97abf79923ced250dc21 /arch/sh/mm/tlb-pteaex.c | |
parent | f8e53553f452dcbf67cb89c8cba63a1cd6eb4cc0 (diff) | |
parent | 4162cf64973df51fc885825bc9ca4d055891c49f (diff) |
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into common/serial-rework
Conflicts:
arch/sh/kernel/cpu/sh2/setup-sh7619.c
arch/sh/kernel/cpu/sh2a/setup-mxg.c
arch/sh/kernel/cpu/sh2a/setup-sh7201.c
arch/sh/kernel/cpu/sh2a/setup-sh7203.c
arch/sh/kernel/cpu/sh2a/setup-sh7206.c
arch/sh/kernel/cpu/sh3/setup-sh7705.c
arch/sh/kernel/cpu/sh3/setup-sh770x.c
arch/sh/kernel/cpu/sh3/setup-sh7710.c
arch/sh/kernel/cpu/sh3/setup-sh7720.c
arch/sh/kernel/cpu/sh4/setup-sh4-202.c
arch/sh/kernel/cpu/sh4/setup-sh7750.c
arch/sh/kernel/cpu/sh4/setup-sh7760.c
arch/sh/kernel/cpu/sh4a/setup-sh7343.c
arch/sh/kernel/cpu/sh4a/setup-sh7366.c
arch/sh/kernel/cpu/sh4a/setup-sh7722.c
arch/sh/kernel/cpu/sh4a/setup-sh7723.c
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
arch/sh/kernel/cpu/sh4a/setup-sh7763.c
arch/sh/kernel/cpu/sh4a/setup-sh7770.c
arch/sh/kernel/cpu/sh4a/setup-sh7780.c
arch/sh/kernel/cpu/sh4a/setup-sh7785.c
arch/sh/kernel/cpu/sh4a/setup-sh7786.c
arch/sh/kernel/cpu/sh4a/setup-shx3.c
arch/sh/kernel/cpu/sh5/setup-sh5.c
drivers/serial/sh-sci.c
drivers/serial/sh-sci.h
include/linux/serial_sci.h
Diffstat (limited to 'arch/sh/mm/tlb-pteaex.c')
-rw-r--r-- | arch/sh/mm/tlb-pteaex.c | 61 |
1 files changed, 36 insertions, 25 deletions
diff --git a/arch/sh/mm/tlb-pteaex.c b/arch/sh/mm/tlb-pteaex.c index 2aab3ea934d7..b71db6af8060 100644 --- a/arch/sh/mm/tlb-pteaex.c +++ b/arch/sh/mm/tlb-pteaex.c | |||
@@ -16,34 +16,16 @@ | |||
16 | #include <asm/mmu_context.h> | 16 | #include <asm/mmu_context.h> |
17 | #include <asm/cacheflush.h> | 17 | #include <asm/cacheflush.h> |
18 | 18 | ||
19 | void update_mmu_cache(struct vm_area_struct * vma, | 19 | void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) |
20 | unsigned long address, pte_t pte) | ||
21 | { | 20 | { |
22 | unsigned long flags; | 21 | unsigned long flags, pteval, vpn; |
23 | unsigned long pteval; | ||
24 | unsigned long vpn; | ||
25 | 22 | ||
26 | /* Ptrace may call this routine. */ | 23 | /* |
24 | * Handle debugger faulting in for debugee. | ||
25 | */ | ||
27 | if (vma && current->active_mm != vma->vm_mm) | 26 | if (vma && current->active_mm != vma->vm_mm) |
28 | return; | 27 | return; |
29 | 28 | ||
30 | #ifndef CONFIG_CACHE_OFF | ||
31 | { | ||
32 | unsigned long pfn = pte_pfn(pte); | ||
33 | |||
34 | if (pfn_valid(pfn)) { | ||
35 | struct page *page = pfn_to_page(pfn); | ||
36 | |||
37 | if (!test_bit(PG_mapped, &page->flags)) { | ||
38 | unsigned long phys = pte_val(pte) & PTE_PHYS_MASK; | ||
39 | __flush_wback_region((void *)P1SEGADDR(phys), | ||
40 | PAGE_SIZE); | ||
41 | __set_bit(PG_mapped, &page->flags); | ||
42 | } | ||
43 | } | ||
44 | } | ||
45 | #endif | ||
46 | |||
47 | local_irq_save(flags); | 29 | local_irq_save(flags); |
48 | 30 | ||
49 | /* Set PTEH register */ | 31 | /* Set PTEH register */ |
@@ -86,11 +68,40 @@ void update_mmu_cache(struct vm_area_struct * vma, | |||
86 | * in extended mode, the legacy 8-bit ASID field in address array 1 has | 68 | * in extended mode, the legacy 8-bit ASID field in address array 1 has |
87 | * undefined behaviour. | 69 | * undefined behaviour. |
88 | */ | 70 | */ |
89 | void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid, | 71 | void local_flush_tlb_one(unsigned long asid, unsigned long page) |
90 | unsigned long page) | ||
91 | { | 72 | { |
92 | jump_to_uncached(); | 73 | jump_to_uncached(); |
93 | __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); | 74 | __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); |
94 | __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); | 75 | __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); |
76 | __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); | ||
77 | __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); | ||
95 | back_to_cached(); | 78 | back_to_cached(); |
96 | } | 79 | } |
80 | |||
81 | void local_flush_tlb_all(void) | ||
82 | { | ||
83 | unsigned long flags, status; | ||
84 | int i; | ||
85 | |||
86 | /* | ||
87 | * Flush all the TLB. | ||
88 | */ | ||
89 | local_irq_save(flags); | ||
90 | jump_to_uncached(); | ||
91 | |||
92 | status = __raw_readl(MMUCR); | ||
93 | status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT); | ||
94 | |||
95 | if (status == 0) | ||
96 | status = MMUCR_URB_NENTRIES; | ||
97 | |||
98 | for (i = 0; i < status; i++) | ||
99 | __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); | ||
100 | |||
101 | for (i = 0; i < 4; i++) | ||
102 | __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); | ||
103 | |||
104 | back_to_cached(); | ||
105 | ctrl_barrier(); | ||
106 | local_irq_restore(flags); | ||
107 | } | ||