Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (187 commits)
  sh: remove dead LED code for migo-r and ms7724se
  sh: ecovec build fix for CONFIG_I2C=n
  sh: ecovec r-standby support
  sh: ms7724se r-standby support
  sh: SH-Mobile R-standby register save/restore
  clocksource: Fix up a registration/IRQ race in the sh drivers.
  sh: ms7724: modify scan_timing for KEYSC
  sh: ms7724: Add sh_sir support
  sh: mach-ecovec24: Add sh_sir support
  sh: wire up SET/GET_UNALIGN_CTL.
  sh: allow alignment fault mode to be configured at kernel boot.
  sh: sh7724: Update FSI/SPU2 clock
  sh: always enable sh7724 vpu_clk and set to 166MHz on Ecovec
  sh: add sh7724 kick callback to clk_div4_table
  sh: introduce struct clk_div4_table
  sh: clock-cpg div4 set_rate() shift fix
  sh: Turn on speculative return for SH7785 and SH7786
  sh: Merge legacy and dynamic PMB modes.
  sh: Use uncached I/O helpers in PMB setup.
  sh: Provide uncached I/O helpers.
  ...

1 files changed, 13 insertions, 35 deletions

diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 986a71b88ca3..1445ca6257df 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -75,52 +75,25 @@ config MEMORY_SIZE
 config 29BIT
         def_bool !32BIT
         depends on SUPERH32
+        select UNCACHED_MAPPING
 
 config 32BIT
         bool
         default y if CPU_SH5
 
-config PMB_ENABLE
-        bool "Support 32-bit physical addressing through PMB"
-        depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP
-        help
-          If you say Y here, physical addressing will be extended to
-          32-bits through the SH-4A PMB. If this is not set, legacy
-          29-bit physical addressing will be used.
-
-choice
-        prompt "PMB handling type"
-        depends on PMB_ENABLE
-        default PMB_FIXED
-
 config PMB
-        bool "PMB"
+        bool "Support 32-bit physical addressing through PMB"
         depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP
+        select 32BIT
+        select UNCACHED_MAPPING
         help
           If you say Y here, physical addressing will be extended to
           32-bits through the SH-4A PMB. If this is not set, legacy
           29-bit physical addressing will be used.
 
-config PMB_FIXED
-        bool "fixed PMB"
-        depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP
-        select 32BIT
-        help
-          If this option is enabled, fixed PMB mappings are inherited
-          from the boot loader, and the kernel does not attempt dynamic
-          management. This is the closest to legacy 29-bit physical mode,
-          and allows systems to support up to 512MiB of system memory.
-
-endchoice
-
 config X2TLB
-        bool "Enable extended TLB mode"
-        depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
-        help
-          Selecting this option will enable the extended mode of the SH-X2
-          TLB. For legacy SH-X behaviour and interoperability, say N. For
-          all of the fun new features and a willingless to submit bug reports,
-          say Y.
+        def_bool y
+        depends on (CPU_SHX2 || CPU_SHX3) && MMU
 
 config VSYSCALL
         bool "Support vsyscall page"
@@ -188,14 +161,19 @@ config ARCH_MEMORY_PROBE
         def_bool y
         depends on MEMORY_HOTPLUG
 
+config IOREMAP_FIXED
+       def_bool y
+       depends on X2TLB || SUPERH64
+
+config UNCACHED_MAPPING
+        bool
+
 choice
         prompt "Kernel page size"
-        default PAGE_SIZE_8KB if X2TLB
         default PAGE_SIZE_4KB
 
 config PAGE_SIZE_4KB
         bool "4kB"
-        depends on !MMU || !X2TLB
         help
           This is the default page size used by all SuperH CPUs.