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authorLinus Torvalds <torvalds@linux-foundation.org>2008-10-20 12:13:34 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-10-20 12:13:34 -0400
commited402af3c23a4804b3f8899263e8d0f97c62ab49 (patch)
tree3aa971aea57f900a3060cc0545b199ef611f4dcf /arch/sh/kernel
parent096e6f673dc02a6394dc9a7d8f8735c6978f5b91 (diff)
parent40e24c403f325715f9c43b9fed2068641201ee0b (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (112 commits) sh: Move SH-4 CPU headers down one more level. sh: Only build in gpio.o when CONFIG_GENERIC_GPIO is selected. sh: Migrate common board headers to mach-common/. sh: Move the CPU definition headers from asm/ to cpu/. serial: sh-sci: Add support SCIF of SH7723 video: add sh_mobile_lcdc platform flags video: remove unused sh_mobile_lcdc platform data sh: remove consistent alloc cruft sh: add dynamic crash base address support sh: reduce Migo-R smc91x overruns sh: Fix up some merge damage. Fix debugfs_create_file's error checking method for arch/sh/mm/ Fix debugfs_create_dir's error checking method for arch/sh/kernel/ sh: ap325rxa: Add support RTC RX-8564LC in AP325RXA board sh: Use sh7720 GPIO on magicpanelr2 board sh: Add sh7720 pinmux code sh: Use sh7203 GPIO on rsk7203 board sh: Add sh7203 pinmux code sh: Use sh7723 GPIO on AP325RXA board sh: Add sh7723 pinmux code ...
Diffstat (limited to 'arch/sh/kernel')
-rw-r--r--arch/sh/kernel/Makefile_323
-rw-r--r--arch/sh/kernel/Makefile_642
-rw-r--r--arch/sh/kernel/cpu/clock.c5
-rw-r--r--arch/sh/kernel/cpu/irq/Makefile2
-rw-r--r--arch/sh/kernel/cpu/irq/intc.c710
-rw-r--r--arch/sh/kernel/cpu/irq/ipr.c4
-rw-r--r--arch/sh/kernel/cpu/sh2a/Makefile5
-rw-r--r--arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c1599
-rw-r--r--arch/sh/kernel/cpu/sh3/Makefile4
-rw-r--r--arch/sh/kernel/cpu/sh3/pinmux-sh7720.c1242
-rw-r--r--arch/sh/kernel/cpu/sh4/fpu.c25
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c5
-rw-r--r--arch/sh/kernel/cpu/sh4/softfloat.c29
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile5
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c1783
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c1909
-rw-r--r--arch/sh/kernel/cpu/sh4a/smp-shx3.c67
-rw-r--r--arch/sh/kernel/cpu/sh5/Makefile5
-rw-r--r--arch/sh/kernel/cpu/sh5/clock-sh5.c79
-rw-r--r--arch/sh/kernel/dump_task.c32
-rw-r--r--arch/sh/kernel/entry-common.S44
-rw-r--r--arch/sh/kernel/gpio.c498
-rw-r--r--arch/sh/kernel/io.c12
-rw-r--r--arch/sh/kernel/io_generic.c67
-rw-r--r--arch/sh/kernel/kprobes.c584
-rw-r--r--arch/sh/kernel/machvec.c4
-rw-r--r--arch/sh/kernel/process_32.c36
-rw-r--r--arch/sh/kernel/process_64.c11
-rw-r--r--arch/sh/kernel/ptrace_32.c298
-rw-r--r--arch/sh/kernel/ptrace_64.c1
-rw-r--r--arch/sh/kernel/setup.c65
-rw-r--r--arch/sh/kernel/sh_ksyms_32.c4
-rw-r--r--arch/sh/kernel/signal_32.c69
-rw-r--r--arch/sh/kernel/signal_64.c26
-rw-r--r--arch/sh/kernel/smp.c43
-rw-r--r--arch/sh/kernel/stacktrace.c23
-rw-r--r--arch/sh/kernel/sys_sh.c9
-rw-r--r--arch/sh/kernel/sys_sh32.c5
-rw-r--r--arch/sh/kernel/time_32.c11
-rw-r--r--arch/sh/kernel/time_64.c168
-rw-r--r--arch/sh/kernel/timers/Makefile1
-rw-r--r--arch/sh/kernel/timers/timer-broadcast.c57
-rw-r--r--arch/sh/kernel/timers/timer-cmt.c2
-rw-r--r--arch/sh/kernel/timers/timer-tmu.c177
-rw-r--r--arch/sh/kernel/traps_32.c95
45 files changed, 8581 insertions, 1244 deletions
diff --git a/arch/sh/kernel/Makefile_32 b/arch/sh/kernel/Makefile_32
index 0e6905fe9fec..48edfb145fb4 100644
--- a/arch/sh/kernel/Makefile_32
+++ b/arch/sh/kernel/Makefile_32
@@ -21,7 +21,8 @@ obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
21obj-$(CONFIG_CRASH_DUMP) += crash_dump.o 21obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
22obj-$(CONFIG_PM) += pm.o 22obj-$(CONFIG_PM) += pm.o
23obj-$(CONFIG_STACKTRACE) += stacktrace.o 23obj-$(CONFIG_STACKTRACE) += stacktrace.o
24obj-$(CONFIG_ELF_CORE) += dump_task.o
25obj-$(CONFIG_IO_TRAPPED) += io_trapped.o 24obj-$(CONFIG_IO_TRAPPED) += io_trapped.o
25obj-$(CONFIG_KPROBES) += kprobes.o
26obj-$(CONFIG_GENERIC_GPIO) += gpio.o
26 27
27EXTRA_CFLAGS += -Werror 28EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/Makefile_64 b/arch/sh/kernel/Makefile_64
index 6edf53b93d94..c97660b2b48d 100644
--- a/arch/sh/kernel/Makefile_64
+++ b/arch/sh/kernel/Makefile_64
@@ -17,7 +17,7 @@ obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
17obj-$(CONFIG_CRASH_DUMP) += crash_dump.o 17obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
18obj-$(CONFIG_PM) += pm.o 18obj-$(CONFIG_PM) += pm.o
19obj-$(CONFIG_STACKTRACE) += stacktrace.o 19obj-$(CONFIG_STACKTRACE) += stacktrace.o
20obj-$(CONFIG_BINFMT_ELF) += dump_task.o
21obj-$(CONFIG_IO_TRAPPED) += io_trapped.o 20obj-$(CONFIG_IO_TRAPPED) += io_trapped.o
21obj-$(CONFIG_GENERIC_GPIO) += gpio.o
22 22
23EXTRA_CFLAGS += -Werror 23EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index f5eb56e6bc59..b7e46d5bba43 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -294,9 +294,10 @@ arch_init_clk_ops(struct clk_ops **ops, int type)
294{ 294{
295} 295}
296 296
297void __init __attribute__ ((weak)) 297int __init __attribute__ ((weak))
298arch_clk_init(void) 298arch_clk_init(void)
299{ 299{
300 return 0;
300} 301}
301 302
302static int show_clocks(char *buf, char **start, off_t off, 303static int show_clocks(char *buf, char **start, off_t off,
@@ -331,7 +332,7 @@ int __init clk_init(void)
331 ret |= clk_register(clk); 332 ret |= clk_register(clk);
332 } 333 }
333 334
334 arch_clk_init(); 335 ret |= arch_clk_init();
335 336
336 /* Kick the child clocks.. */ 337 /* Kick the child clocks.. */
337 propagate_rate(&master_clk); 338 propagate_rate(&master_clk);
diff --git a/arch/sh/kernel/cpu/irq/Makefile b/arch/sh/kernel/cpu/irq/Makefile
index 462a8f6dfee2..f0c7025a67d1 100644
--- a/arch/sh/kernel/cpu/irq/Makefile
+++ b/arch/sh/kernel/cpu/irq/Makefile
@@ -1,8 +1,6 @@
1# 1#
2# Makefile for the Linux/SuperH CPU-specifc IRQ handlers. 2# Makefile for the Linux/SuperH CPU-specifc IRQ handlers.
3# 3#
4obj-y += intc.o
5
6obj-$(CONFIG_SUPERH32) += imask.o 4obj-$(CONFIG_SUPERH32) += imask.o
7obj-$(CONFIG_CPU_SH5) += intc-sh5.o 5obj-$(CONFIG_CPU_SH5) += intc-sh5.o
8obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o 6obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o
diff --git a/arch/sh/kernel/cpu/irq/intc.c b/arch/sh/kernel/cpu/irq/intc.c
deleted file mode 100644
index 8c70e201bde0..000000000000
--- a/arch/sh/kernel/cpu/irq/intc.c
+++ /dev/null
@@ -1,710 +0,0 @@
1/*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007, 2008 Magnus Damm
5 *
6 * Based on intc2.c and ipr.c
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
13 *
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
16 * for more details.
17 */
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/module.h>
21#include <linux/io.h>
22#include <linux/interrupt.h>
23#include <linux/bootmem.h>
24
25#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
26 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
27 ((addr_e) << 16) | ((addr_d << 24)))
28
29#define _INTC_SHIFT(h) (h & 0x1f)
30#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
31#define _INTC_FN(h) ((h >> 9) & 0xf)
32#define _INTC_MODE(h) ((h >> 13) & 0x7)
33#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
34#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
35
36struct intc_handle_int {
37 unsigned int irq;
38 unsigned long handle;
39};
40
41struct intc_desc_int {
42 unsigned long *reg;
43#ifdef CONFIG_SMP
44 unsigned long *smp;
45#endif
46 unsigned int nr_reg;
47 struct intc_handle_int *prio;
48 unsigned int nr_prio;
49 struct intc_handle_int *sense;
50 unsigned int nr_sense;
51 struct irq_chip chip;
52};
53
54#ifdef CONFIG_SMP
55#define IS_SMP(x) x.smp
56#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
57#define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
58#else
59#define IS_SMP(x) 0
60#define INTC_REG(d, x, c) (d->reg[(x)])
61#define SMP_NR(d, x) 1
62#endif
63
64static unsigned int intc_prio_level[NR_IRQS]; /* for now */
65#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
66static unsigned long ack_handle[NR_IRQS];
67#endif
68
69static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
70{
71 struct irq_chip *chip = get_irq_chip(irq);
72 return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
73}
74
75static inline unsigned int set_field(unsigned int value,
76 unsigned int field_value,
77 unsigned int handle)
78{
79 unsigned int width = _INTC_WIDTH(handle);
80 unsigned int shift = _INTC_SHIFT(handle);
81
82 value &= ~(((1 << width) - 1) << shift);
83 value |= field_value << shift;
84 return value;
85}
86
87static void write_8(unsigned long addr, unsigned long h, unsigned long data)
88{
89 ctrl_outb(set_field(0, data, h), addr);
90}
91
92static void write_16(unsigned long addr, unsigned long h, unsigned long data)
93{
94 ctrl_outw(set_field(0, data, h), addr);
95}
96
97static void write_32(unsigned long addr, unsigned long h, unsigned long data)
98{
99 ctrl_outl(set_field(0, data, h), addr);
100}
101
102static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
103{
104 unsigned long flags;
105 local_irq_save(flags);
106 ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
107 local_irq_restore(flags);
108}
109
110static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
111{
112 unsigned long flags;
113 local_irq_save(flags);
114 ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
115 local_irq_restore(flags);
116}
117
118static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
119{
120 unsigned long flags;
121 local_irq_save(flags);
122 ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
123 local_irq_restore(flags);
124}
125
126enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
127
128static void (*intc_reg_fns[])(unsigned long addr,
129 unsigned long h,
130 unsigned long data) = {
131 [REG_FN_WRITE_BASE + 0] = write_8,
132 [REG_FN_WRITE_BASE + 1] = write_16,
133 [REG_FN_WRITE_BASE + 3] = write_32,
134 [REG_FN_MODIFY_BASE + 0] = modify_8,
135 [REG_FN_MODIFY_BASE + 1] = modify_16,
136 [REG_FN_MODIFY_BASE + 3] = modify_32,
137};
138
139enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
140 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
141 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
142 MODE_PRIO_REG, /* Priority value written to enable interrupt */
143 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
144};
145
146static void intc_mode_field(unsigned long addr,
147 unsigned long handle,
148 void (*fn)(unsigned long,
149 unsigned long,
150 unsigned long),
151 unsigned int irq)
152{
153 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
154}
155
156static void intc_mode_zero(unsigned long addr,
157 unsigned long handle,
158 void (*fn)(unsigned long,
159 unsigned long,
160 unsigned long),
161 unsigned int irq)
162{
163 fn(addr, handle, 0);
164}
165
166static void intc_mode_prio(unsigned long addr,
167 unsigned long handle,
168 void (*fn)(unsigned long,
169 unsigned long,
170 unsigned long),
171 unsigned int irq)
172{
173 fn(addr, handle, intc_prio_level[irq]);
174}
175
176static void (*intc_enable_fns[])(unsigned long addr,
177 unsigned long handle,
178 void (*fn)(unsigned long,
179 unsigned long,
180 unsigned long),
181 unsigned int irq) = {
182 [MODE_ENABLE_REG] = intc_mode_field,
183 [MODE_MASK_REG] = intc_mode_zero,
184 [MODE_DUAL_REG] = intc_mode_field,
185 [MODE_PRIO_REG] = intc_mode_prio,
186 [MODE_PCLR_REG] = intc_mode_prio,
187};
188
189static void (*intc_disable_fns[])(unsigned long addr,
190 unsigned long handle,
191 void (*fn)(unsigned long,
192 unsigned long,
193 unsigned long),
194 unsigned int irq) = {
195 [MODE_ENABLE_REG] = intc_mode_zero,
196 [MODE_MASK_REG] = intc_mode_field,
197 [MODE_DUAL_REG] = intc_mode_field,
198 [MODE_PRIO_REG] = intc_mode_zero,
199 [MODE_PCLR_REG] = intc_mode_field,
200};
201
202static inline void _intc_enable(unsigned int irq, unsigned long handle)
203{
204 struct intc_desc_int *d = get_intc_desc(irq);
205 unsigned long addr;
206 unsigned int cpu;
207
208 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
209 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
210 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
211 [_INTC_FN(handle)], irq);
212 }
213}
214
215static void intc_enable(unsigned int irq)
216{
217 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
218}
219
220static void intc_disable(unsigned int irq)
221{
222 struct intc_desc_int *d = get_intc_desc(irq);
223 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
224 unsigned long addr;
225 unsigned int cpu;
226
227 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
228 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
229 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
230 [_INTC_FN(handle)], irq);
231 }
232}
233
234#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
235static void intc_mask_ack(unsigned int irq)
236{
237 struct intc_desc_int *d = get_intc_desc(irq);
238 unsigned long handle = ack_handle[irq];
239 unsigned long addr;
240
241 intc_disable(irq);
242
243 /* read register and write zero only to the assocaited bit */
244
245 if (handle) {
246 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
247 switch (_INTC_FN(handle)) {
248 case REG_FN_MODIFY_BASE + 0: /* 8bit */
249 ctrl_inb(addr);
250 ctrl_outb(0xff ^ set_field(0, 1, handle), addr);
251 break;
252 case REG_FN_MODIFY_BASE + 1: /* 16bit */
253 ctrl_inw(addr);
254 ctrl_outw(0xffff ^ set_field(0, 1, handle), addr);
255 break;
256 case REG_FN_MODIFY_BASE + 3: /* 32bit */
257 ctrl_inl(addr);
258 ctrl_outl(0xffffffff ^ set_field(0, 1, handle), addr);
259 break;
260 default:
261 BUG();
262 break;
263 }
264 }
265}
266#endif
267
268static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
269 unsigned int nr_hp,
270 unsigned int irq)
271{
272 int i;
273
274 /* this doesn't scale well, but...
275 *
276 * this function should only be used for cerain uncommon
277 * operations such as intc_set_priority() and intc_set_sense()
278 * and in those rare cases performance doesn't matter that much.
279 * keeping the memory footprint low is more important.
280 *
281 * one rather simple way to speed this up and still keep the
282 * memory footprint down is to make sure the array is sorted
283 * and then perform a bisect to lookup the irq.
284 */
285
286 for (i = 0; i < nr_hp; i++) {
287 if ((hp + i)->irq != irq)
288 continue;
289
290 return hp + i;
291 }
292
293 return NULL;
294}
295
296int intc_set_priority(unsigned int irq, unsigned int prio)
297{
298 struct intc_desc_int *d = get_intc_desc(irq);
299 struct intc_handle_int *ihp;
300
301 if (!intc_prio_level[irq] || prio <= 1)
302 return -EINVAL;
303
304 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
305 if (ihp) {
306 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
307 return -EINVAL;
308
309 intc_prio_level[irq] = prio;
310
311 /*
312 * only set secondary masking method directly
313 * primary masking method is using intc_prio_level[irq]
314 * priority level will be set during next enable()
315 */
316
317 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
318 _intc_enable(irq, ihp->handle);
319 }
320 return 0;
321}
322
323#define VALID(x) (x | 0x80)
324
325static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
326 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
327 [IRQ_TYPE_EDGE_RISING] = VALID(1),
328 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
329 /* SH7706, SH7707 and SH7709 do not support high level triggered */
330#if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
331 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
332 !defined(CONFIG_CPU_SUBTYPE_SH7709)
333 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
334#endif
335};
336
337static int intc_set_sense(unsigned int irq, unsigned int type)
338{
339 struct intc_desc_int *d = get_intc_desc(irq);
340 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
341 struct intc_handle_int *ihp;
342 unsigned long addr;
343
344 if (!value)
345 return -EINVAL;
346
347 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
348 if (ihp) {
349 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
350 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
351 }
352 return 0;
353}
354
355static unsigned int __init intc_get_reg(struct intc_desc_int *d,
356 unsigned long address)
357{
358 unsigned int k;
359
360 for (k = 0; k < d->nr_reg; k++) {
361 if (d->reg[k] == address)
362 return k;
363 }
364
365 BUG();
366 return 0;
367}
368
369static intc_enum __init intc_grp_id(struct intc_desc *desc,
370 intc_enum enum_id)
371{
372 struct intc_group *g = desc->groups;
373 unsigned int i, j;
374
375 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
376 g = desc->groups + i;
377
378 for (j = 0; g->enum_ids[j]; j++) {
379 if (g->enum_ids[j] != enum_id)
380 continue;
381
382 return g->enum_id;
383 }
384 }
385
386 return 0;
387}
388
389static unsigned int __init intc_mask_data(struct intc_desc *desc,
390 struct intc_desc_int *d,
391 intc_enum enum_id, int do_grps)
392{
393 struct intc_mask_reg *mr = desc->mask_regs;
394 unsigned int i, j, fn, mode;
395 unsigned long reg_e, reg_d;
396
397 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
398 mr = desc->mask_regs + i;
399
400 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
401 if (mr->enum_ids[j] != enum_id)
402 continue;
403
404 if (mr->set_reg && mr->clr_reg) {
405 fn = REG_FN_WRITE_BASE;
406 mode = MODE_DUAL_REG;
407 reg_e = mr->clr_reg;
408 reg_d = mr->set_reg;
409 } else {
410 fn = REG_FN_MODIFY_BASE;
411 if (mr->set_reg) {
412 mode = MODE_ENABLE_REG;
413 reg_e = mr->set_reg;
414 reg_d = mr->set_reg;
415 } else {
416 mode = MODE_MASK_REG;
417 reg_e = mr->clr_reg;
418 reg_d = mr->clr_reg;
419 }
420 }
421
422 fn += (mr->reg_width >> 3) - 1;
423 return _INTC_MK(fn, mode,
424 intc_get_reg(d, reg_e),
425 intc_get_reg(d, reg_d),
426 1,
427 (mr->reg_width - 1) - j);
428 }
429 }
430
431 if (do_grps)
432 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
433
434 return 0;
435}
436
437static unsigned int __init intc_prio_data(struct intc_desc *desc,
438 struct intc_desc_int *d,
439 intc_enum enum_id, int do_grps)
440{
441 struct intc_prio_reg *pr = desc->prio_regs;
442 unsigned int i, j, fn, mode, bit;
443 unsigned long reg_e, reg_d;
444
445 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
446 pr = desc->prio_regs + i;
447
448 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
449 if (pr->enum_ids[j] != enum_id)
450 continue;
451
452 if (pr->set_reg && pr->clr_reg) {
453 fn = REG_FN_WRITE_BASE;
454 mode = MODE_PCLR_REG;
455 reg_e = pr->set_reg;
456 reg_d = pr->clr_reg;
457 } else {
458 fn = REG_FN_MODIFY_BASE;
459 mode = MODE_PRIO_REG;
460 if (!pr->set_reg)
461 BUG();
462 reg_e = pr->set_reg;
463 reg_d = pr->set_reg;
464 }
465
466 fn += (pr->reg_width >> 3) - 1;
467 bit = pr->reg_width - ((j + 1) * pr->field_width);
468
469 BUG_ON(bit < 0);
470
471 return _INTC_MK(fn, mode,
472 intc_get_reg(d, reg_e),
473 intc_get_reg(d, reg_d),
474 pr->field_width, bit);
475 }
476 }
477
478 if (do_grps)
479 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
480
481 return 0;
482}
483
484#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
485static unsigned int __init intc_ack_data(struct intc_desc *desc,
486 struct intc_desc_int *d,
487 intc_enum enum_id)
488{
489 struct intc_mask_reg *mr = desc->ack_regs;
490 unsigned int i, j, fn, mode;
491 unsigned long reg_e, reg_d;
492
493 for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
494 mr = desc->ack_regs + i;
495
496 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
497 if (mr->enum_ids[j] != enum_id)
498 continue;
499
500 fn = REG_FN_MODIFY_BASE;
501 mode = MODE_ENABLE_REG;
502 reg_e = mr->set_reg;
503 reg_d = mr->set_reg;
504
505 fn += (mr->reg_width >> 3) - 1;
506 return _INTC_MK(fn, mode,
507 intc_get_reg(d, reg_e),
508 intc_get_reg(d, reg_d),
509 1,
510 (mr->reg_width - 1) - j);
511 }
512 }
513
514 return 0;
515}
516#endif
517
518static unsigned int __init intc_sense_data(struct intc_desc *desc,
519 struct intc_desc_int *d,
520 intc_enum enum_id)
521{
522 struct intc_sense_reg *sr = desc->sense_regs;
523 unsigned int i, j, fn, bit;
524
525 for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
526 sr = desc->sense_regs + i;
527
528 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
529 if (sr->enum_ids[j] != enum_id)
530 continue;
531
532 fn = REG_FN_MODIFY_BASE;
533 fn += (sr->reg_width >> 3) - 1;
534 bit = sr->reg_width - ((j + 1) * sr->field_width);
535
536 BUG_ON(bit < 0);
537
538 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
539 0, sr->field_width, bit);
540 }
541 }
542
543 return 0;
544}
545
546static void __init intc_register_irq(struct intc_desc *desc,
547 struct intc_desc_int *d,
548 intc_enum enum_id,
549 unsigned int irq)
550{
551 struct intc_handle_int *hp;
552 unsigned int data[2], primary;
553
554 /* Prefer single interrupt source bitmap over other combinations:
555 * 1. bitmap, single interrupt source
556 * 2. priority, single interrupt source
557 * 3. bitmap, multiple interrupt sources (groups)
558 * 4. priority, multiple interrupt sources (groups)
559 */
560
561 data[0] = intc_mask_data(desc, d, enum_id, 0);
562 data[1] = intc_prio_data(desc, d, enum_id, 0);
563
564 primary = 0;
565 if (!data[0] && data[1])
566 primary = 1;
567
568 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
569 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
570
571 if (!data[primary])
572 primary ^= 1;
573
574 BUG_ON(!data[primary]); /* must have primary masking method */
575
576 disable_irq_nosync(irq);
577 set_irq_chip_and_handler_name(irq, &d->chip,
578 handle_level_irq, "level");
579 set_irq_chip_data(irq, (void *)data[primary]);
580
581 /* set priority level
582 * - this needs to be at least 2 for 5-bit priorities on 7780
583 */
584 intc_prio_level[irq] = 2;
585
586 /* enable secondary masking method if present */
587 if (data[!primary])
588 _intc_enable(irq, data[!primary]);
589
590 /* add irq to d->prio list if priority is available */
591 if (data[1]) {
592 hp = d->prio + d->nr_prio;
593 hp->irq = irq;
594 hp->handle = data[1];
595
596 if (primary) {
597 /*
598 * only secondary priority should access registers, so
599 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
600 */
601
602 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
603 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
604 }
605 d->nr_prio++;
606 }
607
608 /* add irq to d->sense list if sense is available */
609 data[0] = intc_sense_data(desc, d, enum_id);
610 if (data[0]) {
611 (d->sense + d->nr_sense)->irq = irq;
612 (d->sense + d->nr_sense)->handle = data[0];
613 d->nr_sense++;
614 }
615
616 /* irq should be disabled by default */
617 d->chip.mask(irq);
618
619#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
620 if (desc->ack_regs)
621 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
622#endif
623}
624
625static unsigned int __init save_reg(struct intc_desc_int *d,
626 unsigned int cnt,
627 unsigned long value,
628 unsigned int smp)
629{
630 if (value) {
631 d->reg[cnt] = value;
632#ifdef CONFIG_SMP
633 d->smp[cnt] = smp;
634#endif
635 return 1;
636 }
637
638 return 0;
639}
640
641
642void __init register_intc_controller(struct intc_desc *desc)
643{
644 unsigned int i, k, smp;
645 struct intc_desc_int *d;
646
647 d = alloc_bootmem(sizeof(*d));
648
649 d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
650 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
651 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
652
653#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
654 d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
655#endif
656 d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
657#ifdef CONFIG_SMP
658 d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
659#endif
660 k = 0;
661
662 if (desc->mask_regs) {
663 for (i = 0; i < desc->nr_mask_regs; i++) {
664 smp = IS_SMP(desc->mask_regs[i]);
665 k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
666 k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
667 }
668 }
669
670 if (desc->prio_regs) {
671 d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
672
673 for (i = 0; i < desc->nr_prio_regs; i++) {
674 smp = IS_SMP(desc->prio_regs[i]);
675 k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
676 k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
677 }
678 }
679
680 if (desc->sense_regs) {
681 d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
682
683 for (i = 0; i < desc->nr_sense_regs; i++) {
684 k += save_reg(d, k, desc->sense_regs[i].reg, 0);
685 }
686 }
687
688 d->chip.name = desc->name;
689 d->chip.mask = intc_disable;
690 d->chip.unmask = intc_enable;
691 d->chip.mask_ack = intc_disable;
692 d->chip.set_type = intc_set_sense;
693
694#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
695 if (desc->ack_regs) {
696 for (i = 0; i < desc->nr_ack_regs; i++)
697 k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
698
699 d->chip.mask_ack = intc_mask_ack;
700 }
701#endif
702
703 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
704
705 for (i = 0; i < desc->nr_vectors; i++) {
706 struct intc_vect *vect = desc->vectors + i;
707
708 intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
709 }
710}
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 56ea7b269b59..3eb17ee5540e 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -33,7 +33,7 @@ static void disable_ipr_irq(unsigned int irq)
33 struct ipr_data *p = get_irq_chip_data(irq); 33 struct ipr_data *p = get_irq_chip_data(irq);
34 unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; 34 unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
35 /* Set the priority in IPR to 0 */ 35 /* Set the priority in IPR to 0 */
36 ctrl_outw(ctrl_inw(addr) & (0xffff ^ (0xf << p->shift)), addr); 36 __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr);
37} 37}
38 38
39static void enable_ipr_irq(unsigned int irq) 39static void enable_ipr_irq(unsigned int irq)
@@ -41,7 +41,7 @@ static void enable_ipr_irq(unsigned int irq)
41 struct ipr_data *p = get_irq_chip_data(irq); 41 struct ipr_data *p = get_irq_chip_data(irq);
42 unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; 42 unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx];
43 /* Set priority in IPR back to original value */ 43 /* Set priority in IPR back to original value */
44 ctrl_outw(ctrl_inw(addr) | (p->priority << p->shift), addr); 44 __raw_writew(__raw_readw(addr) | (p->priority << p->shift), addr);
45} 45}
46 46
47/* 47/*
diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile
index 1ab1ecf4c768..428450cc0809 100644
--- a/arch/sh/kernel/cpu/sh2a/Makefile
+++ b/arch/sh/kernel/cpu/sh2a/Makefile
@@ -12,3 +12,8 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
14obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o 14obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o
15
16# Pinmux setup
17pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o
18
19obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y)
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
new file mode 100644
index 000000000000..39a5b880418f
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
@@ -0,0 +1,1599 @@
1/*
2 * SH7203 Pinmux
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/gpio.h>
14#include <asm/sh7203.h>
15
16enum {
17 PINMUX_RESERVED = 0,
18
19 PINMUX_DATA_BEGIN,
20 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
21 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
22 PB12_DATA,
23 PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
24 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
25 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
26 PC14_DATA, PC13_DATA, PC12_DATA,
27 PC11_DATA, PC10_DATA, PC9_DATA, PC8_DATA,
28 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
29 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
30 PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
31 PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
32 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
33 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
34 PE15_DATA, PE14_DATA, PE13_DATA, PE12_DATA,
35 PE11_DATA, PE10_DATA, PE9_DATA, PE8_DATA,
36 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
37 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
38 PF30_DATA, PF29_DATA, PF28_DATA,
39 PF27_DATA, PF26_DATA, PF25_DATA, PF24_DATA,
40 PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
41 PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA,
42 PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
43 PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
44 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
45 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
46 PINMUX_DATA_END,
47
48 PINMUX_INPUT_BEGIN,
49 PA7_IN, PA6_IN, PA5_IN, PA4_IN,
50 PA3_IN, PA2_IN, PA1_IN, PA0_IN,
51 PB11_IN, PB10_IN, PB9_IN, PB8_IN,
52 PB7_IN, PB6_IN, PB5_IN, PB4_IN,
53 PB3_IN, PB2_IN, PB1_IN, PB0_IN,
54 PC14_IN, PC13_IN, PC12_IN,
55 PC11_IN, PC10_IN, PC9_IN, PC8_IN,
56 PC7_IN, PC6_IN, PC5_IN, PC4_IN,
57 PC3_IN, PC2_IN, PC1_IN, PC0_IN,
58 PD15_IN, PD14_IN, PD13_IN, PD12_IN,
59 PD11_IN, PD10_IN, PD9_IN, PD8_IN,
60 PD7_IN, PD6_IN, PD5_IN, PD4_IN,
61 PD3_IN, PD2_IN, PD1_IN, PD0_IN,
62 PE15_IN, PE14_IN, PE13_IN, PE12_IN,
63 PE11_IN, PE10_IN, PE9_IN, PE8_IN,
64 PE7_IN, PE6_IN, PE5_IN, PE4_IN,
65 PE3_IN, PE2_IN, PE1_IN, PE0_IN,
66 PF30_IN, PF29_IN, PF28_IN,
67 PF27_IN, PF26_IN, PF25_IN, PF24_IN,
68 PF23_IN, PF22_IN, PF21_IN, PF20_IN,
69 PF19_IN, PF18_IN, PF17_IN, PF16_IN,
70 PF15_IN, PF14_IN, PF13_IN, PF12_IN,
71 PF11_IN, PF10_IN, PF9_IN, PF8_IN,
72 PF7_IN, PF6_IN, PF5_IN, PF4_IN,
73 PF3_IN, PF2_IN, PF1_IN, PF0_IN,
74 PINMUX_INPUT_END,
75
76 PINMUX_OUTPUT_BEGIN,
77 PB12_OUT,
78 PB11_OUT, PB10_OUT, PB9_OUT, PB8_OUT,
79 PC14_OUT, PC13_OUT, PC12_OUT,
80 PC11_OUT, PC10_OUT, PC9_OUT, PC8_OUT,
81 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
82 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
83 PD15_OUT, PD14_OUT, PD13_OUT, PD12_OUT,
84 PD11_OUT, PD10_OUT, PD9_OUT, PD8_OUT,
85 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
86 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
87 PE15_OUT, PE14_OUT, PE13_OUT, PE12_OUT,
88 PE11_OUT, PE10_OUT, PE9_OUT, PE8_OUT,
89 PE7_OUT, PE6_OUT, PE5_OUT, PE4_OUT,
90 PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
91 PF30_OUT, PF29_OUT, PF28_OUT,
92 PF27_OUT, PF26_OUT, PF25_OUT, PF24_OUT,
93 PF23_OUT, PF22_OUT, PF21_OUT, PF20_OUT,
94 PF19_OUT, PF18_OUT, PF17_OUT, PF16_OUT,
95 PF15_OUT, PF14_OUT, PF13_OUT, PF12_OUT,
96 PF11_OUT, PF10_OUT, PF9_OUT, PF8_OUT,
97 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
98 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
99 PINMUX_OUTPUT_END,
100
101 PINMUX_FUNCTION_BEGIN,
102 PB11_IOR_IN, PB11_IOR_OUT,
103 PB10_IOR_IN, PB10_IOR_OUT,
104 PB9_IOR_IN, PB9_IOR_OUT,
105 PB8_IOR_IN, PB8_IOR_OUT,
106 PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
107 PB11MD_0, PB11MD_1,
108 PB10MD_0, PB10MD_1,
109 PB9MD_00, PB9MD_01, PB9MD_10,
110 PB8MD_00, PB8MD_01, PB8MD_10,
111 PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
112 PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11,
113 PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11,
114 PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
115 PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11,
116 PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11,
117 PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11,
118 PB0MD_00, PB0MD_01, PB0MD_10, PB0MD_11,
119
120 PB12IRQ_00, PB12IRQ_01, PB12IRQ_10,
121
122 PC14MD_0, PC14MD_1,
123 PC13MD_0, PC13MD_1,
124 PC12MD_0, PC12MD_1,
125 PC11MD_00, PC11MD_01, PC11MD_10,
126 PC10MD_00, PC10MD_01, PC10MD_10,
127 PC9MD_0, PC9MD_1,
128 PC8MD_0, PC8MD_1,
129 PC7MD_0, PC7MD_1,
130 PC6MD_0, PC6MD_1,
131 PC5MD_0, PC5MD_1,
132 PC4MD_0, PC4MD_1,
133 PC3MD_0, PC3MD_1,
134 PC2MD_0, PC2MD_1,
135 PC1MD_0, PC1MD_1,
136 PC0MD_00, PC0MD_01, PC0MD_10,
137
138 PD15MD_000, PD15MD_001, PD15MD_010, PD15MD_100, PD15MD_101,
139 PD14MD_000, PD14MD_001, PD14MD_010, PD14MD_101,
140 PD13MD_000, PD13MD_001, PD13MD_010, PD13MD_100, PD13MD_101,
141 PD12MD_000, PD12MD_001, PD12MD_010, PD12MD_100, PD12MD_101,
142 PD11MD_000, PD11MD_001, PD11MD_010, PD11MD_100, PD11MD_101,
143 PD10MD_000, PD10MD_001, PD10MD_010, PD10MD_100, PD10MD_101,
144 PD9MD_000, PD9MD_001, PD9MD_010, PD9MD_100, PD9MD_101,
145 PD8MD_000, PD8MD_001, PD8MD_010, PD8MD_100, PD8MD_101,
146 PD7MD_000, PD7MD_001, PD7MD_010, PD7MD_011, PD7MD_100, PD7MD_101,
147 PD6MD_000, PD6MD_001, PD6MD_010, PD6MD_011, PD6MD_100, PD6MD_101,
148 PD5MD_000, PD5MD_001, PD5MD_010, PD5MD_011, PD5MD_100, PD5MD_101,
149 PD4MD_000, PD4MD_001, PD4MD_010, PD4MD_011, PD4MD_100, PD4MD_101,
150 PD3MD_000, PD3MD_001, PD3MD_010, PD3MD_011, PD3MD_100, PD3MD_101,
151 PD2MD_000, PD2MD_001, PD2MD_010, PD2MD_011, PD2MD_100, PD2MD_101,
152 PD1MD_000, PD1MD_001, PD1MD_010, PD1MD_011, PD1MD_100, PD1MD_101,
153 PD0MD_000, PD0MD_001, PD0MD_010, PD0MD_011, PD0MD_100, PD0MD_101,
154
155 PE15MD_00, PE15MD_01, PE15MD_11,
156 PE14MD_00, PE14MD_01, PE14MD_11,
157 PE13MD_00, PE13MD_11,
158 PE12MD_00, PE12MD_11,
159 PE11MD_000, PE11MD_001, PE11MD_010, PE11MD_100,
160 PE10MD_000, PE10MD_001, PE10MD_010, PE10MD_100,
161 PE9MD_00, PE9MD_01, PE9MD_10, PE9MD_11,
162 PE8MD_00, PE8MD_01, PE8MD_10, PE8MD_11,
163 PE7MD_000, PE7MD_001, PE7MD_010, PE7MD_011, PE7MD_100,
164 PE6MD_000, PE6MD_001, PE6MD_010, PE6MD_011, PE6MD_100,
165 PE5MD_000, PE5MD_001, PE5MD_010, PE5MD_011, PE5MD_100,
166 PE4MD_000, PE4MD_001, PE4MD_010, PE4MD_011, PE4MD_100,
167 PE3MD_00, PE3MD_01, PE3MD_11,
168 PE2MD_00, PE2MD_01, PE2MD_11,
169 PE1MD_00, PE1MD_01, PE1MD_10, PE1MD_11,
170 PE0MD_000, PE0MD_001, PE0MD_011, PE0MD_100,
171
172 PF30MD_0, PF30MD_1,
173 PF29MD_0, PF29MD_1,
174 PF28MD_0, PF28MD_1,
175 PF27MD_0, PF27MD_1,
176 PF26MD_0, PF26MD_1,
177 PF25MD_0, PF25MD_1,
178 PF24MD_0, PF24MD_1,
179 PF23MD_00, PF23MD_01, PF23MD_10,
180 PF22MD_00, PF22MD_01, PF22MD_10,
181 PF21MD_00, PF21MD_01, PF21MD_10,
182 PF20MD_00, PF20MD_01, PF20MD_10,
183 PF19MD_00, PF19MD_01, PF19MD_10,
184 PF18MD_00, PF18MD_01, PF18MD_10,
185 PF17MD_00, PF17MD_01, PF17MD_10,
186 PF16MD_00, PF16MD_01, PF16MD_10,
187 PF15MD_00, PF15MD_01, PF15MD_10,
188 PF14MD_00, PF14MD_01, PF14MD_10,
189 PF13MD_00, PF13MD_01, PF13MD_10,
190 PF12MD_00, PF12MD_01, PF12MD_10,
191 PF11MD_00, PF11MD_01, PF11MD_10,
192 PF10MD_00, PF10MD_01, PF10MD_10,
193 PF9MD_00, PF9MD_01, PF9MD_10,
194 PF8MD_00, PF8MD_01, PF8MD_10,
195 PF7MD_00, PF7MD_01, PF7MD_10, PF7MD_11,
196 PF6MD_00, PF6MD_01, PF6MD_10, PF6MD_11,
197 PF5MD_00, PF5MD_01, PF5MD_10, PF5MD_11,
198 PF4MD_00, PF4MD_01, PF4MD_10, PF4MD_11,
199 PF3MD_00, PF3MD_01, PF3MD_10, PF3MD_11,
200 PF2MD_00, PF2MD_01, PF2MD_10, PF2MD_11,
201 PF1MD_00, PF1MD_01, PF1MD_10, PF1MD_11,
202 PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11,
203 PINMUX_FUNCTION_END,
204
205 PINMUX_MARK_BEGIN,
206 PINT7_PB_MARK, PINT6_PB_MARK, PINT5_PB_MARK, PINT4_PB_MARK,
207 PINT3_PB_MARK, PINT2_PB_MARK, PINT1_PB_MARK, PINT0_PB_MARK,
208 PINT7_PD_MARK, PINT6_PD_MARK, PINT5_PD_MARK, PINT4_PD_MARK,
209 PINT3_PD_MARK, PINT2_PD_MARK, PINT1_PD_MARK, PINT0_PD_MARK,
210 IRQ7_PB_MARK, IRQ6_PB_MARK, IRQ5_PB_MARK, IRQ4_PB_MARK,
211 IRQ3_PB_MARK, IRQ2_PB_MARK, IRQ1_PB_MARK, IRQ0_PB_MARK,
212 IRQ7_PD_MARK, IRQ6_PD_MARK, IRQ5_PD_MARK, IRQ4_PD_MARK,
213 IRQ3_PD_MARK, IRQ2_PD_MARK, IRQ1_PD_MARK, IRQ0_PD_MARK,
214 IRQ7_PE_MARK, IRQ6_PE_MARK, IRQ5_PE_MARK, IRQ4_PE_MARK,
215 IRQ3_PE_MARK, IRQ2_PE_MARK, IRQ1_PE_MARK, IRQ0_PE_MARK,
216 WDTOVF_MARK, IRQOUT_MARK, REFOUT_MARK, IRQOUT_REFOUT_MARK,
217 UBCTRG_MARK,
218 CTX1_MARK, CRX1_MARK, CTX0_MARK, CTX0_CTX1_MARK,
219 CRX0_MARK, CRX0_CRX1_MARK,
220 SDA3_MARK, SCL3_MARK,
221 SDA2_MARK, SCL2_MARK,
222 SDA1_MARK, SCL1_MARK,
223 SDA0_MARK, SCL0_MARK,
224 TEND0_PD_MARK, TEND0_PE_MARK, DACK0_PD_MARK, DACK0_PE_MARK,
225 DREQ0_PD_MARK, DREQ0_PE_MARK, TEND1_PD_MARK, TEND1_PE_MARK,
226 DACK1_PD_MARK, DACK1_PE_MARK, DREQ1_PD_MARK, DREQ1_PE_MARK,
227 DACK2_MARK, DREQ2_MARK, DACK3_MARK, DREQ3_MARK,
228 ADTRG_PD_MARK, ADTRG_PE_MARK,
229 D31_MARK, D30_MARK, D29_MARK, D28_MARK,
230 D27_MARK, D26_MARK, D25_MARK, D24_MARK,
231 D23_MARK, D22_MARK, D21_MARK, D20_MARK,
232 D19_MARK, D18_MARK, D17_MARK, D16_MARK,
233 A25_MARK, A24_MARK, A23_MARK, A22_MARK,
234 A21_MARK, CS4_MARK, MRES_MARK, BS_MARK,
235 IOIS16_MARK, CS1_MARK, CS6_CE1B_MARK, CE2B_MARK,
236 CS5_CE1A_MARK, CE2A_MARK, FRAME_MARK, WAIT_MARK,
237 RDWR_MARK, CKE_MARK, CASU_MARK, BREQ_MARK,
238 RASU_MARK, BACK_MARK, CASL_MARK, RASL_MARK,
239 WE3_DQMUU_AH_ICIO_WR_MARK, WE2_DQMUL_ICIORD_MARK,
240 WE1_DQMLU_WE_MARK, WE0_DQMLL_MARK,
241 CS3_MARK, CS2_MARK, A1_MARK, A0_MARK, CS7_MARK,
242 TIOC4D_MARK, TIOC4C_MARK, TIOC4B_MARK, TIOC4A_MARK,
243 TIOC3D_MARK, TIOC3C_MARK, TIOC3B_MARK, TIOC3A_MARK,
244 TIOC2B_MARK, TIOC1B_MARK, TIOC2A_MARK, TIOC1A_MARK,
245 TIOC0D_MARK, TIOC0C_MARK, TIOC0B_MARK, TIOC0A_MARK,
246 TCLKD_PD_MARK, TCLKC_PD_MARK, TCLKB_PD_MARK, TCLKA_PD_MARK,
247 TCLKD_PF_MARK, TCLKC_PF_MARK, TCLKB_PF_MARK, TCLKA_PF_MARK,
248 SCS0_PD_MARK, SSO0_PD_MARK, SSI0_PD_MARK, SSCK0_PD_MARK,
249 SCS0_PF_MARK, SSO0_PF_MARK, SSI0_PF_MARK, SSCK0_PF_MARK,
250 SCS1_PD_MARK, SSO1_PD_MARK, SSI1_PD_MARK, SSCK1_PD_MARK,
251 SCS1_PF_MARK, SSO1_PF_MARK, SSI1_PF_MARK, SSCK1_PF_MARK,
252 TXD0_MARK, RXD0_MARK, SCK0_MARK,
253 TXD1_MARK, RXD1_MARK, SCK1_MARK,
254 TXD2_MARK, RXD2_MARK, SCK2_MARK,
255 RTS3_MARK, CTS3_MARK, TXD3_MARK,
256 RXD3_MARK, SCK3_MARK,
257 AUDIO_CLK_MARK,
258 SSIDATA3_MARK, SSIWS3_MARK, SSISCK3_MARK,
259 SSIDATA2_MARK, SSIWS2_MARK, SSISCK2_MARK,
260 SSIDATA1_MARK, SSIWS1_MARK, SSISCK1_MARK,
261 SSIDATA0_MARK, SSIWS0_MARK, SSISCK0_MARK,
262 FCE_MARK, FRB_MARK,
263 NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK,
264 NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK,
265 FSC_MARK, FOE_MARK, FCDE_MARK, FWE_MARK,
266 LCD_VEPWC_MARK, LCD_VCPWC_MARK, LCD_CLK_MARK, LCD_FLM_MARK,
267 LCD_M_DISP_MARK, LCD_CL2_MARK, LCD_CL1_MARK, LCD_DON_MARK,
268 LCD_DATA15_MARK, LCD_DATA14_MARK, LCD_DATA13_MARK, LCD_DATA12_MARK,
269 LCD_DATA11_MARK, LCD_DATA10_MARK, LCD_DATA9_MARK, LCD_DATA8_MARK,
270 LCD_DATA7_MARK, LCD_DATA6_MARK, LCD_DATA5_MARK, LCD_DATA4_MARK,
271 LCD_DATA3_MARK, LCD_DATA2_MARK, LCD_DATA1_MARK, LCD_DATA0_MARK,
272 PINMUX_MARK_END,
273};
274
275static pinmux_enum_t pinmux_data[] = {
276
277 /* PA */
278 PINMUX_DATA(PA7_DATA, PA7_IN),
279 PINMUX_DATA(PA6_DATA, PA6_IN),
280 PINMUX_DATA(PA5_DATA, PA5_IN),
281 PINMUX_DATA(PA4_DATA, PA4_IN),
282 PINMUX_DATA(PA3_DATA, PA3_IN),
283 PINMUX_DATA(PA2_DATA, PA2_IN),
284 PINMUX_DATA(PA1_DATA, PA1_IN),
285 PINMUX_DATA(PA0_DATA, PA0_IN),
286
287 /* PB */
288 PINMUX_DATA(PB12_DATA, PB12MD_00, PB12_OUT),
289 PINMUX_DATA(WDTOVF_MARK, PB12MD_01),
290 PINMUX_DATA(IRQOUT_MARK, PB12MD_10, PB12IRQ_00),
291 PINMUX_DATA(REFOUT_MARK, PB12MD_10, PB12IRQ_01),
292 PINMUX_DATA(IRQOUT_REFOUT_MARK, PB12MD_10, PB12IRQ_10),
293 PINMUX_DATA(UBCTRG_MARK, PB12MD_11),
294
295 PINMUX_DATA(PB11_DATA, PB11MD_0, PB11_IN, PB11_OUT),
296 PINMUX_DATA(CTX1_MARK, PB11MD_1),
297
298 PINMUX_DATA(PB10_DATA, PB10MD_0, PB10_IN, PB10_OUT),
299 PINMUX_DATA(CRX1_MARK, PB10MD_1),
300
301 PINMUX_DATA(PB9_DATA, PB9MD_00, PB9_IN, PB9_OUT),
302 PINMUX_DATA(CTX0_MARK, PB9MD_01),
303 PINMUX_DATA(CTX0_CTX1_MARK, PB9MD_10),
304
305 PINMUX_DATA(PB8_DATA, PB8MD_00, PB8_IN, PB8_OUT),
306 PINMUX_DATA(CRX0_MARK, PB8MD_01),
307 PINMUX_DATA(CRX0_CRX1_MARK, PB8MD_10),
308
309 PINMUX_DATA(PB7_DATA, PB7MD_00, PB7_IN),
310 PINMUX_DATA(SDA3_MARK, PB7MD_01),
311 PINMUX_DATA(PINT7_PB_MARK, PB7MD_10),
312 PINMUX_DATA(IRQ7_PB_MARK, PB7MD_11),
313
314 PINMUX_DATA(PB6_DATA, PB6MD_00, PB6_IN),
315 PINMUX_DATA(SCL3_MARK, PB6MD_01),
316 PINMUX_DATA(PINT6_PB_MARK, PB6MD_10),
317 PINMUX_DATA(IRQ6_PB_MARK, PB6MD_11),
318
319 PINMUX_DATA(PB5_DATA, PB5MD_00, PB5_IN),
320 PINMUX_DATA(SDA2_MARK, PB6MD_01),
321 PINMUX_DATA(PINT5_PB_MARK, PB6MD_10),
322 PINMUX_DATA(IRQ5_PB_MARK, PB6MD_11),
323
324 PINMUX_DATA(PB4_DATA, PB4MD_00, PB4_IN),
325 PINMUX_DATA(SCL2_MARK, PB4MD_01),
326 PINMUX_DATA(PINT4_PB_MARK, PB4MD_10),
327 PINMUX_DATA(IRQ4_PB_MARK, PB4MD_11),
328
329 PINMUX_DATA(PB3_DATA, PB3MD_00, PB3_IN),
330 PINMUX_DATA(SDA1_MARK, PB3MD_01),
331 PINMUX_DATA(PINT3_PB_MARK, PB3MD_10),
332 PINMUX_DATA(IRQ3_PB_MARK, PB3MD_11),
333
334 PINMUX_DATA(PB2_DATA, PB2MD_00, PB2_IN),
335 PINMUX_DATA(SCL1_MARK, PB2MD_01),
336 PINMUX_DATA(PINT2_PB_MARK, PB2MD_10),
337 PINMUX_DATA(IRQ2_PB_MARK, PB2MD_11),
338
339 PINMUX_DATA(PB1_DATA, PB1MD_00, PB1_IN),
340 PINMUX_DATA(SDA0_MARK, PB1MD_01),
341 PINMUX_DATA(PINT1_PB_MARK, PB1MD_10),
342 PINMUX_DATA(IRQ1_PB_MARK, PB1MD_11),
343
344 PINMUX_DATA(PB0_DATA, PB0MD_00, PB0_IN),
345 PINMUX_DATA(SCL0_MARK, PB0MD_01),
346 PINMUX_DATA(PINT0_PB_MARK, PB0MD_10),
347 PINMUX_DATA(IRQ0_PB_MARK, PB0MD_11),
348
349 /* PC */
350 PINMUX_DATA(PC14_DATA, PC14MD_0, PC14_IN, PC14_OUT),
351 PINMUX_DATA(WAIT_MARK, PC14MD_1),
352
353 PINMUX_DATA(PC13_DATA, PC13MD_0, PC13_IN, PC13_OUT),
354 PINMUX_DATA(RDWR_MARK, PC13MD_1),
355
356 PINMUX_DATA(PC12_DATA, PC12MD_0, PC12_IN, PC12_OUT),
357 PINMUX_DATA(CKE_MARK, PC12MD_1),
358
359 PINMUX_DATA(PC11_DATA, PC11MD_00, PC11_IN, PC11_OUT),
360 PINMUX_DATA(CASU_MARK, PC11MD_01),
361 PINMUX_DATA(BREQ_MARK, PC11MD_10),
362
363 PINMUX_DATA(PC10_DATA, PC10MD_00, PC10_IN, PC10_OUT),
364 PINMUX_DATA(RASU_MARK, PC10MD_01),
365 PINMUX_DATA(BACK_MARK, PC10MD_10),
366
367 PINMUX_DATA(PC9_DATA, PC9MD_0, PC9_IN, PC9_OUT),
368 PINMUX_DATA(CASL_MARK, PC9MD_1),
369
370 PINMUX_DATA(PC8_DATA, PC8MD_0, PC8_IN, PC8_OUT),
371 PINMUX_DATA(RASL_MARK, PC8MD_1),
372
373 PINMUX_DATA(PC7_DATA, PC7MD_0, PC7_IN, PC7_OUT),
374 PINMUX_DATA(WE3_DQMUU_AH_ICIO_WR_MARK, PC7MD_1),
375
376 PINMUX_DATA(PC6_DATA, PC6MD_0, PC6_IN, PC6_OUT),
377 PINMUX_DATA(WE2_DQMUL_ICIORD_MARK, PC6MD_1),
378
379 PINMUX_DATA(PC5_DATA, PC5MD_0, PC5_IN, PC5_OUT),
380 PINMUX_DATA(WE1_DQMLU_WE_MARK, PC5MD_1),
381
382 PINMUX_DATA(PC4_DATA, PC4MD_0, PC4_IN, PC4_OUT),
383 PINMUX_DATA(WE0_DQMLL_MARK, PC4MD_1),
384
385 PINMUX_DATA(PC3_DATA, PC3MD_0, PC3_IN, PC3_OUT),
386 PINMUX_DATA(CS3_MARK, PC3MD_1),
387
388 PINMUX_DATA(PC2_DATA, PC2MD_0, PC2_IN, PC2_OUT),
389 PINMUX_DATA(CS2_MARK, PC2MD_1),
390
391 PINMUX_DATA(PC1_DATA, PC1MD_0, PC1_IN, PC1_OUT),
392 PINMUX_DATA(A1_MARK, PC1MD_1),
393
394 PINMUX_DATA(PC0_DATA, PC0MD_00, PC0_IN, PC0_OUT),
395 PINMUX_DATA(A0_MARK, PC0MD_01),
396 PINMUX_DATA(CS7_MARK, PC0MD_10),
397
398 /* PD */
399 PINMUX_DATA(PD15_DATA, PD15MD_000, PD15_IN, PD15_OUT),
400 PINMUX_DATA(D31_MARK, PD15MD_001),
401 PINMUX_DATA(PINT7_PD_MARK, PD15MD_010),
402 PINMUX_DATA(ADTRG_PD_MARK, PD15MD_100),
403 PINMUX_DATA(TIOC4D_MARK, PD15MD_101),
404
405 PINMUX_DATA(PD14_DATA, PD14MD_000, PD14_IN, PD14_OUT),
406 PINMUX_DATA(D30_MARK, PD14MD_001),
407 PINMUX_DATA(PINT6_PD_MARK, PD14MD_010),
408 PINMUX_DATA(TIOC4C_MARK, PD14MD_101),
409
410 PINMUX_DATA(PD13_DATA, PD13MD_000, PD13_IN, PD13_OUT),
411 PINMUX_DATA(D29_MARK, PD13MD_001),
412 PINMUX_DATA(PINT5_PD_MARK, PD13MD_010),
413 PINMUX_DATA(TEND1_PD_MARK, PD13MD_100),
414 PINMUX_DATA(TIOC4B_MARK, PD13MD_101),
415
416 PINMUX_DATA(PD12_DATA, PD12MD_000, PD12_IN, PD12_OUT),
417 PINMUX_DATA(D28_MARK, PD12MD_001),
418 PINMUX_DATA(PINT4_PD_MARK, PD12MD_010),
419 PINMUX_DATA(DACK1_PD_MARK, PD12MD_100),
420 PINMUX_DATA(TIOC4A_MARK, PD12MD_101),
421
422 PINMUX_DATA(PD11_DATA, PD11MD_000, PD11_IN, PD11_OUT),
423 PINMUX_DATA(D27_MARK, PD11MD_001),
424 PINMUX_DATA(PINT3_PD_MARK, PD11MD_010),
425 PINMUX_DATA(DREQ1_PD_MARK, PD11MD_100),
426 PINMUX_DATA(TIOC3D_MARK, PD11MD_101),
427
428 PINMUX_DATA(PD10_DATA, PD10MD_000, PD10_IN, PD10_OUT),
429 PINMUX_DATA(D26_MARK, PD10MD_001),
430 PINMUX_DATA(PINT2_PD_MARK, PD10MD_010),
431 PINMUX_DATA(TEND0_PD_MARK, PD10MD_100),
432 PINMUX_DATA(TIOC3C_MARK, PD10MD_101),
433
434 PINMUX_DATA(PD9_DATA, PD9MD_000, PD9_IN, PD9_OUT),
435 PINMUX_DATA(D25_MARK, PD9MD_001),
436 PINMUX_DATA(PINT1_PD_MARK, PD9MD_010),
437 PINMUX_DATA(DACK0_PD_MARK, PD9MD_100),
438 PINMUX_DATA(TIOC3B_MARK, PD9MD_101),
439
440 PINMUX_DATA(PD8_DATA, PD8MD_000, PD8_IN, PD8_OUT),
441 PINMUX_DATA(D24_MARK, PD8MD_001),
442 PINMUX_DATA(PINT0_PD_MARK, PD8MD_010),
443 PINMUX_DATA(DREQ0_PD_MARK, PD8MD_100),
444 PINMUX_DATA(TIOC3A_MARK, PD8MD_101),
445
446 PINMUX_DATA(PD7_DATA, PD7MD_000, PD7_IN, PD7_OUT),
447 PINMUX_DATA(D23_MARK, PD7MD_001),
448 PINMUX_DATA(IRQ7_PD_MARK, PD7MD_010),
449 PINMUX_DATA(SCS1_PD_MARK, PD7MD_011),
450 PINMUX_DATA(TCLKD_PD_MARK, PD7MD_100),
451 PINMUX_DATA(TIOC2B_MARK, PD7MD_101),
452
453 PINMUX_DATA(PD6_DATA, PD6MD_000, PD6_IN, PD6_OUT),
454 PINMUX_DATA(D22_MARK, PD6MD_001),
455 PINMUX_DATA(IRQ6_PD_MARK, PD6MD_010),
456 PINMUX_DATA(SSO1_PD_MARK, PD6MD_011),
457 PINMUX_DATA(TCLKC_PD_MARK, PD6MD_100),
458 PINMUX_DATA(TIOC2A_MARK, PD6MD_101),
459
460 PINMUX_DATA(PD5_DATA, PD5MD_000, PD5_IN, PD5_OUT),
461 PINMUX_DATA(D21_MARK, PD5MD_001),
462 PINMUX_DATA(IRQ5_PD_MARK, PD5MD_010),
463 PINMUX_DATA(SSI1_PD_MARK, PD5MD_011),
464 PINMUX_DATA(TCLKB_PD_MARK, PD5MD_100),
465 PINMUX_DATA(TIOC1B_MARK, PD5MD_101),
466
467 PINMUX_DATA(PD4_DATA, PD4MD_000, PD4_IN, PD4_OUT),
468 PINMUX_DATA(D20_MARK, PD4MD_001),
469 PINMUX_DATA(IRQ4_PD_MARK, PD4MD_010),
470 PINMUX_DATA(SSCK1_PD_MARK, PD4MD_011),
471 PINMUX_DATA(TCLKA_PD_MARK, PD4MD_100),
472 PINMUX_DATA(TIOC1A_MARK, PD4MD_101),
473
474 PINMUX_DATA(PD3_DATA, PD3MD_000, PD3_IN, PD3_OUT),
475 PINMUX_DATA(D19_MARK, PD3MD_001),
476 PINMUX_DATA(IRQ3_PD_MARK, PD3MD_010),
477 PINMUX_DATA(SCS0_PD_MARK, PD3MD_011),
478 PINMUX_DATA(DACK3_MARK, PD3MD_100),
479 PINMUX_DATA(TIOC0D_MARK, PD3MD_101),
480
481 PINMUX_DATA(PD2_DATA, PD2MD_000, PD2_IN, PD2_OUT),
482 PINMUX_DATA(D18_MARK, PD2MD_001),
483 PINMUX_DATA(IRQ2_PD_MARK, PD2MD_010),
484 PINMUX_DATA(SSO0_PD_MARK, PD2MD_011),
485 PINMUX_DATA(DREQ3_MARK, PD2MD_100),
486 PINMUX_DATA(TIOC0C_MARK, PD2MD_101),
487
488 PINMUX_DATA(PD1_DATA, PD1MD_000, PD1_IN, PD1_OUT),
489 PINMUX_DATA(D17_MARK, PD1MD_001),
490 PINMUX_DATA(IRQ1_PD_MARK, PD1MD_010),
491 PINMUX_DATA(SSI0_PD_MARK, PD1MD_011),
492 PINMUX_DATA(DACK2_MARK, PD1MD_100),
493 PINMUX_DATA(TIOC0B_MARK, PD1MD_101),
494
495 PINMUX_DATA(PD0_DATA, PD0MD_000, PD0_IN, PD0_OUT),
496 PINMUX_DATA(D16_MARK, PD0MD_001),
497 PINMUX_DATA(IRQ0_PD_MARK, PD0MD_010),
498 PINMUX_DATA(SSCK0_PD_MARK, PD0MD_011),
499 PINMUX_DATA(DREQ2_MARK, PD0MD_100),
500 PINMUX_DATA(TIOC0A_MARK, PD0MD_101),
501
502 /* PE */
503 PINMUX_DATA(PE15_DATA, PE15MD_00, PE15_IN, PE15_OUT),
504 PINMUX_DATA(IOIS16_MARK, PE15MD_01),
505 PINMUX_DATA(RTS3_MARK, PE15MD_11),
506
507 PINMUX_DATA(PE14_DATA, PE14MD_00, PE14_IN, PE14_OUT),
508 PINMUX_DATA(CS1_MARK, PE14MD_01),
509 PINMUX_DATA(CTS3_MARK, PE14MD_11),
510
511 PINMUX_DATA(PE13_DATA, PE13MD_00, PE13_IN, PE13_OUT),
512 PINMUX_DATA(TXD3_MARK, PE13MD_11),
513
514 PINMUX_DATA(PE12_DATA, PE12MD_00, PE12_IN, PE12_OUT),
515 PINMUX_DATA(RXD3_MARK, PE12MD_11),
516
517 PINMUX_DATA(PE11_DATA, PE11MD_000, PE11_IN, PE11_OUT),
518 PINMUX_DATA(CS6_CE1B_MARK, PE11MD_001),
519 PINMUX_DATA(IRQ7_PE_MARK, PE11MD_010),
520 PINMUX_DATA(TEND1_PE_MARK, PE11MD_100),
521
522 PINMUX_DATA(PE10_DATA, PE10MD_000, PE10_IN, PE10_OUT),
523 PINMUX_DATA(CE2B_MARK, PE10MD_001),
524 PINMUX_DATA(IRQ6_PE_MARK, PE10MD_010),
525 PINMUX_DATA(TEND0_PE_MARK, PE10MD_100),
526
527 PINMUX_DATA(PE9_DATA, PE9MD_00, PE9_IN, PE9_OUT),
528 PINMUX_DATA(CS5_CE1A_MARK, PE9MD_01),
529 PINMUX_DATA(IRQ5_PE_MARK, PE9MD_10),
530 PINMUX_DATA(SCK3_MARK, PE9MD_11),
531
532 PINMUX_DATA(PE8_DATA, PE8MD_00, PE8_IN, PE8_OUT),
533 PINMUX_DATA(CE2A_MARK, PE8MD_01),
534 PINMUX_DATA(IRQ4_PE_MARK, PE8MD_10),
535 PINMUX_DATA(SCK2_MARK, PE8MD_11),
536
537 PINMUX_DATA(PE7_DATA, PE7MD_000, PE7_IN, PE7_OUT),
538 PINMUX_DATA(FRAME_MARK, PE7MD_001),
539 PINMUX_DATA(IRQ3_PE_MARK, PE7MD_010),
540 PINMUX_DATA(TXD2_MARK, PE7MD_011),
541 PINMUX_DATA(DACK1_PE_MARK, PE7MD_100),
542
543 PINMUX_DATA(PE6_DATA, PE6MD_000, PE6_IN, PE6_OUT),
544 PINMUX_DATA(A25_MARK, PE6MD_001),
545 PINMUX_DATA(IRQ2_PE_MARK, PE6MD_010),
546 PINMUX_DATA(RXD2_MARK, PE6MD_011),
547 PINMUX_DATA(DREQ1_PE_MARK, PE6MD_100),
548
549 PINMUX_DATA(PE5_DATA, PE5MD_000, PE5_IN, PE5_OUT),
550 PINMUX_DATA(A24_MARK, PE5MD_001),
551 PINMUX_DATA(IRQ1_PE_MARK, PE5MD_010),
552 PINMUX_DATA(TXD1_MARK, PE5MD_011),
553 PINMUX_DATA(DACK0_PE_MARK, PE5MD_100),
554
555 PINMUX_DATA(PE4_DATA, PE4MD_000, PE4_IN, PE4_OUT),
556 PINMUX_DATA(A23_MARK, PE4MD_001),
557 PINMUX_DATA(IRQ0_PE_MARK, PE4MD_010),
558 PINMUX_DATA(RXD1_MARK, PE4MD_011),
559 PINMUX_DATA(DREQ0_PE_MARK, PE4MD_100),
560
561 PINMUX_DATA(PE3_DATA, PE3MD_00, PE3_IN, PE3_OUT),
562 PINMUX_DATA(A22_MARK, PE3MD_01),
563 PINMUX_DATA(SCK1_MARK, PE3MD_11),
564
565 PINMUX_DATA(PE2_DATA, PE2MD_00, PE2_IN, PE2_OUT),
566 PINMUX_DATA(A21_MARK, PE2MD_01),
567 PINMUX_DATA(SCK0_MARK, PE2MD_11),
568
569 PINMUX_DATA(PE1_DATA, PE1MD_00, PE1_IN, PE1_OUT),
570 PINMUX_DATA(CS4_MARK, PE1MD_01),
571 PINMUX_DATA(MRES_MARK, PE1MD_10),
572 PINMUX_DATA(TXD0_MARK, PE1MD_11),
573
574 PINMUX_DATA(PE0_DATA, PE0MD_000, PE0_IN, PE0_OUT),
575 PINMUX_DATA(BS_MARK, PE0MD_001),
576 PINMUX_DATA(RXD0_MARK, PE0MD_011),
577 PINMUX_DATA(ADTRG_PE_MARK, PE0MD_100),
578
579 /* PF */
580 PINMUX_DATA(PF30_DATA, PF30MD_0, PF30_IN, PF30_OUT),
581 PINMUX_DATA(AUDIO_CLK_MARK, PF30MD_1),
582
583 PINMUX_DATA(PF29_DATA, PF29MD_0, PF29_IN, PF29_OUT),
584 PINMUX_DATA(SSIDATA3_MARK, PF29MD_1),
585
586 PINMUX_DATA(PF28_DATA, PF28MD_0, PF28_IN, PF28_OUT),
587 PINMUX_DATA(SSIWS3_MARK, PF28MD_1),
588
589 PINMUX_DATA(PF27_DATA, PF27MD_0, PF27_IN, PF27_OUT),
590 PINMUX_DATA(SSISCK3_MARK, PF27MD_1),
591
592 PINMUX_DATA(PF26_DATA, PF26MD_0, PF26_IN, PF26_OUT),
593 PINMUX_DATA(SSIDATA2_MARK, PF26MD_1),
594
595 PINMUX_DATA(PF25_DATA, PF25MD_0, PF25_IN, PF25_OUT),
596 PINMUX_DATA(SSIWS2_MARK, PF25MD_1),
597
598 PINMUX_DATA(PF24_DATA, PF24MD_0, PF24_IN, PF24_OUT),
599 PINMUX_DATA(SSISCK2_MARK, PF24MD_1),
600
601 PINMUX_DATA(PF23_DATA, PF23MD_00, PF23_IN, PF23_OUT),
602 PINMUX_DATA(SSIDATA1_MARK, PF23MD_01),
603 PINMUX_DATA(LCD_VEPWC_MARK, PF23MD_10),
604
605 PINMUX_DATA(PF22_DATA, PF22MD_00, PF22_IN, PF22_OUT),
606 PINMUX_DATA(SSIWS1_MARK, PF22MD_01),
607 PINMUX_DATA(LCD_VCPWC_MARK, PF22MD_10),
608
609 PINMUX_DATA(PF21_DATA, PF21MD_00, PF21_IN, PF21_OUT),
610 PINMUX_DATA(SSISCK1_MARK, PF21MD_01),
611 PINMUX_DATA(LCD_CLK_MARK, PF21MD_10),
612
613 PINMUX_DATA(PF20_DATA, PF20MD_00, PF20_IN, PF20_OUT),
614 PINMUX_DATA(SSIDATA0_MARK, PF20MD_01),
615 PINMUX_DATA(LCD_FLM_MARK, PF20MD_10),
616
617 PINMUX_DATA(PF19_DATA, PF19MD_00, PF19_IN, PF19_OUT),
618 PINMUX_DATA(SSIWS0_MARK, PF19MD_01),
619 PINMUX_DATA(LCD_M_DISP_MARK, PF19MD_10),
620
621 PINMUX_DATA(PF18_DATA, PF18MD_00, PF18_IN, PF18_OUT),
622 PINMUX_DATA(SSISCK0_MARK, PF18MD_01),
623 PINMUX_DATA(LCD_CL2_MARK, PF18MD_10),
624
625 PINMUX_DATA(PF17_DATA, PF17MD_00, PF17_IN, PF17_OUT),
626 PINMUX_DATA(FCE_MARK, PF17MD_01),
627 PINMUX_DATA(LCD_CL1_MARK, PF17MD_10),
628
629 PINMUX_DATA(PF16_DATA, PF16MD_00, PF16_IN, PF16_OUT),
630 PINMUX_DATA(FRB_MARK, PF16MD_01),
631 PINMUX_DATA(LCD_DON_MARK, PF16MD_10),
632
633 PINMUX_DATA(PF15_DATA, PF15MD_00, PF15_IN, PF15_OUT),
634 PINMUX_DATA(NAF7_MARK, PF15MD_01),
635 PINMUX_DATA(LCD_DATA15_MARK, PF15MD_10),
636
637 PINMUX_DATA(PF14_DATA, PF14MD_00, PF14_IN, PF14_OUT),
638 PINMUX_DATA(NAF6_MARK, PF14MD_01),
639 PINMUX_DATA(LCD_DATA14_MARK, PF14MD_10),
640
641 PINMUX_DATA(PF13_DATA, PF13MD_00, PF13_IN, PF13_OUT),
642 PINMUX_DATA(NAF5_MARK, PF13MD_01),
643 PINMUX_DATA(LCD_DATA13_MARK, PF13MD_10),
644
645 PINMUX_DATA(PF12_DATA, PF12MD_00, PF12_IN, PF12_OUT),
646 PINMUX_DATA(NAF4_MARK, PF12MD_01),
647 PINMUX_DATA(LCD_DATA12_MARK, PF12MD_10),
648
649 PINMUX_DATA(PF11_DATA, PF11MD_00, PF11_IN, PF11_OUT),
650 PINMUX_DATA(NAF3_MARK, PF11MD_01),
651 PINMUX_DATA(LCD_DATA11_MARK, PF11MD_10),
652
653 PINMUX_DATA(PF10_DATA, PF10MD_00, PF10_IN, PF10_OUT),
654 PINMUX_DATA(NAF2_MARK, PF10MD_01),
655 PINMUX_DATA(LCD_DATA10_MARK, PF10MD_10),
656
657 PINMUX_DATA(PF9_DATA, PF9MD_00, PF9_IN, PF9_OUT),
658 PINMUX_DATA(NAF1_MARK, PF9MD_01),
659 PINMUX_DATA(LCD_DATA9_MARK, PF9MD_10),
660
661 PINMUX_DATA(PF8_DATA, PF8MD_00, PF8_IN, PF8_OUT),
662 PINMUX_DATA(NAF0_MARK, PF8MD_01),
663 PINMUX_DATA(LCD_DATA8_MARK, PF8MD_10),
664
665 PINMUX_DATA(PF7_DATA, PF7MD_00, PF7_IN, PF7_OUT),
666 PINMUX_DATA(FSC_MARK, PF7MD_01),
667 PINMUX_DATA(LCD_DATA7_MARK, PF7MD_10),
668 PINMUX_DATA(SCS1_PF_MARK, PF7MD_11),
669
670 PINMUX_DATA(PF6_DATA, PF6MD_00, PF6_IN, PF6_OUT),
671 PINMUX_DATA(FOE_MARK, PF6MD_01),
672 PINMUX_DATA(LCD_DATA6_MARK, PF6MD_10),
673 PINMUX_DATA(SSO1_PF_MARK, PF6MD_11),
674
675 PINMUX_DATA(PF5_DATA, PF5MD_00, PF5_IN, PF5_OUT),
676 PINMUX_DATA(FCDE_MARK, PF5MD_01),
677 PINMUX_DATA(LCD_DATA5_MARK, PF5MD_10),
678 PINMUX_DATA(SSI1_PF_MARK, PF5MD_11),
679
680 PINMUX_DATA(PF4_DATA, PF4MD_00, PF4_IN, PF4_OUT),
681 PINMUX_DATA(FWE_MARK, PF4MD_01),
682 PINMUX_DATA(LCD_DATA4_MARK, PF4MD_10),
683 PINMUX_DATA(SSCK1_PF_MARK, PF4MD_11),
684
685 PINMUX_DATA(PF3_DATA, PF3MD_00, PF3_IN, PF3_OUT),
686 PINMUX_DATA(TCLKD_PF_MARK, PF3MD_01),
687 PINMUX_DATA(LCD_DATA3_MARK, PF3MD_10),
688 PINMUX_DATA(SCS0_PF_MARK, PF3MD_11),
689
690 PINMUX_DATA(PF2_DATA, PF2MD_00, PF2_IN, PF2_OUT),
691 PINMUX_DATA(TCLKC_PF_MARK, PF2MD_01),
692 PINMUX_DATA(LCD_DATA2_MARK, PF2MD_10),
693 PINMUX_DATA(SSO0_PF_MARK, PF2MD_11),
694
695 PINMUX_DATA(PF1_DATA, PF1MD_00, PF1_IN, PF1_OUT),
696 PINMUX_DATA(TCLKB_PF_MARK, PF1MD_01),
697 PINMUX_DATA(LCD_DATA1_MARK, PF1MD_10),
698 PINMUX_DATA(SSI0_PF_MARK, PF1MD_11),
699
700 PINMUX_DATA(PF0_DATA, PF0MD_00, PF0_IN, PF0_OUT),
701 PINMUX_DATA(TCLKA_PF_MARK, PF0MD_01),
702 PINMUX_DATA(LCD_DATA0_MARK, PF0MD_10),
703 PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11),
704};
705
706static struct pinmux_gpio pinmux_gpios[] = {
707
708 /* PA */
709 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
710 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
711 PINMUX_GPIO(GPIO_PA5, PA5_DATA),
712 PINMUX_GPIO(GPIO_PA4, PA4_DATA),
713 PINMUX_GPIO(GPIO_PA3, PA3_DATA),
714 PINMUX_GPIO(GPIO_PA2, PA2_DATA),
715 PINMUX_GPIO(GPIO_PA1, PA1_DATA),
716 PINMUX_GPIO(GPIO_PA0, PA0_DATA),
717
718 /* PB */
719 PINMUX_GPIO(GPIO_PB12, PB12_DATA),
720 PINMUX_GPIO(GPIO_PB11, PB11_DATA),
721 PINMUX_GPIO(GPIO_PB10, PB10_DATA),
722 PINMUX_GPIO(GPIO_PB9, PB9_DATA),
723 PINMUX_GPIO(GPIO_PB8, PB8_DATA),
724 PINMUX_GPIO(GPIO_PB7, PB7_DATA),
725 PINMUX_GPIO(GPIO_PB6, PB6_DATA),
726 PINMUX_GPIO(GPIO_PB5, PB5_DATA),
727 PINMUX_GPIO(GPIO_PB4, PB4_DATA),
728 PINMUX_GPIO(GPIO_PB3, PB3_DATA),
729 PINMUX_GPIO(GPIO_PB2, PB2_DATA),
730 PINMUX_GPIO(GPIO_PB1, PB1_DATA),
731 PINMUX_GPIO(GPIO_PB0, PB0_DATA),
732
733 /* PC */
734 PINMUX_GPIO(GPIO_PC14, PC14_DATA),
735 PINMUX_GPIO(GPIO_PC13, PC13_DATA),
736 PINMUX_GPIO(GPIO_PC12, PC12_DATA),
737 PINMUX_GPIO(GPIO_PC11, PC11_DATA),
738 PINMUX_GPIO(GPIO_PC10, PC10_DATA),
739 PINMUX_GPIO(GPIO_PC9, PC9_DATA),
740 PINMUX_GPIO(GPIO_PC8, PC8_DATA),
741 PINMUX_GPIO(GPIO_PC7, PC7_DATA),
742 PINMUX_GPIO(GPIO_PC6, PC6_DATA),
743 PINMUX_GPIO(GPIO_PC5, PC5_DATA),
744 PINMUX_GPIO(GPIO_PC4, PC4_DATA),
745 PINMUX_GPIO(GPIO_PC3, PC3_DATA),
746 PINMUX_GPIO(GPIO_PC2, PC2_DATA),
747 PINMUX_GPIO(GPIO_PC1, PC1_DATA),
748 PINMUX_GPIO(GPIO_PC0, PC0_DATA),
749
750 /* PD */
751 PINMUX_GPIO(GPIO_PD15, PD15_DATA),
752 PINMUX_GPIO(GPIO_PD14, PD14_DATA),
753 PINMUX_GPIO(GPIO_PD13, PD13_DATA),
754 PINMUX_GPIO(GPIO_PD12, PD12_DATA),
755 PINMUX_GPIO(GPIO_PD11, PD11_DATA),
756 PINMUX_GPIO(GPIO_PD10, PD10_DATA),
757 PINMUX_GPIO(GPIO_PD9, PD9_DATA),
758 PINMUX_GPIO(GPIO_PD8, PD8_DATA),
759 PINMUX_GPIO(GPIO_PD7, PD7_DATA),
760 PINMUX_GPIO(GPIO_PD6, PD6_DATA),
761 PINMUX_GPIO(GPIO_PD5, PD5_DATA),
762 PINMUX_GPIO(GPIO_PD4, PD4_DATA),
763 PINMUX_GPIO(GPIO_PD3, PD3_DATA),
764 PINMUX_GPIO(GPIO_PD2, PD2_DATA),
765 PINMUX_GPIO(GPIO_PD1, PD1_DATA),
766 PINMUX_GPIO(GPIO_PD0, PD0_DATA),
767
768 /* PE */
769 PINMUX_GPIO(GPIO_PE15, PE15_DATA),
770 PINMUX_GPIO(GPIO_PE14, PE14_DATA),
771 PINMUX_GPIO(GPIO_PE13, PE13_DATA),
772 PINMUX_GPIO(GPIO_PE12, PE12_DATA),
773 PINMUX_GPIO(GPIO_PE11, PE11_DATA),
774 PINMUX_GPIO(GPIO_PE10, PE10_DATA),
775 PINMUX_GPIO(GPIO_PE9, PE9_DATA),
776 PINMUX_GPIO(GPIO_PE8, PE8_DATA),
777 PINMUX_GPIO(GPIO_PE7, PE7_DATA),
778 PINMUX_GPIO(GPIO_PE6, PE6_DATA),
779 PINMUX_GPIO(GPIO_PE5, PE5_DATA),
780 PINMUX_GPIO(GPIO_PE4, PE4_DATA),
781 PINMUX_GPIO(GPIO_PE3, PE3_DATA),
782 PINMUX_GPIO(GPIO_PE2, PE2_DATA),
783 PINMUX_GPIO(GPIO_PE1, PE1_DATA),
784 PINMUX_GPIO(GPIO_PE0, PE0_DATA),
785
786 /* PF */
787 PINMUX_GPIO(GPIO_PF30, PF30_DATA),
788 PINMUX_GPIO(GPIO_PF29, PF29_DATA),
789 PINMUX_GPIO(GPIO_PF28, PF28_DATA),
790 PINMUX_GPIO(GPIO_PF27, PF27_DATA),
791 PINMUX_GPIO(GPIO_PF26, PF26_DATA),
792 PINMUX_GPIO(GPIO_PF25, PF25_DATA),
793 PINMUX_GPIO(GPIO_PF24, PF24_DATA),
794 PINMUX_GPIO(GPIO_PF23, PF23_DATA),
795 PINMUX_GPIO(GPIO_PF22, PF22_DATA),
796 PINMUX_GPIO(GPIO_PF21, PF21_DATA),
797 PINMUX_GPIO(GPIO_PF20, PF20_DATA),
798 PINMUX_GPIO(GPIO_PF19, PF19_DATA),
799 PINMUX_GPIO(GPIO_PF18, PF18_DATA),
800 PINMUX_GPIO(GPIO_PF17, PF17_DATA),
801 PINMUX_GPIO(GPIO_PF16, PF16_DATA),
802 PINMUX_GPIO(GPIO_PF15, PF15_DATA),
803 PINMUX_GPIO(GPIO_PF14, PF14_DATA),
804 PINMUX_GPIO(GPIO_PF13, PF13_DATA),
805 PINMUX_GPIO(GPIO_PF12, PF12_DATA),
806 PINMUX_GPIO(GPIO_PF11, PF11_DATA),
807 PINMUX_GPIO(GPIO_PF10, PF10_DATA),
808 PINMUX_GPIO(GPIO_PF9, PF9_DATA),
809 PINMUX_GPIO(GPIO_PF8, PF8_DATA),
810 PINMUX_GPIO(GPIO_PF7, PF7_DATA),
811 PINMUX_GPIO(GPIO_PF6, PF6_DATA),
812 PINMUX_GPIO(GPIO_PF5, PF5_DATA),
813 PINMUX_GPIO(GPIO_PF4, PF4_DATA),
814 PINMUX_GPIO(GPIO_PF3, PF3_DATA),
815 PINMUX_GPIO(GPIO_PF2, PF2_DATA),
816 PINMUX_GPIO(GPIO_PF1, PF1_DATA),
817 PINMUX_GPIO(GPIO_PF0, PF0_DATA),
818
819 /* INTC */
820 PINMUX_GPIO(GPIO_FN_PINT7_PB, PINT7_PB_MARK),
821 PINMUX_GPIO(GPIO_FN_PINT6_PB, PINT6_PB_MARK),
822 PINMUX_GPIO(GPIO_FN_PINT5_PB, PINT5_PB_MARK),
823 PINMUX_GPIO(GPIO_FN_PINT4_PB, PINT4_PB_MARK),
824 PINMUX_GPIO(GPIO_FN_PINT3_PB, PINT3_PB_MARK),
825 PINMUX_GPIO(GPIO_FN_PINT2_PB, PINT2_PB_MARK),
826 PINMUX_GPIO(GPIO_FN_PINT1_PB, PINT1_PB_MARK),
827 PINMUX_GPIO(GPIO_FN_PINT0_PB, PINT0_PB_MARK),
828 PINMUX_GPIO(GPIO_FN_PINT7_PD, PINT7_PD_MARK),
829 PINMUX_GPIO(GPIO_FN_PINT6_PD, PINT6_PD_MARK),
830 PINMUX_GPIO(GPIO_FN_PINT5_PD, PINT5_PD_MARK),
831 PINMUX_GPIO(GPIO_FN_PINT4_PD, PINT4_PD_MARK),
832 PINMUX_GPIO(GPIO_FN_PINT3_PD, PINT3_PD_MARK),
833 PINMUX_GPIO(GPIO_FN_PINT2_PD, PINT2_PD_MARK),
834 PINMUX_GPIO(GPIO_FN_PINT1_PD, PINT1_PD_MARK),
835 PINMUX_GPIO(GPIO_FN_PINT0_PD, PINT0_PD_MARK),
836 PINMUX_GPIO(GPIO_FN_IRQ7_PB, IRQ7_PB_MARK),
837 PINMUX_GPIO(GPIO_FN_IRQ6_PB, IRQ6_PB_MARK),
838 PINMUX_GPIO(GPIO_FN_IRQ5_PB, IRQ5_PB_MARK),
839 PINMUX_GPIO(GPIO_FN_IRQ4_PB, IRQ4_PB_MARK),
840 PINMUX_GPIO(GPIO_FN_IRQ3_PB, IRQ3_PB_MARK),
841 PINMUX_GPIO(GPIO_FN_IRQ2_PB, IRQ2_PB_MARK),
842 PINMUX_GPIO(GPIO_FN_IRQ1_PB, IRQ1_PB_MARK),
843 PINMUX_GPIO(GPIO_FN_IRQ0_PB, IRQ0_PB_MARK),
844 PINMUX_GPIO(GPIO_FN_IRQ7_PD, IRQ7_PD_MARK),
845 PINMUX_GPIO(GPIO_FN_IRQ6_PD, IRQ6_PD_MARK),
846 PINMUX_GPIO(GPIO_FN_IRQ5_PD, IRQ5_PD_MARK),
847 PINMUX_GPIO(GPIO_FN_IRQ4_PD, IRQ4_PD_MARK),
848 PINMUX_GPIO(GPIO_FN_IRQ3_PD, IRQ3_PD_MARK),
849 PINMUX_GPIO(GPIO_FN_IRQ2_PD, IRQ2_PD_MARK),
850 PINMUX_GPIO(GPIO_FN_IRQ1_PD, IRQ1_PD_MARK),
851 PINMUX_GPIO(GPIO_FN_IRQ0_PD, IRQ0_PD_MARK),
852 PINMUX_GPIO(GPIO_FN_IRQ7_PE, IRQ7_PE_MARK),
853 PINMUX_GPIO(GPIO_FN_IRQ6_PE, IRQ6_PE_MARK),
854 PINMUX_GPIO(GPIO_FN_IRQ5_PE, IRQ5_PE_MARK),
855 PINMUX_GPIO(GPIO_FN_IRQ4_PE, IRQ4_PE_MARK),
856 PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK),
857 PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK),
858 PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK),
859 PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK),
860
861 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
862 PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
863 PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK),
864 PINMUX_GPIO(GPIO_FN_IRQOUT_REFOUT, IRQOUT_REFOUT_MARK),
865 PINMUX_GPIO(GPIO_FN_UBCTRG, UBCTRG_MARK),
866
867 /* CAN */
868 PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
869 PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
870 PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
871 PINMUX_GPIO(GPIO_FN_CTX0_CTX1, CTX0_CTX1_MARK),
872 PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
873 PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK),
874
875 /* IIC3 */
876 PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
877 PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
878 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
879 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
880 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
881 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
882 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
883 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
884
885 /* DMAC */
886 PINMUX_GPIO(GPIO_FN_TEND0_PD, TEND0_PD_MARK),
887 PINMUX_GPIO(GPIO_FN_TEND0_PE, TEND0_PE_MARK),
888 PINMUX_GPIO(GPIO_FN_DACK0_PD, DACK0_PD_MARK),
889 PINMUX_GPIO(GPIO_FN_DACK0_PE, DACK0_PE_MARK),
890 PINMUX_GPIO(GPIO_FN_DREQ0_PD, DREQ0_PD_MARK),
891 PINMUX_GPIO(GPIO_FN_DREQ0_PE, DREQ0_PE_MARK),
892 PINMUX_GPIO(GPIO_FN_TEND1_PD, TEND1_PD_MARK),
893 PINMUX_GPIO(GPIO_FN_TEND1_PE, TEND1_PE_MARK),
894 PINMUX_GPIO(GPIO_FN_DACK1_PD, DACK1_PD_MARK),
895 PINMUX_GPIO(GPIO_FN_DACK1_PE, DACK1_PE_MARK),
896 PINMUX_GPIO(GPIO_FN_DREQ1_PD, DREQ1_PD_MARK),
897 PINMUX_GPIO(GPIO_FN_DREQ1_PE, DREQ1_PE_MARK),
898 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
899 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
900 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
901 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
902
903 /* ADC */
904 PINMUX_GPIO(GPIO_FN_ADTRG_PD, ADTRG_PD_MARK),
905 PINMUX_GPIO(GPIO_FN_ADTRG_PE, ADTRG_PE_MARK),
906
907 /* BSC */
908 PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
909 PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
910 PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
911 PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
912 PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
913 PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
914 PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
915 PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
916 PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
917 PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
918 PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
919 PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
920 PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
921 PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
922 PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
923 PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
924 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
925 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
926 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
927 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
928 PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
929 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
930 PINMUX_GPIO(GPIO_FN_MRES, MRES_MARK),
931 PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
932 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
933 PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
934 PINMUX_GPIO(GPIO_FN_CS6_CE1B, CS6_CE1B_MARK),
935 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
936 PINMUX_GPIO(GPIO_FN_CS5_CE1A, CS5_CE1A_MARK),
937 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
938 PINMUX_GPIO(GPIO_FN_FRAME, FRAME_MARK),
939 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
940 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
941 PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
942 PINMUX_GPIO(GPIO_FN_CASU, CASU_MARK),
943 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
944 PINMUX_GPIO(GPIO_FN_RASU, RASU_MARK),
945 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
946 PINMUX_GPIO(GPIO_FN_CASL, CASL_MARK),
947 PINMUX_GPIO(GPIO_FN_RASL, RASL_MARK),
948 PINMUX_GPIO(GPIO_FN_WE3_DQMUU_AH_ICIO_WR, WE3_DQMUU_AH_ICIO_WR_MARK),
949 PINMUX_GPIO(GPIO_FN_WE2_DQMUL_ICIORD, WE2_DQMUL_ICIORD_MARK),
950 PINMUX_GPIO(GPIO_FN_WE1_DQMLU_WE, WE1_DQMLU_WE_MARK),
951 PINMUX_GPIO(GPIO_FN_WE0_DQMLL, WE0_DQMLL_MARK),
952 PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
953 PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
954 PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
955 PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
956 PINMUX_GPIO(GPIO_FN_CS7, CS7_MARK),
957
958 /* TMU */
959 PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
960 PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
961 PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
962 PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
963 PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
964 PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
965 PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
966 PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
967 PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
968 PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
969 PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
970 PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
971 PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
972 PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
973 PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
974 PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
975 PINMUX_GPIO(GPIO_FN_TCLKD_PD, TCLKD_PD_MARK),
976 PINMUX_GPIO(GPIO_FN_TCLKC_PD, TCLKC_PD_MARK),
977 PINMUX_GPIO(GPIO_FN_TCLKB_PD, TCLKB_PD_MARK),
978 PINMUX_GPIO(GPIO_FN_TCLKA_PD, TCLKA_PD_MARK),
979 PINMUX_GPIO(GPIO_FN_TCLKD_PF, TCLKD_PF_MARK),
980 PINMUX_GPIO(GPIO_FN_TCLKC_PF, TCLKC_PF_MARK),
981 PINMUX_GPIO(GPIO_FN_TCLKB_PF, TCLKB_PF_MARK),
982 PINMUX_GPIO(GPIO_FN_TCLKA_PF, TCLKA_PF_MARK),
983
984 /* SSU */
985 PINMUX_GPIO(GPIO_FN_SCS0_PD, SCS0_PD_MARK),
986 PINMUX_GPIO(GPIO_FN_SSO0_PD, SSO0_PD_MARK),
987 PINMUX_GPIO(GPIO_FN_SSI0_PD, SSI0_PD_MARK),
988 PINMUX_GPIO(GPIO_FN_SSCK0_PD, SSCK0_PD_MARK),
989 PINMUX_GPIO(GPIO_FN_SCS0_PF, SCS0_PF_MARK),
990 PINMUX_GPIO(GPIO_FN_SSO0_PF, SSO0_PF_MARK),
991 PINMUX_GPIO(GPIO_FN_SSI0_PF, SSI0_PF_MARK),
992 PINMUX_GPIO(GPIO_FN_SSCK0_PF, SSCK0_PF_MARK),
993 PINMUX_GPIO(GPIO_FN_SCS1_PD, SCS1_PD_MARK),
994 PINMUX_GPIO(GPIO_FN_SSO1_PD, SSO1_PD_MARK),
995 PINMUX_GPIO(GPIO_FN_SSI1_PD, SSI1_PD_MARK),
996 PINMUX_GPIO(GPIO_FN_SSCK1_PD, SSCK1_PD_MARK),
997 PINMUX_GPIO(GPIO_FN_SCS1_PF, SCS1_PF_MARK),
998 PINMUX_GPIO(GPIO_FN_SSO1_PF, SSO1_PF_MARK),
999 PINMUX_GPIO(GPIO_FN_SSI1_PF, SSI1_PF_MARK),
1000 PINMUX_GPIO(GPIO_FN_SSCK1_PF, SSCK1_PF_MARK),
1001
1002 /* SCIF */
1003 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
1004 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
1005 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
1006 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
1007 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
1008 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
1009 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
1010 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
1011 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
1012 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
1013 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
1014 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
1015 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
1016 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
1017
1018 /* SSI */
1019 PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
1020 PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
1021 PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
1022 PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
1023 PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
1024 PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
1025 PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
1026 PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
1027 PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
1028 PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
1029 PINMUX_GPIO(GPIO_FN_SSIDATA0, SSIDATA0_MARK),
1030 PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
1031 PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
1032
1033 /* FLCTL */
1034 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
1035 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
1036 PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK),
1037 PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK),
1038 PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK),
1039 PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK),
1040 PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK),
1041 PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK),
1042 PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK),
1043 PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK),
1044 PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK),
1045 PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK),
1046 PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK),
1047 PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
1048
1049 /* LCDC */
1050 PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK),
1051 PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK),
1052 PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
1053 PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK),
1054 PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
1055 PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK),
1056 PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK),
1057 PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK),
1058 PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
1059 PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
1060 PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
1061 PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
1062 PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
1063 PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
1064 PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
1065 PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
1066 PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
1067 PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
1068 PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
1069 PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
1070 PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
1071 PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
1072 PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
1073 PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
1074};
1075
1076static struct pinmux_cfg_reg pinmux_config_regs[] = {
1077 { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) {
1078 0, 0,
1079 0, 0,
1080 0, 0,
1081 0, 0,
1082 PB11_IN, PB11_OUT,
1083 PB10_IN, PB10_OUT,
1084 PB9_IN, PB9_OUT,
1085 PB8_IN, PB8_OUT,
1086 0, 0,
1087 0, 0,
1088 0, 0,
1089 0, 0,
1090 0, 0,
1091 0, 0,
1092 0, 0,
1093 0, 0 }
1094 },
1095 { PINMUX_CFG_REG("PBCRL4", 0xfffe3890, 16, 4) {
1096 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1097
1098 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1099
1100 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1101
1102 PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
1103 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1104 },
1105 { PINMUX_CFG_REG("PBCRL3", 0xfffe3892, 16, 4) {
1106 PB11MD_0, PB11MD_1,
1107 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1108
1109 PB10MD_0, PB10MD_1,
1110 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1111
1112 PB9MD_00, PB9MD_01, PB9MD_10, 0,
1113 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1114
1115 PB8MD_00, PB8MD_01, PB8MD_10, 0,
1116 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1117 },
1118 { PINMUX_CFG_REG("PBCRL2", 0xfffe3894, 16, 4) {
1119 PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
1120 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1121
1122 PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11,
1123 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1124
1125 PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11,
1126 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1127
1128 PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
1129 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1130 },
1131 { PINMUX_CFG_REG("PBCRL1", 0xfffe3896, 16, 4) {
1132 PB3MD_00, PB3MD_01, PB3MD_10, PB3MD_11,
1133 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1134
1135 PB2MD_00, PB2MD_01, PB2MD_10, PB2MD_11,
1136 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1137
1138 PB1MD_00, PB1MD_01, PB1MD_10, PB1MD_11,
1139 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1140
1141 PB0MD_00, PB0MD_01, PB0MD_10, PB0MD_11,
1142 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1143 },
1144 { PINMUX_CFG_REG("IFCR", 0xfffe38a2, 16, 4) {
1145 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1146
1147 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1148
1149 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1150
1151 PB12IRQ_00, PB12IRQ_01, PB12IRQ_10, 0,
1152 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1153 },
1154 { PINMUX_CFG_REG("PCIORL", 0xfffe3906, 16, 1) {
1155 0, 0,
1156 PC14_IN, PC14_OUT,
1157 PC13_IN, PC13_OUT,
1158 PC12_IN, PC12_OUT,
1159 PC11_IN, PC11_OUT,
1160 PC10_IN, PC10_OUT,
1161 PC9_IN, PC9_OUT,
1162 PC8_IN, PC8_OUT,
1163 PC7_IN, PC7_OUT,
1164 PC6_IN, PC6_OUT,
1165 PC5_IN, PC5_OUT,
1166 PC4_IN, PC4_OUT,
1167 PC3_IN, PC3_OUT,
1168 PC2_IN, PC2_OUT,
1169 PC1_IN, PC1_OUT,
1170 PC0_IN, PC0_OUT }
1171 },
1172 { PINMUX_CFG_REG("PCCRL4", 0xfffe3910, 16, 4) {
1173 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1174
1175 PC14MD_0, PC14MD_1,
1176 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1177
1178 PC13MD_0, PC13MD_1,
1179 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1180
1181 PC12MD_0, PC12MD_1,
1182 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1183 },
1184 { PINMUX_CFG_REG("PCCRL3", 0xfffe3912, 16, 4) {
1185 PC11MD_00, PC11MD_01, PC11MD_10, 0,
1186 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1187
1188 PC10MD_00, PC10MD_01, PC10MD_10, 0,
1189 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1190
1191 PC9MD_0, PC9MD_1,
1192 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1193
1194 PC8MD_0, PC8MD_1,
1195 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1196 },
1197 { PINMUX_CFG_REG("PCCRL2", 0xfffe3914, 16, 4) {
1198 PC7MD_0, PC7MD_1,
1199 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1200
1201 PC6MD_0, PC6MD_1,
1202 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1203
1204 PC5MD_0, PC5MD_1,
1205 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1206
1207 PC4MD_0, PC4MD_1,
1208 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1209 },
1210 { PINMUX_CFG_REG("PCCRL1", 0xfffe3916, 16, 4) {
1211 PC3MD_0, PC3MD_1,
1212 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1213
1214 PC2MD_0, PC2MD_1,
1215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1216
1217 PC1MD_0, PC1MD_1,
1218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1219
1220 PC0MD_00, PC0MD_01, PC0MD_10, 0,
1221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1222 },
1223 { PINMUX_CFG_REG("PDIORL", 0xfffe3986, 16, 1) {
1224 PD15_IN, PD15_OUT,
1225 PD14_IN, PD14_OUT,
1226 PD13_IN, PD13_OUT,
1227 PD12_IN, PD12_OUT,
1228 PD11_IN, PD11_OUT,
1229 PD10_IN, PD10_OUT,
1230 PD9_IN, PD9_OUT,
1231 PD8_IN, PD8_OUT,
1232 PD7_IN, PD7_OUT,
1233 PD6_IN, PD6_OUT,
1234 PD5_IN, PD5_OUT,
1235 PD4_IN, PD4_OUT,
1236 PD3_IN, PD3_OUT,
1237 PD2_IN, PD2_OUT,
1238 PD1_IN, PD1_OUT,
1239 PD0_IN, PD0_OUT }
1240 },
1241 { PINMUX_CFG_REG("PDCRL4", 0xfffe3990, 16, 4) {
1242 PD15MD_000, PD15MD_001, PD15MD_010, 0,
1243 PD15MD_100, PD15MD_101, 0, 0,
1244 0, 0, 0, 0, 0, 0, 0, 0,
1245
1246 PD14MD_000, PD14MD_001, PD14MD_010, 0,
1247 0, PD14MD_101, 0, 0,
1248 0, 0, 0, 0, 0, 0, 0, 0,
1249
1250 PD13MD_000, PD13MD_001, PD13MD_010, 0,
1251 PD13MD_100, PD13MD_101, 0, 0,
1252 0, 0, 0, 0, 0, 0, 0, 0,
1253
1254 PD12MD_000, PD12MD_001, PD12MD_010, 0,
1255 PD12MD_100, PD12MD_101, 0, 0,
1256 0, 0, 0, 0, 0, 0, 0, 0 }
1257 },
1258 { PINMUX_CFG_REG("PDCRL3", 0xfffe3992, 16, 4) {
1259 PD11MD_000, PD11MD_001, PD11MD_010, 0,
1260 PD11MD_100, PD11MD_101, 0, 0,
1261 0, 0, 0, 0, 0, 0, 0, 0,
1262
1263 PD10MD_000, PD10MD_001, PD10MD_010, 0,
1264 PD10MD_100, PD10MD_101, 0, 0,
1265 0, 0, 0, 0, 0, 0, 0, 0,
1266
1267 PD9MD_000, PD9MD_001, PD9MD_010, 0,
1268 PD9MD_100, PD9MD_101, 0, 0,
1269 0, 0, 0, 0, 0, 0, 0, 0,
1270
1271 PD8MD_000, PD8MD_001, PD8MD_010, 0,
1272 PD8MD_100, PD8MD_101, 0, 0,
1273 0, 0, 0, 0, 0, 0, 0, 0 }
1274 },
1275 { PINMUX_CFG_REG("PDCRL2", 0xfffe3994, 16, 4) {
1276 PD7MD_000, PD7MD_001, PD7MD_010, PD7MD_011,
1277 PD7MD_100, PD7MD_101, 0, 0,
1278 0, 0, 0, 0, 0, 0, 0, 0,
1279
1280 PD6MD_000, PD6MD_001, PD6MD_010, PD6MD_011,
1281 PD6MD_100, PD6MD_101, 0, 0,
1282 0, 0, 0, 0, 0, 0, 0, 0,
1283
1284 PD5MD_000, PD5MD_001, PD5MD_010, PD5MD_011,
1285 PD5MD_100, PD5MD_101, 0, 0,
1286 0, 0, 0, 0, 0, 0, 0, 0,
1287
1288 PD4MD_000, PD4MD_001, PD4MD_010, PD4MD_011,
1289 PD4MD_100, PD4MD_101, 0, 0,
1290 0, 0, 0, 0, 0, 0, 0, 0 }
1291 },
1292 { PINMUX_CFG_REG("PDCRL1", 0xfffe3996, 16, 4) {
1293 PD3MD_000, PD3MD_001, PD3MD_010, PD3MD_011,
1294 PD3MD_100, PD3MD_101, 0, 0,
1295 0, 0, 0, 0, 0, 0, 0, 0,
1296
1297 PD2MD_000, PD2MD_001, PD2MD_010, PD2MD_011,
1298 PD2MD_100, PD2MD_101, 0, 0,
1299 0, 0, 0, 0, 0, 0, 0, 0,
1300
1301 PD1MD_000, PD1MD_001, PD1MD_010, PD1MD_011,
1302 PD1MD_100, PD1MD_101, 0, 0,
1303 0, 0, 0, 0, 0, 0, 0, 0,
1304
1305 PD0MD_000, PD0MD_001, PD0MD_010, PD0MD_011,
1306 PD0MD_100, PD0MD_101, 0, 0,
1307 0, 0, 0, 0, 0, 0, 0, 0 }
1308 },
1309 { PINMUX_CFG_REG("PEIORL", 0xfffe3a06, 16, 1) {
1310 PE15_IN, PE15_OUT,
1311 PE14_IN, PE14_OUT,
1312 PE13_IN, PE13_OUT,
1313 PE12_IN, PE12_OUT,
1314 PE11_IN, PE11_OUT,
1315 PE10_IN, PE10_OUT,
1316 PE9_IN, PE9_OUT,
1317 PE8_IN, PE8_OUT,
1318 PE7_IN, PE7_OUT,
1319 PE6_IN, PE6_OUT,
1320 PE5_IN, PE5_OUT,
1321 PE4_IN, PE4_OUT,
1322 PE3_IN, PE3_OUT,
1323 PE2_IN, PE2_OUT,
1324 PE1_IN, PE1_OUT,
1325 PE0_IN, PE0_OUT }
1326 },
1327 { PINMUX_CFG_REG("PECRL4", 0xfffe3a10, 16, 4) {
1328 PE15MD_00, PE15MD_01, 0, PE15MD_11,
1329 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1330
1331 PE14MD_00, PE14MD_01, 0, PE14MD_11,
1332 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1333
1334 PE13MD_00, 0, 0, PE13MD_11,
1335 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1336
1337 PE12MD_00, 0, 0, PE12MD_11,
1338 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1339 },
1340 { PINMUX_CFG_REG("PECRL3", 0xfffe3a12, 16, 4) {
1341 PE11MD_000, PE11MD_001, PE11MD_010, 0,
1342 PE11MD_100, 0, 0, 0,
1343 0, 0, 0, 0, 0, 0, 0, 0,
1344
1345 PE10MD_000, PE10MD_001, PE10MD_010, 0,
1346 PE10MD_100, 0, 0, 0,
1347 0, 0, 0, 0, 0, 0, 0, 0,
1348
1349 PE9MD_00, PE9MD_01, PE9MD_10, PE9MD_11,
1350 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1351
1352 PE8MD_00, PE8MD_01, PE8MD_10, PE8MD_11,
1353 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1354 },
1355 { PINMUX_CFG_REG("PECRL2", 0xfffe3a14, 16, 4) {
1356 PE7MD_000, PE7MD_001, PE7MD_010, PE7MD_011,
1357 PE7MD_100, 0, 0, 0,
1358 0, 0, 0, 0, 0, 0, 0, 0,
1359
1360 PE6MD_000, PE6MD_001, PE6MD_010, PE6MD_011,
1361 PE6MD_100, 0, 0, 0,
1362 0, 0, 0, 0, 0, 0, 0, 0,
1363
1364 PE5MD_000, PE5MD_001, PE5MD_010, PE5MD_011,
1365 PE5MD_100, 0, 0, 0,
1366 0, 0, 0, 0, 0, 0, 0, 0,
1367
1368 PE4MD_000, PE4MD_001, PE4MD_010, PE4MD_011,
1369 PE4MD_100, 0, 0, 0,
1370 0, 0, 0, 0, 0, 0, 0, 0 }
1371 },
1372 { PINMUX_CFG_REG("PECRL1", 0xfffe3a16, 16, 4) {
1373 PE3MD_00, PE3MD_01, 0, PE3MD_11,
1374 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1375
1376 PE2MD_00, PE2MD_01, 0, PE2MD_11,
1377 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1378
1379 PE1MD_00, PE1MD_01, PE1MD_10, PE1MD_11,
1380 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1381
1382 PE0MD_000, PE0MD_001, 0, PE0MD_011,
1383 PE0MD_100, 0, 0, 0,
1384 0, 0, 0, 0, 0, 0, 0, 0 }
1385 },
1386 { PINMUX_CFG_REG("PFIORH", 0xfffe3a84, 16, 1) {
1387 0, 0,
1388 PF30_IN, PF30_OUT,
1389 PF29_IN, PF29_OUT,
1390 PF28_IN, PF28_OUT,
1391 PF27_IN, PF27_OUT,
1392 PF26_IN, PF26_OUT,
1393 PF25_IN, PF25_OUT,
1394 PF24_IN, PF24_OUT,
1395 PF23_IN, PF23_OUT,
1396 PF22_IN, PF22_OUT,
1397 PF21_IN, PF21_OUT,
1398 PF20_IN, PF20_OUT,
1399 PF19_IN, PF19_OUT,
1400 PF18_IN, PF18_OUT,
1401 PF17_IN, PF17_OUT,
1402 PF16_IN, PF16_OUT }
1403 },
1404 { PINMUX_CFG_REG("PFIORL", 0xfffe3a86, 16, 1) {
1405 PF15_IN, PF15_OUT,
1406 PF14_IN, PF14_OUT,
1407 PF13_IN, PF13_OUT,
1408 PF12_IN, PF12_OUT,
1409 PF11_IN, PF11_OUT,
1410 PF10_IN, PF10_OUT,
1411 PF9_IN, PF9_OUT,
1412 PF8_IN, PF8_OUT,
1413 PF7_IN, PF7_OUT,
1414 PF6_IN, PF6_OUT,
1415 PF5_IN, PF5_OUT,
1416 PF4_IN, PF4_OUT,
1417 PF3_IN, PF3_OUT,
1418 PF2_IN, PF2_OUT,
1419 PF1_IN, PF1_OUT,
1420 PF0_IN, PF0_OUT }
1421 },
1422 { PINMUX_CFG_REG("PFCRH4", 0xfffe3a88, 16, 4) {
1423 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1424
1425 PF30MD_0, PF30MD_1,
1426 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1427
1428 PF29MD_0, PF29MD_1,
1429 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1430
1431 PF28MD_0, PF28MD_1,
1432 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1433 },
1434 { PINMUX_CFG_REG("PFCRH3", 0xfffe3a8a, 16, 4) {
1435 PF27MD_0, PF27MD_1,
1436 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1437
1438 PF26MD_0, PF26MD_1,
1439 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1440
1441 PF25MD_0, PF25MD_1,
1442 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1443
1444 PF24MD_0, PF24MD_1,
1445 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1446 },
1447 { PINMUX_CFG_REG("PFCRH2", 0xfffe3a8c, 16, 4) {
1448 PF23MD_00, PF23MD_01, PF23MD_10, 0,
1449 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1450
1451 PF22MD_00, PF22MD_01, PF22MD_10, 0,
1452 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1453
1454 PF21MD_00, PF21MD_01, PF21MD_10, 0,
1455 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1456
1457 PF20MD_00, PF20MD_01, PF20MD_10, 0,
1458 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1459 },
1460 { PINMUX_CFG_REG("PFCRH1", 0xfffe3a8e, 16, 4) {
1461 PF19MD_00, PF19MD_01, PF19MD_10, 0,
1462 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1463
1464 PF18MD_00, PF18MD_01, PF18MD_10, 0,
1465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1466
1467 PF17MD_00, PF17MD_01, PF17MD_10, 0,
1468 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1469
1470 PF16MD_00, PF16MD_01, PF16MD_10, 0,
1471 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1472 },
1473 { PINMUX_CFG_REG("PFCRL4", 0xfffe3a90, 16, 4) {
1474 PF15MD_00, PF15MD_01, PF15MD_10, 0,
1475 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1476
1477 PF14MD_00, PF14MD_01, PF14MD_10, 0,
1478 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1479
1480 PF13MD_00, PF13MD_01, PF13MD_10, 0,
1481 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1482
1483 PF12MD_00, PF12MD_01, PF12MD_10, 0,
1484 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1485 },
1486 { PINMUX_CFG_REG("PFCRL3", 0xfffe3a92, 16, 4) {
1487 PF11MD_00, PF11MD_01, PF11MD_10, 0,
1488 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1489
1490 PF10MD_00, PF10MD_01, PF10MD_10, 0,
1491 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1492
1493 PF9MD_00, PF9MD_01, PF9MD_10, 0,
1494 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1495
1496 PF8MD_00, PF8MD_01, PF8MD_10, 0,
1497 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1498 },
1499 { PINMUX_CFG_REG("PFCRL2", 0xfffe3a94, 16, 4) {
1500 PF7MD_00, PF7MD_01, PF7MD_10, PF7MD_11,
1501 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1502
1503 PF6MD_00, PF6MD_01, PF6MD_10, PF6MD_11,
1504 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1505
1506 PF5MD_00, PF5MD_01, PF5MD_10, PF5MD_11,
1507 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1508
1509 PF4MD_00, PF4MD_01, PF4MD_10, PF4MD_11,
1510 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1511 },
1512 { PINMUX_CFG_REG("PFCRL1", 0xfffe3a96, 16, 4) {
1513 PF3MD_00, PF3MD_01, PF3MD_10, PF3MD_11,
1514 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1515
1516 PF2MD_00, PF2MD_01, PF2MD_10, PF2MD_11,
1517 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1518
1519 PF1MD_00, PF1MD_01, PF1MD_10, PF1MD_11,
1520 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1521
1522 PF0MD_00, PF0MD_01, PF0MD_10, PF0MD_11,
1523 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1524 },
1525 {}
1526};
1527
1528static struct pinmux_data_reg pinmux_data_regs[] = {
1529 { PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) {
1530 0, 0, 0, 0,
1531 0, 0, 0, 0,
1532 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
1533 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
1534 },
1535 { PINMUX_DATA_REG("PBDRL", 0xfffe3882, 16) {
1536 0, 0, 0, PB12_DATA,
1537 PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
1538 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
1539 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
1540 },
1541 { PINMUX_DATA_REG("PCDRL", 0xfffe3902, 16) {
1542 0, PC14_DATA, PC13_DATA, PC12_DATA,
1543 PC11_DATA, PC10_DATA, PC9_DATA, PC8_DATA,
1544 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
1545 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
1546 },
1547 { PINMUX_DATA_REG("PDDRL", 0xfffe3982, 16) {
1548 PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
1549 PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
1550 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
1551 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
1552 },
1553 { PINMUX_DATA_REG("PEDRL", 0xfffe3a02, 16) {
1554 PE15_DATA, PE14_DATA, PE13_DATA, PE12_DATA,
1555 PE11_DATA, PE10_DATA, PE9_DATA, PE8_DATA,
1556 PE7_DATA, PE6_DATA, PE5_DATA, PE4_DATA,
1557 PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
1558 },
1559 { PINMUX_DATA_REG("PFDRH", 0xfffe3a80, 16) {
1560 0, PF30_DATA, PF29_DATA, PF28_DATA,
1561 PF27_DATA, PF26_DATA, PF25_DATA, PF24_DATA,
1562 PF23_DATA, PF22_DATA, PF21_DATA, PF20_DATA,
1563 PF19_DATA, PF18_DATA, PF17_DATA, PF16_DATA }
1564 },
1565 { PINMUX_DATA_REG("PFDRL", 0xfffe3a82, 16) {
1566 PF15_DATA, PF14_DATA, PF13_DATA, PF12_DATA,
1567 PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
1568 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
1569 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
1570 },
1571 { },
1572};
1573
1574static struct pinmux_info sh7203_pinmux_info = {
1575 .name = "sh7203_pfc",
1576 .reserved_id = PINMUX_RESERVED,
1577 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1578 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1579 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1580 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1581 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1582
1583 .first_gpio = GPIO_PA7,
1584 .last_gpio = GPIO_FN_LCD_DATA0,
1585
1586 .gpios = pinmux_gpios,
1587 .cfg_regs = pinmux_config_regs,
1588 .data_regs = pinmux_data_regs,
1589
1590 .gpio_data = pinmux_data,
1591 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1592};
1593
1594static int __init plat_pinmux_setup(void)
1595{
1596 return register_pinmux(&sh7203_pinmux_info);
1597}
1598
1599arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile
index 511de55af832..e07c69e16d9b 100644
--- a/arch/sh/kernel/cpu/sh3/Makefile
+++ b/arch/sh/kernel/cpu/sh3/Makefile
@@ -24,4 +24,8 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7710) := clock-sh7710.o
24clock-$(CONFIG_CPU_SUBTYPE_SH7720) := clock-sh7710.o 24clock-$(CONFIG_CPU_SUBTYPE_SH7720) := clock-sh7710.o
25clock-$(CONFIG_CPU_SUBTYPE_SH7712) := clock-sh7712.o 25clock-$(CONFIG_CPU_SUBTYPE_SH7712) := clock-sh7712.o
26 26
27# Pinmux setup
28pinmux-$(CONFIG_CPU_SUBTYPE_SH7720) := pinmux-sh7720.o
29
27obj-y += $(clock-y) 30obj-y += $(clock-y)
31obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y)
diff --git a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
new file mode 100644
index 000000000000..9ca154627147
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
@@ -0,0 +1,1242 @@
1/*
2 * SH7720 Pinmux
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/gpio.h>
14#include <cpu/sh7720.h>
15
16enum {
17 PINMUX_RESERVED = 0,
18
19 PINMUX_DATA_BEGIN,
20 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
21 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
22 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
23 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
24 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
25 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
26 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
27 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
28 PTE6_DATA, PTE5_DATA, PTE4_DATA,
29 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
30 PTF6_DATA, PTF5_DATA, PTF4_DATA,
31 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
32 PTG6_DATA, PTG5_DATA, PTG4_DATA,
33 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
34 PTH6_DATA, PTH5_DATA, PTH4_DATA,
35 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
36 PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
37 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
38 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
39 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, PTL3_DATA,
40 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
41 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
42 PTP4_DATA, PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA,
43 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
44 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
45 PTS4_DATA, PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
46 PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
47 PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
48 PTV4_DATA, PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
49 PINMUX_DATA_END,
50
51 PINMUX_INPUT_BEGIN,
52 PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
53 PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
54 PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
55 PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
56 PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
57 PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
58 PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
59 PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
60 PTE6_IN, PTE5_IN, PTE4_IN,
61 PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
62 PTF6_IN, PTF5_IN, PTF4_IN,
63 PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
64 PTG6_IN, PTG5_IN, PTG4_IN,
65 PTG3_IN, PTG2_IN, PTG1_IN, PTG0_IN,
66 PTH6_IN, PTH5_IN, PTH4_IN,
67 PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
68 PTJ6_IN, PTJ5_IN, PTJ4_IN,
69 PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
70 PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
71 PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, PTL3_IN,
72 PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
73 PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
74 PTP4_IN, PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN,
75 PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
76 PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
77 PTS4_IN, PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
78 PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
79 PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
80 PTV4_IN, PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
81 PINMUX_INPUT_END,
82
83 PINMUX_INPUT_PULLUP_BEGIN,
84 PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU,
85 PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
86 PTB7_IN_PU, PTB6_IN_PU, PTB5_IN_PU, PTB4_IN_PU,
87 PTB3_IN_PU, PTB2_IN_PU, PTB1_IN_PU, PTB0_IN_PU,
88 PTC7_IN_PU, PTC6_IN_PU, PTC5_IN_PU, PTC4_IN_PU,
89 PTC3_IN_PU, PTC2_IN_PU, PTC1_IN_PU, PTC0_IN_PU,
90 PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
91 PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU,
92 PTE4_IN_PU, PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU,
93 PTF0_IN_PU,
94 PTG6_IN_PU, PTG5_IN_PU, PTG4_IN_PU,
95 PTG3_IN_PU, PTG2_IN_PU, PTG1_IN_PU, PTG0_IN_PU,
96 PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU,
97 PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU,
98 PTJ6_IN_PU, PTJ5_IN_PU, PTJ4_IN_PU,
99 PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU,
100 PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU,
101 PTL7_IN_PU, PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU, PTL3_IN_PU,
102 PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU,
103 PTM3_IN_PU, PTM2_IN_PU, PTM1_IN_PU, PTM0_IN_PU,
104 PTP4_IN_PU, PTP3_IN_PU, PTP2_IN_PU, PTP1_IN_PU, PTP0_IN_PU,
105 PTR7_IN_PU, PTR6_IN_PU, PTR5_IN_PU, PTR4_IN_PU,
106 PTR3_IN_PU, PTR2_IN_PU, PTR1_IN_PU, PTR0_IN_PU,
107 PTS4_IN_PU, PTS3_IN_PU, PTS2_IN_PU, PTS1_IN_PU, PTS0_IN_PU,
108 PTT4_IN_PU, PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU,
109 PTU4_IN_PU, PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
110 PTV4_IN_PU, PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU,
111 PINMUX_INPUT_PULLUP_END,
112
113 PINMUX_OUTPUT_BEGIN,
114 PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
115 PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
116 PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
117 PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
118 PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
119 PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
120 PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
121 PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
122 PTE4_OUT, PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
123 PTF0_OUT,
124 PTG6_OUT, PTG5_OUT, PTG4_OUT,
125 PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
126 PTH6_OUT, PTH5_OUT, PTH4_OUT,
127 PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
128 PTJ6_OUT, PTJ5_OUT, PTJ4_OUT,
129 PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
130 PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
131 PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, PTL3_OUT,
132 PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
133 PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
134 PTP4_OUT, PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT,
135 PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
136 PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT,
137 PTS4_OUT, PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
138 PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
139 PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
140 PTV4_OUT, PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
141 PINMUX_OUTPUT_END,
142
143 PINMUX_FUNCTION_BEGIN,
144 PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
145 PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
146 PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
147 PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
148 PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
149 PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
150 PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
151 PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
152 PTE6_FN, PTE5_FN, PTE4_FN,
153 PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
154 PTF6_FN, PTF5_FN, PTF4_FN,
155 PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
156 PTG6_FN, PTG5_FN, PTG4_FN,
157 PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
158 PTH6_FN, PTH5_FN, PTH4_FN,
159 PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
160 PTJ6_FN, PTJ5_FN, PTJ4_FN,
161 PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
162 PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
163 PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN, PTL3_FN,
164 PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
165 PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
166 PTP4_FN, PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN,
167 PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
168 PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
169 PTS4_FN, PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
170 PTT4_FN, PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
171 PTU4_FN, PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
172 PTV4_FN, PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
173
174 PSELA_1_0_00, PSELA_1_0_01, PSELA_1_0_10,
175 PSELA_3_2_00, PSELA_3_2_01, PSELA_3_2_10, PSELA_3_2_11,
176 PSELA_5_4_00, PSELA_5_4_01, PSELA_5_4_10, PSELA_5_4_11,
177 PSELA_7_6_00, PSELA_7_6_01, PSELA_7_6_10,
178 PSELA_9_8_00, PSELA_9_8_01, PSELA_9_8_10,
179 PSELA_11_10_00, PSELA_11_10_01, PSELA_11_10_10,
180 PSELA_13_12_00, PSELA_13_12_10,
181 PSELA_15_14_00, PSELA_15_14_10,
182 PSELB_9_8_00, PSELB_9_8_11,
183 PSELB_11_10_00, PSELB_11_10_01, PSELB_11_10_10, PSELB_11_10_11,
184 PSELB_13_12_00, PSELB_13_12_01, PSELB_13_12_10, PSELB_13_12_11,
185 PSELB_15_14_00, PSELB_15_14_11,
186 PSELC_9_8_00, PSELC_9_8_10,
187 PSELC_11_10_00, PSELC_11_10_10,
188 PSELC_13_12_00, PSELC_13_12_01, PSELC_13_12_10,
189 PSELC_15_14_00, PSELC_15_14_01, PSELC_15_14_10,
190 PSELD_1_0_00, PSELD_1_0_10,
191 PSELD_11_10_00, PSELD_11_10_01,
192 PSELD_15_14_00, PSELD_15_14_01, PSELD_15_14_10,
193 PINMUX_FUNCTION_END,
194
195 PINMUX_MARK_BEGIN,
196 D31_MARK, D30_MARK, D29_MARK, D28_MARK,
197 D27_MARK, D26_MARK, D25_MARK, D24_MARK,
198 D23_MARK, D22_MARK, D21_MARK, D20_MARK,
199 D19_MARK, D18_MARK, D17_MARK, D16_MARK,
200 IOIS16_MARK, RAS_MARK, CAS_MARK, CKE_MARK,
201 CS5B_CE1A_MARK, CS6B_CE1B_MARK,
202 A25_MARK, A24_MARK, A23_MARK, A22_MARK,
203 A21_MARK, A20_MARK, A19_MARK, A0_MARK,
204 REFOUT_MARK, IRQOUT_MARK,
205 LCD_DATA15_MARK, LCD_DATA14_MARK,
206 LCD_DATA13_MARK, LCD_DATA12_MARK,
207 LCD_DATA11_MARK, LCD_DATA10_MARK,
208 LCD_DATA9_MARK, LCD_DATA8_MARK,
209 LCD_DATA7_MARK, LCD_DATA6_MARK,
210 LCD_DATA5_MARK, LCD_DATA4_MARK,
211 LCD_DATA3_MARK, LCD_DATA2_MARK,
212 LCD_DATA1_MARK, LCD_DATA0_MARK,
213 LCD_M_DISP_MARK,
214 LCD_CL1_MARK, LCD_CL2_MARK,
215 LCD_DON_MARK, LCD_FLM_MARK,
216 LCD_VEPWC_MARK, LCD_VCPWC_MARK,
217 AFE_RXIN_MARK, AFE_RDET_MARK,
218 AFE_FS_MARK, AFE_TXOUT_MARK,
219 AFE_SCLK_MARK, AFE_RLYCNT_MARK,
220 AFE_HC1_MARK,
221 IIC_SCL_MARK, IIC_SDA_MARK,
222 DA1_MARK, DA0_MARK,
223 AN3_MARK, AN2_MARK, AN1_MARK, AN0_MARK, ADTRG_MARK,
224 USB1D_RCV_MARK, USB1D_TXSE0_MARK,
225 USB1D_TXDPLS_MARK, USB1D_DMNS_MARK,
226 USB1D_DPLS_MARK, USB1D_SPEED_MARK,
227 USB1D_TXENL_MARK,
228 USB2_PWR_EN_MARK, USB1_PWR_EN_USBF_UPLUP_MARK, USB1D_SUSPEND_MARK,
229 IRQ5_MARK, IRQ4_MARK,
230 IRQ3_IRL3_MARK, IRQ2_IRL2_MARK,
231 IRQ1_IRL1_MARK, IRQ0_IRL0_MARK,
232 PCC_REG_MARK, PCC_DRV_MARK,
233 PCC_BVD2_MARK, PCC_BVD1_MARK,
234 PCC_CD2_MARK, PCC_CD1_MARK,
235 PCC_RESET_MARK, PCC_RDY_MARK,
236 PCC_VS2_MARK, PCC_VS1_MARK,
237 AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK,
238 AUDCK_MARK, AUDSYNC_MARK, ASEBRKAK_MARK, TRST_MARK,
239 TMS_MARK, TDO_MARK, TDI_MARK, TCK_MARK,
240 DACK1_MARK, DREQ1_MARK, DACK0_MARK, DREQ0_MARK,
241 TEND1_MARK, TEND0_MARK,
242 SIOF0_SYNC_MARK, SIOF0_MCLK_MARK,
243 SIOF0_TXD_MARK, SIOF0_RXD_MARK,
244 SIOF0_SCK_MARK,
245 SIOF1_SYNC_MARK, SIOF1_MCLK_MARK,
246 SIOF1_TXD_MARK, SIOF1_RXD_MARK,
247 SIOF1_SCK_MARK,
248 SCIF0_TXD_MARK, SCIF0_RXD_MARK,
249 SCIF0_RTS_MARK, SCIF0_CTS_MARK, SCIF0_SCK_MARK,
250 SCIF1_TXD_MARK, SCIF1_RXD_MARK,
251 SCIF1_RTS_MARK, SCIF1_CTS_MARK, SCIF1_SCK_MARK,
252 TPU_TO1_MARK, TPU_TO0_MARK,
253 TPU_TI3B_MARK, TPU_TI3A_MARK,
254 TPU_TI2B_MARK, TPU_TI2A_MARK,
255 TPU_TO3_MARK, TPU_TO2_MARK,
256 SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK,
257 MMC_DAT_MARK, MMC_CMD_MARK,
258 MMC_CLK_MARK, MMC_VDDON_MARK,
259 MMC_ODMOD_MARK,
260 STATUS0_MARK, STATUS1_MARK,
261 PINMUX_MARK_END,
262};
263
264static pinmux_enum_t pinmux_data[] = {
265 /* PTA GPIO */
266 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
267 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
268 PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT, PTA5_IN_PU),
269 PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU),
270 PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU),
271 PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU),
272 PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU),
273 PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU),
274
275 /* PTB GPIO */
276 PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT, PTB7_IN_PU),
277 PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT, PTB6_IN_PU),
278 PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT, PTB5_IN_PU),
279 PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT, PTB4_IN_PU),
280 PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT, PTB3_IN_PU),
281 PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU),
282 PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU),
283 PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT, PTB0_IN_PU),
284
285 /* PTC GPIO */
286 PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT, PTC7_IN_PU),
287 PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT, PTC6_IN_PU),
288 PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT, PTC5_IN_PU),
289 PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT, PTC4_IN_PU),
290 PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT, PTC3_IN_PU),
291 PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT, PTC2_IN_PU),
292 PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT, PTC1_IN_PU),
293 PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT, PTC0_IN_PU),
294
295 /* PTD GPIO */
296 PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT, PTD7_IN_PU),
297 PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT, PTD6_IN_PU),
298 PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT, PTD5_IN_PU),
299 PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT, PTD4_IN_PU),
300 PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT, PTD3_IN_PU),
301 PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT, PTD2_IN_PU),
302 PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT, PTD1_IN_PU),
303 PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT, PTD0_IN_PU),
304
305 /* PTE GPIO */
306 PINMUX_DATA(PTE6_DATA, PTE6_IN),
307 PINMUX_DATA(PTE5_DATA, PTE5_IN),
308 PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT, PTE4_IN_PU),
309 PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT, PTE3_IN_PU),
310 PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT, PTE2_IN_PU),
311 PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT, PTE1_IN_PU),
312 PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT, PTE0_IN_PU),
313
314 /* PTF GPIO */
315 PINMUX_DATA(PTF6_DATA, PTF6_IN),
316 PINMUX_DATA(PTF5_DATA, PTF5_IN),
317 PINMUX_DATA(PTF4_DATA, PTF4_IN),
318 PINMUX_DATA(PTF3_DATA, PTF3_IN),
319 PINMUX_DATA(PTF2_DATA, PTF2_IN),
320 PINMUX_DATA(PTF1_DATA, PTF1_IN),
321 PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT, PTF0_IN_PU),
322
323 /* PTG GPIO */
324 PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT, PTG6_IN_PU),
325 PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT, PTG5_IN_PU),
326 PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT, PTG4_IN_PU),
327 PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT, PTG3_IN_PU),
328 PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT, PTG2_IN_PU),
329 PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT, PTG1_IN_PU),
330 PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT, PTG0_IN_PU),
331
332 /* PTH GPIO */
333 PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT, PTH6_IN_PU),
334 PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT, PTH5_IN_PU),
335 PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT, PTH4_IN_PU),
336 PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT, PTH3_IN_PU),
337 PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT, PTH2_IN_PU),
338 PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT, PTH1_IN_PU),
339 PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT, PTH0_IN_PU),
340
341 /* PTJ GPIO */
342 PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT, PTJ6_IN_PU),
343 PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT, PTJ5_IN_PU),
344 PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT, PTJ4_IN_PU),
345 PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT, PTJ3_IN_PU),
346 PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT, PTJ2_IN_PU),
347 PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT, PTJ1_IN_PU),
348 PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT, PTJ0_IN_PU),
349
350 /* PTK GPIO */
351 PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT, PTK3_IN_PU),
352 PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT, PTK2_IN_PU),
353 PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT, PTK1_IN_PU),
354 PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT, PTK0_IN_PU),
355
356 /* PTL GPIO */
357 PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT, PTL7_IN_PU),
358 PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT, PTL6_IN_PU),
359 PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT, PTL5_IN_PU),
360 PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT, PTL4_IN_PU),
361 PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT, PTL3_IN_PU),
362
363 /* PTM GPIO */
364 PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT, PTM7_IN_PU),
365 PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT, PTM6_IN_PU),
366 PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT, PTM5_IN_PU),
367 PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT, PTM4_IN_PU),
368 PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT, PTM3_IN_PU),
369 PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT, PTM2_IN_PU),
370 PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT, PTM1_IN_PU),
371 PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT, PTM0_IN_PU),
372
373 /* PTP GPIO */
374 PINMUX_DATA(PTP4_DATA, PTP4_IN, PTP4_OUT, PTP4_IN_PU),
375 PINMUX_DATA(PTP3_DATA, PTP3_IN, PTP3_OUT, PTP3_IN_PU),
376 PINMUX_DATA(PTP2_DATA, PTP2_IN, PTP2_OUT, PTP2_IN_PU),
377 PINMUX_DATA(PTP1_DATA, PTP1_IN, PTP1_OUT, PTP1_IN_PU),
378 PINMUX_DATA(PTP0_DATA, PTP0_IN, PTP0_OUT, PTP0_IN_PU),
379
380 /* PTR GPIO */
381 PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT, PTR7_IN_PU),
382 PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT, PTR6_IN_PU),
383 PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT, PTR5_IN_PU),
384 PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT, PTR4_IN_PU),
385 PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT, PTR3_IN_PU),
386 PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT, PTR2_IN_PU),
387 PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT, PTR1_IN_PU),
388 PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT, PTR0_IN_PU),
389
390 /* PTS GPIO */
391 PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT, PTS4_IN_PU),
392 PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT, PTS3_IN_PU),
393 PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT, PTS2_IN_PU),
394 PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT, PTS1_IN_PU),
395 PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT, PTS0_IN_PU),
396
397 /* PTT GPIO */
398 PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT, PTT4_IN_PU),
399 PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT, PTT3_IN_PU),
400 PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT, PTT2_IN_PU),
401 PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT, PTT1_IN_PU),
402 PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT, PTT0_IN_PU),
403
404 /* PTU GPIO */
405 PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT, PTU4_IN_PU),
406 PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT, PTU3_IN_PU),
407 PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT, PTU2_IN_PU),
408 PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT, PTU1_IN_PU),
409 PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT, PTU0_IN_PU),
410
411 /* PTV GPIO */
412 PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT, PTV4_IN_PU),
413 PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT, PTV3_IN_PU),
414 PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT, PTV2_IN_PU),
415 PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT, PTV1_IN_PU),
416 PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT, PTV0_IN_PU),
417
418 /* PTA FN */
419 PINMUX_DATA(D23_MARK, PTA7_FN),
420 PINMUX_DATA(D22_MARK, PTA6_FN),
421 PINMUX_DATA(D21_MARK, PTA5_FN),
422 PINMUX_DATA(D20_MARK, PTA4_FN),
423 PINMUX_DATA(D19_MARK, PTA3_FN),
424 PINMUX_DATA(D18_MARK, PTA2_FN),
425 PINMUX_DATA(D17_MARK, PTA1_FN),
426 PINMUX_DATA(D16_MARK, PTA0_FN),
427
428 /* PTB FN */
429 PINMUX_DATA(D31_MARK, PTB7_FN),
430 PINMUX_DATA(D30_MARK, PTB6_FN),
431 PINMUX_DATA(D29_MARK, PTB5_FN),
432 PINMUX_DATA(D28_MARK, PTB4_FN),
433 PINMUX_DATA(D27_MARK, PTB3_FN),
434 PINMUX_DATA(D26_MARK, PTB2_FN),
435 PINMUX_DATA(D25_MARK, PTB1_FN),
436 PINMUX_DATA(D24_MARK, PTB0_FN),
437
438 /* PTC FN */
439 PINMUX_DATA(LCD_DATA7_MARK, PTC7_FN),
440 PINMUX_DATA(LCD_DATA6_MARK, PTC6_FN),
441 PINMUX_DATA(LCD_DATA5_MARK, PTC5_FN),
442 PINMUX_DATA(LCD_DATA4_MARK, PTC4_FN),
443 PINMUX_DATA(LCD_DATA3_MARK, PTC3_FN),
444 PINMUX_DATA(LCD_DATA2_MARK, PTC2_FN),
445 PINMUX_DATA(LCD_DATA1_MARK, PTC1_FN),
446 PINMUX_DATA(LCD_DATA0_MARK, PTC0_FN),
447
448 /* PTD FN */
449 PINMUX_DATA(LCD_DATA15_MARK, PTD7_FN),
450 PINMUX_DATA(LCD_DATA14_MARK, PTD6_FN),
451 PINMUX_DATA(LCD_DATA13_MARK, PTD5_FN),
452 PINMUX_DATA(LCD_DATA12_MARK, PTD4_FN),
453 PINMUX_DATA(LCD_DATA11_MARK, PTD3_FN),
454 PINMUX_DATA(LCD_DATA10_MARK, PTD2_FN),
455 PINMUX_DATA(LCD_DATA9_MARK, PTD1_FN),
456 PINMUX_DATA(LCD_DATA8_MARK, PTD0_FN),
457
458 /* PTE FN */
459 PINMUX_DATA(IIC_SCL_MARK, PSELB_9_8_00, PTE6_FN),
460 PINMUX_DATA(AFE_RXIN_MARK, PSELB_9_8_11, PTE6_FN),
461 PINMUX_DATA(IIC_SDA_MARK, PSELB_9_8_00, PTE5_FN),
462 PINMUX_DATA(AFE_RDET_MARK, PSELB_9_8_11, PTE5_FN),
463 PINMUX_DATA(LCD_M_DISP_MARK, PTE4_FN),
464 PINMUX_DATA(LCD_CL1_MARK, PTE3_FN),
465 PINMUX_DATA(LCD_CL2_MARK, PTE2_FN),
466 PINMUX_DATA(LCD_DON_MARK, PTE1_FN),
467 PINMUX_DATA(LCD_FLM_MARK, PTE0_FN),
468
469 /* PTF FN */
470 PINMUX_DATA(DA1_MARK, PTF6_FN),
471 PINMUX_DATA(DA0_MARK, PTF5_FN),
472 PINMUX_DATA(AN3_MARK, PTF4_FN),
473 PINMUX_DATA(AN2_MARK, PTF3_FN),
474 PINMUX_DATA(AN1_MARK, PTF2_FN),
475 PINMUX_DATA(AN0_MARK, PTF1_FN),
476 PINMUX_DATA(ADTRG_MARK, PTF0_FN),
477
478 /* PTG FN */
479 PINMUX_DATA(USB1D_RCV_MARK, PSELA_3_2_00, PTG6_FN),
480 PINMUX_DATA(AFE_FS_MARK, PSELA_3_2_01, PTG6_FN),
481 PINMUX_DATA(PCC_REG_MARK, PSELA_3_2_10, PTG6_FN),
482 PINMUX_DATA(IRQ5_MARK, PSELA_3_2_11, PTG6_FN),
483 PINMUX_DATA(USB1D_TXSE0_MARK, PSELA_5_4_00, PTG5_FN),
484 PINMUX_DATA(AFE_TXOUT_MARK, PSELA_5_4_01, PTG5_FN),
485 PINMUX_DATA(PCC_DRV_MARK, PSELA_5_4_10, PTG5_FN),
486 PINMUX_DATA(IRQ4_MARK, PSELA_5_4_11, PTG5_FN),
487 PINMUX_DATA(USB1D_TXDPLS_MARK, PSELA_7_6_00, PTG4_FN),
488 PINMUX_DATA(AFE_SCLK_MARK, PSELA_7_6_01, PTG4_FN),
489 PINMUX_DATA(IOIS16_MARK, PSELA_7_6_10, PTG4_FN),
490 PINMUX_DATA(USB1D_DMNS_MARK, PSELA_9_8_00, PTG3_FN),
491 PINMUX_DATA(AFE_RLYCNT_MARK, PSELA_9_8_01, PTG3_FN),
492 PINMUX_DATA(PCC_BVD2_MARK, PSELA_9_8_10, PTG3_FN),
493 PINMUX_DATA(USB1D_DPLS_MARK, PSELA_11_10_00, PTG2_FN),
494 PINMUX_DATA(AFE_HC1_MARK, PSELA_11_10_01, PTG2_FN),
495 PINMUX_DATA(PCC_BVD1_MARK, PSELA_11_10_10, PTG2_FN),
496 PINMUX_DATA(USB1D_SPEED_MARK, PSELA_13_12_00, PTG1_FN),
497 PINMUX_DATA(PCC_CD2_MARK, PSELA_13_12_10, PTG1_FN),
498 PINMUX_DATA(USB1D_TXENL_MARK, PSELA_15_14_00, PTG0_FN),
499 PINMUX_DATA(PCC_CD1_MARK, PSELA_15_14_10, PTG0_FN),
500
501 /* PTH FN */
502 PINMUX_DATA(RAS_MARK, PTH6_FN),
503 PINMUX_DATA(CAS_MARK, PTH5_FN),
504 PINMUX_DATA(CKE_MARK, PTH4_FN),
505 PINMUX_DATA(STATUS1_MARK, PTH3_FN),
506 PINMUX_DATA(STATUS0_MARK, PTH2_FN),
507 PINMUX_DATA(USB2_PWR_EN_MARK, PTH1_FN),
508 PINMUX_DATA(USB1_PWR_EN_USBF_UPLUP_MARK, PTH0_FN),
509
510 /* PTJ FN */
511 PINMUX_DATA(AUDCK_MARK, PTJ6_FN),
512 PINMUX_DATA(ASEBRKAK_MARK, PTJ5_FN),
513 PINMUX_DATA(AUDATA3_MARK, PTJ4_FN),
514 PINMUX_DATA(AUDATA2_MARK, PTJ3_FN),
515 PINMUX_DATA(AUDATA1_MARK, PTJ2_FN),
516 PINMUX_DATA(AUDATA0_MARK, PTJ1_FN),
517 PINMUX_DATA(AUDSYNC_MARK, PTJ0_FN),
518
519 /* PTK FN */
520 PINMUX_DATA(PCC_RESET_MARK, PTK3_FN),
521 PINMUX_DATA(PCC_RDY_MARK, PTK2_FN),
522 PINMUX_DATA(PCC_VS2_MARK, PTK1_FN),
523 PINMUX_DATA(PCC_VS1_MARK, PTK0_FN),
524
525 /* PTL FN */
526 PINMUX_DATA(TRST_MARK, PTL7_FN),
527 PINMUX_DATA(TMS_MARK, PTL6_FN),
528 PINMUX_DATA(TDO_MARK, PTL5_FN),
529 PINMUX_DATA(TDI_MARK, PTL4_FN),
530 PINMUX_DATA(TCK_MARK, PTL3_FN),
531
532 /* PTM FN */
533 PINMUX_DATA(DREQ1_MARK, PTM7_FN),
534 PINMUX_DATA(DREQ0_MARK, PTM6_FN),
535 PINMUX_DATA(DACK1_MARK, PTM5_FN),
536 PINMUX_DATA(DACK0_MARK, PTM4_FN),
537 PINMUX_DATA(TEND1_MARK, PTM3_FN),
538 PINMUX_DATA(TEND0_MARK, PTM2_FN),
539 PINMUX_DATA(CS5B_CE1A_MARK, PTM1_FN),
540 PINMUX_DATA(CS6B_CE1B_MARK, PTM0_FN),
541
542 /* PTP FN */
543 PINMUX_DATA(USB1D_SUSPEND_MARK, PSELA_1_0_00, PTP4_FN),
544 PINMUX_DATA(REFOUT_MARK, PSELA_1_0_01, PTP4_FN),
545 PINMUX_DATA(IRQOUT_MARK, PSELA_1_0_10, PTP4_FN),
546 PINMUX_DATA(IRQ3_IRL3_MARK, PTP3_FN),
547 PINMUX_DATA(IRQ2_IRL2_MARK, PTP2_FN),
548 PINMUX_DATA(IRQ1_IRL1_MARK, PTP1_FN),
549 PINMUX_DATA(IRQ0_IRL0_MARK, PTP0_FN),
550
551 /* PTR FN */
552 PINMUX_DATA(A25_MARK, PTR7_FN),
553 PINMUX_DATA(A24_MARK, PTR6_FN),
554 PINMUX_DATA(A23_MARK, PTR5_FN),
555 PINMUX_DATA(A22_MARK, PTR4_FN),
556 PINMUX_DATA(A21_MARK, PTR3_FN),
557 PINMUX_DATA(A20_MARK, PTR2_FN),
558 PINMUX_DATA(A19_MARK, PTR1_FN),
559 PINMUX_DATA(A0_MARK, PTR0_FN),
560
561 /* PTS FN */
562 PINMUX_DATA(SIOF0_SYNC_MARK, PTS4_FN),
563 PINMUX_DATA(SIOF0_MCLK_MARK, PTS3_FN),
564 PINMUX_DATA(SIOF0_TXD_MARK, PTS2_FN),
565 PINMUX_DATA(SIOF0_RXD_MARK, PTS1_FN),
566 PINMUX_DATA(SIOF0_SCK_MARK, PTS0_FN),
567
568 /* PTT FN */
569 PINMUX_DATA(SCIF0_CTS_MARK, PSELB_15_14_00, PTT4_FN),
570 PINMUX_DATA(TPU_TO1_MARK, PSELB_15_14_11, PTT4_FN),
571 PINMUX_DATA(SCIF0_RTS_MARK, PSELB_15_14_00, PTT3_FN),
572 PINMUX_DATA(TPU_TO0_MARK, PSELB_15_14_11, PTT3_FN),
573 PINMUX_DATA(SCIF0_TXD_MARK, PTT2_FN),
574 PINMUX_DATA(SCIF0_RXD_MARK, PTT1_FN),
575 PINMUX_DATA(SCIF0_SCK_MARK, PTT0_FN),
576
577 /* PTU FN */
578 PINMUX_DATA(SIOF1_SYNC_MARK, PTU4_FN),
579 PINMUX_DATA(SIOF1_MCLK_MARK, PSELD_11_10_00, PTU3_FN),
580 PINMUX_DATA(TPU_TI3B_MARK, PSELD_11_10_01, PTU3_FN),
581 PINMUX_DATA(SIOF1_TXD_MARK, PSELD_15_14_00, PTU2_FN),
582 PINMUX_DATA(TPU_TI3A_MARK, PSELD_15_14_01, PTU2_FN),
583 PINMUX_DATA(MMC_DAT_MARK, PSELD_15_14_10, PTU2_FN),
584 PINMUX_DATA(SIOF1_RXD_MARK, PSELC_13_12_00, PTU1_FN),
585 PINMUX_DATA(TPU_TI2B_MARK, PSELC_13_12_01, PTU1_FN),
586 PINMUX_DATA(MMC_CMD_MARK, PSELC_13_12_10, PTU1_FN),
587 PINMUX_DATA(SIOF1_SCK_MARK, PSELC_15_14_00, PTU0_FN),
588 PINMUX_DATA(TPU_TI2A_MARK, PSELC_15_14_01, PTU0_FN),
589 PINMUX_DATA(MMC_CLK_MARK, PSELC_15_14_10, PTU0_FN),
590
591 /* PTV FN */
592 PINMUX_DATA(SCIF1_CTS_MARK, PSELB_11_10_00, PTV4_FN),
593 PINMUX_DATA(TPU_TO3_MARK, PSELB_11_10_01, PTV4_FN),
594 PINMUX_DATA(MMC_VDDON_MARK, PSELB_11_10_10, PTV4_FN),
595 PINMUX_DATA(LCD_VEPWC_MARK, PSELB_11_10_11, PTV4_FN),
596 PINMUX_DATA(SCIF1_RTS_MARK, PSELB_13_12_00, PTV3_FN),
597 PINMUX_DATA(TPU_TO2_MARK, PSELB_13_12_01, PTV3_FN),
598 PINMUX_DATA(MMC_ODMOD_MARK, PSELB_13_12_10, PTV3_FN),
599 PINMUX_DATA(LCD_VCPWC_MARK, PSELB_13_12_11, PTV3_FN),
600 PINMUX_DATA(SCIF1_TXD_MARK, PSELC_9_8_00, PTV2_FN),
601 PINMUX_DATA(SIM_D_MARK, PSELC_9_8_10, PTV2_FN),
602 PINMUX_DATA(SCIF1_RXD_MARK, PSELC_11_10_00, PTV1_FN),
603 PINMUX_DATA(SIM_RST_MARK, PSELC_11_10_10, PTV1_FN),
604 PINMUX_DATA(SCIF1_SCK_MARK, PSELD_1_0_00, PTV0_FN),
605 PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN),
606};
607
608static struct pinmux_gpio pinmux_gpios[] = {
609 /* PTA */
610 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
611 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
612 PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
613 PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
614 PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
615 PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
616 PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
617 PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
618
619 /* PTB */
620 PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
621 PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
622 PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
623 PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
624 PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
625 PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
626 PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
627 PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
628
629 /* PTC */
630 PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
631 PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
632 PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
633 PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
634 PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
635 PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
636 PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
637 PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
638
639 /* PTD */
640 PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
641 PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
642 PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
643 PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
644 PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
645 PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
646 PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
647 PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
648
649 /* PTE */
650 PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
651 PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
652 PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
653 PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
654 PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
655 PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
656 PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
657
658 /* PTF */
659 PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
660 PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
661 PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
662 PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
663 PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
664 PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
665 PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
666
667 /* PTG */
668 PINMUX_GPIO(GPIO_PTG6, PTG6_DATA),
669 PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
670 PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
671 PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
672 PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
673 PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
674 PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
675
676 /* PTH */
677 PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
678 PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
679 PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
680 PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
681 PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
682 PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
683 PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
684
685 /* PTJ */
686 PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
687 PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
688 PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA),
689 PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
690 PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
691 PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
692 PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
693
694 /* PTK */
695 PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
696 PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
697 PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
698 PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
699
700 /* PTL */
701 PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
702 PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
703 PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
704 PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
705 PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
706
707 /* PTM */
708 PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
709 PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
710 PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
711 PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
712 PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
713 PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
714 PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
715 PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
716
717 /* PTP */
718 PINMUX_GPIO(GPIO_PTP4, PTP4_DATA),
719 PINMUX_GPIO(GPIO_PTP3, PTP3_DATA),
720 PINMUX_GPIO(GPIO_PTP2, PTP2_DATA),
721 PINMUX_GPIO(GPIO_PTP1, PTP1_DATA),
722 PINMUX_GPIO(GPIO_PTP0, PTP0_DATA),
723
724 /* PTR */
725 PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
726 PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
727 PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
728 PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
729 PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
730 PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
731 PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
732 PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
733
734 /* PTS */
735 PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
736 PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
737 PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
738 PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
739 PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
740
741 /* PTT */
742 PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
743 PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
744 PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
745 PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
746 PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
747
748 /* PTU */
749 PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
750 PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
751 PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
752 PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
753 PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
754
755 /* PTV */
756 PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
757 PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
758 PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
759 PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
760 PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
761
762 /* BSC */
763 PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
764 PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
765 PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
766 PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
767 PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
768 PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
769 PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
770 PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
771 PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
772 PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
773 PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
774 PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
775 PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
776 PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
777 PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
778 PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
779 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
780 PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
781 PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
782 PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
783 PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK),
784 PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
785 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
786 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
787 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
788 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
789 PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
790 PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
791 PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
792 PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
793 PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK),
794 PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
795
796 /* LCDC */
797 PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
798 PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
799 PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
800 PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
801 PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
802 PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
803 PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
804 PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
805 PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
806 PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
807 PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
808 PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
809 PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
810 PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
811 PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
812 PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
813 PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
814 PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK),
815 PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK),
816 PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK),
817 PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK),
818 PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK),
819 PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK),
820
821 /* AFEIF */
822 PINMUX_GPIO(GPIO_FN_AFE_RXIN, AFE_RXIN_MARK),
823 PINMUX_GPIO(GPIO_FN_AFE_RDET, AFE_RDET_MARK),
824 PINMUX_GPIO(GPIO_FN_AFE_FS, AFE_FS_MARK),
825 PINMUX_GPIO(GPIO_FN_AFE_TXOUT, AFE_TXOUT_MARK),
826 PINMUX_GPIO(GPIO_FN_AFE_SCLK, AFE_SCLK_MARK),
827 PINMUX_GPIO(GPIO_FN_AFE_RLYCNT, AFE_RLYCNT_MARK),
828 PINMUX_GPIO(GPIO_FN_AFE_HC1, AFE_HC1_MARK),
829
830 /* IIC */
831 PINMUX_GPIO(GPIO_FN_IIC_SCL, IIC_SCL_MARK),
832 PINMUX_GPIO(GPIO_FN_IIC_SDA, IIC_SDA_MARK),
833
834 /* DAC */
835 PINMUX_GPIO(GPIO_FN_DA1, DA1_MARK),
836 PINMUX_GPIO(GPIO_FN_DA0, DA0_MARK),
837
838 /* ADC */
839 PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK),
840 PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK),
841 PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK),
842 PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK),
843 PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
844
845 /* USB */
846 PINMUX_GPIO(GPIO_FN_USB1D_RCV, USB1D_RCV_MARK),
847 PINMUX_GPIO(GPIO_FN_USB1D_TXSE0, USB1D_TXSE0_MARK),
848 PINMUX_GPIO(GPIO_FN_USB1D_TXDPLS, USB1D_TXDPLS_MARK),
849 PINMUX_GPIO(GPIO_FN_USB1D_DMNS, USB1D_DMNS_MARK),
850 PINMUX_GPIO(GPIO_FN_USB1D_DPLS, USB1D_DPLS_MARK),
851 PINMUX_GPIO(GPIO_FN_USB1D_SPEED, USB1D_SPEED_MARK),
852 PINMUX_GPIO(GPIO_FN_USB1D_TXENL, USB1D_TXENL_MARK),
853
854 PINMUX_GPIO(GPIO_FN_USB2_PWR_EN, USB2_PWR_EN_MARK),
855 PINMUX_GPIO(GPIO_FN_USB1_PWR_EN_USBF_UPLUP,
856 USB1_PWR_EN_USBF_UPLUP_MARK),
857 PINMUX_GPIO(GPIO_FN_USB1D_SUSPEND, USB1D_SUSPEND_MARK),
858
859 /* INTC */
860 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
861 PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
862 PINMUX_GPIO(GPIO_FN_IRQ3_IRL3, IRQ3_IRL3_MARK),
863 PINMUX_GPIO(GPIO_FN_IRQ2_IRL2, IRQ2_IRL2_MARK),
864 PINMUX_GPIO(GPIO_FN_IRQ1_IRL1, IRQ1_IRL1_MARK),
865 PINMUX_GPIO(GPIO_FN_IRQ0_IRL0, IRQ0_IRL0_MARK),
866
867 /* PCC */
868 PINMUX_GPIO(GPIO_FN_PCC_REG, PCC_REG_MARK),
869 PINMUX_GPIO(GPIO_FN_PCC_DRV, PCC_DRV_MARK),
870 PINMUX_GPIO(GPIO_FN_PCC_BVD2, PCC_BVD2_MARK),
871 PINMUX_GPIO(GPIO_FN_PCC_BVD1, PCC_BVD1_MARK),
872 PINMUX_GPIO(GPIO_FN_PCC_CD2, PCC_CD2_MARK),
873 PINMUX_GPIO(GPIO_FN_PCC_CD1, PCC_CD1_MARK),
874 PINMUX_GPIO(GPIO_FN_PCC_RESET, PCC_RESET_MARK),
875 PINMUX_GPIO(GPIO_FN_PCC_RDY, PCC_RDY_MARK),
876 PINMUX_GPIO(GPIO_FN_PCC_VS2, PCC_VS2_MARK),
877 PINMUX_GPIO(GPIO_FN_PCC_VS1, PCC_VS1_MARK),
878
879 /* HUDI */
880 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
881 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
882 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
883 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
884 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
885 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
886 PINMUX_GPIO(GPIO_FN_ASEBRKAK, ASEBRKAK_MARK),
887 PINMUX_GPIO(GPIO_FN_TRST, TRST_MARK),
888 PINMUX_GPIO(GPIO_FN_TMS, TMS_MARK),
889 PINMUX_GPIO(GPIO_FN_TDO, TDO_MARK),
890 PINMUX_GPIO(GPIO_FN_TDI, TDI_MARK),
891 PINMUX_GPIO(GPIO_FN_TCK, TCK_MARK),
892
893 /* DMAC */
894 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
895 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
896 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
897 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
898 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
899 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
900
901 /* SIOF0 */
902 PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK),
903 PINMUX_GPIO(GPIO_FN_SIOF0_MCLK, SIOF0_MCLK_MARK),
904 PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK),
905 PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK),
906 PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK),
907
908 /* SIOF1 */
909 PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK),
910 PINMUX_GPIO(GPIO_FN_SIOF1_MCLK, SIOF1_MCLK_MARK),
911 PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK),
912 PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK),
913 PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK),
914
915 /* SCIF0 */
916 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
917 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
918 PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
919 PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
920 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
921
922 /* SCIF1 */
923 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
924 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
925 PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK),
926 PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK),
927 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
928
929 /* TPU */
930 PINMUX_GPIO(GPIO_FN_TPU_TO1, TPU_TO1_MARK),
931 PINMUX_GPIO(GPIO_FN_TPU_TO0, TPU_TO0_MARK),
932 PINMUX_GPIO(GPIO_FN_TPU_TI3B, TPU_TI3B_MARK),
933 PINMUX_GPIO(GPIO_FN_TPU_TI3A, TPU_TI3A_MARK),
934 PINMUX_GPIO(GPIO_FN_TPU_TI2B, TPU_TI2B_MARK),
935 PINMUX_GPIO(GPIO_FN_TPU_TI2A, TPU_TI2A_MARK),
936 PINMUX_GPIO(GPIO_FN_TPU_TO3, TPU_TO3_MARK),
937 PINMUX_GPIO(GPIO_FN_TPU_TO2, TPU_TO2_MARK),
938
939 /* SIM */
940 PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
941 PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
942 PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
943
944 /* MMC */
945 PINMUX_GPIO(GPIO_FN_MMC_DAT, MMC_DAT_MARK),
946 PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK),
947 PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK),
948 PINMUX_GPIO(GPIO_FN_MMC_VDDON, MMC_VDDON_MARK),
949 PINMUX_GPIO(GPIO_FN_MMC_ODMOD, MMC_ODMOD_MARK),
950
951 /* SYSC */
952 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
953 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
954};
955
956static struct pinmux_cfg_reg pinmux_config_regs[] = {
957 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
958 PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
959 PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
960 PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN,
961 PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN,
962 PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN,
963 PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN,
964 PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN,
965 PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN }
966 },
967 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
968 PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN,
969 PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN,
970 PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN,
971 PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN,
972 PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN,
973 PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN,
974 PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN,
975 PTB0_FN, PTB0_OUT, PTB0_IN_PU, PTB0_IN }
976 },
977 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
978 PTC7_FN, PTC7_OUT, PTC7_IN_PU, PTC7_IN,
979 PTC6_FN, PTC6_OUT, PTC6_IN_PU, PTC6_IN,
980 PTC5_FN, PTC5_OUT, PTC5_IN_PU, PTC5_IN,
981 PTC4_FN, PTC4_OUT, PTC4_IN_PU, PTC4_IN,
982 PTC3_FN, PTC3_OUT, PTC3_IN_PU, PTC3_IN,
983 PTC2_FN, PTC2_OUT, PTC2_IN_PU, PTC2_IN,
984 PTC1_FN, PTC1_OUT, PTC1_IN_PU, PTC1_IN,
985 PTC0_FN, PTC0_OUT, PTC0_IN_PU, PTC0_IN }
986 },
987 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
988 PTD7_FN, PTD7_OUT, PTD7_IN_PU, PTD7_IN,
989 PTD6_FN, PTD6_OUT, PTD6_IN_PU, PTD6_IN,
990 PTD5_FN, PTD5_OUT, PTD5_IN_PU, PTD5_IN,
991 PTD4_FN, PTD4_OUT, PTD4_IN_PU, PTD4_IN,
992 PTD3_FN, PTD3_OUT, PTD3_IN_PU, PTD3_IN,
993 PTD2_FN, PTD2_OUT, PTD2_IN_PU, PTD2_IN,
994 PTD1_FN, PTD1_OUT, PTD1_IN_PU, PTD1_IN,
995 PTD0_FN, PTD0_OUT, PTD0_IN_PU, PTD0_IN }
996 },
997 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
998 0, 0, 0, 0,
999 PTE6_FN, 0, 0, PTE6_IN,
1000 PTE5_FN, 0, 0, PTE5_IN,
1001 PTE4_FN, PTE4_OUT, PTE4_IN_PU, PTE4_IN,
1002 PTE3_FN, PTE3_OUT, PTE3_IN_PU, PTE3_IN,
1003 PTE2_FN, PTE2_OUT, PTE2_IN_PU, PTE2_IN,
1004 PTE1_FN, PTE1_OUT, PTE1_IN_PU, PTE1_IN,
1005 PTE0_FN, PTE0_OUT, PTE0_IN_PU, PTE0_IN }
1006 },
1007 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
1008 0, 0, 0, 0,
1009 PTF6_FN, 0, 0, PTF6_IN,
1010 PTF5_FN, 0, 0, PTF5_IN,
1011 PTF4_FN, 0, 0, PTF4_IN,
1012 PTF3_FN, 0, 0, PTF3_IN,
1013 PTF2_FN, 0, 0, PTF2_IN,
1014 PTF1_FN, 0, 0, PTF1_IN,
1015 PTF0_FN, 0, 0, PTF0_IN }
1016 },
1017 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
1018 0, 0, 0, 0,
1019 PTG6_FN, PTG6_OUT, PTG6_IN_PU, PTG6_IN,
1020 PTG5_FN, PTG5_OUT, PTG5_IN_PU, PTG5_IN,
1021 PTG4_FN, PTG4_OUT, PTG4_IN_PU, PTG4_IN,
1022 PTG3_FN, PTG3_OUT, PTG3_IN_PU, PTG3_IN,
1023 PTG2_FN, PTG2_OUT, PTG2_IN_PU, PTG2_IN,
1024 PTG1_FN, PTG1_OUT, PTG1_IN_PU, PTG1_IN,
1025 PTG0_FN, PTG0_OUT, PTG0_IN_PU, PTG0_IN }
1026 },
1027 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
1028 0, 0, 0, 0,
1029 PTH6_FN, PTH6_OUT, PTH6_IN_PU, PTH6_IN,
1030 PTH5_FN, PTH5_OUT, PTH5_IN_PU, PTH5_IN,
1031 PTH4_FN, PTH4_OUT, PTH4_IN_PU, PTH4_IN,
1032 PTH3_FN, PTH3_OUT, PTH3_IN_PU, PTH3_IN,
1033 PTH2_FN, PTH2_OUT, PTH2_IN_PU, PTH2_IN,
1034 PTH1_FN, PTH1_OUT, PTH1_IN_PU, PTH1_IN,
1035 PTH0_FN, PTH0_OUT, PTH0_IN_PU, PTH0_IN }
1036 },
1037 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
1038 0, 0, 0, 0,
1039 PTJ6_FN, PTJ6_OUT, PTJ6_IN_PU, PTJ6_IN,
1040 PTJ5_FN, PTJ5_OUT, PTJ5_IN_PU, PTJ5_IN,
1041 PTJ4_FN, PTJ4_OUT, PTJ4_IN_PU, PTJ4_IN,
1042 PTJ3_FN, PTJ3_OUT, PTJ3_IN_PU, PTJ3_IN,
1043 PTJ2_FN, PTJ2_OUT, PTJ2_IN_PU, PTJ2_IN,
1044 PTJ1_FN, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN,
1045 PTJ0_FN, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN }
1046 },
1047 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
1048 0, 0, 0, 0,
1049 0, 0, 0, 0,
1050 0, 0, 0, 0,
1051 0, 0, 0, 0,
1052 PTK3_FN, PTK3_OUT, PTK3_IN_PU, PTK3_IN,
1053 PTK2_FN, PTK2_OUT, PTK2_IN_PU, PTK2_IN,
1054 PTK1_FN, PTK1_OUT, PTK1_IN_PU, PTK1_IN,
1055 PTK0_FN, PTK0_OUT, PTK0_IN_PU, PTK0_IN }
1056 },
1057 { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
1058 PTL7_FN, PTL7_OUT, PTL7_IN_PU, PTL7_IN,
1059 PTL6_FN, PTL6_OUT, PTL6_IN_PU, PTL6_IN,
1060 PTL5_FN, PTL5_OUT, PTL5_IN_PU, PTL5_IN,
1061 PTL4_FN, PTL4_OUT, PTL4_IN_PU, PTL4_IN,
1062 PTL3_FN, PTL3_OUT, PTL3_IN_PU, PTL3_IN,
1063 0, 0, 0, 0,
1064 0, 0, 0, 0,
1065 0, 0, 0, 0 }
1066 },
1067 { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
1068 PTM7_FN, PTM7_OUT, PTM7_IN_PU, PTM7_IN,
1069 PTM6_FN, PTM6_OUT, PTM6_IN_PU, PTM6_IN,
1070 PTM5_FN, PTM5_OUT, PTM5_IN_PU, PTM5_IN,
1071 PTM4_FN, PTM4_OUT, PTM4_IN_PU, PTM4_IN,
1072 PTM3_FN, PTM3_OUT, PTM3_IN_PU, PTM3_IN,
1073 PTM2_FN, PTM2_OUT, PTM2_IN_PU, PTM2_IN,
1074 PTM1_FN, PTM1_OUT, PTM1_IN_PU, PTM1_IN,
1075 PTM0_FN, PTM0_OUT, PTM0_IN_PU, PTM0_IN }
1076 },
1077 { PINMUX_CFG_REG("PPCR", 0xa4050118, 16, 2) {
1078 0, 0, 0, 0,
1079 0, 0, 0, 0,
1080 0, 0, 0, 0,
1081 PTP4_FN, PTP4_OUT, PTP4_IN_PU, PTP4_IN,
1082 PTP3_FN, PTP3_OUT, PTP3_IN_PU, PTP3_IN,
1083 PTP2_FN, PTP2_OUT, PTP2_IN_PU, PTP2_IN,
1084 PTP1_FN, PTP1_OUT, PTP1_IN_PU, PTP1_IN,
1085 PTP0_FN, PTP0_OUT, PTP0_IN_PU, PTP0_IN }
1086 },
1087 { PINMUX_CFG_REG("PRCR", 0xa405011a, 16, 2) {
1088 PTR7_FN, PTR7_OUT, PTR7_IN_PU, PTR7_IN,
1089 PTR6_FN, PTR6_OUT, PTR6_IN_PU, PTR6_IN,
1090 PTR5_FN, PTR5_OUT, PTR5_IN_PU, PTR5_IN,
1091 PTR4_FN, PTR4_OUT, PTR4_IN_PU, PTR4_IN,
1092 PTR3_FN, PTR3_OUT, PTR3_IN_PU, PTR3_IN,
1093 PTR2_FN, PTR2_OUT, PTR2_IN_PU, PTR2_IN,
1094 PTR1_FN, PTR1_OUT, PTR1_IN_PU, PTR1_IN,
1095 PTR0_FN, PTR0_OUT, PTR0_IN_PU, PTR0_IN }
1096 },
1097 { PINMUX_CFG_REG("PSCR", 0xa405011c, 16, 2) {
1098 0, 0, 0, 0,
1099 0, 0, 0, 0,
1100 0, 0, 0, 0,
1101 PTS4_FN, PTS4_OUT, PTS4_IN_PU, PTS4_IN,
1102 PTS3_FN, PTS3_OUT, PTS3_IN_PU, PTS3_IN,
1103 PTS2_FN, PTS2_OUT, PTS2_IN_PU, PTS2_IN,
1104 PTS1_FN, PTS1_OUT, PTS1_IN_PU, PTS1_IN,
1105 PTS0_FN, PTS0_OUT, PTS0_IN_PU, PTS0_IN }
1106 },
1107 { PINMUX_CFG_REG("PTCR", 0xa405011e, 16, 2) {
1108 0, 0, 0, 0,
1109 0, 0, 0, 0,
1110 0, 0, 0, 0,
1111 PTT4_FN, PTT4_OUT, PTT4_IN_PU, PTT4_IN,
1112 PTT3_FN, PTT3_OUT, PTT3_IN_PU, PTT3_IN,
1113 PTT2_FN, PTT2_OUT, PTT2_IN_PU, PTT2_IN,
1114 PTT1_FN, PTT1_OUT, PTT1_IN_PU, PTT1_IN,
1115 PTT0_FN, PTT0_OUT, PTT0_IN_PU, PTT0_IN }
1116 },
1117 { PINMUX_CFG_REG("PUCR", 0xa4050120, 16, 2) {
1118 0, 0, 0, 0,
1119 0, 0, 0, 0,
1120 0, 0, 0, 0,
1121 PTU4_FN, PTU4_OUT, PTU4_IN_PU, PTU4_IN,
1122 PTU3_FN, PTU3_OUT, PTU3_IN_PU, PTU3_IN,
1123 PTU2_FN, PTU2_OUT, PTU2_IN_PU, PTU2_IN,
1124 PTU1_FN, PTU1_OUT, PTU1_IN_PU, PTU1_IN,
1125 PTU0_FN, PTU0_OUT, PTU0_IN_PU, PTU0_IN }
1126 },
1127 { PINMUX_CFG_REG("PVCR", 0xa4050122, 16, 2) {
1128 0, 0, 0, 0,
1129 0, 0, 0, 0,
1130 0, 0, 0, 0,
1131 PTV4_FN, PTV4_OUT, PTV4_IN_PU, PTV4_IN,
1132 PTV3_FN, PTV3_OUT, PTV3_IN_PU, PTV3_IN,
1133 PTV2_FN, PTV2_OUT, PTV2_IN_PU, PTV2_IN,
1134 PTV1_FN, PTV1_OUT, PTV1_IN_PU, PTV1_IN,
1135 PTV0_FN, PTV0_OUT, PTV0_IN_PU, PTV0_IN }
1136 },
1137 {}
1138};
1139
1140static struct pinmux_data_reg pinmux_data_regs[] = {
1141 { PINMUX_DATA_REG("PADR", 0xa4050140, 8) {
1142 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
1143 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
1144 },
1145 { PINMUX_DATA_REG("PBDR", 0xa4050142, 8) {
1146 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
1147 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
1148 },
1149 { PINMUX_DATA_REG("PCDR", 0xa4050144, 8) {
1150 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
1151 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
1152 },
1153 { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
1154 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
1155 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
1156 },
1157 { PINMUX_DATA_REG("PEDR", 0xa4050148, 8) {
1158 0, PTE6_DATA, PTE5_DATA, PTE4_DATA,
1159 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
1160 },
1161 { PINMUX_DATA_REG("PFDR", 0xa405014a, 8) {
1162 0, PTF6_DATA, PTF5_DATA, PTF4_DATA,
1163 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
1164 },
1165 { PINMUX_DATA_REG("PGDR", 0xa405014c, 8) {
1166 0, PTG6_DATA, PTG5_DATA, PTG4_DATA,
1167 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
1168 },
1169 { PINMUX_DATA_REG("PHDR", 0xa405014e, 8) {
1170 0, PTH6_DATA, PTH5_DATA, PTH4_DATA,
1171 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
1172 },
1173 { PINMUX_DATA_REG("PJDR", 0xa4050150, 8) {
1174 0, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
1175 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
1176 },
1177 { PINMUX_DATA_REG("PKDR", 0xa4050152, 8) {
1178 0, 0, 0, 0,
1179 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
1180 },
1181 { PINMUX_DATA_REG("PLDR", 0xa4050154, 8) {
1182 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
1183 PTL3_DATA, 0, 0, 0 }
1184 },
1185 { PINMUX_DATA_REG("PMDR", 0xa4050156, 8) {
1186 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
1187 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
1188 },
1189 { PINMUX_DATA_REG("PPDR", 0xa4050158, 8) {
1190 0, 0, 0, PTP4_DATA,
1191 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA }
1192 },
1193 { PINMUX_DATA_REG("PRDR", 0xa405015a, 8) {
1194 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
1195 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
1196 },
1197 { PINMUX_DATA_REG("PSDR", 0xa405015c, 8) {
1198 0, 0, 0, PTS4_DATA,
1199 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
1200 },
1201 { PINMUX_DATA_REG("PTDR", 0xa405015e, 8) {
1202 0, 0, 0, PTT4_DATA,
1203 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
1204 },
1205 { PINMUX_DATA_REG("PUDR", 0xa4050160, 8) {
1206 0, 0, 0, PTU4_DATA,
1207 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
1208 },
1209 { PINMUX_DATA_REG("PVDR", 0xa4050162, 8) {
1210 0, 0, 0, PTV4_DATA,
1211 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
1212 },
1213 { },
1214};
1215
1216static struct pinmux_info sh7720_pinmux_info = {
1217 .name = "sh7720_pfc",
1218 .reserved_id = PINMUX_RESERVED,
1219 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1220 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1221 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1222 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1223 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1224 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1225
1226 .first_gpio = GPIO_PTA7,
1227 .last_gpio = GPIO_FN_STATUS1,
1228
1229 .gpios = pinmux_gpios,
1230 .cfg_regs = pinmux_config_regs,
1231 .data_regs = pinmux_data_regs,
1232
1233 .gpio_data = pinmux_data,
1234 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1235};
1236
1237static int __init plat_pinmux_setup(void)
1238{
1239 return register_pinmux(&sh7720_pinmux_info);
1240}
1241
1242arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4/fpu.c b/arch/sh/kernel/cpu/sh4/fpu.c
index 2d452f67fb87..2780917c0088 100644
--- a/arch/sh/kernel/cpu/sh4/fpu.c
+++ b/arch/sh/kernel/cpu/sh4/fpu.c
@@ -36,7 +36,7 @@ extern unsigned long int float32_add(unsigned long int a, unsigned long int b);
36extern unsigned long long float64_sub(unsigned long long a, 36extern unsigned long long float64_sub(unsigned long long a,
37 unsigned long long b); 37 unsigned long long b);
38extern unsigned long int float32_sub(unsigned long int a, unsigned long int b); 38extern unsigned long int float32_sub(unsigned long int a, unsigned long int b);
39 39extern unsigned long int float64_to_float32(unsigned long long a);
40static unsigned int fpu_exception_flags; 40static unsigned int fpu_exception_flags;
41 41
42/* 42/*
@@ -417,6 +417,29 @@ static int ieee_fpe_handler(struct pt_regs *regs)
417 417
418 regs->pc = nextpc; 418 regs->pc = nextpc;
419 return 1; 419 return 1;
420 } else if ((finsn & 0xf0bd) == 0xf0bd) {
421 /* fcnvds - double to single precision convert */
422 struct task_struct *tsk = current;
423 int m;
424 unsigned int hx;
425
426 m = (finsn >> 9) & 0x7;
427 hx = tsk->thread.fpu.hard.fp_regs[m];
428
429 if ((tsk->thread.fpu.hard.fpscr & FPSCR_CAUSE_ERROR)
430 && ((hx & 0x7fffffff) < 0x00100000)) {
431 /* subnormal double to float conversion */
432 long long llx;
433
434 llx = ((long long)tsk->thread.fpu.hard.fp_regs[m] << 32)
435 | tsk->thread.fpu.hard.fp_regs[m + 1];
436
437 tsk->thread.fpu.hard.fpul = float64_to_float32(llx);
438 } else
439 return 0;
440
441 regs->pc = nextpc;
442 return 1;
420 } 443 }
421 444
422 return 0; 445 return 0;
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 254c5c55ab91..d9bdc931ac09 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -11,6 +11,7 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/io.h>
14 15
15enum { 16enum {
16 UNUSED = 0, 17 UNUSED = 0,
@@ -178,10 +179,14 @@ static int __init sh7760_devices_setup(void)
178} 179}
179__initcall(sh7760_devices_setup); 180__initcall(sh7760_devices_setup);
180 181
182#define INTC_ICR 0xffd00000UL
183#define INTC_ICR_IRLM (1 << 7)
184
181void __init plat_irq_setup_pins(int mode) 185void __init plat_irq_setup_pins(int mode)
182{ 186{
183 switch (mode) { 187 switch (mode) {
184 case IRQ_MODE_IRQ: 188 case IRQ_MODE_IRQ:
189 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
185 register_intc_controller(&intc_desc_irq); 190 register_intc_controller(&intc_desc_irq);
186 break; 191 break;
187 default: 192 default:
diff --git a/arch/sh/kernel/cpu/sh4/softfloat.c b/arch/sh/kernel/cpu/sh4/softfloat.c
index 828cb57cb959..2b747f3b02bd 100644
--- a/arch/sh/kernel/cpu/sh4/softfloat.c
+++ b/arch/sh/kernel/cpu/sh4/softfloat.c
@@ -85,6 +85,7 @@ float64 float64_div(float64 a, float64 b);
85float32 float32_div(float32 a, float32 b); 85float32 float32_div(float32 a, float32 b);
86float32 float32_mul(float32 a, float32 b); 86float32 float32_mul(float32 a, float32 b);
87float64 float64_mul(float64 a, float64 b); 87float64 float64_mul(float64 a, float64 b);
88float32 float64_to_float32(float64 a);
88inline void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, 89inline void add128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr,
89 bits64 * z1Ptr); 90 bits64 * z1Ptr);
90inline void sub128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr, 91inline void sub128(bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 * z0Ptr,
@@ -890,3 +891,31 @@ float64 float64_mul(float64 a, float64 b)
890 } 891 }
891 return roundAndPackFloat64(zSign, zExp, zSig0); 892 return roundAndPackFloat64(zSign, zExp, zSig0);
892} 893}
894
895/*
896 * -------------------------------------------------------------------------------
897 * Returns the result of converting the double-precision floating-point value
898 * `a' to the single-precision floating-point format. The conversion is
899 * performed according to the IEC/IEEE Standard for Binary Floating-point
900 * Arithmetic.
901 * -------------------------------------------------------------------------------
902 * */
903float32 float64_to_float32(float64 a)
904{
905 flag aSign;
906 int16 aExp;
907 bits64 aSig;
908 bits32 zSig;
909
910 aSig = extractFloat64Frac( a );
911 aExp = extractFloat64Exp( a );
912 aSign = extractFloat64Sign( a );
913
914 shift64RightJamming( aSig, 22, &aSig );
915 zSig = aSig;
916 if ( aExp || zSig ) {
917 zSig |= 0x40000000;
918 aExp -= 0x381;
919 }
920 return roundAndPackFloat32(aSign, aExp, zSig);
921}
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 9381ad8da263..be9a0c185958 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -27,5 +27,10 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o
27clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o 27clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o
28clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 28clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
29 29
30# Pinmux setup
31pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
32pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
33
30obj-y += $(clock-y) 34obj-y += $(clock-y)
31obj-$(CONFIG_SMP) += $(smp-y) 35obj-$(CONFIG_SMP) += $(smp-y)
36obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y)
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
new file mode 100644
index 000000000000..cb9d07bd59f8
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
@@ -0,0 +1,1783 @@
1#include <linux/init.h>
2#include <linux/kernel.h>
3#include <linux/gpio.h>
4#include <cpu/sh7722.h>
5
6enum {
7 PINMUX_RESERVED = 0,
8
9 PINMUX_DATA_BEGIN,
10 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
11 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
12 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
13 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
14 PTC7_DATA, PTC5_DATA, PTC4_DATA, PTC3_DATA, PTC2_DATA, PTC0_DATA,
15 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
16 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
17 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, PTE1_DATA, PTE0_DATA,
18 PTF6_DATA, PTF5_DATA, PTF4_DATA,
19 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
20 PTG4_DATA, PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
21 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
22 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
23 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ1_DATA, PTJ0_DATA,
24 PTK6_DATA, PTK5_DATA, PTK4_DATA,
25 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
26 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
27 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
28 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
29 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
30 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
31 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
32 PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
33 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
34 PTR4_DATA, PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
35 PTS4_DATA, PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
36 PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
37 PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
38 PTV4_DATA, PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
39 PTW6_DATA, PTW5_DATA, PTW4_DATA,
40 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
41 PTX6_DATA, PTX5_DATA, PTX4_DATA,
42 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
43 PTY6_DATA, PTY5_DATA, PTY4_DATA,
44 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
45 PTZ5_DATA, PTZ4_DATA, PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
46 PINMUX_DATA_END,
47
48 PINMUX_INPUT_BEGIN,
49 PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
50 PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
51 PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
52 PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
53 PTC7_IN, PTC5_IN, PTC4_IN, PTC3_IN, PTC2_IN, PTC0_IN,
54 PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN, PTD3_IN, PTD2_IN, PTD1_IN,
55 PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN, PTE1_IN, PTE0_IN,
56 PTF6_IN, PTF5_IN, PTF4_IN, PTF3_IN, PTF2_IN, PTF1_IN,
57 PTH6_IN, PTH5_IN, PTH1_IN, PTH0_IN,
58 PTJ1_IN, PTJ0_IN,
59 PTK6_IN, PTK5_IN, PTK4_IN, PTK3_IN, PTK2_IN, PTK0_IN,
60 PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
61 PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
62 PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
63 PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
64 PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
65 PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
66 PTQ5_IN, PTQ4_IN, PTQ3_IN, PTQ2_IN, PTQ0_IN,
67 PTR2_IN,
68 PTS4_IN, PTS2_IN, PTS1_IN,
69 PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN,
70 PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
71 PTV4_IN, PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
72 PTW6_IN, PTW4_IN, PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
73 PTX6_IN, PTX5_IN, PTX4_IN, PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
74 PTY5_IN, PTY4_IN, PTY3_IN, PTY2_IN, PTY0_IN,
75 PTZ5_IN, PTZ4_IN, PTZ3_IN, PTZ2_IN, PTZ1_IN,
76 PINMUX_INPUT_END,
77
78 PINMUX_INPUT_PULLDOWN_BEGIN,
79 PTA7_IN_PD, PTA6_IN_PD, PTA5_IN_PD, PTA4_IN_PD,
80 PTA3_IN_PD, PTA2_IN_PD, PTA1_IN_PD, PTA0_IN_PD,
81 PTE7_IN_PD, PTE6_IN_PD, PTE5_IN_PD, PTE4_IN_PD, PTE1_IN_PD, PTE0_IN_PD,
82 PTF6_IN_PD, PTF5_IN_PD, PTF4_IN_PD, PTF3_IN_PD, PTF2_IN_PD, PTF1_IN_PD,
83 PTH6_IN_PD, PTH5_IN_PD, PTH1_IN_PD, PTH0_IN_PD,
84 PTK6_IN_PD, PTK5_IN_PD, PTK4_IN_PD, PTK3_IN_PD, PTK2_IN_PD, PTK0_IN_PD,
85 PTL7_IN_PD, PTL6_IN_PD, PTL5_IN_PD, PTL4_IN_PD,
86 PTL3_IN_PD, PTL2_IN_PD, PTL1_IN_PD, PTL0_IN_PD,
87 PTM7_IN_PD, PTM6_IN_PD, PTM5_IN_PD, PTM4_IN_PD,
88 PTM3_IN_PD, PTM2_IN_PD, PTM1_IN_PD, PTM0_IN_PD,
89 PTQ5_IN_PD, PTQ4_IN_PD, PTQ3_IN_PD, PTQ2_IN_PD,
90 PTS4_IN_PD, PTS2_IN_PD, PTS1_IN_PD,
91 PTT4_IN_PD, PTT3_IN_PD, PTT2_IN_PD, PTT1_IN_PD,
92 PTU4_IN_PD, PTU3_IN_PD, PTU2_IN_PD, PTU1_IN_PD, PTU0_IN_PD,
93 PTV4_IN_PD, PTV3_IN_PD, PTV2_IN_PD, PTV1_IN_PD, PTV0_IN_PD,
94 PTW6_IN_PD, PTW4_IN_PD, PTW3_IN_PD, PTW2_IN_PD, PTW1_IN_PD, PTW0_IN_PD,
95 PTX6_IN_PD, PTX5_IN_PD, PTX4_IN_PD,
96 PTX3_IN_PD, PTX2_IN_PD, PTX1_IN_PD, PTX0_IN_PD,
97 PINMUX_INPUT_PULLDOWN_END,
98
99 PINMUX_INPUT_PULLUP_BEGIN,
100 PTC7_IN_PU, PTC5_IN_PU,
101 PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
102 PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU,
103 PTJ1_IN_PU, PTJ0_IN_PU,
104 PTQ0_IN_PU,
105 PTR2_IN_PU,
106 PTX6_IN_PU,
107 PTY5_IN_PU, PTY4_IN_PU, PTY3_IN_PU, PTY2_IN_PU, PTY0_IN_PU,
108 PTZ5_IN_PU, PTZ4_IN_PU, PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU,
109 PINMUX_INPUT_PULLUP_END,
110
111 PINMUX_OUTPUT_BEGIN,
112 PTA7_OUT, PTA5_OUT,
113 PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
114 PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
115 PTC4_OUT, PTC3_OUT, PTC2_OUT, PTC0_OUT,
116 PTD6_OUT, PTD5_OUT, PTD4_OUT,
117 PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
118 PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT, PTE1_OUT, PTE0_OUT,
119 PTF6_OUT, PTF5_OUT, PTF4_OUT, PTF3_OUT, PTF2_OUT, PTF0_OUT,
120 PTG4_OUT, PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
121 PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
122 PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
123 PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ1_OUT, PTJ0_OUT,
124 PTK6_OUT, PTK5_OUT, PTK4_OUT, PTK3_OUT, PTK1_OUT, PTK0_OUT,
125 PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
126 PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
127 PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
128 PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
129 PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
130 PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT, PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
131 PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
132 PTR4_OUT, PTR3_OUT, PTR1_OUT, PTR0_OUT,
133 PTS3_OUT, PTS2_OUT, PTS0_OUT,
134 PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT0_OUT,
135 PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU0_OUT,
136 PTV4_OUT, PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
137 PTW5_OUT, PTW4_OUT, PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
138 PTX6_OUT, PTX5_OUT, PTX4_OUT, PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
139 PTY5_OUT, PTY4_OUT, PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
140 PINMUX_OUTPUT_END,
141
142 PINMUX_MARK_BEGIN,
143 SCIF0_TXD_MARK, SCIF0_RXD_MARK,
144 SCIF0_RTS_MARK, SCIF0_CTS_MARK, SCIF0_SCK_MARK,
145 SCIF1_TXD_MARK, SCIF1_RXD_MARK,
146 SCIF1_RTS_MARK, SCIF1_CTS_MARK, SCIF1_SCK_MARK,
147 SCIF2_TXD_MARK, SCIF2_RXD_MARK,
148 SCIF2_RTS_MARK, SCIF2_CTS_MARK, SCIF2_SCK_MARK,
149 SIOTXD_MARK, SIORXD_MARK,
150 SIOD_MARK, SIOSTRB0_MARK, SIOSTRB1_MARK,
151 SIOSCK_MARK, SIOMCK_MARK,
152 VIO_D15_MARK, VIO_D14_MARK, VIO_D13_MARK, VIO_D12_MARK,
153 VIO_D11_MARK, VIO_D10_MARK, VIO_D9_MARK, VIO_D8_MARK,
154 VIO_D7_MARK, VIO_D6_MARK, VIO_D5_MARK, VIO_D4_MARK,
155 VIO_D3_MARK, VIO_D2_MARK, VIO_D1_MARK, VIO_D0_MARK,
156 VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK, VIO_FLD_MARK,
157 VIO_CKO_MARK, VIO_STEX_MARK, VIO_STEM_MARK, VIO_VD2_MARK,
158 VIO_HD2_MARK, VIO_CLK2_MARK,
159 LCDD23_MARK, LCDD22_MARK, LCDD21_MARK, LCDD20_MARK,
160 LCDD19_MARK, LCDD18_MARK, LCDD17_MARK, LCDD16_MARK,
161 LCDD15_MARK, LCDD14_MARK, LCDD13_MARK, LCDD12_MARK,
162 LCDD11_MARK, LCDD10_MARK, LCDD9_MARK, LCDD8_MARK,
163 LCDD7_MARK, LCDD6_MARK, LCDD5_MARK, LCDD4_MARK,
164 LCDD3_MARK, LCDD2_MARK, LCDD1_MARK, LCDD0_MARK,
165 LCDLCLK_MARK, LCDDON_MARK, LCDVCPWC_MARK, LCDVEPWC_MARK,
166 LCDVSYN_MARK, LCDDCK_MARK, LCDHSYN_MARK, LCDDISP_MARK,
167 LCDRS_MARK, LCDCS_MARK, LCDWR_MARK, LCDRD_MARK,
168 LCDDON2_MARK, LCDVCPWC2_MARK, LCDVEPWC2_MARK, LCDVSYN2_MARK,
169 LCDCS2_MARK,
170 IOIS16_MARK, A25_MARK, A24_MARK, A23_MARK, A22_MARK,
171 BS_MARK, CS6B_CE1B_MARK, WAIT_MARK, CS6A_CE2B_MARK,
172 HPD63_MARK, HPD62_MARK, HPD61_MARK, HPD60_MARK,
173 HPD59_MARK, HPD58_MARK, HPD57_MARK, HPD56_MARK,
174 HPD55_MARK, HPD54_MARK, HPD53_MARK, HPD52_MARK,
175 HPD51_MARK, HPD50_MARK, HPD49_MARK, HPD48_MARK,
176 HPDQM7_MARK, HPDQM6_MARK, HPDQM5_MARK, HPDQM4_MARK,
177 IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK,
178 IRQ4_MARK, IRQ5_MARK, IRQ6_MARK, IRQ7_MARK,
179 SDHICD_MARK, SDHIWP_MARK, SDHID3_MARK, SDHID2_MARK,
180 SDHID1_MARK, SDHID0_MARK, SDHICMD_MARK, SDHICLK_MARK,
181 SIUAOLR_MARK, SIUAOBT_MARK, SIUAISLD_MARK, SIUAILR_MARK,
182 SIUAIBT_MARK, SIUAOSLD_MARK, SIUMCKA_MARK, SIUFCKA_MARK,
183 SIUBOLR_MARK, SIUBOBT_MARK, SIUBISLD_MARK, SIUBILR_MARK,
184 SIUBIBT_MARK, SIUBOSLD_MARK, SIUMCKB_MARK, SIUFCKB_MARK,
185 AUDSYNC_MARK, AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK,
186 DACK_MARK, DREQ0_MARK,
187 DV_CLKI_MARK, DV_CLK_MARK, DV_HSYNC_MARK, DV_VSYNC_MARK,
188 DV_D15_MARK, DV_D14_MARK, DV_D13_MARK, DV_D12_MARK,
189 DV_D11_MARK, DV_D10_MARK, DV_D9_MARK, DV_D8_MARK,
190 DV_D7_MARK, DV_D6_MARK, DV_D5_MARK, DV_D4_MARK,
191 DV_D3_MARK, DV_D2_MARK, DV_D1_MARK, DV_D0_MARK,
192 STATUS0_MARK, PDSTATUS_MARK,
193 SIOF0_MCK_MARK, SIOF0_SCK_MARK,
194 SIOF0_SYNC_MARK, SIOF0_SS1_MARK, SIOF0_SS2_MARK,
195 SIOF0_TXD_MARK, SIOF0_RXD_MARK,
196 SIOF1_MCK_MARK, SIOF1_SCK_MARK,
197 SIOF1_SYNC_MARK, SIOF1_SS1_MARK, SIOF1_SS2_MARK,
198 SIOF1_TXD_MARK, SIOF1_RXD_MARK,
199 SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK,
200 TS_SDAT_MARK, TS_SCK_MARK, TS_SDEN_MARK, TS_SPSYNC_MARK,
201 IRDA_IN_MARK, IRDA_OUT_MARK,
202 TPUTO_MARK,
203 FCE_MARK, NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK,
204 NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK, FCDE_MARK,
205 FOE_MARK, FSC_MARK, FWE_MARK, FRB_MARK,
206 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, KEYIN4_MARK,
207 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
208 KEYOUT4_IN6_MARK, KEYOUT5_IN5_MARK,
209 PINMUX_MARK_END,
210
211 PINMUX_FUNCTION_BEGIN,
212 VIO_D7_SCIF1_SCK, VIO_D6_SCIF1_RXD, VIO_D5_SCIF1_TXD, VIO_D4,
213 VIO_D3, VIO_D2, VIO_D1, VIO_D0_LCDLCLK,
214 HPD55, HPD54, HPD53, HPD52, HPD51, HPD50, HPD49, HPD48,
215 IOIS16, HPDQM7, HPDQM6, HPDQM5, HPDQM4,
216 SDHICD, SDHIWP, SDHID3, IRQ2_SDHID2, SDHID1, SDHID0, SDHICMD, SDHICLK,
217 A25, A24, A23, A22, IRQ5, IRQ4_BS,
218 PTF6, SIOSCK_SIUBOBT, SIOSTRB1_SIUBOLR,
219 SIOSTRB0_SIUBIBT, SIOD_SIUBILR, SIORXD_SIUBISLD, SIOTXD_SIUBOSLD,
220 AUDSYNC, AUDATA3, AUDATA2, AUDATA1, AUDATA0,
221 LCDVCPWC_LCDVCPWC2, LCDVSYN2_DACK, LCDVSYN, LCDDISP_LCDRS,
222 LCDHSYN_LCDCS, LCDDON_LCDDON2, LCDD17_DV_HSYNC, LCDD16_DV_VSYNC,
223 STATUS0, PDSTATUS, IRQ1, IRQ0,
224 SIUAILR_SIOF1_SS2, SIUAIBT_SIOF1_SS1, SIUAOLR_SIOF1_SYNC,
225 SIUAOBT_SIOF1_SCK, SIUAISLD_SIOF1_RXD, SIUAOSLD_SIOF1_TXD, PTK0,
226 LCDD15_DV_D15, LCDD14_DV_D14, LCDD13_DV_D13, LCDD12_DV_D12,
227 LCDD11_DV_D11, LCDD10_DV_D10, LCDD9_DV_D9, LCDD8_DV_D8,
228 LCDD7_DV_D7, LCDD6_DV_D6, LCDD5_DV_D5, LCDD4_DV_D4,
229 LCDD3_DV_D3, LCDD2_DV_D2, LCDD1_DV_D1, LCDD0_DV_D0,
230 HPD63, HPD62, HPD61, HPD60, HPD59, HPD58, HPD57, HPD56,
231 SIOF0_SS2_SIM_RST, SIOF0_SS1_TS_SPSYNC, SIOF0_SYNC_TS_SDEN,
232 SIOF0_SCK_TS_SCK, PTQ2, PTQ1, PTQ0,
233 LCDRD, CS6B_CE1B_LCDCS2, WAIT, LCDDCK_LCDWR, LCDVEPWC_LCDVEPWC2,
234 SCIF0_CTS_SIUAISPD, SCIF0_RTS_SIUAOSPD,
235 SCIF0_SCK_TPUTO, SCIF0_RXD, SCIF0_TXD,
236 FOE_VIO_VD2, FWE, FSC, DREQ0, FCDE,
237 NAF2_VIO_D10, NAF1_VIO_D9, NAF0_VIO_D8,
238 FRB_VIO_CLK2, FCE_VIO_HD2,
239 NAF7_VIO_D15, NAF6_VIO_D14, NAF5_VIO_D13, NAF4_VIO_D12, NAF3_VIO_D11,
240 VIO_FLD_SCIF2_CTS, VIO_CKO_SCIF2_RTS, VIO_STEX_SCIF2_SCK,
241 VIO_STEM_SCIF2_TXD, VIO_HD_SCIF2_RXD,
242 VIO_VD_SCIF1_CTS, VIO_CLK_SCIF1_RTS,
243 CS6A_CE2B, LCDD23, LCDD22, LCDD21, LCDD20,
244 LCDD19_DV_CLKI, LCDD18_DV_CLK,
245 KEYOUT5_IN5, KEYOUT4_IN6, KEYOUT3, KEYOUT2, KEYOUT1, KEYOUT0,
246 KEYIN4_IRQ7, KEYIN3, KEYIN2, KEYIN1, KEYIN0_IRQ6,
247
248 PSA15_KEYIN0, PSA15_IRQ6, PSA14_KEYIN4, PSA14_IRQ7,
249 PSA9_IRQ4, PSA9_BS, PSA4_IRQ2, PSA4_SDHID2,
250 PSB15_SIOTXD, PSB15_SIUBOSLD, PSB14_SIORXD, PSB14_SIUBISLD,
251 PSB13_SIOD, PSB13_SIUBILR, PSB12_SIOSTRB0, PSB12_SIUBIBT,
252 PSB11_SIOSTRB1, PSB11_SIUBOLR, PSB10_SIOSCK, PSB10_SIUBOBT,
253 PSB9_SIOMCK, PSB9_SIUMCKB, PSB8_SIOF0_MCK, PSB8_IRQ3,
254 PSB7_SIOF0_TXD, PSB7_IRDA_OUT, PSB6_SIOF0_RXD, PSB6_IRDA_IN,
255 PSB5_SIOF0_SCK, PSB5_TS_SCK, PSB4_SIOF0_SYNC, PSB4_TS_SDEN,
256 PSB3_SIOF0_SS1, PSB3_TS_SPSYNC, PSB2_SIOF0_SS2, PSB2_SIM_RST,
257 PSB1_SIUMCKA, PSB1_SIOF1_MCK, PSB0_SIUAOSLD, PSB0_SIOF1_TXD,
258 PSC15_SIUAISLD, PSC15_SIOF1_RXD, PSC14_SIUAOBT, PSC14_SIOF1_SCK,
259 PSC13_SIUAOLR, PSC13_SIOF1_SYNC, PSC12_SIUAIBT, PSC12_SIOF1_SS1,
260 PSC11_SIUAILR, PSC11_SIOF1_SS2, PSC0_NAF, PSC0_VIO,
261 PSD13_VIO, PSD13_SCIF2, PSD12_VIO, PSD12_SCIF1,
262 PSD11_VIO, PSD11_SCIF1, PSD10_VIO_D0, PSD10_LCDLCLK,
263 PSD9_SIOMCK_SIUMCKB, PSD9_SIUFCKB, PSD8_SCIF0_SCK, PSD8_TPUTO,
264 PSD7_SCIF0_RTS, PSD7_SIUAOSPD, PSD6_SCIF0_CTS, PSD6_SIUAISPD,
265 PSD5_CS6B_CE1B, PSD5_LCDCS2,
266 PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2,
267 PSD2_LCDDON, PSD2_LCDDON2, PSD0_LCDD19_LCDD0, PSD0_DV,
268 PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D,
269 PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK,
270 PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT, PSE12_LCDVSYN2, PSE12_DACK,
271 PSE11_SIUMCKA_SIOF1_MCK, PSE11_SIUFCKA,
272 PSE3_FLCTL, PSE3_VIO, PSE2_NAF2, PSE2_VIO_D10,
273 PSE1_NAF1, PSE1_VIO_D9, PSE0_NAF0, PSE0_VIO_D8,
274
275 HIZA14_KEYSC, HIZA14_HIZ,
276 HIZA10_NAF, HIZA10_HIZ,
277 HIZA9_VIO, HIZA9_HIZ,
278 HIZA8_LCDC, HIZA8_HIZ,
279 HIZA7_LCDC, HIZA7_HIZ,
280 HIZA6_LCDC, HIZA6_HIZ,
281 HIZB1_VIO, HIZB1_HIZ,
282 HIZB0_VIO, HIZB0_HIZ,
283 HIZC15_IRQ7, HIZC15_HIZ,
284 HIZC14_IRQ6, HIZC14_HIZ,
285 HIZC13_IRQ5, HIZC13_HIZ,
286 HIZC12_IRQ4, HIZC12_HIZ,
287 HIZC11_IRQ3, HIZC11_HIZ,
288 HIZC10_IRQ2, HIZC10_HIZ,
289 HIZC9_IRQ1, HIZC9_HIZ,
290 HIZC8_IRQ0, HIZC8_HIZ,
291 MSELB9_VIO, MSELB9_VIO2,
292 MSELB8_RGB, MSELB8_SYS,
293 PINMUX_FUNCTION_END,
294};
295
296static pinmux_enum_t pinmux_data[] = {
297 /* PTA */
298 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT),
299 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD),
300 PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_IN_PD, PTA5_OUT),
301 PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_IN_PD),
302 PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_IN_PD),
303 PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_IN_PD),
304 PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_IN_PD),
305 PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_IN_PD),
306
307 /* PTB */
308 PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
309 PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
310 PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
311 PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
312 PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
313 PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT),
314 PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT),
315 PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
316
317 /* PTC */
318 PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_IN_PU),
319 PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_IN_PU),
320 PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
321 PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
322 PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
323 PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
324
325 /* PTD */
326 PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_IN_PU),
327 PINMUX_DATA(PTD6_DATA, PTD6_OUT, PTD6_IN, PTD6_IN_PU),
328 PINMUX_DATA(PTD5_DATA, PTD5_OUT, PTD5_IN, PTD5_IN_PU),
329 PINMUX_DATA(PTD4_DATA, PTD4_OUT, PTD4_IN, PTD4_IN_PU),
330 PINMUX_DATA(PTD3_DATA, PTD3_OUT, PTD3_IN, PTD3_IN_PU),
331 PINMUX_DATA(PTD2_DATA, PTD2_OUT, PTD2_IN, PTD2_IN_PU),
332 PINMUX_DATA(PTD1_DATA, PTD1_OUT, PTD1_IN, PTD1_IN_PU),
333 PINMUX_DATA(PTD0_DATA, PTD0_OUT),
334
335 /* PTE */
336 PINMUX_DATA(PTE7_DATA, PTE7_OUT, PTE7_IN, PTE7_IN_PD),
337 PINMUX_DATA(PTE6_DATA, PTE6_OUT, PTE6_IN, PTE6_IN_PD),
338 PINMUX_DATA(PTE5_DATA, PTE5_OUT, PTE5_IN, PTE5_IN_PD),
339 PINMUX_DATA(PTE4_DATA, PTE4_OUT, PTE4_IN, PTE4_IN_PD),
340 PINMUX_DATA(PTE1_DATA, PTE1_OUT, PTE1_IN, PTE1_IN_PD),
341 PINMUX_DATA(PTE0_DATA, PTE0_OUT, PTE0_IN, PTE0_IN_PD),
342
343 /* PTF */
344 PINMUX_DATA(PTF6_DATA, PTF6_OUT, PTF6_IN, PTF6_IN_PD),
345 PINMUX_DATA(PTF5_DATA, PTF5_OUT, PTF5_IN, PTF5_IN_PD),
346 PINMUX_DATA(PTF4_DATA, PTF4_OUT, PTF4_IN, PTF4_IN_PD),
347 PINMUX_DATA(PTF3_DATA, PTF3_OUT, PTF3_IN, PTF3_IN_PD),
348 PINMUX_DATA(PTF2_DATA, PTF2_OUT, PTF2_IN, PTF2_IN_PD),
349 PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_IN_PD),
350 PINMUX_DATA(PTF0_DATA, PTF0_OUT),
351
352 /* PTG */
353 PINMUX_DATA(PTG4_DATA, PTG4_OUT),
354 PINMUX_DATA(PTG3_DATA, PTG3_OUT),
355 PINMUX_DATA(PTG2_DATA, PTG2_OUT),
356 PINMUX_DATA(PTG1_DATA, PTG1_OUT),
357 PINMUX_DATA(PTG0_DATA, PTG0_OUT),
358
359 /* PTH */
360 PINMUX_DATA(PTH7_DATA, PTH7_OUT),
361 PINMUX_DATA(PTH6_DATA, PTH6_OUT, PTH6_IN, PTH6_IN_PD),
362 PINMUX_DATA(PTH5_DATA, PTH5_OUT, PTH5_IN, PTH5_IN_PD),
363 PINMUX_DATA(PTH4_DATA, PTH4_OUT),
364 PINMUX_DATA(PTH3_DATA, PTH3_OUT),
365 PINMUX_DATA(PTH2_DATA, PTH2_OUT),
366 PINMUX_DATA(PTH1_DATA, PTH1_OUT, PTH1_IN, PTH1_IN_PD),
367 PINMUX_DATA(PTH0_DATA, PTH0_OUT, PTH0_IN, PTH0_IN_PD),
368
369 /* PTJ */
370 PINMUX_DATA(PTJ7_DATA, PTJ7_OUT),
371 PINMUX_DATA(PTJ6_DATA, PTJ6_OUT),
372 PINMUX_DATA(PTJ5_DATA, PTJ5_OUT),
373 PINMUX_DATA(PTJ1_DATA, PTJ1_OUT, PTJ1_IN, PTJ1_IN_PU),
374 PINMUX_DATA(PTJ0_DATA, PTJ0_OUT, PTJ0_IN, PTJ0_IN_PU),
375
376 /* PTK */
377 PINMUX_DATA(PTK6_DATA, PTK6_OUT, PTK6_IN, PTK6_IN_PD),
378 PINMUX_DATA(PTK5_DATA, PTK5_OUT, PTK5_IN, PTK5_IN_PD),
379 PINMUX_DATA(PTK4_DATA, PTK4_OUT, PTK4_IN, PTK4_IN_PD),
380 PINMUX_DATA(PTK3_DATA, PTK3_OUT, PTK3_IN, PTK3_IN_PD),
381 PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_IN_PD),
382 PINMUX_DATA(PTK1_DATA, PTK1_OUT),
383 PINMUX_DATA(PTK0_DATA, PTK0_OUT, PTK0_IN, PTK0_IN_PD),
384
385 /* PTL */
386 PINMUX_DATA(PTL7_DATA, PTL7_OUT, PTL7_IN, PTL7_IN_PD),
387 PINMUX_DATA(PTL6_DATA, PTL6_OUT, PTL6_IN, PTL6_IN_PD),
388 PINMUX_DATA(PTL5_DATA, PTL5_OUT, PTL5_IN, PTL5_IN_PD),
389 PINMUX_DATA(PTL4_DATA, PTL4_OUT, PTL4_IN, PTL4_IN_PD),
390 PINMUX_DATA(PTL3_DATA, PTL3_OUT, PTL3_IN, PTL3_IN_PD),
391 PINMUX_DATA(PTL2_DATA, PTL2_OUT, PTL2_IN, PTL2_IN_PD),
392 PINMUX_DATA(PTL1_DATA, PTL1_OUT, PTL1_IN, PTL1_IN_PD),
393 PINMUX_DATA(PTL0_DATA, PTL0_OUT, PTL0_IN, PTL0_IN_PD),
394
395 /* PTM */
396 PINMUX_DATA(PTM7_DATA, PTM7_OUT, PTM7_IN, PTM7_IN_PD),
397 PINMUX_DATA(PTM6_DATA, PTM6_OUT, PTM6_IN, PTM6_IN_PD),
398 PINMUX_DATA(PTM5_DATA, PTM5_OUT, PTM5_IN, PTM5_IN_PD),
399 PINMUX_DATA(PTM4_DATA, PTM4_OUT, PTM4_IN, PTM4_IN_PD),
400 PINMUX_DATA(PTM3_DATA, PTM3_OUT, PTM3_IN, PTM3_IN_PD),
401 PINMUX_DATA(PTM2_DATA, PTM2_OUT, PTM2_IN, PTM2_IN_PD),
402 PINMUX_DATA(PTM1_DATA, PTM1_OUT, PTM1_IN, PTM1_IN_PD),
403 PINMUX_DATA(PTM0_DATA, PTM0_OUT, PTM0_IN, PTM0_IN_PD),
404
405 /* PTN */
406 PINMUX_DATA(PTN7_DATA, PTN7_OUT, PTN7_IN),
407 PINMUX_DATA(PTN6_DATA, PTN6_OUT, PTN6_IN),
408 PINMUX_DATA(PTN5_DATA, PTN5_OUT, PTN5_IN),
409 PINMUX_DATA(PTN4_DATA, PTN4_OUT, PTN4_IN),
410 PINMUX_DATA(PTN3_DATA, PTN3_OUT, PTN3_IN),
411 PINMUX_DATA(PTN2_DATA, PTN2_OUT, PTN2_IN),
412 PINMUX_DATA(PTN1_DATA, PTN1_OUT, PTN1_IN),
413 PINMUX_DATA(PTN0_DATA, PTN0_OUT, PTN0_IN),
414
415 /* PTQ */
416 PINMUX_DATA(PTQ6_DATA, PTQ6_OUT),
417 PINMUX_DATA(PTQ5_DATA, PTQ5_OUT, PTQ5_IN, PTQ5_IN_PD),
418 PINMUX_DATA(PTQ4_DATA, PTQ4_OUT, PTQ4_IN, PTQ4_IN_PD),
419 PINMUX_DATA(PTQ3_DATA, PTQ3_OUT, PTQ3_IN, PTQ3_IN_PD),
420 PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_IN_PD),
421 PINMUX_DATA(PTQ1_DATA, PTQ1_OUT),
422 PINMUX_DATA(PTQ0_DATA, PTQ0_OUT, PTQ0_IN, PTQ0_IN_PU),
423
424 /* PTR */
425 PINMUX_DATA(PTR4_DATA, PTR4_OUT),
426 PINMUX_DATA(PTR3_DATA, PTR3_OUT),
427 PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU),
428 PINMUX_DATA(PTR1_DATA, PTR1_OUT),
429 PINMUX_DATA(PTR0_DATA, PTR0_OUT),
430
431 /* PTS */
432 PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_IN_PD),
433 PINMUX_DATA(PTS3_DATA, PTS3_OUT),
434 PINMUX_DATA(PTS2_DATA, PTS2_OUT, PTS2_IN, PTS2_IN_PD),
435 PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_IN_PD),
436 PINMUX_DATA(PTS0_DATA, PTS0_OUT),
437
438 /* PTT */
439 PINMUX_DATA(PTT4_DATA, PTT4_OUT, PTT4_IN, PTT4_IN_PD),
440 PINMUX_DATA(PTT3_DATA, PTT3_OUT, PTT3_IN, PTT3_IN_PD),
441 PINMUX_DATA(PTT2_DATA, PTT2_OUT, PTT2_IN, PTT2_IN_PD),
442 PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_IN_PD),
443 PINMUX_DATA(PTT0_DATA, PTT0_OUT),
444
445 /* PTU */
446 PINMUX_DATA(PTU4_DATA, PTU4_OUT, PTU4_IN, PTU4_IN_PD),
447 PINMUX_DATA(PTU3_DATA, PTU3_OUT, PTU3_IN, PTU3_IN_PD),
448 PINMUX_DATA(PTU2_DATA, PTU2_OUT, PTU2_IN, PTU2_IN_PD),
449 PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_IN_PD),
450 PINMUX_DATA(PTU0_DATA, PTU0_OUT, PTU0_IN, PTU0_IN_PD),
451
452 /* PTV */
453 PINMUX_DATA(PTV4_DATA, PTV4_OUT, PTV4_IN, PTV4_IN_PD),
454 PINMUX_DATA(PTV3_DATA, PTV3_OUT, PTV3_IN, PTV3_IN_PD),
455 PINMUX_DATA(PTV2_DATA, PTV2_OUT, PTV2_IN, PTV2_IN_PD),
456 PINMUX_DATA(PTV1_DATA, PTV1_OUT, PTV1_IN, PTV1_IN_PD),
457 PINMUX_DATA(PTV0_DATA, PTV0_OUT, PTV0_IN, PTV0_IN_PD),
458
459 /* PTW */
460 PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_IN_PD),
461 PINMUX_DATA(PTW5_DATA, PTW5_OUT),
462 PINMUX_DATA(PTW4_DATA, PTW4_OUT, PTW4_IN, PTW4_IN_PD),
463 PINMUX_DATA(PTW3_DATA, PTW3_OUT, PTW3_IN, PTW3_IN_PD),
464 PINMUX_DATA(PTW2_DATA, PTW2_OUT, PTW2_IN, PTW2_IN_PD),
465 PINMUX_DATA(PTW1_DATA, PTW1_OUT, PTW1_IN, PTW1_IN_PD),
466 PINMUX_DATA(PTW0_DATA, PTW0_OUT, PTW0_IN, PTW0_IN_PD),
467
468 /* PTX */
469 PINMUX_DATA(PTX6_DATA, PTX6_OUT, PTX6_IN, PTX6_IN_PD),
470 PINMUX_DATA(PTX5_DATA, PTX5_OUT, PTX5_IN, PTX5_IN_PD),
471 PINMUX_DATA(PTX4_DATA, PTX4_OUT, PTX4_IN, PTX4_IN_PD),
472 PINMUX_DATA(PTX3_DATA, PTX3_OUT, PTX3_IN, PTX3_IN_PD),
473 PINMUX_DATA(PTX2_DATA, PTX2_OUT, PTX2_IN, PTX2_IN_PD),
474 PINMUX_DATA(PTX1_DATA, PTX1_OUT, PTX1_IN, PTX1_IN_PD),
475 PINMUX_DATA(PTX0_DATA, PTX0_OUT, PTX0_IN, PTX0_IN_PD),
476
477 /* PTY */
478 PINMUX_DATA(PTY5_DATA, PTY5_OUT, PTY5_IN, PTY5_IN_PU),
479 PINMUX_DATA(PTY4_DATA, PTY4_OUT, PTY4_IN, PTY4_IN_PU),
480 PINMUX_DATA(PTY3_DATA, PTY3_OUT, PTY3_IN, PTY3_IN_PU),
481 PINMUX_DATA(PTY2_DATA, PTY2_OUT, PTY2_IN, PTY2_IN_PU),
482 PINMUX_DATA(PTY1_DATA, PTY1_OUT),
483 PINMUX_DATA(PTY0_DATA, PTY0_OUT, PTY0_IN, PTY0_IN_PU),
484
485 /* PTZ */
486 PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_IN_PU),
487 PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_IN_PU),
488 PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_IN_PU),
489 PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_IN_PU),
490 PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_IN_PU),
491
492 /* SCIF0 */
493 PINMUX_DATA(SCIF0_TXD_MARK, SCIF0_TXD),
494 PINMUX_DATA(SCIF0_RXD_MARK, SCIF0_RXD),
495 PINMUX_DATA(SCIF0_RTS_MARK, PSD7_SCIF0_RTS, SCIF0_RTS_SIUAOSPD),
496 PINMUX_DATA(SCIF0_CTS_MARK, PSD6_SCIF0_CTS, SCIF0_CTS_SIUAISPD),
497 PINMUX_DATA(SCIF0_SCK_MARK, PSD8_SCIF0_SCK, SCIF0_SCK_TPUTO),
498
499 /* SCIF1 */
500 PINMUX_DATA(SCIF1_TXD_MARK, PSD11_SCIF1, VIO_D5_SCIF1_TXD),
501 PINMUX_DATA(SCIF1_RXD_MARK, PSD11_SCIF1, VIO_D6_SCIF1_RXD),
502 PINMUX_DATA(SCIF1_RTS_MARK, PSD12_SCIF1, VIO_CLK_SCIF1_RTS),
503 PINMUX_DATA(SCIF1_CTS_MARK, PSD12_SCIF1, VIO_VD_SCIF1_CTS),
504 PINMUX_DATA(SCIF1_SCK_MARK, PSD11_SCIF1, VIO_D7_SCIF1_SCK),
505
506 /* SCIF2 */
507 PINMUX_DATA(SCIF2_TXD_MARK, PSD13_SCIF2, VIO_STEM_SCIF2_TXD),
508 PINMUX_DATA(SCIF2_RXD_MARK, PSD13_SCIF2, VIO_HD_SCIF2_RXD),
509 PINMUX_DATA(SCIF2_RTS_MARK, PSD13_SCIF2, VIO_CKO_SCIF2_RTS),
510 PINMUX_DATA(SCIF2_CTS_MARK, PSD13_SCIF2, VIO_FLD_SCIF2_CTS),
511 PINMUX_DATA(SCIF2_SCK_MARK, PSD13_SCIF2, VIO_STEX_SCIF2_SCK),
512
513 /* SIO */
514 PINMUX_DATA(SIOTXD_MARK, PSB15_SIOTXD, SIOTXD_SIUBOSLD),
515 PINMUX_DATA(SIORXD_MARK, PSB14_SIORXD, SIORXD_SIUBISLD),
516 PINMUX_DATA(SIOD_MARK, PSB13_SIOD, SIOD_SIUBILR),
517 PINMUX_DATA(SIOSTRB0_MARK, PSB12_SIOSTRB0, SIOSTRB0_SIUBIBT),
518 PINMUX_DATA(SIOSTRB1_MARK, PSB11_SIOSTRB1, SIOSTRB1_SIUBOLR),
519 PINMUX_DATA(SIOSCK_MARK, PSB10_SIOSCK, SIOSCK_SIUBOBT),
520 PINMUX_DATA(SIOMCK_MARK, PSD9_SIOMCK_SIUMCKB, PSB9_SIOMCK, PTF6),
521
522 /* CEU */
523 PINMUX_DATA(VIO_D15_MARK, PSC0_VIO, HIZA10_NAF, NAF7_VIO_D15),
524 PINMUX_DATA(VIO_D14_MARK, PSC0_VIO, HIZA10_NAF, NAF6_VIO_D14),
525 PINMUX_DATA(VIO_D13_MARK, PSC0_VIO, HIZA10_NAF, NAF5_VIO_D13),
526 PINMUX_DATA(VIO_D12_MARK, PSC0_VIO, HIZA10_NAF, NAF4_VIO_D12),
527 PINMUX_DATA(VIO_D11_MARK, PSC0_VIO, HIZA10_NAF, NAF3_VIO_D11),
528 PINMUX_DATA(VIO_D10_MARK, PSE2_VIO_D10, HIZB0_VIO, NAF2_VIO_D10),
529 PINMUX_DATA(VIO_D9_MARK, PSE1_VIO_D9, HIZB0_VIO, NAF1_VIO_D9),
530 PINMUX_DATA(VIO_D8_MARK, PSE0_VIO_D8, HIZB0_VIO, NAF0_VIO_D8),
531 PINMUX_DATA(VIO_D7_MARK, PSD11_VIO, VIO_D7_SCIF1_SCK),
532 PINMUX_DATA(VIO_D6_MARK, PSD11_VIO, VIO_D6_SCIF1_RXD),
533 PINMUX_DATA(VIO_D5_MARK, PSD11_VIO, VIO_D5_SCIF1_TXD),
534 PINMUX_DATA(VIO_D4_MARK, VIO_D4),
535 PINMUX_DATA(VIO_D3_MARK, VIO_D3),
536 PINMUX_DATA(VIO_D2_MARK, VIO_D2),
537 PINMUX_DATA(VIO_D1_MARK, VIO_D1),
538 PINMUX_DATA(VIO_D0_MARK, PSD10_VIO_D0, VIO_D0_LCDLCLK),
539 PINMUX_DATA(VIO_CLK_MARK, PSD12_VIO, MSELB9_VIO, VIO_CLK_SCIF1_RTS),
540 PINMUX_DATA(VIO_VD_MARK, PSD12_VIO, MSELB9_VIO, VIO_VD_SCIF1_CTS),
541 PINMUX_DATA(VIO_HD_MARK, PSD13_VIO, MSELB9_VIO, VIO_HD_SCIF2_RXD),
542 PINMUX_DATA(VIO_FLD_MARK, PSD13_VIO, HIZA9_VIO, VIO_FLD_SCIF2_CTS),
543 PINMUX_DATA(VIO_CKO_MARK, PSD13_VIO, HIZA9_VIO, VIO_CKO_SCIF2_RTS),
544 PINMUX_DATA(VIO_STEX_MARK, PSD13_VIO, HIZA9_VIO, VIO_STEX_SCIF2_SCK),
545 PINMUX_DATA(VIO_STEM_MARK, PSD13_VIO, HIZA9_VIO, VIO_STEM_SCIF2_TXD),
546 PINMUX_DATA(VIO_VD2_MARK, PSE3_VIO, MSELB9_VIO2,
547 HIZB0_VIO, FOE_VIO_VD2),
548 PINMUX_DATA(VIO_HD2_MARK, PSE3_VIO, MSELB9_VIO2,
549 HIZB1_VIO, HIZB1_VIO, FCE_VIO_HD2),
550 PINMUX_DATA(VIO_CLK2_MARK, PSE3_VIO, MSELB9_VIO2,
551 HIZB1_VIO, FRB_VIO_CLK2),
552
553 /* LCDC */
554 PINMUX_DATA(LCDD23_MARK, HIZA8_LCDC, LCDD23),
555 PINMUX_DATA(LCDD22_MARK, HIZA8_LCDC, LCDD22),
556 PINMUX_DATA(LCDD21_MARK, HIZA8_LCDC, LCDD21),
557 PINMUX_DATA(LCDD20_MARK, HIZA8_LCDC, LCDD20),
558 PINMUX_DATA(LCDD19_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD19_DV_CLKI),
559 PINMUX_DATA(LCDD18_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD18_DV_CLK),
560 PINMUX_DATA(LCDD17_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC,
561 LCDD17_DV_HSYNC),
562 PINMUX_DATA(LCDD16_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC,
563 LCDD16_DV_VSYNC),
564 PINMUX_DATA(LCDD15_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD15_DV_D15),
565 PINMUX_DATA(LCDD14_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD14_DV_D14),
566 PINMUX_DATA(LCDD13_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD13_DV_D13),
567 PINMUX_DATA(LCDD12_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD12_DV_D12),
568 PINMUX_DATA(LCDD11_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD11_DV_D11),
569 PINMUX_DATA(LCDD10_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD10_DV_D10),
570 PINMUX_DATA(LCDD9_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD9_DV_D9),
571 PINMUX_DATA(LCDD8_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD8_DV_D8),
572 PINMUX_DATA(LCDD7_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD7_DV_D7),
573 PINMUX_DATA(LCDD6_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD6_DV_D6),
574 PINMUX_DATA(LCDD5_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD5_DV_D5),
575 PINMUX_DATA(LCDD4_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD4_DV_D4),
576 PINMUX_DATA(LCDD3_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD3_DV_D3),
577 PINMUX_DATA(LCDD2_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD2_DV_D2),
578 PINMUX_DATA(LCDD1_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD1_DV_D1),
579 PINMUX_DATA(LCDD0_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD0_DV_D0),
580 PINMUX_DATA(LCDLCLK_MARK, PSD10_LCDLCLK, VIO_D0_LCDLCLK),
581 /* Main LCD */
582 PINMUX_DATA(LCDDON_MARK, PSD2_LCDDON, HIZA7_LCDC, LCDDON_LCDDON2),
583 PINMUX_DATA(LCDVCPWC_MARK, PSD3_LCDVEPWC_LCDVCPWC,
584 HIZA6_LCDC, LCDVCPWC_LCDVCPWC2),
585 PINMUX_DATA(LCDVEPWC_MARK, PSD3_LCDVEPWC_LCDVCPWC,
586 HIZA6_LCDC, LCDVEPWC_LCDVEPWC2),
587 PINMUX_DATA(LCDVSYN_MARK, HIZA7_LCDC, LCDVSYN),
588 /* Main LCD - RGB Mode */
589 PINMUX_DATA(LCDDCK_MARK, MSELB8_RGB, HIZA8_LCDC, LCDDCK_LCDWR),
590 PINMUX_DATA(LCDHSYN_MARK, MSELB8_RGB, HIZA7_LCDC, LCDHSYN_LCDCS),
591 PINMUX_DATA(LCDDISP_MARK, MSELB8_RGB, HIZA7_LCDC, LCDDISP_LCDRS),
592 /* Main LCD - SYS Mode */
593 PINMUX_DATA(LCDRS_MARK, MSELB8_SYS, HIZA7_LCDC, LCDDISP_LCDRS),
594 PINMUX_DATA(LCDCS_MARK, MSELB8_SYS, HIZA7_LCDC, LCDHSYN_LCDCS),
595 PINMUX_DATA(LCDWR_MARK, MSELB8_SYS, HIZA8_LCDC, LCDDCK_LCDWR),
596 PINMUX_DATA(LCDRD_MARK, HIZA7_LCDC, LCDRD),
597 /* Sub LCD - SYS Mode */
598 PINMUX_DATA(LCDDON2_MARK, PSD2_LCDDON2, HIZA7_LCDC, LCDDON_LCDDON2),
599 PINMUX_DATA(LCDVCPWC2_MARK, PSD3_LCDVEPWC2_LCDVCPWC2,
600 HIZA6_LCDC, LCDVCPWC_LCDVCPWC2),
601 PINMUX_DATA(LCDVEPWC2_MARK, PSD3_LCDVEPWC2_LCDVCPWC2,
602 HIZA6_LCDC, LCDVEPWC_LCDVEPWC2),
603 PINMUX_DATA(LCDVSYN2_MARK, PSE12_LCDVSYN2, HIZA8_LCDC, LCDVSYN2_DACK),
604 PINMUX_DATA(LCDCS2_MARK, PSD5_LCDCS2, CS6B_CE1B_LCDCS2),
605
606 /* BSC */
607 PINMUX_DATA(IOIS16_MARK, IOIS16),
608 PINMUX_DATA(A25_MARK, A25),
609 PINMUX_DATA(A24_MARK, A24),
610 PINMUX_DATA(A23_MARK, A23),
611 PINMUX_DATA(A22_MARK, A22),
612 PINMUX_DATA(BS_MARK, PSA9_BS, IRQ4_BS),
613 PINMUX_DATA(CS6B_CE1B_MARK, PSD5_CS6B_CE1B, CS6B_CE1B_LCDCS2),
614 PINMUX_DATA(WAIT_MARK, WAIT),
615 PINMUX_DATA(CS6A_CE2B_MARK, CS6A_CE2B),
616
617 /* SBSC */
618 PINMUX_DATA(HPD63_MARK, HPD63),
619 PINMUX_DATA(HPD62_MARK, HPD62),
620 PINMUX_DATA(HPD61_MARK, HPD61),
621 PINMUX_DATA(HPD60_MARK, HPD60),
622 PINMUX_DATA(HPD59_MARK, HPD59),
623 PINMUX_DATA(HPD58_MARK, HPD58),
624 PINMUX_DATA(HPD57_MARK, HPD57),
625 PINMUX_DATA(HPD56_MARK, HPD56),
626 PINMUX_DATA(HPD55_MARK, HPD55),
627 PINMUX_DATA(HPD54_MARK, HPD54),
628 PINMUX_DATA(HPD53_MARK, HPD53),
629 PINMUX_DATA(HPD52_MARK, HPD52),
630 PINMUX_DATA(HPD51_MARK, HPD51),
631 PINMUX_DATA(HPD50_MARK, HPD50),
632 PINMUX_DATA(HPD49_MARK, HPD49),
633 PINMUX_DATA(HPD48_MARK, HPD48),
634 PINMUX_DATA(HPDQM7_MARK, HPDQM7),
635 PINMUX_DATA(HPDQM6_MARK, HPDQM6),
636 PINMUX_DATA(HPDQM5_MARK, HPDQM5),
637 PINMUX_DATA(HPDQM4_MARK, HPDQM4),
638
639 /* IRQ */
640 PINMUX_DATA(IRQ0_MARK, HIZC8_IRQ0, IRQ0),
641 PINMUX_DATA(IRQ1_MARK, HIZC9_IRQ1, IRQ1),
642 PINMUX_DATA(IRQ2_MARK, PSA4_IRQ2, HIZC10_IRQ2, IRQ2_SDHID2),
643 PINMUX_DATA(IRQ3_MARK, PSE15_SIOF0_MCK_IRQ3, PSB8_IRQ3,
644 HIZC11_IRQ3, PTQ0),
645 PINMUX_DATA(IRQ4_MARK, PSA9_IRQ4, HIZC12_IRQ4, IRQ4_BS),
646 PINMUX_DATA(IRQ5_MARK, HIZC13_IRQ5, IRQ5),
647 PINMUX_DATA(IRQ6_MARK, PSA15_IRQ6, HIZC14_IRQ6, KEYIN0_IRQ6),
648 PINMUX_DATA(IRQ7_MARK, PSA14_IRQ7, HIZC15_IRQ7, KEYIN4_IRQ7),
649
650 /* SDHI */
651 PINMUX_DATA(SDHICD_MARK, SDHICD),
652 PINMUX_DATA(SDHIWP_MARK, SDHIWP),
653 PINMUX_DATA(SDHID3_MARK, SDHID3),
654 PINMUX_DATA(SDHID2_MARK, PSA4_SDHID2, IRQ2_SDHID2),
655 PINMUX_DATA(SDHID1_MARK, SDHID1),
656 PINMUX_DATA(SDHID0_MARK, SDHID0),
657 PINMUX_DATA(SDHICMD_MARK, SDHICMD),
658 PINMUX_DATA(SDHICLK_MARK, SDHICLK),
659
660 /* SIU - Port A */
661 PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, SIUAOLR_SIOF1_SYNC),
662 PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, SIUAOBT_SIOF1_SCK),
663 PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, SIUAISLD_SIOF1_RXD),
664 PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, SIUAILR_SIOF1_SS2),
665 PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, SIUAIBT_SIOF1_SS1),
666 PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, SIUAOSLD_SIOF1_TXD),
667 PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, PSB1_SIUMCKA, PTK0),
668 PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, PTK0),
669
670 /* SIU - Port B */
671 PINMUX_DATA(SIUBOLR_MARK, PSB11_SIUBOLR, SIOSTRB1_SIUBOLR),
672 PINMUX_DATA(SIUBOBT_MARK, PSB10_SIUBOBT, SIOSCK_SIUBOBT),
673 PINMUX_DATA(SIUBISLD_MARK, PSB14_SIUBISLD, SIORXD_SIUBISLD),
674 PINMUX_DATA(SIUBILR_MARK, PSB13_SIUBILR, SIOD_SIUBILR),
675 PINMUX_DATA(SIUBIBT_MARK, PSB12_SIUBIBT, SIOSTRB0_SIUBIBT),
676 PINMUX_DATA(SIUBOSLD_MARK, PSB15_SIUBOSLD, SIOTXD_SIUBOSLD),
677 PINMUX_DATA(SIUMCKB_MARK, PSD9_SIOMCK_SIUMCKB, PSB9_SIUMCKB, PTF6),
678 PINMUX_DATA(SIUFCKB_MARK, PSD9_SIUFCKB, PTF6),
679
680 /* AUD */
681 PINMUX_DATA(AUDSYNC_MARK, AUDSYNC),
682 PINMUX_DATA(AUDATA3_MARK, AUDATA3),
683 PINMUX_DATA(AUDATA2_MARK, AUDATA2),
684 PINMUX_DATA(AUDATA1_MARK, AUDATA1),
685 PINMUX_DATA(AUDATA0_MARK, AUDATA0),
686
687 /* DMAC */
688 PINMUX_DATA(DACK_MARK, PSE12_DACK, LCDVSYN2_DACK),
689 PINMUX_DATA(DREQ0_MARK, DREQ0),
690
691 /* VOU */
692 PINMUX_DATA(DV_CLKI_MARK, PSD0_DV, LCDD19_DV_CLKI),
693 PINMUX_DATA(DV_CLK_MARK, PSD0_DV, LCDD18_DV_CLK),
694 PINMUX_DATA(DV_HSYNC_MARK, PSD0_DV, LCDD17_DV_HSYNC),
695 PINMUX_DATA(DV_VSYNC_MARK, PSD0_DV, LCDD16_DV_VSYNC),
696 PINMUX_DATA(DV_D15_MARK, PSD0_DV, LCDD15_DV_D15),
697 PINMUX_DATA(DV_D14_MARK, PSD0_DV, LCDD14_DV_D14),
698 PINMUX_DATA(DV_D13_MARK, PSD0_DV, LCDD13_DV_D13),
699 PINMUX_DATA(DV_D12_MARK, PSD0_DV, LCDD12_DV_D12),
700 PINMUX_DATA(DV_D11_MARK, PSD0_DV, LCDD11_DV_D11),
701 PINMUX_DATA(DV_D10_MARK, PSD0_DV, LCDD10_DV_D10),
702 PINMUX_DATA(DV_D9_MARK, PSD0_DV, LCDD9_DV_D9),
703 PINMUX_DATA(DV_D8_MARK, PSD0_DV, LCDD8_DV_D8),
704 PINMUX_DATA(DV_D7_MARK, PSD0_DV, LCDD7_DV_D7),
705 PINMUX_DATA(DV_D6_MARK, PSD0_DV, LCDD6_DV_D6),
706 PINMUX_DATA(DV_D5_MARK, PSD0_DV, LCDD5_DV_D5),
707 PINMUX_DATA(DV_D4_MARK, PSD0_DV, LCDD4_DV_D4),
708 PINMUX_DATA(DV_D3_MARK, PSD0_DV, LCDD3_DV_D3),
709 PINMUX_DATA(DV_D2_MARK, PSD0_DV, LCDD2_DV_D2),
710 PINMUX_DATA(DV_D1_MARK, PSD0_DV, LCDD1_DV_D1),
711 PINMUX_DATA(DV_D0_MARK, PSD0_DV, LCDD0_DV_D0),
712
713 /* CPG */
714 PINMUX_DATA(STATUS0_MARK, STATUS0),
715 PINMUX_DATA(PDSTATUS_MARK, PDSTATUS),
716
717 /* SIOF0 */
718 PINMUX_DATA(SIOF0_MCK_MARK, PSE15_SIOF0_MCK_IRQ3, PSB8_SIOF0_MCK, PTQ0),
719 PINMUX_DATA(SIOF0_SCK_MARK, PSB5_SIOF0_SCK, SIOF0_SCK_TS_SCK),
720 PINMUX_DATA(SIOF0_SYNC_MARK, PSB4_SIOF0_SYNC, SIOF0_SYNC_TS_SDEN),
721 PINMUX_DATA(SIOF0_SS1_MARK, PSB3_SIOF0_SS1, SIOF0_SS1_TS_SPSYNC),
722 PINMUX_DATA(SIOF0_SS2_MARK, PSB2_SIOF0_SS2, SIOF0_SS2_SIM_RST),
723 PINMUX_DATA(SIOF0_TXD_MARK, PSE14_SIOF0_TXD_IRDA_OUT,
724 PSB7_SIOF0_TXD, PTQ1),
725 PINMUX_DATA(SIOF0_RXD_MARK, PSE13_SIOF0_RXD_IRDA_IN,
726 PSB6_SIOF0_RXD, PTQ2),
727
728 /* SIOF1 */
729 PINMUX_DATA(SIOF1_MCK_MARK, PSE11_SIUMCKA_SIOF1_MCK,
730 PSB1_SIOF1_MCK, PTK0),
731 PINMUX_DATA(SIOF1_SCK_MARK, PSC14_SIOF1_SCK, SIUAOBT_SIOF1_SCK),
732 PINMUX_DATA(SIOF1_SYNC_MARK, PSC13_SIOF1_SYNC, SIUAOLR_SIOF1_SYNC),
733 PINMUX_DATA(SIOF1_SS1_MARK, PSC12_SIOF1_SS1, SIUAIBT_SIOF1_SS1),
734 PINMUX_DATA(SIOF1_SS2_MARK, PSC11_SIOF1_SS2, SIUAILR_SIOF1_SS2),
735 PINMUX_DATA(SIOF1_TXD_MARK, PSB0_SIOF1_TXD, SIUAOSLD_SIOF1_TXD),
736 PINMUX_DATA(SIOF1_RXD_MARK, PSC15_SIOF1_RXD, SIUAISLD_SIOF1_RXD),
737
738 /* SIM */
739 PINMUX_DATA(SIM_D_MARK, PSE15_SIM_D, PTQ0),
740 PINMUX_DATA(SIM_CLK_MARK, PSE14_SIM_CLK, PTQ1),
741 PINMUX_DATA(SIM_RST_MARK, PSB2_SIM_RST, SIOF0_SS2_SIM_RST),
742
743 /* TSIF */
744 PINMUX_DATA(TS_SDAT_MARK, PSE13_TS_SDAT, PTQ2),
745 PINMUX_DATA(TS_SCK_MARK, PSB5_TS_SCK, SIOF0_SCK_TS_SCK),
746 PINMUX_DATA(TS_SDEN_MARK, PSB4_TS_SDEN, SIOF0_SYNC_TS_SDEN),
747 PINMUX_DATA(TS_SPSYNC_MARK, PSB3_TS_SPSYNC, SIOF0_SS1_TS_SPSYNC),
748
749 /* IRDA */
750 PINMUX_DATA(IRDA_IN_MARK, PSE13_SIOF0_RXD_IRDA_IN, PSB6_IRDA_IN, PTQ2),
751 PINMUX_DATA(IRDA_OUT_MARK, PSE14_SIOF0_TXD_IRDA_OUT,
752 PSB7_IRDA_OUT, PTQ1),
753
754 /* TPU */
755 PINMUX_DATA(TPUTO_MARK, PSD8_TPUTO, SCIF0_SCK_TPUTO),
756
757 /* FLCTL */
758 PINMUX_DATA(FCE_MARK, PSE3_FLCTL, FCE_VIO_HD2),
759 PINMUX_DATA(NAF7_MARK, PSC0_NAF, HIZA10_NAF, NAF7_VIO_D15),
760 PINMUX_DATA(NAF6_MARK, PSC0_NAF, HIZA10_NAF, NAF6_VIO_D14),
761 PINMUX_DATA(NAF5_MARK, PSC0_NAF, HIZA10_NAF, NAF5_VIO_D13),
762 PINMUX_DATA(NAF4_MARK, PSC0_NAF, HIZA10_NAF, NAF4_VIO_D12),
763 PINMUX_DATA(NAF3_MARK, PSC0_NAF, HIZA10_NAF, NAF3_VIO_D11),
764 PINMUX_DATA(NAF2_MARK, PSE2_NAF2, HIZB0_VIO, NAF2_VIO_D10),
765 PINMUX_DATA(NAF1_MARK, PSE1_NAF1, HIZB0_VIO, NAF1_VIO_D9),
766 PINMUX_DATA(NAF0_MARK, PSE0_NAF0, HIZB0_VIO, NAF0_VIO_D8),
767 PINMUX_DATA(FCDE_MARK, FCDE),
768 PINMUX_DATA(FOE_MARK, PSE3_FLCTL, HIZB0_VIO, FOE_VIO_VD2),
769 PINMUX_DATA(FSC_MARK, FSC),
770 PINMUX_DATA(FWE_MARK, FWE),
771 PINMUX_DATA(FRB_MARK, PSE3_FLCTL, FRB_VIO_CLK2),
772
773 /* KEYSC */
774 PINMUX_DATA(KEYIN0_MARK, PSA15_KEYIN0, HIZC14_IRQ6, KEYIN0_IRQ6),
775 PINMUX_DATA(KEYIN1_MARK, HIZA14_KEYSC, KEYIN1),
776 PINMUX_DATA(KEYIN2_MARK, HIZA14_KEYSC, KEYIN2),
777 PINMUX_DATA(KEYIN3_MARK, HIZA14_KEYSC, KEYIN3),
778 PINMUX_DATA(KEYIN4_MARK, PSA14_KEYIN4, HIZC15_IRQ7, KEYIN4_IRQ7),
779 PINMUX_DATA(KEYOUT0_MARK, HIZA14_KEYSC, KEYOUT0),
780 PINMUX_DATA(KEYOUT1_MARK, HIZA14_KEYSC, KEYOUT1),
781 PINMUX_DATA(KEYOUT2_MARK, HIZA14_KEYSC, KEYOUT2),
782 PINMUX_DATA(KEYOUT3_MARK, HIZA14_KEYSC, KEYOUT3),
783 PINMUX_DATA(KEYOUT4_IN6_MARK, HIZA14_KEYSC, KEYOUT4_IN6),
784 PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5),
785};
786
787static struct pinmux_gpio pinmux_gpios[] = {
788 /* PTA */
789 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
790 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
791 PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
792 PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
793 PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
794 PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
795 PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
796 PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
797
798 /* PTB */
799 PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
800 PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
801 PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
802 PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
803 PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
804 PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
805 PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
806 PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
807
808 /* PTC */
809 PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
810 PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
811 PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
812 PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
813 PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
814 PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
815
816 /* PTD */
817 PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
818 PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
819 PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
820 PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
821 PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
822 PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
823 PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
824 PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
825
826 /* PTE */
827 PINMUX_GPIO(GPIO_PTE7, PTE7_DATA),
828 PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
829 PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
830 PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
831 PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
832 PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
833
834 /* PTF */
835 PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
836 PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
837 PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
838 PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
839 PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
840 PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
841 PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
842
843 /* PTG */
844 PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
845 PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
846 PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
847 PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
848 PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
849
850 /* PTH */
851 PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
852 PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
853 PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
854 PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
855 PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
856 PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
857 PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
858 PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
859
860 /* PTJ */
861 PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
862 PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
863 PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
864 PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
865 PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
866
867 /* PTK */
868 PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
869 PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
870 PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
871 PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
872 PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
873 PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
874 PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
875
876 /* PTL */
877 PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
878 PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
879 PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
880 PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
881 PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
882 PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
883 PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
884 PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
885
886 /* PTM */
887 PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
888 PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
889 PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
890 PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
891 PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
892 PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
893 PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
894 PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
895
896 /* PTN */
897 PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
898 PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
899 PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
900 PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
901 PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
902 PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
903 PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
904 PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
905
906 /* PTQ */
907 PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA),
908 PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA),
909 PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA),
910 PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
911 PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
912 PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
913 PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
914
915 /* PTR */
916 PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
917 PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
918 PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
919 PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
920 PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
921
922 /* PTS */
923 PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
924 PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
925 PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
926 PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
927 PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
928
929 /* PTT */
930 PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
931 PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
932 PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
933 PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
934 PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
935
936 /* PTU */
937 PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
938 PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
939 PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
940 PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
941 PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
942
943 /* PTV */
944 PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
945 PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
946 PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
947 PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
948 PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
949
950 /* PTW */
951 PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
952 PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
953 PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
954 PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
955 PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
956 PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
957 PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
958
959 /* PTX */
960 PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
961 PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
962 PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
963 PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
964 PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
965 PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
966 PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
967
968 /* PTY */
969 PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
970 PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
971 PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
972 PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
973 PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
974 PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
975
976 /* PTZ */
977 PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
978 PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
979 PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
980 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
981 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
982
983 /* SCIF0 */
984 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
985 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
986 PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
987 PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
988 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
989
990 /* SCIF1 */
991 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
992 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
993 PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK),
994 PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK),
995 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
996
997 /* SCIF2 */
998 PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK),
999 PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK),
1000 PINMUX_GPIO(GPIO_FN_SCIF2_RTS, SCIF2_RTS_MARK),
1001 PINMUX_GPIO(GPIO_FN_SCIF2_CTS, SCIF2_CTS_MARK),
1002 PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK),
1003
1004 /* SIO */
1005 PINMUX_GPIO(GPIO_FN_SIOTXD, SIOTXD_MARK),
1006 PINMUX_GPIO(GPIO_FN_SIORXD, SIORXD_MARK),
1007 PINMUX_GPIO(GPIO_FN_SIOD, SIOD_MARK),
1008 PINMUX_GPIO(GPIO_FN_SIOSTRB0, SIOSTRB0_MARK),
1009 PINMUX_GPIO(GPIO_FN_SIOSTRB1, SIOSTRB1_MARK),
1010 PINMUX_GPIO(GPIO_FN_SIOSCK, SIOSCK_MARK),
1011 PINMUX_GPIO(GPIO_FN_SIOMCK, SIOMCK_MARK),
1012
1013 /* CEU */
1014 PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK),
1015 PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK),
1016 PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK),
1017 PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK),
1018 PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK),
1019 PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK),
1020 PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK),
1021 PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK),
1022 PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK),
1023 PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK),
1024 PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK),
1025 PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK),
1026 PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK),
1027 PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK),
1028 PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK),
1029 PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK),
1030 PINMUX_GPIO(GPIO_FN_VIO_CLK, VIO_CLK_MARK),
1031 PINMUX_GPIO(GPIO_FN_VIO_VD, VIO_VD_MARK),
1032 PINMUX_GPIO(GPIO_FN_VIO_HD, VIO_HD_MARK),
1033 PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK),
1034 PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK),
1035 PINMUX_GPIO(GPIO_FN_VIO_STEX, VIO_STEX_MARK),
1036 PINMUX_GPIO(GPIO_FN_VIO_STEM, VIO_STEM_MARK),
1037 PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK),
1038 PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK),
1039 PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK),
1040
1041 /* LCDC */
1042 PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK),
1043 PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK),
1044 PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK),
1045 PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK),
1046 PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK),
1047 PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK),
1048 PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK),
1049 PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK),
1050 PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK),
1051 PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK),
1052 PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK),
1053 PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK),
1054 PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK),
1055 PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK),
1056 PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK),
1057 PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK),
1058 PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK),
1059 PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK),
1060 PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK),
1061 PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK),
1062 PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK),
1063 PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK),
1064 PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK),
1065 PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK),
1066 PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK),
1067 /* Main LCD */
1068 PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK),
1069 PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK),
1070 PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK),
1071 PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK),
1072 /* Main LCD - RGB Mode */
1073 PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK),
1074 PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK),
1075 PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK),
1076 /* Main LCD - SYS Mode */
1077 PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK),
1078 PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK),
1079 PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK),
1080 PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK),
1081 /* Sub LCD - SYS Mode */
1082 PINMUX_GPIO(GPIO_FN_LCDDON2, LCDDON2_MARK),
1083 PINMUX_GPIO(GPIO_FN_LCDVCPWC2, LCDVCPWC2_MARK),
1084 PINMUX_GPIO(GPIO_FN_LCDVEPWC2, LCDVEPWC2_MARK),
1085 PINMUX_GPIO(GPIO_FN_LCDVSYN2, LCDVSYN2_MARK),
1086 PINMUX_GPIO(GPIO_FN_LCDCS2, LCDCS2_MARK),
1087
1088 /* BSC */
1089 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
1090 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1091 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1092 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
1093 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
1094 PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
1095 PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
1096 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
1097 PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK),
1098
1099 /* SBSC */
1100 PINMUX_GPIO(GPIO_FN_HPD63, HPD63_MARK),
1101 PINMUX_GPIO(GPIO_FN_HPD62, HPD62_MARK),
1102 PINMUX_GPIO(GPIO_FN_HPD61, HPD61_MARK),
1103 PINMUX_GPIO(GPIO_FN_HPD60, HPD60_MARK),
1104 PINMUX_GPIO(GPIO_FN_HPD59, HPD59_MARK),
1105 PINMUX_GPIO(GPIO_FN_HPD58, HPD58_MARK),
1106 PINMUX_GPIO(GPIO_FN_HPD57, HPD57_MARK),
1107 PINMUX_GPIO(GPIO_FN_HPD56, HPD56_MARK),
1108 PINMUX_GPIO(GPIO_FN_HPD55, HPD55_MARK),
1109 PINMUX_GPIO(GPIO_FN_HPD54, HPD54_MARK),
1110 PINMUX_GPIO(GPIO_FN_HPD53, HPD53_MARK),
1111 PINMUX_GPIO(GPIO_FN_HPD52, HPD52_MARK),
1112 PINMUX_GPIO(GPIO_FN_HPD51, HPD51_MARK),
1113 PINMUX_GPIO(GPIO_FN_HPD50, HPD50_MARK),
1114 PINMUX_GPIO(GPIO_FN_HPD49, HPD49_MARK),
1115 PINMUX_GPIO(GPIO_FN_HPD48, HPD48_MARK),
1116 PINMUX_GPIO(GPIO_FN_HPDQM7, HPDQM7_MARK),
1117 PINMUX_GPIO(GPIO_FN_HPDQM6, HPDQM6_MARK),
1118 PINMUX_GPIO(GPIO_FN_HPDQM5, HPDQM5_MARK),
1119 PINMUX_GPIO(GPIO_FN_HPDQM4, HPDQM4_MARK),
1120
1121 /* IRQ */
1122 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
1123 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
1124 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
1125 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
1126 PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
1127 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
1128 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
1129 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
1130
1131 /* SDHI */
1132 PINMUX_GPIO(GPIO_FN_SDHICD, SDHICD_MARK),
1133 PINMUX_GPIO(GPIO_FN_SDHIWP, SDHIWP_MARK),
1134 PINMUX_GPIO(GPIO_FN_SDHID3, SDHID3_MARK),
1135 PINMUX_GPIO(GPIO_FN_SDHID2, SDHID2_MARK),
1136 PINMUX_GPIO(GPIO_FN_SDHID1, SDHID1_MARK),
1137 PINMUX_GPIO(GPIO_FN_SDHID0, SDHID0_MARK),
1138 PINMUX_GPIO(GPIO_FN_SDHICMD, SDHICMD_MARK),
1139 PINMUX_GPIO(GPIO_FN_SDHICLK, SDHICLK_MARK),
1140
1141 /* SIU - Port A */
1142 PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK),
1143 PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK),
1144 PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK),
1145 PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK),
1146 PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK),
1147 PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK),
1148 PINMUX_GPIO(GPIO_FN_SIUMCKA, SIUMCKA_MARK),
1149 PINMUX_GPIO(GPIO_FN_SIUFCKA, SIUFCKA_MARK),
1150
1151 /* SIU - Port B */
1152 PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK),
1153 PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK),
1154 PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK),
1155 PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK),
1156 PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK),
1157 PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK),
1158 PINMUX_GPIO(GPIO_FN_SIUMCKB, SIUMCKB_MARK),
1159 PINMUX_GPIO(GPIO_FN_SIUFCKB, SIUFCKB_MARK),
1160
1161 /* AUD */
1162 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
1163 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
1164 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
1165 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
1166 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
1167
1168 /* DMAC */
1169 PINMUX_GPIO(GPIO_FN_DACK, DACK_MARK),
1170 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
1171
1172 /* VOU */
1173 PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK),
1174 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
1175 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
1176 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
1177 PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK),
1178 PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK),
1179 PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK),
1180 PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK),
1181 PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK),
1182 PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK),
1183 PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK),
1184 PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK),
1185 PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK),
1186 PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK),
1187 PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK),
1188 PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK),
1189 PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK),
1190 PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK),
1191 PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK),
1192 PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK),
1193
1194 /* CPG */
1195 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
1196 PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK),
1197
1198 /* SIOF0 */
1199 PINMUX_GPIO(GPIO_FN_SIOF0_MCK, SIOF0_MCK_MARK),
1200 PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK),
1201 PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK),
1202 PINMUX_GPIO(GPIO_FN_SIOF0_SS1, SIOF0_SS1_MARK),
1203 PINMUX_GPIO(GPIO_FN_SIOF0_SS2, SIOF0_SS2_MARK),
1204 PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK),
1205 PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK),
1206
1207 /* SIOF1 */
1208 PINMUX_GPIO(GPIO_FN_SIOF1_MCK, SIOF1_MCK_MARK),
1209 PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK),
1210 PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK),
1211 PINMUX_GPIO(GPIO_FN_SIOF1_SS1, SIOF1_SS1_MARK),
1212 PINMUX_GPIO(GPIO_FN_SIOF1_SS2, SIOF1_SS2_MARK),
1213 PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK),
1214 PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK),
1215
1216 /* SIM */
1217 PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
1218 PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
1219 PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
1220
1221 /* TSIF */
1222 PINMUX_GPIO(GPIO_FN_TS_SDAT, TS_SDAT_MARK),
1223 PINMUX_GPIO(GPIO_FN_TS_SCK, TS_SCK_MARK),
1224 PINMUX_GPIO(GPIO_FN_TS_SDEN, TS_SDEN_MARK),
1225 PINMUX_GPIO(GPIO_FN_TS_SPSYNC, TS_SPSYNC_MARK),
1226
1227 /* IRDA */
1228 PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK),
1229 PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK),
1230
1231 /* TPU */
1232 PINMUX_GPIO(GPIO_FN_TPUTO, TPUTO_MARK),
1233
1234 /* FLCTL */
1235 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
1236 PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK),
1237 PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK),
1238 PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK),
1239 PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK),
1240 PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK),
1241 PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK),
1242 PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK),
1243 PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK),
1244 PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK),
1245 PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK),
1246 PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK),
1247 PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
1248 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
1249
1250 /* KEYSC */
1251 PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK),
1252 PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK),
1253 PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK),
1254 PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK),
1255 PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK),
1256 PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK),
1257 PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK),
1258 PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK),
1259 PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK),
1260 PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK),
1261 PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK),
1262};
1263
1264static struct pinmux_cfg_reg pinmux_config_regs[] = {
1265 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1266 VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN,
1267 VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN,
1268 VIO_D5_SCIF1_TXD, PTA5_OUT, PTA5_IN_PD, PTA5_IN,
1269 VIO_D4, 0, PTA4_IN_PD, PTA4_IN,
1270 VIO_D3, 0, PTA3_IN_PD, PTA3_IN,
1271 VIO_D2, 0, PTA2_IN_PD, PTA2_IN,
1272 VIO_D1, 0, PTA1_IN_PD, PTA1_IN,
1273 VIO_D0_LCDLCLK, 0, PTA0_IN_PD, PTA0_IN }
1274 },
1275 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
1276 HPD55, PTB7_OUT, 0, PTB7_IN,
1277 HPD54, PTB6_OUT, 0, PTB6_IN,
1278 HPD53, PTB5_OUT, 0, PTB5_IN,
1279 HPD52, PTB4_OUT, 0, PTB4_IN,
1280 HPD51, PTB3_OUT, 0, PTB3_IN,
1281 HPD50, PTB2_OUT, 0, PTB2_IN,
1282 HPD49, PTB1_OUT, 0, PTB1_IN,
1283 HPD48, PTB0_OUT, 0, PTB0_IN }
1284 },
1285 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
1286 0, 0, PTC7_IN_PU, PTC7_IN,
1287 0, 0, 0, 0,
1288 IOIS16, 0, PTC5_IN_PU, PTC5_IN,
1289 HPDQM7, PTC4_OUT, 0, PTC4_IN,
1290 HPDQM6, PTC3_OUT, 0, PTC3_IN,
1291 HPDQM5, PTC2_OUT, 0, PTC2_IN,
1292 0, 0, 0, 0,
1293 HPDQM4, PTC0_OUT, 0, PTC0_IN }
1294 },
1295 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
1296 SDHICD, 0, PTD7_IN_PU, PTD7_IN,
1297 SDHIWP, PTD6_OUT, PTD6_IN_PU, PTD6_IN,
1298 SDHID3, PTD5_OUT, PTD5_IN_PU, PTD5_IN,
1299 IRQ2_SDHID2, PTD4_OUT, PTD4_IN_PU, PTD4_IN,
1300 SDHID1, PTD3_OUT, PTD3_IN_PU, PTD3_IN,
1301 SDHID0, PTD2_OUT, PTD2_IN_PU, PTD2_IN,
1302 SDHICMD, PTD1_OUT, PTD1_IN_PU, PTD1_IN,
1303 SDHICLK, PTD0_OUT, 0, 0 }
1304 },
1305 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
1306 A25, PTE7_OUT, PTE7_IN_PD, PTE7_IN,
1307 A24, PTE6_OUT, PTE6_IN_PD, PTE6_IN,
1308 A23, PTE5_OUT, PTE5_IN_PD, PTE5_IN,
1309 A22, PTE4_OUT, PTE4_IN_PD, PTE4_IN,
1310 0, 0, 0, 0,
1311 0, 0, 0, 0,
1312 IRQ5, PTE1_OUT, PTE1_IN_PD, PTE1_IN,
1313 IRQ4_BS, PTE0_OUT, PTE0_IN_PD, PTE0_IN }
1314 },
1315 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
1316 0, 0, 0, 0,
1317 PTF6, PTF6_OUT, PTF6_IN_PD, PTF6_IN,
1318 SIOSCK_SIUBOBT, PTF5_OUT, PTF5_IN_PD, PTF5_IN,
1319 SIOSTRB1_SIUBOLR, PTF4_OUT, PTF4_IN_PD, PTF4_IN,
1320 SIOSTRB0_SIUBIBT, PTF3_OUT, PTF3_IN_PD, PTF3_IN,
1321 SIOD_SIUBILR, PTF2_OUT, PTF2_IN_PD, PTF2_IN,
1322 SIORXD_SIUBISLD, 0, PTF1_IN_PD, PTF1_IN,
1323 SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 }
1324 },
1325 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
1326 0, 0, 0, 0,
1327 0, 0, 0, 0,
1328 0, 0, 0, 0,
1329 AUDSYNC, PTG4_OUT, 0, 0,
1330 AUDATA3, PTG3_OUT, 0, 0,
1331 AUDATA2, PTG2_OUT, 0, 0,
1332 AUDATA1, PTG1_OUT, 0, 0,
1333 AUDATA0, PTG0_OUT, 0, 0 }
1334 },
1335 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
1336 LCDVCPWC_LCDVCPWC2, PTH7_OUT, 0, 0,
1337 LCDVSYN2_DACK, PTH6_OUT, PTH6_IN_PD, PTH6_IN,
1338 LCDVSYN, PTH5_OUT, PTH5_IN_PD, PTH5_IN,
1339 LCDDISP_LCDRS, PTH4_OUT, 0, 0,
1340 LCDHSYN_LCDCS, PTH3_OUT, 0, 0,
1341 LCDDON_LCDDON2, PTH2_OUT, 0, 0,
1342 LCDD17_DV_HSYNC, PTH1_OUT, PTH1_IN_PD, PTH1_IN,
1343 LCDD16_DV_VSYNC, PTH0_OUT, PTH0_IN_PD, PTH0_IN }
1344 },
1345 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
1346 STATUS0, PTJ7_OUT, 0, 0,
1347 0, PTJ6_OUT, 0, 0,
1348 PDSTATUS, PTJ5_OUT, 0, 0,
1349 0, 0, 0, 0,
1350 0, 0, 0, 0,
1351 0, 0, 0, 0,
1352 IRQ1, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN,
1353 IRQ0, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN }
1354 },
1355 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
1356 0, 0, 0, 0,
1357 SIUAILR_SIOF1_SS2, PTK6_OUT, PTK6_IN_PD, PTK6_IN,
1358 SIUAIBT_SIOF1_SS1, PTK5_OUT, PTK5_IN_PD, PTK5_IN,
1359 SIUAOLR_SIOF1_SYNC, PTK4_OUT, PTK4_IN_PD, PTK4_IN,
1360 SIUAOBT_SIOF1_SCK, PTK3_OUT, PTK3_IN_PD, PTK3_IN,
1361 SIUAISLD_SIOF1_RXD, 0, PTK2_IN_PD, PTK2_IN,
1362 SIUAOSLD_SIOF1_TXD, PTK1_OUT, 0, 0,
1363 PTK0, PTK0_OUT, PTK0_IN_PD, PTK0_IN }
1364 },
1365 { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
1366 LCDD15_DV_D15, PTL7_OUT, PTL7_IN_PD, PTL7_IN,
1367 LCDD14_DV_D14, PTL6_OUT, PTL6_IN_PD, PTL6_IN,
1368 LCDD13_DV_D13, PTL5_OUT, PTL5_IN_PD, PTL5_IN,
1369 LCDD12_DV_D12, PTL4_OUT, PTL4_IN_PD, PTL4_IN,
1370 LCDD11_DV_D11, PTL3_OUT, PTL3_IN_PD, PTL3_IN,
1371 LCDD10_DV_D10, PTL2_OUT, PTL2_IN_PD, PTL2_IN,
1372 LCDD9_DV_D9, PTL1_OUT, PTL1_IN_PD, PTL1_IN,
1373 LCDD8_DV_D8, PTL0_OUT, PTL0_IN_PD, PTL0_IN }
1374 },
1375 { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
1376 LCDD7_DV_D7, PTM7_OUT, PTM7_IN_PD, PTM7_IN,
1377 LCDD6_DV_D6, PTM6_OUT, PTM6_IN_PD, PTM6_IN,
1378 LCDD5_DV_D5, PTM5_OUT, PTM5_IN_PD, PTM5_IN,
1379 LCDD4_DV_D4, PTM4_OUT, PTM4_IN_PD, PTM4_IN,
1380 LCDD3_DV_D3, PTM3_OUT, PTM3_IN_PD, PTM3_IN,
1381 LCDD2_DV_D2, PTM2_OUT, PTM2_IN_PD, PTM2_IN,
1382 LCDD1_DV_D1, PTM1_OUT, PTM1_IN_PD, PTM1_IN,
1383 LCDD0_DV_D0, PTM0_OUT, PTM0_IN_PD, PTM0_IN }
1384 },
1385 { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
1386 HPD63, PTN7_OUT, 0, PTN7_IN,
1387 HPD62, PTN6_OUT, 0, PTN6_IN,
1388 HPD61, PTN5_OUT, 0, PTN5_IN,
1389 HPD60, PTN4_OUT, 0, PTN4_IN,
1390 HPD59, PTN3_OUT, 0, PTN3_IN,
1391 HPD58, PTN2_OUT, 0, PTN2_IN,
1392 HPD57, PTN1_OUT, 0, PTN1_IN,
1393 HPD56, PTN0_OUT, 0, PTN0_IN }
1394 },
1395 { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
1396 0, 0, 0, 0,
1397 SIOF0_SS2_SIM_RST, PTQ6_OUT, 0, 0,
1398 SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, PTQ5_IN_PD, PTQ5_IN,
1399 SIOF0_SYNC_TS_SDEN, PTQ4_OUT, PTQ4_IN_PD, PTQ4_IN,
1400 SIOF0_SCK_TS_SCK, PTQ3_OUT, PTQ3_IN_PD, PTQ3_IN,
1401 PTQ2, 0, PTQ2_IN_PD, PTQ2_IN,
1402 PTQ1, PTQ1_OUT, 0, 0,
1403 PTQ0, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN }
1404 },
1405 { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
1406 0, 0, 0, 0,
1407 0, 0, 0, 0,
1408 0, 0, 0, 0,
1409 LCDRD, PTR4_OUT, 0, 0,
1410 CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0,
1411 WAIT, 0, PTR2_IN_PU, PTR2_IN,
1412 LCDDCK_LCDWR, PTR1_OUT, 0, 0,
1413 LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 }
1414 },
1415 { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) {
1416 0, 0, 0, 0,
1417 0, 0, 0, 0,
1418 0, 0, 0, 0,
1419 SCIF0_CTS_SIUAISPD, 0, PTS4_IN_PD, PTS4_IN,
1420 SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0,
1421 SCIF0_SCK_TPUTO, PTS2_OUT, PTS2_IN_PD, PTS2_IN,
1422 SCIF0_RXD, 0, PTS1_IN_PD, PTS1_IN,
1423 SCIF0_TXD, PTS0_OUT, 0, 0 }
1424 },
1425 { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
1426 0, 0, 0, 0,
1427 0, 0, 0, 0,
1428 0, 0, 0, 0,
1429 FOE_VIO_VD2, PTT4_OUT, PTT4_IN_PD, PTT4_IN,
1430 FWE, PTT3_OUT, PTT3_IN_PD, PTT3_IN,
1431 FSC, PTT2_OUT, PTT2_IN_PD, PTT2_IN,
1432 DREQ0, 0, PTT1_IN_PD, PTT1_IN,
1433 FCDE, PTT0_OUT, 0, 0 }
1434 },
1435 { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
1436 0, 0, 0, 0,
1437 0, 0, 0, 0,
1438 0, 0, 0, 0,
1439 NAF2_VIO_D10, PTU4_OUT, PTU4_IN_PD, PTU4_IN,
1440 NAF1_VIO_D9, PTU3_OUT, PTU3_IN_PD, PTU3_IN,
1441 NAF0_VIO_D8, PTU2_OUT, PTU2_IN_PD, PTU2_IN,
1442 FRB_VIO_CLK2, 0, PTU1_IN_PD, PTU1_IN,
1443 FCE_VIO_HD2, PTU0_OUT, PTU0_IN_PD, PTU0_IN }
1444 },
1445 { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
1446 0, 0, 0, 0,
1447 0, 0, 0, 0,
1448 0, 0, 0, 0,
1449 NAF7_VIO_D15, PTV4_OUT, PTV4_IN_PD, PTV4_IN,
1450 NAF6_VIO_D14, PTV3_OUT, PTV3_IN_PD, PTV3_IN,
1451 NAF5_VIO_D13, PTV2_OUT, PTV2_IN_PD, PTV2_IN,
1452 NAF4_VIO_D12, PTV1_OUT, PTV1_IN_PD, PTV1_IN,
1453 NAF3_VIO_D11, PTV0_OUT, PTV0_IN_PD, PTV0_IN }
1454 },
1455 { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
1456 0, 0, 0, 0,
1457 VIO_FLD_SCIF2_CTS, 0, PTW6_IN_PD, PTW6_IN,
1458 VIO_CKO_SCIF2_RTS, PTW5_OUT, 0, 0,
1459 VIO_STEX_SCIF2_SCK, PTW4_OUT, PTW4_IN_PD, PTW4_IN,
1460 VIO_STEM_SCIF2_TXD, PTW3_OUT, PTW3_IN_PD, PTW3_IN,
1461 VIO_HD_SCIF2_RXD, PTW2_OUT, PTW2_IN_PD, PTW2_IN,
1462 VIO_VD_SCIF1_CTS, PTW1_OUT, PTW1_IN_PD, PTW1_IN,
1463 VIO_CLK_SCIF1_RTS, PTW0_OUT, PTW0_IN_PD, PTW0_IN }
1464 },
1465 { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
1466 0, 0, 0, 0,
1467 CS6A_CE2B, PTX6_OUT, PTX6_IN_PU, PTX6_IN,
1468 LCDD23, PTX5_OUT, PTX5_IN_PD, PTX5_IN,
1469 LCDD22, PTX4_OUT, PTX4_IN_PD, PTX4_IN,
1470 LCDD21, PTX3_OUT, PTX3_IN_PD, PTX3_IN,
1471 LCDD20, PTX2_OUT, PTX2_IN_PD, PTX2_IN,
1472 LCDD19_DV_CLKI, PTX1_OUT, PTX1_IN_PD, PTX1_IN,
1473 LCDD18_DV_CLK, PTX0_OUT, PTX0_IN_PD, PTX0_IN }
1474 },
1475 { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
1476 0, 0, 0, 0,
1477 0, 0, 0, 0,
1478 KEYOUT5_IN5, PTY5_OUT, PTY5_IN_PU, PTY5_IN,
1479 KEYOUT4_IN6, PTY4_OUT, PTY4_IN_PU, PTY4_IN,
1480 KEYOUT3, PTY3_OUT, PTY3_IN_PU, PTY3_IN,
1481 KEYOUT2, PTY2_OUT, PTY2_IN_PU, PTY2_IN,
1482 KEYOUT1, PTY1_OUT, 0, 0,
1483 KEYOUT0, PTY0_OUT, PTY0_IN_PU, PTY0_IN }
1484 },
1485 { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
1486 0, 0, 0, 0,
1487 0, 0, 0, 0,
1488 KEYIN4_IRQ7, 0, PTZ5_IN_PU, PTZ5_IN,
1489 KEYIN3, 0, PTZ4_IN_PU, PTZ4_IN,
1490 KEYIN2, 0, PTZ3_IN_PU, PTZ3_IN,
1491 KEYIN1, 0, PTZ2_IN_PU, PTZ2_IN,
1492 KEYIN0_IRQ6, 0, PTZ1_IN_PU, PTZ1_IN,
1493 0, 0, 0, 0 }
1494 },
1495 { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) {
1496 PSA15_KEYIN0, PSA15_IRQ6,
1497 PSA14_KEYIN4, PSA14_IRQ7,
1498 0, 0,
1499 0, 0,
1500 0, 0,
1501 0, 0,
1502 PSA9_IRQ4, PSA9_BS,
1503 0, 0,
1504 0, 0,
1505 0, 0,
1506 0, 0,
1507 PSA4_IRQ2, PSA4_SDHID2,
1508 0, 0,
1509 0, 0,
1510 0, 0,
1511 0, 0 }
1512 },
1513 { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) {
1514 PSB15_SIOTXD, PSB15_SIUBOSLD,
1515 PSB14_SIORXD, PSB14_SIUBISLD,
1516 PSB13_SIOD, PSB13_SIUBILR,
1517 PSB12_SIOSTRB0, PSB12_SIUBIBT,
1518 PSB11_SIOSTRB1, PSB11_SIUBOLR,
1519 PSB10_SIOSCK, PSB10_SIUBOBT,
1520 PSB9_SIOMCK, PSB9_SIUMCKB,
1521 PSB8_SIOF0_MCK, PSB8_IRQ3,
1522 PSB7_SIOF0_TXD, PSB7_IRDA_OUT,
1523 PSB6_SIOF0_RXD, PSB6_IRDA_IN,
1524 PSB5_SIOF0_SCK, PSB5_TS_SCK,
1525 PSB4_SIOF0_SYNC, PSB4_TS_SDEN,
1526 PSB3_SIOF0_SS1, PSB3_TS_SPSYNC,
1527 PSB2_SIOF0_SS2, PSB2_SIM_RST,
1528 PSB1_SIUMCKA, PSB1_SIOF1_MCK,
1529 PSB0_SIUAOSLD, PSB0_SIOF1_TXD }
1530 },
1531 { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) {
1532 PSC15_SIUAISLD, PSC15_SIOF1_RXD,
1533 PSC14_SIUAOBT, PSC14_SIOF1_SCK,
1534 PSC13_SIUAOLR, PSC13_SIOF1_SYNC,
1535 PSC12_SIUAIBT, PSC12_SIOF1_SS1,
1536 PSC11_SIUAILR, PSC11_SIOF1_SS2,
1537 0, 0,
1538 0, 0,
1539 0, 0,
1540 0, 0,
1541 0, 0,
1542 0, 0,
1543 0, 0,
1544 0, 0,
1545 0, 0,
1546 0, 0,
1547 PSC0_NAF, PSC0_VIO }
1548 },
1549 { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) {
1550 0, 0,
1551 0, 0,
1552 PSD13_VIO, PSD13_SCIF2,
1553 PSD12_VIO, PSD12_SCIF1,
1554 PSD11_VIO, PSD11_SCIF1,
1555 PSD10_VIO_D0, PSD10_LCDLCLK,
1556 PSD9_SIOMCK_SIUMCKB, PSD9_SIUFCKB,
1557 PSD8_SCIF0_SCK, PSD8_TPUTO,
1558 PSD7_SCIF0_RTS, PSD7_SIUAOSPD,
1559 PSD6_SCIF0_CTS, PSD6_SIUAISPD,
1560 PSD5_CS6B_CE1B, PSD5_LCDCS2,
1561 0, 0,
1562 PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2,
1563 PSD2_LCDDON, PSD2_LCDDON2,
1564 0, 0,
1565 PSD0_LCDD19_LCDD0, PSD0_DV }
1566 },
1567 { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) {
1568 PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D,
1569 PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK,
1570 PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT,
1571 PSE12_LCDVSYN2, PSE12_DACK,
1572 PSE11_SIUMCKA_SIOF1_MCK, PSE11_SIUFCKA,
1573 0, 0,
1574 0, 0,
1575 0, 0,
1576 0, 0,
1577 0, 0,
1578 0, 0,
1579 0, 0,
1580 PSE3_FLCTL, PSE3_VIO,
1581 PSE2_NAF2, PSE2_VIO_D10,
1582 PSE1_NAF1, PSE1_VIO_D9,
1583 PSE0_NAF0, PSE0_VIO_D8 }
1584 },
1585 { PINMUX_CFG_REG("HIZCRA", 0xa4050158, 16, 1) {
1586 0, 0,
1587 HIZA14_KEYSC, HIZA14_HIZ,
1588 0, 0,
1589 0, 0,
1590 0, 0,
1591 HIZA10_NAF, HIZA10_HIZ,
1592 HIZA9_VIO, HIZA9_HIZ,
1593 HIZA8_LCDC, HIZA8_HIZ,
1594 HIZA7_LCDC, HIZA7_HIZ,
1595 HIZA6_LCDC, HIZA6_HIZ,
1596 0, 0,
1597 0, 0,
1598 0, 0,
1599 0, 0,
1600 0, 0,
1601 0, 0 }
1602 },
1603 { PINMUX_CFG_REG("HIZCRB", 0xa405015a, 16, 1) {
1604 0, 0,
1605 0, 0,
1606 0, 0,
1607 0, 0,
1608 0, 0,
1609 0, 0,
1610 0, 0,
1611 0, 0,
1612 0, 0,
1613 0, 0,
1614 0, 0,
1615 0, 0,
1616 0, 0,
1617 0, 0,
1618 HIZB1_VIO, HIZB1_HIZ,
1619 HIZB0_VIO, HIZB0_HIZ }
1620 },
1621 { PINMUX_CFG_REG("HIZCRC", 0xa405015c, 16, 1) {
1622 HIZC15_IRQ7, HIZC15_HIZ,
1623 HIZC14_IRQ6, HIZC14_HIZ,
1624 HIZC13_IRQ5, HIZC13_HIZ,
1625 HIZC12_IRQ4, HIZC12_HIZ,
1626 HIZC11_IRQ3, HIZC11_HIZ,
1627 HIZC10_IRQ2, HIZC10_HIZ,
1628 HIZC9_IRQ1, HIZC9_HIZ,
1629 HIZC8_IRQ0, HIZC8_HIZ,
1630 0, 0,
1631 0, 0,
1632 0, 0,
1633 0, 0,
1634 0, 0,
1635 0, 0,
1636 0, 0,
1637 0, 0 }
1638 },
1639 { PINMUX_CFG_REG("MSELCRB", 0xa4050182, 16, 1) {
1640 0, 0,
1641 0, 0,
1642 0, 0,
1643 0, 0,
1644 0, 0,
1645 0, 0,
1646 MSELB9_VIO, MSELB9_VIO2,
1647 MSELB8_RGB, MSELB8_SYS,
1648 0, 0,
1649 0, 0,
1650 0, 0,
1651 0, 0,
1652 0, 0,
1653 0, 0,
1654 0, 0,
1655 0, 0 }
1656 },
1657 {}
1658};
1659
1660static struct pinmux_data_reg pinmux_data_regs[] = {
1661 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
1662 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
1663 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
1664 },
1665 { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
1666 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
1667 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
1668 },
1669 { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
1670 PTC7_DATA, 0, PTC5_DATA, PTC4_DATA,
1671 PTC3_DATA, PTC2_DATA, 0, PTC0_DATA }
1672 },
1673 { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
1674 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
1675 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
1676 },
1677 { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
1678 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
1679 0, 0, PTE1_DATA, PTE0_DATA }
1680 },
1681 { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
1682 0, PTF6_DATA, PTF5_DATA, PTF4_DATA,
1683 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
1684 },
1685 { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
1686 0, 0, 0, PTG4_DATA,
1687 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
1688 },
1689 { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
1690 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
1691 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
1692 },
1693 { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
1694 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
1695 0, 0, PTJ1_DATA, PTJ0_DATA }
1696 },
1697 { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
1698 0, PTK6_DATA, PTK5_DATA, PTK4_DATA,
1699 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
1700 },
1701 { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
1702 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
1703 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
1704 },
1705 { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
1706 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
1707 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
1708 },
1709 { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
1710 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
1711 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
1712 },
1713 { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
1714 0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
1715 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
1716 },
1717 { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
1718 0, 0, 0, PTR4_DATA,
1719 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
1720 },
1721 { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
1722 0, 0, 0, PTS4_DATA,
1723 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
1724 },
1725 { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
1726 0, 0, 0, PTT4_DATA,
1727 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
1728 },
1729 { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
1730 0, 0, 0, PTU4_DATA,
1731 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
1732 },
1733 { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
1734 0, 0, 0, PTV4_DATA,
1735 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
1736 },
1737 { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
1738 0, PTW6_DATA, PTW5_DATA, PTW4_DATA,
1739 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
1740 },
1741 { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
1742 0, PTX6_DATA, PTX5_DATA, PTX4_DATA,
1743 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
1744 },
1745 { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
1746 0, PTY6_DATA, PTY5_DATA, PTY4_DATA,
1747 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
1748 },
1749 { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
1750 0, 0, PTZ5_DATA, PTZ4_DATA,
1751 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
1752 },
1753 { },
1754};
1755
1756static struct pinmux_info sh7722_pinmux_info = {
1757 .name = "sh7722_pfc",
1758 .reserved_id = PINMUX_RESERVED,
1759 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1760 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1761 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
1762 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1763 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1764 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1765 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1766
1767 .first_gpio = GPIO_PTA7,
1768 .last_gpio = GPIO_FN_KEYOUT5_IN5,
1769
1770 .gpios = pinmux_gpios,
1771 .cfg_regs = pinmux_config_regs,
1772 .data_regs = pinmux_data_regs,
1773
1774 .gpio_data = pinmux_data,
1775 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1776};
1777
1778static int __init plat_pinmux_setup(void)
1779{
1780 return register_pinmux(&sh7722_pinmux_info);
1781}
1782
1783arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
new file mode 100644
index 000000000000..88bf5ecda849
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
@@ -0,0 +1,1909 @@
1/*
2 * SH7723 Pinmux
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/gpio.h>
14#include <cpu/sh7723.h>
15
16enum {
17 PINMUX_RESERVED = 0,
18
19 PINMUX_DATA_BEGIN,
20 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
21 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
22 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
23 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
24 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
25 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
26 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
27 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
28 PTE5_DATA, PTE4_DATA, PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
29 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
30 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
31 PTG5_DATA, PTG4_DATA, PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
32 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
33 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
34 PTJ7_DATA, PTJ5_DATA, PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
35 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
36 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
37 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
38 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
39 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
40 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
41 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
42 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
43 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
44 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
45 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
46 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
47 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
48 PTT5_DATA, PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
49 PTU5_DATA, PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
50 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
51 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
52 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
53 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
54 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
55 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
56 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
57 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
58 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
59 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
60 PINMUX_DATA_END,
61
62 PINMUX_INPUT_BEGIN,
63 PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
64 PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
65 PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
66 PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
67 PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
68 PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
69 PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
70 PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
71 PTE5_IN, PTE4_IN, PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
72 PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
73 PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
74 PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
75 PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
76 PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
77 PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
78 PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
79 PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
80 PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
81 PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
82 PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
83 PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
84 PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
85 PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
86 PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
87 PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
88 PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN,
89 PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
90 PTT5_IN, PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
91 PTU5_IN, PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
92 PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
93 PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
94 PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
95 PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
96 PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
97 PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
98 PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
99 PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
100 PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
101 PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
102 PINMUX_INPUT_END,
103
104 PINMUX_INPUT_PULLUP_BEGIN,
105 PTA4_IN_PU, PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
106 PTB2_IN_PU, PTB1_IN_PU,
107 PTR2_IN_PU,
108 PINMUX_INPUT_PULLUP_END,
109
110 PINMUX_OUTPUT_BEGIN,
111 PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
112 PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
113 PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
114 PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
115 PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
116 PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
117 PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
118 PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
119 PTE5_OUT, PTE4_OUT, PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
120 PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
121 PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
122 PTG5_OUT, PTG4_OUT, PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
123 PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
124 PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
125 PTJ7_OUT, PTJ5_OUT, PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
126 PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
127 PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
128 PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
129 PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
130 PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
131 PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
132 PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
133 PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
134 PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
135 PTR1_OUT, PTR0_OUT,
136 PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT,
137 PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
138 PTT5_OUT, PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
139 PTU5_OUT, PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
140 PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
141 PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
142 PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
143 PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
144 PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
145 PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
146 PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
147 PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
148 PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
149 PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
150 PINMUX_OUTPUT_END,
151
152 PINMUX_FUNCTION_BEGIN,
153 PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
154 PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
155 PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
156 PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
157 PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
158 PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
159 PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
160 PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
161 PTE5_FN, PTE4_FN, PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
162 PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
163 PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
164 PTG5_FN, PTG4_FN, PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
165 PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
166 PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
167 PTJ7_FN, PTJ5_FN, PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
168 PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
169 PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
170 PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN,
171 PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
172 PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
173 PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
174 PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN,
175 PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
176 PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
177 PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
178 PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
179 PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN,
180 PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
181 PTT5_FN, PTT4_FN, PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
182 PTU5_FN, PTU4_FN, PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
183 PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
184 PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
185 PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
186 PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
187 PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
188 PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
189 PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
190 PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
191 PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
192 PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
193
194
195 PSA15_PSA14_FN1, PSA15_PSA14_FN2,
196 PSA13_PSA12_FN1, PSA13_PSA12_FN2,
197 PSA11_PSA10_FN1, PSA11_PSA10_FN2,
198 PSA5_PSA4_FN1, PSA5_PSA4_FN2, PSA5_PSA4_FN3,
199 PSA3_PSA2_FN1, PSA3_PSA2_FN2,
200 PSB15_PSB14_FN1, PSB15_PSB14_FN2,
201 PSB13_PSB12_LCDC_RGB, PSB13_PSB12_LCDC_SYS,
202 PSB9_PSB8_FN1, PSB9_PSB8_FN2, PSB9_PSB8_FN3,
203 PSB7_PSB6_FN1, PSB7_PSB6_FN2,
204 PSB5_PSB4_FN1, PSB5_PSB4_FN2,
205 PSB3_PSB2_FN1, PSB3_PSB2_FN2,
206 PSC15_PSC14_FN1, PSC15_PSC14_FN2,
207 PSC13_PSC12_FN1, PSC13_PSC12_FN2,
208 PSC11_PSC10_FN1, PSC11_PSC10_FN2, PSC11_PSC10_FN3,
209 PSC9_PSC8_FN1, PSC9_PSC8_FN2,
210 PSC7_PSC6_FN1, PSC7_PSC6_FN2, PSC7_PSC6_FN3,
211 PSD15_PSD14_FN1, PSD15_PSD14_FN2,
212 PSD13_PSD12_FN1, PSD13_PSD12_FN2,
213 PSD11_PSD10_FN1, PSD11_PSD10_FN2, PSD11_PSD10_FN3,
214 PSD9_PSD8_FN1, PSD9_PSD8_FN2,
215 PSD7_PSD6_FN1, PSD7_PSD6_FN2,
216 PSD5_PSD4_FN1, PSD5_PSD4_FN2,
217 PSD3_PSD2_FN1, PSD3_PSD2_FN2,
218 PSD1_PSD0_FN1, PSD1_PSD0_FN2,
219 PINMUX_FUNCTION_END,
220
221 PINMUX_MARK_BEGIN,
222 SCIF0_PTT_TXD_MARK, SCIF0_PTT_RXD_MARK,
223 SCIF0_PTT_SCK_MARK, SCIF0_PTU_TXD_MARK,
224 SCIF0_PTU_RXD_MARK, SCIF0_PTU_SCK_MARK,
225
226 SCIF1_PTS_TXD_MARK, SCIF1_PTS_RXD_MARK,
227 SCIF1_PTS_SCK_MARK, SCIF1_PTV_TXD_MARK,
228 SCIF1_PTV_RXD_MARK, SCIF1_PTV_SCK_MARK,
229
230 SCIF2_PTT_TXD_MARK, SCIF2_PTT_RXD_MARK,
231 SCIF2_PTT_SCK_MARK, SCIF2_PTU_TXD_MARK,
232 SCIF2_PTU_RXD_MARK, SCIF2_PTU_SCK_MARK,
233
234 SCIF3_PTS_TXD_MARK, SCIF3_PTS_RXD_MARK,
235 SCIF3_PTS_SCK_MARK, SCIF3_PTS_RTS_MARK,
236 SCIF3_PTS_CTS_MARK, SCIF3_PTV_TXD_MARK,
237 SCIF3_PTV_RXD_MARK, SCIF3_PTV_SCK_MARK,
238 SCIF3_PTV_RTS_MARK, SCIF3_PTV_CTS_MARK,
239
240 SCIF4_PTE_TXD_MARK, SCIF4_PTE_RXD_MARK,
241 SCIF4_PTE_SCK_MARK, SCIF4_PTN_TXD_MARK,
242 SCIF4_PTN_RXD_MARK, SCIF4_PTN_SCK_MARK,
243
244 SCIF5_PTE_TXD_MARK, SCIF5_PTE_RXD_MARK,
245 SCIF5_PTE_SCK_MARK, SCIF5_PTN_TXD_MARK,
246 SCIF5_PTN_RXD_MARK, SCIF5_PTN_SCK_MARK,
247
248 VIO_D15_MARK, VIO_D14_MARK, VIO_D13_MARK, VIO_D12_MARK,
249 VIO_D11_MARK, VIO_D10_MARK, VIO_D9_MARK, VIO_D8_MARK,
250 VIO_D7_MARK, VIO_D6_MARK, VIO_D5_MARK, VIO_D4_MARK,
251 VIO_D3_MARK, VIO_D2_MARK, VIO_D1_MARK, VIO_D0_MARK,
252 VIO_FLD_MARK, VIO_CKO_MARK,
253 VIO_VD1_MARK, VIO_HD1_MARK, VIO_CLK1_MARK,
254 VIO_HD2_MARK, VIO_VD2_MARK, VIO_CLK2_MARK,
255
256 LCDD23_MARK, LCDD22_MARK, LCDD21_MARK, LCDD20_MARK,
257 LCDD19_MARK, LCDD18_MARK, LCDD17_MARK, LCDD16_MARK,
258 LCDD15_MARK, LCDD14_MARK, LCDD13_MARK, LCDD12_MARK,
259 LCDD11_MARK, LCDD10_MARK, LCDD9_MARK, LCDD8_MARK,
260 LCDD7_MARK, LCDD6_MARK, LCDD5_MARK, LCDD4_MARK,
261 LCDD3_MARK, LCDD2_MARK, LCDD1_MARK, LCDD0_MARK,
262 LCDDON_MARK, LCDVCPWC_MARK, LCDVEPWC_MARK,
263 LCDVSYN_MARK, LCDDCK_MARK, LCDHSYN_MARK, LCDDISP_MARK,
264 LCDRS_MARK, LCDCS_MARK, LCDWR_MARK, LCDRD_MARK,
265 LCDLCLK_PTR_MARK, LCDLCLK_PTW_MARK,
266
267 IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK,
268 IRQ4_MARK, IRQ5_MARK, IRQ6_MARK, IRQ7_MARK,
269
270 AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK,
271 AUDCK_MARK, AUDSYNC_MARK,
272
273 SDHI0CD_PTD_MARK, SDHI0WP_PTD_MARK,
274 SDHI0D3_PTD_MARK, SDHI0D2_PTD_MARK,
275 SDHI0D1_PTD_MARK, SDHI0D0_PTD_MARK,
276 SDHI0CMD_PTD_MARK, SDHI0CLK_PTD_MARK,
277
278 SDHI0CD_PTS_MARK, SDHI0WP_PTS_MARK,
279 SDHI0D3_PTS_MARK, SDHI0D2_PTS_MARK,
280 SDHI0D1_PTS_MARK, SDHI0D0_PTS_MARK,
281 SDHI0CMD_PTS_MARK, SDHI0CLK_PTS_MARK,
282
283 SDHI1CD_MARK, SDHI1WP_MARK, SDHI1D3_MARK, SDHI1D2_MARK,
284 SDHI1D1_MARK, SDHI1D0_MARK, SDHI1CMD_MARK, SDHI1CLK_MARK,
285
286 SIUAFCK_MARK, SIUAILR_MARK, SIUAIBT_MARK, SIUAISLD_MARK,
287 SIUAOLR_MARK, SIUAOBT_MARK, SIUAOSLD_MARK, SIUAMCK_MARK,
288 SIUAISPD_MARK, SIUAOSPD_MARK,
289
290 SIUBFCK_MARK, SIUBILR_MARK, SIUBIBT_MARK, SIUBISLD_MARK,
291 SIUBOLR_MARK, SIUBOBT_MARK, SIUBOSLD_MARK, SIUBMCK_MARK,
292
293 IRDA_IN_MARK, IRDA_OUT_MARK,
294
295 DV_CLKI_MARK, DV_CLK_MARK, DV_HSYNC_MARK, DV_VSYNC_MARK,
296 DV_D15_MARK, DV_D14_MARK, DV_D13_MARK, DV_D12_MARK,
297 DV_D11_MARK, DV_D10_MARK, DV_D9_MARK, DV_D8_MARK,
298 DV_D7_MARK, DV_D6_MARK, DV_D5_MARK, DV_D4_MARK,
299 DV_D3_MARK, DV_D2_MARK, DV_D1_MARK, DV_D0_MARK,
300
301 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, KEYIN4_MARK,
302 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
303 KEYOUT4_IN6_MARK, KEYOUT5_IN5_MARK,
304
305 MSIOF0_PTF_TXD_MARK, MSIOF0_PTF_RXD_MARK, MSIOF0_PTF_MCK_MARK,
306 MSIOF0_PTF_TSYNC_MARK, MSIOF0_PTF_TSCK_MARK, MSIOF0_PTF_RSYNC_MARK,
307 MSIOF0_PTF_RSCK_MARK, MSIOF0_PTF_SS1_MARK, MSIOF0_PTF_SS2_MARK,
308
309 MSIOF0_PTT_TXD_MARK, MSIOF0_PTT_RXD_MARK, MSIOF0_PTX_MCK_MARK,
310 MSIOF0_PTT_TSYNC_MARK, MSIOF0_PTT_TSCK_MARK, MSIOF0_PTT_RSYNC_MARK,
311 MSIOF0_PTT_RSCK_MARK, MSIOF0_PTT_SS1_MARK, MSIOF0_PTT_SS2_MARK,
312
313 MSIOF1_TXD_MARK, MSIOF1_RXD_MARK, MSIOF1_MCK_MARK,
314 MSIOF1_TSYNC_MARK, MSIOF1_TSCK_MARK, MSIOF1_RSYNC_MARK,
315 MSIOF1_RSCK_MARK, MSIOF1_SS1_MARK, MSIOF1_SS2_MARK,
316
317 TS0_SDAT_MARK, TS0_SCK_MARK, TS0_SDEN_MARK, TS0_SPSYNC_MARK,
318
319 FCE_MARK, NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK,
320 NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK, FCDE_MARK,
321 FOE_MARK, FSC_MARK, FWE_MARK, FRB_MARK,
322
323 DACK1_MARK, DREQ1_MARK, DACK0_MARK, DREQ0_MARK,
324
325 AN3_MARK, AN2_MARK, AN1_MARK, AN0_MARK, ADTRG_MARK,
326
327 STATUS0_MARK, PDSTATUS_MARK,
328
329 TPUTO3_MARK, TPUTO2_MARK, TPUTO1_MARK, TPUTO0_MARK,
330
331 D31_MARK, D30_MARK, D29_MARK, D28_MARK,
332 D27_MARK, D26_MARK, D25_MARK, D24_MARK,
333 D23_MARK, D22_MARK, D21_MARK, D20_MARK,
334 D19_MARK, D18_MARK, D17_MARK, D16_MARK,
335 IOIS16_MARK, WAIT_MARK, BS_MARK,
336 A25_MARK, A24_MARK, A23_MARK, A22_MARK,
337 CS6B_CE1B_MARK, CS6A_CE2B_MARK,
338 CS5B_CE1A_MARK, CS5A_CE2A_MARK,
339 WE3_ICIOWR_MARK, WE2_ICIORD_MARK,
340
341 IDED15_MARK, IDED14_MARK, IDED13_MARK, IDED12_MARK,
342 IDED11_MARK, IDED10_MARK, IDED9_MARK, IDED8_MARK,
343 IDED7_MARK, IDED6_MARK, IDED5_MARK, IDED4_MARK,
344 IDED3_MARK, IDED2_MARK, IDED1_MARK, IDED0_MARK,
345 DIRECTION_MARK, EXBUF_ENB_MARK, IDERST_MARK, IODACK_MARK,
346 IODREQ_MARK, IDEIORDY_MARK, IDEINT_MARK, IDEIOWR_MARK,
347 IDEIORD_MARK, IDECS1_MARK, IDECS0_MARK, IDEA2_MARK,
348 IDEA1_MARK, IDEA0_MARK,
349 PINMUX_MARK_END,
350};
351
352static pinmux_enum_t pinmux_data[] = {
353 /* PTA GPIO */
354 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
355 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
356 PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
357 PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU),
358 PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU),
359 PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU),
360 PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU),
361 PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU),
362
363 /* PTB GPIO */
364 PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
365 PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
366 PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
367 PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
368 PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
369 PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU),
370 PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU),
371 PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
372
373 /* PTC GPIO */
374 PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT),
375 PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT),
376 PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT),
377 PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
378 PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
379 PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
380 PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT),
381 PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
382
383 /* PTD GPIO */
384 PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT),
385 PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT),
386 PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT),
387 PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT),
388 PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT),
389 PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT),
390 PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT),
391 PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
392
393 /* PTE GPIO */
394 PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT),
395 PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
396 PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
397 PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT),
398 PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT),
399 PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT),
400
401 /* PTF GPIO */
402 PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT),
403 PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT),
404 PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT),
405 PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT),
406 PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT),
407 PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT),
408 PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT),
409 PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT),
410
411 /* PTG GPIO */
412 PINMUX_DATA(PTG5_DATA, PTG5_OUT),
413 PINMUX_DATA(PTG4_DATA, PTG4_OUT),
414 PINMUX_DATA(PTG3_DATA, PTG3_OUT),
415 PINMUX_DATA(PTG2_DATA, PTG2_OUT),
416 PINMUX_DATA(PTG1_DATA, PTG1_OUT),
417 PINMUX_DATA(PTG0_DATA, PTG0_OUT),
418
419 /* PTH GPIO */
420 PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT),
421 PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT),
422 PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT),
423 PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT),
424 PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT),
425 PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT),
426 PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT),
427 PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT),
428
429 /* PTJ GPIO */
430 PINMUX_DATA(PTJ7_DATA, PTJ7_OUT),
431 PINMUX_DATA(PTJ5_DATA, PTJ5_OUT),
432 PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT),
433 PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT),
434 PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT),
435 PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT),
436
437 /* PTK GPIO */
438 PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT),
439 PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT),
440 PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT),
441 PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT),
442 PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT),
443 PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT),
444 PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT),
445 PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
446
447 /* PTL GPIO */
448 PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT),
449 PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
450 PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
451 PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
452 PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT),
453 PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT),
454 PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT),
455 PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT),
456
457 /* PTM GPIO */
458 PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT),
459 PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT),
460 PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT),
461 PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT),
462 PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT),
463 PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT),
464 PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT),
465 PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
466
467 /* PTN GPIO */
468 PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT),
469 PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT),
470 PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT),
471 PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT),
472 PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT),
473 PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT),
474 PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT),
475 PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT),
476
477 /* PTQ GPIO */
478 PINMUX_DATA(PTQ3_DATA, PTQ3_IN),
479 PINMUX_DATA(PTQ2_DATA, PTQ2_IN),
480 PINMUX_DATA(PTQ1_DATA, PTQ1_IN),
481 PINMUX_DATA(PTQ0_DATA, PTQ0_IN),
482
483 /* PTR GPIO */
484 PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT),
485 PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT),
486 PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT),
487 PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT),
488 PINMUX_DATA(PTR3_DATA, PTR3_IN),
489 PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU),
490 PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT),
491 PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT),
492
493 /* PTS GPIO */
494 PINMUX_DATA(PTS7_DATA, PTS7_IN, PTS7_OUT),
495 PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT),
496 PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT),
497 PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT),
498 PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT),
499 PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT),
500 PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT),
501 PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
502
503 /* PTT GPIO */
504 PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT),
505 PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
506 PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
507 PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT),
508 PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT),
509 PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT),
510
511 /* PTU GPIO */
512 PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT),
513 PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT),
514 PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT),
515 PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT),
516 PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT),
517 PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT),
518
519 /* PTV GPIO */
520 PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT),
521 PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT),
522 PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT),
523 PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT),
524 PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT),
525 PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT),
526 PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT),
527 PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT),
528
529 /* PTW GPIO */
530 PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT),
531 PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT),
532 PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT),
533 PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT),
534 PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT),
535 PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT),
536 PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT),
537 PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT),
538
539 /* PTX GPIO */
540 PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT),
541 PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT),
542 PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT),
543 PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT),
544 PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT),
545 PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT),
546 PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT),
547 PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT),
548
549 /* PTY GPIO */
550 PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT),
551 PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT),
552 PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT),
553 PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT),
554 PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT),
555 PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT),
556 PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT),
557 PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT),
558
559 /* PTZ GPIO */
560 PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT),
561 PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT),
562 PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT),
563 PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT),
564 PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT),
565 PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT),
566 PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT),
567 PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT),
568
569 /* PTA FN */
570 PINMUX_DATA(D23_MARK, PSA15_PSA14_FN1, PTA7_FN),
571 PINMUX_DATA(KEYOUT2_MARK, PSA15_PSA14_FN2, PTA7_FN),
572 PINMUX_DATA(D22_MARK, PSA15_PSA14_FN1, PTA6_FN),
573 PINMUX_DATA(KEYOUT1_MARK, PSA15_PSA14_FN2, PTA6_FN),
574 PINMUX_DATA(D21_MARK, PSA15_PSA14_FN1, PTA5_FN),
575 PINMUX_DATA(KEYOUT0_MARK, PSA15_PSA14_FN2, PTA5_FN),
576 PINMUX_DATA(D20_MARK, PSA15_PSA14_FN1, PTA4_FN),
577 PINMUX_DATA(KEYIN4_MARK, PSA15_PSA14_FN2, PTA4_FN),
578 PINMUX_DATA(D19_MARK, PSA15_PSA14_FN1, PTA3_FN),
579 PINMUX_DATA(KEYIN3_MARK, PSA15_PSA14_FN2, PTA3_FN),
580 PINMUX_DATA(D18_MARK, PSA15_PSA14_FN1, PTA2_FN),
581 PINMUX_DATA(KEYIN2_MARK, PSA15_PSA14_FN2, PTA2_FN),
582 PINMUX_DATA(D17_MARK, PSA15_PSA14_FN1, PTA1_FN),
583 PINMUX_DATA(KEYIN1_MARK, PSA15_PSA14_FN2, PTA1_FN),
584 PINMUX_DATA(D16_MARK, PSA15_PSA14_FN1, PTA0_FN),
585 PINMUX_DATA(KEYIN0_MARK, PSA15_PSA14_FN2, PTA0_FN),
586
587 /* PTB FN */
588 PINMUX_DATA(D31_MARK, PTB7_FN),
589 PINMUX_DATA(D30_MARK, PTB6_FN),
590 PINMUX_DATA(D29_MARK, PTB5_FN),
591 PINMUX_DATA(D28_MARK, PTB4_FN),
592 PINMUX_DATA(D27_MARK, PTB3_FN),
593 PINMUX_DATA(D26_MARK, PSA15_PSA14_FN1, PTB2_FN),
594 PINMUX_DATA(KEYOUT5_IN5_MARK, PSA15_PSA14_FN2, PTB2_FN),
595 PINMUX_DATA(D25_MARK, PSA15_PSA14_FN1, PTB1_FN),
596 PINMUX_DATA(KEYOUT4_IN6_MARK, PSA15_PSA14_FN2, PTB1_FN),
597 PINMUX_DATA(D24_MARK, PSA15_PSA14_FN1, PTB0_FN),
598 PINMUX_DATA(KEYOUT3_MARK, PSA15_PSA14_FN2, PTB0_FN),
599
600 /* PTC FN */
601 PINMUX_DATA(IDED15_MARK, PSA11_PSA10_FN1, PTC7_FN),
602 PINMUX_DATA(SDHI1CD_MARK, PSA11_PSA10_FN2, PTC7_FN),
603 PINMUX_DATA(IDED14_MARK, PSA11_PSA10_FN1, PTC6_FN),
604 PINMUX_DATA(SDHI1WP_MARK, PSA11_PSA10_FN2, PTC6_FN),
605 PINMUX_DATA(IDED13_MARK, PSA11_PSA10_FN1, PTC5_FN),
606 PINMUX_DATA(SDHI1D3_MARK, PSA11_PSA10_FN2, PTC5_FN),
607 PINMUX_DATA(IDED12_MARK, PSA11_PSA10_FN1, PTC4_FN),
608 PINMUX_DATA(SDHI1D2_MARK, PSA11_PSA10_FN2, PTC4_FN),
609 PINMUX_DATA(IDED11_MARK, PSA11_PSA10_FN1, PTC3_FN),
610 PINMUX_DATA(SDHI1D1_MARK, PSA11_PSA10_FN2, PTC3_FN),
611 PINMUX_DATA(IDED10_MARK, PSA11_PSA10_FN1, PTC2_FN),
612 PINMUX_DATA(SDHI1D0_MARK, PSA11_PSA10_FN2, PTC2_FN),
613 PINMUX_DATA(IDED9_MARK, PSA11_PSA10_FN1, PTC1_FN),
614 PINMUX_DATA(SDHI1CMD_MARK, PSA11_PSA10_FN2, PTC1_FN),
615 PINMUX_DATA(IDED8_MARK, PSA11_PSA10_FN1, PTC0_FN),
616 PINMUX_DATA(SDHI1CLK_MARK, PSA11_PSA10_FN2, PTC0_FN),
617
618 /* PTD FN */
619 PINMUX_DATA(IDED7_MARK, PSA11_PSA10_FN1, PTD7_FN),
620 PINMUX_DATA(SDHI0CD_PTD_MARK, PSA11_PSA10_FN2, PTD7_FN),
621 PINMUX_DATA(IDED6_MARK, PSA11_PSA10_FN1, PTD6_FN),
622 PINMUX_DATA(SDHI0WP_PTD_MARK, PSA11_PSA10_FN2, PTD6_FN),
623 PINMUX_DATA(IDED5_MARK, PSA11_PSA10_FN1, PTD5_FN),
624 PINMUX_DATA(SDHI0D3_PTD_MARK, PSA11_PSA10_FN2, PTD5_FN),
625 PINMUX_DATA(IDED4_MARK, PSA11_PSA10_FN1, PTD4_FN),
626 PINMUX_DATA(SDHI0D2_PTD_MARK, PSA11_PSA10_FN2, PTD4_FN),
627 PINMUX_DATA(IDED3_MARK, PSA11_PSA10_FN1, PTD3_FN),
628 PINMUX_DATA(SDHI0D1_PTD_MARK, PSA11_PSA10_FN2, PTD3_FN),
629 PINMUX_DATA(IDED2_MARK, PSA11_PSA10_FN1, PTD2_FN),
630 PINMUX_DATA(SDHI0D0_PTD_MARK, PSA11_PSA10_FN2, PTD2_FN),
631 PINMUX_DATA(IDED1_MARK, PSA11_PSA10_FN1, PTD1_FN),
632 PINMUX_DATA(SDHI0CMD_PTD_MARK, PSA11_PSA10_FN2, PTD1_FN),
633 PINMUX_DATA(IDED0_MARK, PSA11_PSA10_FN1, PTD0_FN),
634 PINMUX_DATA(SDHI0CLK_PTD_MARK, PSA11_PSA10_FN2, PTD0_FN),
635
636 /* PTE FN */
637 PINMUX_DATA(DIRECTION_MARK, PSA11_PSA10_FN1, PTE5_FN),
638 PINMUX_DATA(SCIF5_PTE_SCK_MARK, PSA11_PSA10_FN2, PTE5_FN),
639 PINMUX_DATA(EXBUF_ENB_MARK, PSA11_PSA10_FN1, PTE4_FN),
640 PINMUX_DATA(SCIF5_PTE_RXD_MARK, PSA11_PSA10_FN2, PTE4_FN),
641 PINMUX_DATA(IDERST_MARK, PSA11_PSA10_FN1, PTE3_FN),
642 PINMUX_DATA(SCIF5_PTE_TXD_MARK, PSA11_PSA10_FN2, PTE3_FN),
643 PINMUX_DATA(IODACK_MARK, PSA11_PSA10_FN1, PTE2_FN),
644 PINMUX_DATA(SCIF4_PTE_SCK_MARK, PSA11_PSA10_FN2, PTE2_FN),
645 PINMUX_DATA(IODREQ_MARK, PSA11_PSA10_FN1, PTE1_FN),
646 PINMUX_DATA(SCIF4_PTE_RXD_MARK, PSA11_PSA10_FN2, PTE1_FN),
647 PINMUX_DATA(IDEIORDY_MARK, PSA11_PSA10_FN1, PTE0_FN),
648 PINMUX_DATA(SCIF4_PTE_TXD_MARK, PSA11_PSA10_FN2, PTE0_FN),
649
650 /* PTF FN */
651 PINMUX_DATA(IDEINT_MARK, PTF7_FN),
652 PINMUX_DATA(IDEIOWR_MARK, PSA5_PSA4_FN1, PTF6_FN),
653 PINMUX_DATA(MSIOF0_PTF_SS2_MARK, PSA5_PSA4_FN2, PTF6_FN),
654 PINMUX_DATA(MSIOF0_PTF_RSYNC_MARK, PSA5_PSA4_FN3, PTF6_FN),
655 PINMUX_DATA(IDEIORD_MARK, PSA5_PSA4_FN1, PTF5_FN),
656 PINMUX_DATA(MSIOF0_PTF_SS1_MARK, PSA5_PSA4_FN2, PTF5_FN),
657 PINMUX_DATA(MSIOF0_PTF_RSCK_MARK, PSA5_PSA4_FN3, PTF5_FN),
658 PINMUX_DATA(IDECS1_MARK, PSA11_PSA10_FN1, PTF4_FN),
659 PINMUX_DATA(MSIOF0_PTF_TSYNC_MARK, PSA11_PSA10_FN2, PTF4_FN),
660 PINMUX_DATA(IDECS0_MARK, PSA11_PSA10_FN1, PTF3_FN),
661 PINMUX_DATA(MSIOF0_PTF_TSCK_MARK, PSA11_PSA10_FN2, PTF3_FN),
662 PINMUX_DATA(IDEA2_MARK, PSA11_PSA10_FN1, PTF2_FN),
663 PINMUX_DATA(MSIOF0_PTF_RXD_MARK, PSA11_PSA10_FN2, PTF2_FN),
664 PINMUX_DATA(IDEA1_MARK, PSA11_PSA10_FN1, PTF1_FN),
665 PINMUX_DATA(MSIOF0_PTF_TXD_MARK, PSA11_PSA10_FN2, PTF1_FN),
666 PINMUX_DATA(IDEA0_MARK, PSA11_PSA10_FN1, PTF0_FN),
667 PINMUX_DATA(MSIOF0_PTF_MCK_MARK, PSA11_PSA10_FN2, PTF0_FN),
668
669 /* PTG FN */
670 PINMUX_DATA(AUDCK_MARK, PTG5_FN),
671 PINMUX_DATA(AUDSYNC_MARK, PTG4_FN),
672 PINMUX_DATA(AUDATA3_MARK, PSA3_PSA2_FN1, PTG3_FN),
673 PINMUX_DATA(TPUTO3_MARK, PSA3_PSA2_FN2, PTG3_FN),
674 PINMUX_DATA(AUDATA2_MARK, PSA3_PSA2_FN1, PTG2_FN),
675 PINMUX_DATA(TPUTO2_MARK, PSA3_PSA2_FN2, PTG2_FN),
676 PINMUX_DATA(AUDATA1_MARK, PSA3_PSA2_FN1, PTG1_FN),
677 PINMUX_DATA(TPUTO1_MARK, PSA3_PSA2_FN2, PTG1_FN),
678 PINMUX_DATA(AUDATA0_MARK, PSA3_PSA2_FN1, PTG0_FN),
679 PINMUX_DATA(TPUTO0_MARK, PSA3_PSA2_FN2, PTG0_FN),
680
681 /* PTG FN */
682 PINMUX_DATA(LCDVCPWC_MARK, PTH7_FN),
683 PINMUX_DATA(LCDRD_MARK, PSB15_PSB14_FN1, PTH6_FN),
684 PINMUX_DATA(DV_CLKI_MARK, PSB15_PSB14_FN2, PTH6_FN),
685 PINMUX_DATA(LCDVSYN_MARK, PSB15_PSB14_FN1, PTH5_FN),
686 PINMUX_DATA(DV_CLK_MARK, PSB15_PSB14_FN2, PTH5_FN),
687 PINMUX_DATA(LCDDISP_MARK, PSB13_PSB12_LCDC_RGB, PTH4_FN),
688 PINMUX_DATA(LCDRS_MARK, PSB13_PSB12_LCDC_SYS, PTH4_FN),
689 PINMUX_DATA(LCDHSYN_MARK, PSB13_PSB12_LCDC_RGB, PTH3_FN),
690 PINMUX_DATA(LCDCS_MARK, PSB13_PSB12_LCDC_SYS, PTH3_FN),
691 PINMUX_DATA(LCDDON_MARK, PTH2_FN),
692 PINMUX_DATA(LCDDCK_MARK, PSB13_PSB12_LCDC_RGB, PTH1_FN),
693 PINMUX_DATA(LCDWR_MARK, PSB13_PSB12_LCDC_SYS, PTH1_FN),
694 PINMUX_DATA(LCDVEPWC_MARK, PTH0_FN),
695
696 /* PTJ FN */
697 PINMUX_DATA(STATUS0_MARK, PTJ7_FN),
698 PINMUX_DATA(PDSTATUS_MARK, PTJ5_FN),
699 PINMUX_DATA(A25_MARK, PTJ3_FN),
700 PINMUX_DATA(A24_MARK, PTJ2_FN),
701 PINMUX_DATA(A23_MARK, PTJ1_FN),
702 PINMUX_DATA(A22_MARK, PTJ0_FN),
703
704 /* PTK FN */
705 PINMUX_DATA(SIUAFCK_MARK, PTK7_FN),
706 PINMUX_DATA(SIUAILR_MARK, PSB9_PSB8_FN1, PTK6_FN),
707 PINMUX_DATA(MSIOF1_SS2_MARK, PSB9_PSB8_FN2, PTK6_FN),
708 PINMUX_DATA(MSIOF1_RSYNC_MARK, PSB9_PSB8_FN3, PTK6_FN),
709 PINMUX_DATA(SIUAIBT_MARK, PSB9_PSB8_FN1, PTK5_FN),
710 PINMUX_DATA(MSIOF1_SS1_MARK, PSB9_PSB8_FN2, PTK5_FN),
711 PINMUX_DATA(MSIOF1_RSCK_MARK, PSB9_PSB8_FN3, PTK5_FN),
712 PINMUX_DATA(SIUAISLD_MARK, PSB7_PSB6_FN1, PTK4_FN),
713 PINMUX_DATA(MSIOF1_RXD_MARK, PSB7_PSB6_FN2, PTK4_FN),
714 PINMUX_DATA(SIUAOLR_MARK, PSB7_PSB6_FN1, PTK3_FN),
715 PINMUX_DATA(MSIOF1_TSYNC_MARK, PSB7_PSB6_FN2, PTK3_FN),
716 PINMUX_DATA(SIUAOBT_MARK, PSB7_PSB6_FN1, PTK2_FN),
717 PINMUX_DATA(MSIOF1_TSCK_MARK, PSB7_PSB6_FN2, PTK2_FN),
718 PINMUX_DATA(SIUAOSLD_MARK, PSB7_PSB6_FN1, PTK1_FN),
719 PINMUX_DATA(MSIOF1_RXD_MARK, PSB7_PSB6_FN2, PTK1_FN),
720 PINMUX_DATA(SIUAMCK_MARK, PSB7_PSB6_FN1, PTK0_FN),
721 PINMUX_DATA(MSIOF1_MCK_MARK, PSB7_PSB6_FN2, PTK0_FN),
722
723 /* PTL FN */
724 PINMUX_DATA(LCDD15_MARK, PSB5_PSB4_FN1, PTL7_FN),
725 PINMUX_DATA(DV_D15_MARK, PSB5_PSB4_FN2, PTL7_FN),
726 PINMUX_DATA(LCDD14_MARK, PSB5_PSB4_FN1, PTL6_FN),
727 PINMUX_DATA(DV_D14_MARK, PSB5_PSB4_FN2, PTL6_FN),
728 PINMUX_DATA(LCDD13_MARK, PSB5_PSB4_FN1, PTL5_FN),
729 PINMUX_DATA(DV_D13_MARK, PSB5_PSB4_FN2, PTL5_FN),
730 PINMUX_DATA(LCDD12_MARK, PSB5_PSB4_FN1, PTL4_FN),
731 PINMUX_DATA(DV_D12_MARK, PSB5_PSB4_FN2, PTL4_FN),
732 PINMUX_DATA(LCDD11_MARK, PSB5_PSB4_FN1, PTL3_FN),
733 PINMUX_DATA(DV_D11_MARK, PSB5_PSB4_FN2, PTL3_FN),
734 PINMUX_DATA(LCDD10_MARK, PSB5_PSB4_FN1, PTL2_FN),
735 PINMUX_DATA(DV_D10_MARK, PSB5_PSB4_FN2, PTL2_FN),
736 PINMUX_DATA(LCDD9_MARK, PSB5_PSB4_FN1, PTL1_FN),
737 PINMUX_DATA(DV_D9_MARK, PSB5_PSB4_FN2, PTL1_FN),
738 PINMUX_DATA(LCDD8_MARK, PSB5_PSB4_FN1, PTL0_FN),
739 PINMUX_DATA(DV_D8_MARK, PSB5_PSB4_FN2, PTL0_FN),
740
741 /* PTM FN */
742 PINMUX_DATA(LCDD7_MARK, PSB5_PSB4_FN1, PTM7_FN),
743 PINMUX_DATA(DV_D7_MARK, PSB5_PSB4_FN2, PTM7_FN),
744 PINMUX_DATA(LCDD6_MARK, PSB5_PSB4_FN1, PTM6_FN),
745 PINMUX_DATA(DV_D6_MARK, PSB5_PSB4_FN2, PTM6_FN),
746 PINMUX_DATA(LCDD5_MARK, PSB5_PSB4_FN1, PTM5_FN),
747 PINMUX_DATA(DV_D5_MARK, PSB5_PSB4_FN2, PTM5_FN),
748 PINMUX_DATA(LCDD4_MARK, PSB5_PSB4_FN1, PTM4_FN),
749 PINMUX_DATA(DV_D4_MARK, PSB5_PSB4_FN2, PTM4_FN),
750 PINMUX_DATA(LCDD3_MARK, PSB5_PSB4_FN1, PTM3_FN),
751 PINMUX_DATA(DV_D3_MARK, PSB5_PSB4_FN2, PTM3_FN),
752 PINMUX_DATA(LCDD2_MARK, PSB5_PSB4_FN1, PTM2_FN),
753 PINMUX_DATA(DV_D2_MARK, PSB5_PSB4_FN2, PTM2_FN),
754 PINMUX_DATA(LCDD1_MARK, PSB5_PSB4_FN1, PTM1_FN),
755 PINMUX_DATA(DV_D1_MARK, PSB5_PSB4_FN2, PTM1_FN),
756 PINMUX_DATA(LCDD0_MARK, PSB5_PSB4_FN1, PTM0_FN),
757 PINMUX_DATA(DV_D0_MARK, PSB5_PSB4_FN2, PTM0_FN),
758
759 /* PTN FN */
760 PINMUX_DATA(LCDD23_MARK, PSB3_PSB2_FN1, PTN7_FN),
761 PINMUX_DATA(SCIF5_PTN_SCK_MARK, PSB3_PSB2_FN2, PTN7_FN),
762 PINMUX_DATA(LCDD22_MARK, PSB3_PSB2_FN1, PTN6_FN),
763 PINMUX_DATA(SCIF5_PTN_RXD_MARK, PSB3_PSB2_FN2, PTN6_FN),
764 PINMUX_DATA(LCDD21_MARK, PSB3_PSB2_FN1, PTN5_FN),
765 PINMUX_DATA(SCIF5_PTN_TXD_MARK, PSB3_PSB2_FN2, PTN5_FN),
766 PINMUX_DATA(LCDD20_MARK, PSB3_PSB2_FN1, PTN4_FN),
767 PINMUX_DATA(SCIF4_PTN_SCK_MARK, PSB3_PSB2_FN2, PTN4_FN),
768 PINMUX_DATA(LCDD19_MARK, PSB3_PSB2_FN1, PTN3_FN),
769 PINMUX_DATA(SCIF4_PTN_RXD_MARK, PSB3_PSB2_FN2, PTN3_FN),
770 PINMUX_DATA(LCDD18_MARK, PSB3_PSB2_FN1, PTN2_FN),
771 PINMUX_DATA(SCIF4_PTN_TXD_MARK, PSB3_PSB2_FN2, PTN2_FN),
772 PINMUX_DATA(LCDD17_MARK, PSB5_PSB4_FN1, PTN1_FN),
773 PINMUX_DATA(DV_VSYNC_MARK, PSB5_PSB4_FN2, PTN1_FN),
774 PINMUX_DATA(LCDD16_MARK, PSB5_PSB4_FN1, PTN0_FN),
775 PINMUX_DATA(DV_HSYNC_MARK, PSB5_PSB4_FN2, PTN0_FN),
776
777 /* PTQ FN */
778 PINMUX_DATA(AN3_MARK, PTQ3_FN),
779 PINMUX_DATA(AN2_MARK, PTQ2_FN),
780 PINMUX_DATA(AN1_MARK, PTQ1_FN),
781 PINMUX_DATA(AN0_MARK, PTQ0_FN),
782
783 /* PTR FN */
784 PINMUX_DATA(CS6B_CE1B_MARK, PTR7_FN),
785 PINMUX_DATA(CS6A_CE2B_MARK, PTR6_FN),
786 PINMUX_DATA(CS5B_CE1A_MARK, PTR5_FN),
787 PINMUX_DATA(CS5A_CE2A_MARK, PTR4_FN),
788 PINMUX_DATA(IOIS16_MARK, PSA13_PSA12_FN1, PTR3_FN),
789 PINMUX_DATA(LCDLCLK_PTR_MARK, PSA13_PSA12_FN2, PTR3_FN),
790 PINMUX_DATA(WAIT_MARK, PTR2_FN),
791 PINMUX_DATA(WE3_ICIOWR_MARK, PTR1_FN),
792 PINMUX_DATA(WE2_ICIORD_MARK, PTR0_FN),
793
794 /* PTS FN */
795 PINMUX_DATA(SCIF1_PTS_SCK_MARK, PSC15_PSC14_FN1, PTS7_FN),
796 PINMUX_DATA(SDHI0CD_PTS_MARK, PSC15_PSC14_FN2, PTS7_FN),
797 PINMUX_DATA(SCIF1_PTS_RXD_MARK, PSC15_PSC14_FN1, PTS6_FN),
798 PINMUX_DATA(SDHI0WP_PTS_MARK, PSC15_PSC14_FN2, PTS6_FN),
799 PINMUX_DATA(SCIF1_PTS_TXD_MARK, PSC15_PSC14_FN1, PTS5_FN),
800 PINMUX_DATA(SDHI0D3_PTS_MARK, PSC15_PSC14_FN2, PTS5_FN),
801 PINMUX_DATA(SCIF3_PTS_CTS_MARK, PSC15_PSC14_FN1, PTS4_FN),
802 PINMUX_DATA(SDHI0D2_PTS_MARK, PSC15_PSC14_FN2, PTS4_FN),
803 PINMUX_DATA(SCIF3_PTS_RTS_MARK, PSC15_PSC14_FN1, PTS3_FN),
804 PINMUX_DATA(SDHI0D1_PTS_MARK, PSC15_PSC14_FN2, PTS3_FN),
805 PINMUX_DATA(SCIF3_PTS_SCK_MARK, PSC15_PSC14_FN1, PTS2_FN),
806 PINMUX_DATA(SDHI0D0_PTS_MARK, PSC15_PSC14_FN2, PTS2_FN),
807 PINMUX_DATA(SCIF3_PTS_RXD_MARK, PSC15_PSC14_FN1, PTS1_FN),
808 PINMUX_DATA(SDHI0CMD_PTS_MARK, PSC15_PSC14_FN2, PTS1_FN),
809 PINMUX_DATA(SCIF3_PTS_TXD_MARK, PSC15_PSC14_FN1, PTS0_FN),
810 PINMUX_DATA(SDHI0CLK_PTS_MARK, PSC15_PSC14_FN2, PTS0_FN),
811
812 /* PTT FN */
813 PINMUX_DATA(SCIF0_PTT_SCK_MARK, PSC13_PSC12_FN1, PTT5_FN),
814 PINMUX_DATA(MSIOF0_PTT_TSCK_MARK, PSC13_PSC12_FN2, PTT5_FN),
815 PINMUX_DATA(SCIF0_PTT_RXD_MARK, PSC13_PSC12_FN1, PTT4_FN),
816 PINMUX_DATA(MSIOF0_PTT_RXD_MARK, PSC13_PSC12_FN2, PTT4_FN),
817 PINMUX_DATA(SCIF0_PTT_TXD_MARK, PSC13_PSC12_FN1, PTT3_FN),
818 PINMUX_DATA(MSIOF0_PTT_TXD_MARK, PSC13_PSC12_FN2, PTT3_FN),
819 PINMUX_DATA(SCIF2_PTT_SCK_MARK, PSC11_PSC10_FN1, PTT2_FN),
820 PINMUX_DATA(MSIOF0_PTT_TSYNC_MARK, PSC11_PSC10_FN2, PTT2_FN),
821 PINMUX_DATA(SCIF2_PTT_RXD_MARK, PSC11_PSC10_FN1, PTT1_FN),
822 PINMUX_DATA(MSIOF0_PTT_SS1_MARK, PSC11_PSC10_FN2, PTT1_FN),
823 PINMUX_DATA(MSIOF0_PTT_RSCK_MARK, PSC11_PSC10_FN3, PTT1_FN),
824 PINMUX_DATA(SCIF2_PTT_TXD_MARK, PSC11_PSC10_FN1, PTT0_FN),
825 PINMUX_DATA(MSIOF0_PTT_SS2_MARK, PSC11_PSC10_FN2, PTT0_FN),
826 PINMUX_DATA(MSIOF0_PTT_RSYNC_MARK, PSC11_PSC10_FN3, PTT0_FN),
827
828 /* PTU FN */
829 PINMUX_DATA(FCDE_MARK, PSC9_PSC8_FN1, PTU5_FN),
830 PINMUX_DATA(SCIF0_PTU_SCK_MARK, PSC9_PSC8_FN2, PTU5_FN),
831 PINMUX_DATA(FSC_MARK, PSC9_PSC8_FN1, PTU4_FN),
832 PINMUX_DATA(SCIF0_PTU_RXD_MARK, PSC9_PSC8_FN2, PTU4_FN),
833 PINMUX_DATA(FWE_MARK, PSC9_PSC8_FN1, PTU3_FN),
834 PINMUX_DATA(SCIF0_PTU_TXD_MARK, PSC9_PSC8_FN2, PTU3_FN),
835 PINMUX_DATA(FOE_MARK, PSC7_PSC6_FN1, PTU2_FN),
836 PINMUX_DATA(SCIF2_PTU_SCK_MARK, PSC7_PSC6_FN2, PTU2_FN),
837 PINMUX_DATA(VIO_VD2_MARK, PSC7_PSC6_FN3, PTU2_FN),
838 PINMUX_DATA(FRB_MARK, PSC7_PSC6_FN1, PTU1_FN),
839 PINMUX_DATA(SCIF2_PTU_RXD_MARK, PSC7_PSC6_FN2, PTU1_FN),
840 PINMUX_DATA(VIO_CLK2_MARK, PSC7_PSC6_FN3, PTU1_FN),
841 PINMUX_DATA(FCE_MARK, PSC7_PSC6_FN1, PTU0_FN),
842 PINMUX_DATA(SCIF2_PTU_TXD_MARK, PSC7_PSC6_FN2, PTU0_FN),
843 PINMUX_DATA(VIO_HD2_MARK, PSC7_PSC6_FN3, PTU0_FN),
844
845 /* PTV FN */
846 PINMUX_DATA(NAF7_MARK, PSC7_PSC6_FN1, PTV7_FN),
847 PINMUX_DATA(SCIF1_PTV_SCK_MARK, PSC7_PSC6_FN2, PTV7_FN),
848 PINMUX_DATA(VIO_D15_MARK, PSC7_PSC6_FN3, PTV7_FN),
849 PINMUX_DATA(NAF6_MARK, PSC7_PSC6_FN1, PTV6_FN),
850 PINMUX_DATA(SCIF1_PTV_RXD_MARK, PSC7_PSC6_FN2, PTV6_FN),
851 PINMUX_DATA(VIO_D14_MARK, PSC7_PSC6_FN3, PTV6_FN),
852 PINMUX_DATA(NAF5_MARK, PSC7_PSC6_FN1, PTV5_FN),
853 PINMUX_DATA(SCIF1_PTV_TXD_MARK, PSC7_PSC6_FN2, PTV5_FN),
854 PINMUX_DATA(VIO_D13_MARK, PSC7_PSC6_FN3, PTV5_FN),
855 PINMUX_DATA(NAF4_MARK, PSC7_PSC6_FN1, PTV4_FN),
856 PINMUX_DATA(SCIF3_PTV_CTS_MARK, PSC7_PSC6_FN2, PTV4_FN),
857 PINMUX_DATA(VIO_D12_MARK, PSC7_PSC6_FN3, PTV4_FN),
858 PINMUX_DATA(NAF3_MARK, PSC7_PSC6_FN1, PTV3_FN),
859 PINMUX_DATA(SCIF3_PTV_RTS_MARK, PSC7_PSC6_FN2, PTV3_FN),
860 PINMUX_DATA(VIO_D11_MARK, PSC7_PSC6_FN3, PTV3_FN),
861 PINMUX_DATA(NAF2_MARK, PSC7_PSC6_FN1, PTV2_FN),
862 PINMUX_DATA(SCIF3_PTV_SCK_MARK, PSC7_PSC6_FN2, PTV2_FN),
863 PINMUX_DATA(VIO_D10_MARK, PSC7_PSC6_FN3, PTV2_FN),
864 PINMUX_DATA(NAF1_MARK, PSC7_PSC6_FN1, PTV1_FN),
865 PINMUX_DATA(SCIF3_PTV_RXD_MARK, PSC7_PSC6_FN2, PTV1_FN),
866 PINMUX_DATA(VIO_D9_MARK, PSC7_PSC6_FN3, PTV1_FN),
867 PINMUX_DATA(NAF0_MARK, PSC7_PSC6_FN1, PTV0_FN),
868 PINMUX_DATA(SCIF3_PTV_TXD_MARK, PSC7_PSC6_FN2, PTV0_FN),
869 PINMUX_DATA(VIO_D8_MARK, PSC7_PSC6_FN3, PTV0_FN),
870
871 /* PTW FN */
872 PINMUX_DATA(IRQ7_MARK, PTW7_FN),
873 PINMUX_DATA(IRQ6_MARK, PTW6_FN),
874 PINMUX_DATA(IRQ5_MARK, PTW5_FN),
875 PINMUX_DATA(IRQ4_MARK, PSD15_PSD14_FN1, PTW4_FN),
876 PINMUX_DATA(LCDLCLK_PTW_MARK, PSD15_PSD14_FN2, PTW4_FN),
877 PINMUX_DATA(IRQ3_MARK, PSD13_PSD12_FN1, PTW3_FN),
878 PINMUX_DATA(ADTRG_MARK, PSD13_PSD12_FN2, PTW3_FN),
879 PINMUX_DATA(IRQ2_MARK, PSD11_PSD10_FN1, PTW2_FN),
880 PINMUX_DATA(BS_MARK, PSD11_PSD10_FN2, PTW2_FN),
881 PINMUX_DATA(VIO_CKO_MARK, PSD11_PSD10_FN3, PTW2_FN),
882 PINMUX_DATA(IRQ1_MARK, PSD9_PSD8_FN1, PTW1_FN),
883 PINMUX_DATA(SIUAISPD_MARK, PSD9_PSD8_FN2, PTW1_FN),
884 PINMUX_DATA(IRQ0_MARK, PSD7_PSD6_FN1, PTW0_FN),
885 PINMUX_DATA(SIUAOSPD_MARK, PSD7_PSD6_FN2, PTW0_FN),
886
887 /* PTX FN */
888 PINMUX_DATA(DACK1_MARK, PTX7_FN),
889 PINMUX_DATA(DREQ1_MARK, PSD3_PSD2_FN1, PTX6_FN),
890 PINMUX_DATA(MSIOF0_PTX_MCK_MARK, PSD3_PSD2_FN2, PTX6_FN),
891 PINMUX_DATA(DACK1_MARK, PTX5_FN),
892 PINMUX_DATA(IRDA_OUT_MARK, PSD5_PSD4_FN2, PTX5_FN),
893 PINMUX_DATA(DREQ1_MARK, PTX4_FN),
894 PINMUX_DATA(IRDA_IN_MARK, PSD5_PSD4_FN2, PTX4_FN),
895 PINMUX_DATA(TS0_SDAT_MARK, PTX3_FN),
896 PINMUX_DATA(TS0_SCK_MARK, PTX2_FN),
897 PINMUX_DATA(TS0_SDEN_MARK, PTX1_FN),
898 PINMUX_DATA(TS0_SPSYNC_MARK, PTX0_FN),
899
900 /* PTY FN */
901 PINMUX_DATA(VIO_D7_MARK, PTY7_FN),
902 PINMUX_DATA(VIO_D6_MARK, PTY6_FN),
903 PINMUX_DATA(VIO_D5_MARK, PTY5_FN),
904 PINMUX_DATA(VIO_D4_MARK, PTY4_FN),
905 PINMUX_DATA(VIO_D3_MARK, PTY3_FN),
906 PINMUX_DATA(VIO_D2_MARK, PTY2_FN),
907 PINMUX_DATA(VIO_D1_MARK, PTY1_FN),
908 PINMUX_DATA(VIO_D0_MARK, PTY0_FN),
909
910 /* PTZ FN */
911 PINMUX_DATA(SIUBOBT_MARK, PTZ7_FN),
912 PINMUX_DATA(SIUBOLR_MARK, PTZ6_FN),
913 PINMUX_DATA(SIUBOSLD_MARK, PTZ5_FN),
914 PINMUX_DATA(SIUBMCK_MARK, PTZ4_FN),
915 PINMUX_DATA(VIO_FLD_MARK, PSD1_PSD0_FN1, PTZ3_FN),
916 PINMUX_DATA(SIUBFCK_MARK, PSD1_PSD0_FN2, PTZ3_FN),
917 PINMUX_DATA(VIO_HD1_MARK, PSD1_PSD0_FN1, PTZ2_FN),
918 PINMUX_DATA(SIUBILR_MARK, PSD1_PSD0_FN2, PTZ2_FN),
919 PINMUX_DATA(VIO_VD1_MARK, PSD1_PSD0_FN1, PTZ1_FN),
920 PINMUX_DATA(SIUBIBT_MARK, PSD1_PSD0_FN2, PTZ1_FN),
921 PINMUX_DATA(VIO_CLK1_MARK, PSD1_PSD0_FN1, PTZ0_FN),
922 PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN),
923};
924
925static struct pinmux_gpio pinmux_gpios[] = {
926 /* PTA */
927 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
928 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
929 PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
930 PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
931 PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
932 PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
933 PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
934 PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
935
936 /* PTB */
937 PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
938 PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
939 PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
940 PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
941 PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
942 PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
943 PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
944 PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
945
946 /* PTC */
947 PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
948 PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
949 PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
950 PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
951 PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
952 PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
953 PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
954 PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
955
956 /* PTD */
957 PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
958 PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
959 PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
960 PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
961 PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
962 PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
963 PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
964 PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
965
966 /* PTE */
967 PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
968 PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
969 PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
970 PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
971 PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
972 PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
973
974 /* PTF */
975 PINMUX_GPIO(GPIO_PTF7, PTF7_DATA),
976 PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
977 PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
978 PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
979 PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
980 PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
981 PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
982 PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
983
984 /* PTG */
985 PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
986 PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
987 PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
988 PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
989 PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
990 PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
991
992 /* PTH */
993 PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
994 PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
995 PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
996 PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
997 PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
998 PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
999 PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
1000 PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
1001
1002 /* PTJ */
1003 PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
1004 PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
1005 PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
1006 PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
1007 PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
1008 PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
1009
1010 /* PTK */
1011 PINMUX_GPIO(GPIO_PTK7, PTK7_DATA),
1012 PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
1013 PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
1014 PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
1015 PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
1016 PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
1017 PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
1018 PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
1019
1020 /* PTL */
1021 PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
1022 PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
1023 PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
1024 PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
1025 PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
1026 PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
1027 PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
1028 PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
1029
1030 /* PTM */
1031 PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
1032 PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
1033 PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
1034 PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
1035 PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
1036 PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
1037 PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
1038 PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
1039
1040 /* PTN */
1041 PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
1042 PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
1043 PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
1044 PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
1045 PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
1046 PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
1047 PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
1048 PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
1049
1050 /* PTQ */
1051 PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
1052 PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
1053 PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
1054 PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
1055
1056 /* PTR */
1057 PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
1058 PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
1059 PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
1060 PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
1061 PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
1062 PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
1063 PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
1064 PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
1065
1066 /* PTS */
1067 PINMUX_GPIO(GPIO_PTS7, PTS7_DATA),
1068 PINMUX_GPIO(GPIO_PTS6, PTS6_DATA),
1069 PINMUX_GPIO(GPIO_PTS5, PTS5_DATA),
1070 PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
1071 PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
1072 PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
1073 PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
1074 PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
1075
1076 /* PTT */
1077 PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
1078 PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
1079 PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
1080 PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
1081 PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
1082 PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
1083
1084 /* PTU */
1085 PINMUX_GPIO(GPIO_PTU5, PTU5_DATA),
1086 PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
1087 PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
1088 PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
1089 PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
1090 PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
1091
1092 /* PTV */
1093 PINMUX_GPIO(GPIO_PTV7, PTV7_DATA),
1094 PINMUX_GPIO(GPIO_PTV6, PTV6_DATA),
1095 PINMUX_GPIO(GPIO_PTV5, PTV5_DATA),
1096 PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
1097 PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
1098 PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
1099 PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
1100 PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
1101
1102 /* PTW */
1103 PINMUX_GPIO(GPIO_PTW7, PTW7_DATA),
1104 PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
1105 PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
1106 PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
1107 PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
1108 PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
1109 PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
1110 PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
1111
1112 /* PTX */
1113 PINMUX_GPIO(GPIO_PTX7, PTX7_DATA),
1114 PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
1115 PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
1116 PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
1117 PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
1118 PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
1119 PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
1120 PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
1121
1122 /* PTY */
1123 PINMUX_GPIO(GPIO_PTY7, PTY7_DATA),
1124 PINMUX_GPIO(GPIO_PTY6, PTY6_DATA),
1125 PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
1126 PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
1127 PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
1128 PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
1129 PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
1130 PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
1131
1132 /* PTZ */
1133 PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA),
1134 PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA),
1135 PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
1136 PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
1137 PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
1138 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
1139 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1140 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1141
1142 /* SCIF0 */
1143 PINMUX_GPIO(GPIO_FN_SCIF0_PTT_TXD, SCIF0_PTT_TXD_MARK),
1144 PINMUX_GPIO(GPIO_FN_SCIF0_PTT_RXD, SCIF0_PTT_RXD_MARK),
1145 PINMUX_GPIO(GPIO_FN_SCIF0_PTT_SCK, SCIF0_PTT_SCK_MARK),
1146 PINMUX_GPIO(GPIO_FN_SCIF0_PTU_TXD, SCIF0_PTU_TXD_MARK),
1147 PINMUX_GPIO(GPIO_FN_SCIF0_PTU_RXD, SCIF0_PTU_RXD_MARK),
1148 PINMUX_GPIO(GPIO_FN_SCIF0_PTU_SCK, SCIF0_PTU_SCK_MARK),
1149
1150 /* SCIF1 */
1151 PINMUX_GPIO(GPIO_FN_SCIF1_PTS_TXD, SCIF1_PTS_TXD_MARK),
1152 PINMUX_GPIO(GPIO_FN_SCIF1_PTS_RXD, SCIF1_PTS_RXD_MARK),
1153 PINMUX_GPIO(GPIO_FN_SCIF1_PTS_SCK, SCIF1_PTS_SCK_MARK),
1154 PINMUX_GPIO(GPIO_FN_SCIF1_PTV_TXD, SCIF1_PTV_TXD_MARK),
1155 PINMUX_GPIO(GPIO_FN_SCIF1_PTV_RXD, SCIF1_PTV_RXD_MARK),
1156 PINMUX_GPIO(GPIO_FN_SCIF1_PTV_SCK, SCIF1_PTV_SCK_MARK),
1157
1158 /* SCIF2 */
1159 PINMUX_GPIO(GPIO_FN_SCIF2_PTT_TXD, SCIF2_PTT_TXD_MARK),
1160 PINMUX_GPIO(GPIO_FN_SCIF2_PTT_RXD, SCIF2_PTT_RXD_MARK),
1161 PINMUX_GPIO(GPIO_FN_SCIF2_PTT_SCK, SCIF2_PTT_SCK_MARK),
1162 PINMUX_GPIO(GPIO_FN_SCIF2_PTU_TXD, SCIF2_PTU_TXD_MARK),
1163 PINMUX_GPIO(GPIO_FN_SCIF2_PTU_RXD, SCIF2_PTU_RXD_MARK),
1164 PINMUX_GPIO(GPIO_FN_SCIF2_PTU_SCK, SCIF2_PTU_SCK_MARK),
1165
1166 /* SCIF3 */
1167 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_TXD, SCIF3_PTS_TXD_MARK),
1168 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RXD, SCIF3_PTS_RXD_MARK),
1169 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_SCK, SCIF3_PTS_SCK_MARK),
1170 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RTS, SCIF3_PTS_RTS_MARK),
1171 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_CTS, SCIF3_PTS_CTS_MARK),
1172 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_TXD, SCIF3_PTV_TXD_MARK),
1173 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RXD, SCIF3_PTV_RXD_MARK),
1174 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_SCK, SCIF3_PTV_SCK_MARK),
1175 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RTS, SCIF3_PTV_RTS_MARK),
1176 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_CTS, SCIF3_PTV_CTS_MARK),
1177
1178 /* SCIF4 */
1179 PINMUX_GPIO(GPIO_FN_SCIF4_PTE_TXD, SCIF4_PTE_TXD_MARK),
1180 PINMUX_GPIO(GPIO_FN_SCIF4_PTE_RXD, SCIF4_PTE_RXD_MARK),
1181 PINMUX_GPIO(GPIO_FN_SCIF4_PTE_SCK, SCIF4_PTE_SCK_MARK),
1182 PINMUX_GPIO(GPIO_FN_SCIF4_PTN_TXD, SCIF4_PTN_TXD_MARK),
1183 PINMUX_GPIO(GPIO_FN_SCIF4_PTN_RXD, SCIF4_PTN_RXD_MARK),
1184 PINMUX_GPIO(GPIO_FN_SCIF4_PTN_SCK, SCIF4_PTN_SCK_MARK),
1185
1186 /* SCIF5 */
1187 PINMUX_GPIO(GPIO_FN_SCIF5_PTE_TXD, SCIF5_PTE_TXD_MARK),
1188 PINMUX_GPIO(GPIO_FN_SCIF5_PTE_RXD, SCIF5_PTE_RXD_MARK),
1189 PINMUX_GPIO(GPIO_FN_SCIF5_PTE_SCK, SCIF5_PTE_SCK_MARK),
1190 PINMUX_GPIO(GPIO_FN_SCIF5_PTN_TXD, SCIF5_PTN_TXD_MARK),
1191 PINMUX_GPIO(GPIO_FN_SCIF5_PTN_RXD, SCIF5_PTN_RXD_MARK),
1192 PINMUX_GPIO(GPIO_FN_SCIF5_PTN_SCK, SCIF5_PTN_SCK_MARK),
1193
1194 /* CEU */
1195 PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK),
1196 PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK),
1197 PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK),
1198 PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK),
1199 PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK),
1200 PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK),
1201 PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK),
1202 PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK),
1203 PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK),
1204 PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK),
1205 PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK),
1206 PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK),
1207 PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK),
1208 PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK),
1209 PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK),
1210 PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK),
1211 PINMUX_GPIO(GPIO_FN_VIO_CLK1, VIO_CLK1_MARK),
1212 PINMUX_GPIO(GPIO_FN_VIO_VD1, VIO_VD1_MARK),
1213 PINMUX_GPIO(GPIO_FN_VIO_HD1, VIO_HD1_MARK),
1214 PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK),
1215 PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK),
1216 PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK),
1217 PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK),
1218 PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK),
1219
1220 /* LCDC */
1221 PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK),
1222 PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK),
1223 PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK),
1224 PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK),
1225 PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK),
1226 PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK),
1227 PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK),
1228 PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK),
1229 PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK),
1230 PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK),
1231 PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK),
1232 PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK),
1233 PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK),
1234 PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK),
1235 PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK),
1236 PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK),
1237 PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK),
1238 PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK),
1239 PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK),
1240 PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK),
1241 PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK),
1242 PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK),
1243 PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK),
1244 PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK),
1245 PINMUX_GPIO(GPIO_FN_LCDLCLK_PTR, LCDLCLK_PTR_MARK),
1246 PINMUX_GPIO(GPIO_FN_LCDLCLK_PTW, LCDLCLK_PTW_MARK),
1247 /* Main LCD */
1248 PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK),
1249 PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK),
1250 PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK),
1251 PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK),
1252 /* Main LCD - RGB Mode */
1253 PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK),
1254 PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK),
1255 PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK),
1256 /* Main LCD - SYS Mode */
1257 PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK),
1258 PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK),
1259 PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK),
1260 PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK),
1261
1262 /* IRQ */
1263 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
1264 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
1265 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
1266 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
1267 PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
1268 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
1269 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
1270 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
1271
1272 /* AUD */
1273 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
1274 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
1275 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
1276 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
1277 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
1278 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
1279
1280 /* SDHI0 (PTD) */
1281 PINMUX_GPIO(GPIO_FN_SDHI0CD_PTD, SDHI0CD_PTD_MARK),
1282 PINMUX_GPIO(GPIO_FN_SDHI0WP_PTD, SDHI0WP_PTD_MARK),
1283 PINMUX_GPIO(GPIO_FN_SDHI0D3_PTD, SDHI0D3_PTD_MARK),
1284 PINMUX_GPIO(GPIO_FN_SDHI0D2_PTD, SDHI0D2_PTD_MARK),
1285 PINMUX_GPIO(GPIO_FN_SDHI0D1_PTD, SDHI0D1_PTD_MARK),
1286 PINMUX_GPIO(GPIO_FN_SDHI0D0_PTD, SDHI0D0_PTD_MARK),
1287 PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTD, SDHI0CMD_PTD_MARK),
1288 PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTD, SDHI0CLK_PTD_MARK),
1289
1290 /* SDHI0 (PTS) */
1291 PINMUX_GPIO(GPIO_FN_SDHI0CD_PTS, SDHI0CD_PTS_MARK),
1292 PINMUX_GPIO(GPIO_FN_SDHI0WP_PTS, SDHI0WP_PTS_MARK),
1293 PINMUX_GPIO(GPIO_FN_SDHI0D3_PTS, SDHI0D3_PTS_MARK),
1294 PINMUX_GPIO(GPIO_FN_SDHI0D2_PTS, SDHI0D2_PTS_MARK),
1295 PINMUX_GPIO(GPIO_FN_SDHI0D1_PTS, SDHI0D1_PTS_MARK),
1296 PINMUX_GPIO(GPIO_FN_SDHI0D0_PTS, SDHI0D0_PTS_MARK),
1297 PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTS, SDHI0CMD_PTS_MARK),
1298 PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTS, SDHI0CLK_PTS_MARK),
1299
1300 /* SDHI1 */
1301 PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK),
1302 PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK),
1303 PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK),
1304 PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK),
1305 PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK),
1306 PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK),
1307 PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK),
1308 PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK),
1309
1310 /* SIUA */
1311 PINMUX_GPIO(GPIO_FN_SIUAFCK, SIUAFCK_MARK),
1312 PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK),
1313 PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK),
1314 PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK),
1315 PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK),
1316 PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK),
1317 PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK),
1318 PINMUX_GPIO(GPIO_FN_SIUAMCK, SIUAMCK_MARK),
1319 PINMUX_GPIO(GPIO_FN_SIUAISPD, SIUAISPD_MARK),
1320 PINMUX_GPIO(GPIO_FN_SIUOSPD, SIUAOSPD_MARK),
1321
1322 /* SIUB */
1323 PINMUX_GPIO(GPIO_FN_SIUBFCK, SIUBFCK_MARK),
1324 PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK),
1325 PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK),
1326 PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK),
1327 PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK),
1328 PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK),
1329 PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK),
1330 PINMUX_GPIO(GPIO_FN_SIUBMCK, SIUBMCK_MARK),
1331
1332 /* IRDA */
1333 PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK),
1334 PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK),
1335
1336 /* VOU */
1337 PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK),
1338 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
1339 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
1340 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
1341 PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK),
1342 PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK),
1343 PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK),
1344 PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK),
1345 PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK),
1346 PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK),
1347 PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK),
1348 PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK),
1349 PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK),
1350 PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK),
1351 PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK),
1352 PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK),
1353 PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK),
1354 PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK),
1355 PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK),
1356 PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK),
1357
1358 /* KEYSC */
1359 PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK),
1360 PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK),
1361 PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK),
1362 PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK),
1363 PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK),
1364 PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK),
1365 PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK),
1366 PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK),
1367 PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK),
1368 PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK),
1369 PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK),
1370
1371 /* MSIOF0 (PTF) */
1372 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TXD, MSIOF0_PTF_TXD_MARK),
1373 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RXD, MSIOF0_PTF_RXD_MARK),
1374 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_MCK, MSIOF0_PTF_MCK_MARK),
1375 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSYNC, MSIOF0_PTF_TSYNC_MARK),
1376 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSCK, MSIOF0_PTF_TSCK_MARK),
1377 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSYNC, MSIOF0_PTF_RSYNC_MARK),
1378 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSCK, MSIOF0_PTF_RSCK_MARK),
1379 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS1, MSIOF0_PTF_SS1_MARK),
1380 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS2, MSIOF0_PTF_SS2_MARK),
1381
1382 /* MSIOF0 (PTT+PTX) */
1383 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TXD, MSIOF0_PTT_TXD_MARK),
1384 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RXD, MSIOF0_PTT_RXD_MARK),
1385 PINMUX_GPIO(GPIO_FN_MSIOF0_PTX_MCK, MSIOF0_PTX_MCK_MARK),
1386 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSYNC, MSIOF0_PTT_TSYNC_MARK),
1387 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSCK, MSIOF0_PTT_TSCK_MARK),
1388 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSYNC, MSIOF0_PTT_RSYNC_MARK),
1389 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSCK, MSIOF0_PTT_RSCK_MARK),
1390 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS1, MSIOF0_PTT_SS1_MARK),
1391 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS2, MSIOF0_PTT_SS2_MARK),
1392
1393 /* MSIOF1 */
1394 PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK),
1395 PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK),
1396 PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK),
1397 PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK),
1398 PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK),
1399 PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK),
1400 PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK),
1401 PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK),
1402 PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK),
1403
1404 /* TSIF */
1405 PINMUX_GPIO(GPIO_FN_TS0_SDAT, TS0_SDAT_MARK),
1406 PINMUX_GPIO(GPIO_FN_TS0_SCK, TS0_SCK_MARK),
1407 PINMUX_GPIO(GPIO_FN_TS0_SDEN, TS0_SDEN_MARK),
1408 PINMUX_GPIO(GPIO_FN_TS0_SPSYNC, TS0_SPSYNC_MARK),
1409
1410 /* FLCTL */
1411 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
1412 PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK),
1413 PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK),
1414 PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK),
1415 PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK),
1416 PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK),
1417 PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK),
1418 PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK),
1419 PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK),
1420 PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK),
1421 PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK),
1422 PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK),
1423 PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
1424 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
1425
1426 /* DMAC */
1427 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
1428 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
1429 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
1430 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
1431
1432 /* ADC */
1433 PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK),
1434 PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK),
1435 PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK),
1436 PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK),
1437 PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
1438
1439 /* CPG */
1440 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
1441 PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK),
1442
1443 /* TPU */
1444 PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK),
1445 PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK),
1446 PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK),
1447 PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK),
1448
1449 /* BSC */
1450 PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
1451 PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
1452 PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
1453 PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
1454 PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
1455 PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
1456 PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
1457 PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
1458 PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
1459 PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
1460 PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
1461 PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
1462 PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
1463 PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
1464 PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
1465 PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
1466 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
1467 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
1468 PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
1469 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1470 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1471 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
1472 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
1473 PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
1474 PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK),
1475 PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK),
1476 PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK),
1477 PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK),
1478 PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK),
1479
1480 /* ATAPI */
1481 PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK),
1482 PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK),
1483 PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK),
1484 PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK),
1485 PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK),
1486 PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK),
1487 PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK),
1488 PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK),
1489 PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK),
1490 PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK),
1491 PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK),
1492 PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK),
1493 PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK),
1494 PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK),
1495 PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK),
1496 PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK),
1497 PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK),
1498 PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK),
1499 PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK),
1500 PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK),
1501 PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK),
1502 PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK),
1503 PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK),
1504 PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK),
1505 PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK),
1506 PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK),
1507 PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK),
1508 PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK),
1509 PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK),
1510 PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK),
1511 };
1512
1513static struct pinmux_cfg_reg pinmux_config_regs[] = {
1514 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1515 PTA7_FN, PTA7_OUT, 0, PTA7_IN,
1516 PTA6_FN, PTA6_OUT, 0, PTA6_IN,
1517 PTA5_FN, PTA5_OUT, 0, PTA5_IN,
1518 PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN,
1519 PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN,
1520 PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN,
1521 PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN,
1522 PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN }
1523 },
1524 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
1525 PTB7_FN, PTB7_OUT, 0, PTB7_IN,
1526 PTB6_FN, PTB6_OUT, 0, PTB6_IN,
1527 PTB5_FN, PTB5_OUT, 0, PTB5_IN,
1528 PTB4_FN, PTB4_OUT, 0, PTB4_IN,
1529 PTB3_FN, PTB3_OUT, 0, PTB3_IN,
1530 PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN,
1531 PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN,
1532 PTB0_FN, PTB0_OUT, 0, PTB0_IN }
1533 },
1534 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
1535 PTC7_FN, PTC7_OUT, 0, PTC7_IN,
1536 PTC6_FN, PTC6_OUT, 0, PTC6_IN,
1537 PTC5_FN, PTC5_OUT, 0, PTC5_IN,
1538 PTC4_FN, PTC4_OUT, 0, PTC4_IN,
1539 PTC3_FN, PTC3_OUT, 0, PTC3_IN,
1540 PTC2_FN, PTC2_OUT, 0, PTC2_IN,
1541 PTC1_FN, PTC1_OUT, 0, PTC1_IN,
1542 PTC0_FN, PTC0_OUT, 0, PTC0_IN }
1543 },
1544 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
1545 PTD7_FN, PTD7_OUT, 0, PTD7_IN,
1546 PTD6_FN, PTD6_OUT, 0, PTD6_IN,
1547 PTD5_FN, PTD5_OUT, 0, PTD5_IN,
1548 PTD4_FN, PTD4_OUT, 0, PTD4_IN,
1549 PTD3_FN, PTD3_OUT, 0, PTD3_IN,
1550 PTD2_FN, PTD2_OUT, 0, PTD2_IN,
1551 PTD1_FN, PTD1_OUT, 0, PTD1_IN,
1552 PTD0_FN, PTD0_OUT, 0, PTD0_IN }
1553 },
1554 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
1555 0, 0, 0, 0,
1556 0, 0, 0, 0,
1557 PTE5_FN, PTE5_OUT, 0, PTE5_IN,
1558 PTE4_FN, PTE4_OUT, 0, PTE4_IN,
1559 PTE3_FN, PTE3_OUT, 0, PTE3_IN,
1560 PTE2_FN, PTE2_OUT, 0, PTE2_IN,
1561 PTE1_FN, PTE1_OUT, 0, PTE1_IN,
1562 PTE0_FN, PTE0_OUT, 0, PTE0_IN }
1563 },
1564 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
1565 PTF7_FN, PTF7_OUT, 0, PTF7_IN,
1566 PTF6_FN, PTF6_OUT, 0, PTF6_IN,
1567 PTF5_FN, PTF5_OUT, 0, PTF5_IN,
1568 PTF4_FN, PTF4_OUT, 0, PTF4_IN,
1569 PTF3_FN, PTF3_OUT, 0, PTF3_IN,
1570 PTF2_FN, PTF2_OUT, 0, PTF2_IN,
1571 PTF1_FN, PTF1_OUT, 0, PTF1_IN,
1572 PTF0_FN, PTF0_OUT, 0, PTF0_IN }
1573 },
1574 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
1575 0, 0, 0, 0,
1576 0, 0, 0, 0,
1577 PTG5_FN, PTG5_OUT, 0, 0,
1578 PTG4_FN, PTG4_OUT, 0, 0,
1579 PTG3_FN, PTG3_OUT, 0, 0,
1580 PTG2_FN, PTG2_OUT, 0, 0,
1581 PTG1_FN, PTG1_OUT, 0, 0,
1582 PTG0_FN, PTG0_OUT, 0, 0 }
1583 },
1584 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
1585 PTH7_FN, PTH7_OUT, 0, PTH7_IN,
1586 PTH6_FN, PTH6_OUT, 0, PTH6_IN,
1587 PTH5_FN, PTH5_OUT, 0, PTH5_IN,
1588 PTH4_FN, PTH4_OUT, 0, PTH4_IN,
1589 PTH3_FN, PTH3_OUT, 0, PTH3_IN,
1590 PTH2_FN, PTH2_OUT, 0, PTH2_IN,
1591 PTH1_FN, PTH1_OUT, 0, PTH1_IN,
1592 PTH0_FN, PTH0_OUT, 0, PTH0_IN }
1593 },
1594 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
1595 PTJ7_FN, PTJ7_OUT, 0, 0,
1596 0, 0, 0, 0,
1597 PTJ5_FN, PTJ5_OUT, 0, 0,
1598 0, 0, 0, 0,
1599 PTJ3_FN, PTJ3_OUT, 0, PTJ3_IN,
1600 PTJ2_FN, PTJ2_OUT, 0, PTJ2_IN,
1601 PTJ1_FN, PTJ1_OUT, 0, PTJ1_IN,
1602 PTJ0_FN, PTJ0_OUT, 0, PTJ0_IN }
1603 },
1604 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
1605 PTK7_FN, PTK7_OUT, 0, PTK7_IN,
1606 PTK6_FN, PTK6_OUT, 0, PTK6_IN,
1607 PTK5_FN, PTK5_OUT, 0, PTK5_IN,
1608 PTK4_FN, PTK4_OUT, 0, PTK4_IN,
1609 PTK3_FN, PTK3_OUT, 0, PTK3_IN,
1610 PTK2_FN, PTK2_OUT, 0, PTK2_IN,
1611 PTK1_FN, PTK1_OUT, 0, PTK1_IN,
1612 PTK0_FN, PTK0_OUT, 0, PTK0_IN }
1613 },
1614 { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
1615 PTL7_FN, PTL7_OUT, 0, PTL7_IN,
1616 PTL6_FN, PTL6_OUT, 0, PTL6_IN,
1617 PTL5_FN, PTL5_OUT, 0, PTL5_IN,
1618 PTL4_FN, PTL4_OUT, 0, PTL4_IN,
1619 PTL3_FN, PTL3_OUT, 0, PTL3_IN,
1620 PTL2_FN, PTL2_OUT, 0, PTL2_IN,
1621 PTL1_FN, PTL1_OUT, 0, PTL1_IN,
1622 PTL0_FN, PTL0_OUT, 0, PTL0_IN }
1623 },
1624 { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
1625 PTM7_FN, PTM7_OUT, 0, PTM7_IN,
1626 PTM6_FN, PTM6_OUT, 0, PTM6_IN,
1627 PTM5_FN, PTM5_OUT, 0, PTM5_IN,
1628 PTM4_FN, PTM4_OUT, 0, PTM4_IN,
1629 PTM3_FN, PTM3_OUT, 0, PTM3_IN,
1630 PTM2_FN, PTM2_OUT, 0, PTM2_IN,
1631 PTM1_FN, PTM1_OUT, 0, PTM1_IN,
1632 PTM0_FN, PTM0_OUT, 0, PTM0_IN }
1633 },
1634 { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
1635 PTN7_FN, PTN7_OUT, 0, PTN7_IN,
1636 PTN6_FN, PTN6_OUT, 0, PTN6_IN,
1637 PTN5_FN, PTN5_OUT, 0, PTN5_IN,
1638 PTN4_FN, PTN4_OUT, 0, PTN4_IN,
1639 PTN3_FN, PTN3_OUT, 0, PTN3_IN,
1640 PTN2_FN, PTN2_OUT, 0, PTN2_IN,
1641 PTN1_FN, PTN1_OUT, 0, PTN1_IN,
1642 PTN0_FN, PTN0_OUT, 0, PTN0_IN }
1643 },
1644 { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
1645 0, 0, 0, 0,
1646 0, 0, 0, 0,
1647 0, 0, 0, 0,
1648 0, 0, 0, 0,
1649 PTQ3_FN, 0, 0, PTQ3_IN,
1650 PTQ2_FN, 0, 0, PTQ2_IN,
1651 PTQ1_FN, 0, 0, PTQ1_IN,
1652 PTQ0_FN, 0, 0, PTQ0_IN }
1653 },
1654 { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
1655 PTR7_FN, PTR7_OUT, 0, PTR7_IN,
1656 PTR6_FN, PTR6_OUT, 0, PTR6_IN,
1657 PTR5_FN, PTR5_OUT, 0, PTR5_IN,
1658 PTR4_FN, PTR4_OUT, 0, PTR4_IN,
1659 PTR3_FN, 0, 0, PTR3_IN,
1660 PTR2_FN, 0, PTR2_IN_PU, PTR2_IN,
1661 PTR1_FN, PTR1_OUT, 0, PTR1_IN,
1662 PTR0_FN, PTR0_OUT, 0, PTR0_IN }
1663 },
1664 { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) {
1665 PTS7_FN, PTS7_OUT, 0, PTS7_IN,
1666 PTS6_FN, PTS6_OUT, 0, PTS6_IN,
1667 PTS5_FN, PTS5_OUT, 0, PTS5_IN,
1668 PTS4_FN, PTS4_OUT, 0, PTS4_IN,
1669 PTS3_FN, PTS3_OUT, 0, PTS3_IN,
1670 PTS2_FN, PTS2_OUT, 0, PTS2_IN,
1671 PTS1_FN, PTS1_OUT, 0, PTS1_IN,
1672 PTS0_FN, PTS0_OUT, 0, PTS0_IN }
1673 },
1674 { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
1675 0, 0, 0, 0,
1676 0, 0, 0, 0,
1677 PTT5_FN, PTT5_OUT, 0, PTT5_IN,
1678 PTT4_FN, PTT4_OUT, 0, PTT4_IN,
1679 PTT3_FN, PTT3_OUT, 0, PTT3_IN,
1680 PTT2_FN, PTT2_OUT, 0, PTT2_IN,
1681 PTT1_FN, PTT1_OUT, 0, PTT1_IN,
1682 PTT0_FN, PTT0_OUT, 0, PTT0_IN }
1683 },
1684 { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
1685 0, 0, 0, 0,
1686 0, 0, 0, 0,
1687 PTU5_FN, PTU5_OUT, 0, PTU5_IN,
1688 PTU4_FN, PTU4_OUT, 0, PTU4_IN,
1689 PTU3_FN, PTU3_OUT, 0, PTU3_IN,
1690 PTU2_FN, PTU2_OUT, 0, PTU2_IN,
1691 PTU1_FN, PTU1_OUT, 0, PTU1_IN,
1692 PTU0_FN, PTU0_OUT, 0, PTU0_IN }
1693 },
1694 { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
1695 PTV7_FN, PTV7_OUT, 0, PTV7_IN,
1696 PTV6_FN, PTV6_OUT, 0, PTV6_IN,
1697 PTV5_FN, PTV5_OUT, 0, PTV5_IN,
1698 PTV4_FN, PTV4_OUT, 0, PTV4_IN,
1699 PTV3_FN, PTV3_OUT, 0, PTV3_IN,
1700 PTV2_FN, PTV2_OUT, 0, PTV2_IN,
1701 PTV1_FN, PTV1_OUT, 0, PTV1_IN,
1702 PTV0_FN, PTV0_OUT, 0, PTV0_IN }
1703 },
1704 { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
1705 PTW7_FN, PTW7_OUT, 0, PTW7_IN,
1706 PTW6_FN, PTW6_OUT, 0, PTW6_IN,
1707 PTW5_FN, PTW5_OUT, 0, PTW5_IN,
1708 PTW4_FN, PTW4_OUT, 0, PTW4_IN,
1709 PTW3_FN, PTW3_OUT, 0, PTW3_IN,
1710 PTW2_FN, PTW2_OUT, 0, PTW2_IN,
1711 PTW1_FN, PTW1_OUT, 0, PTW1_IN,
1712 PTW0_FN, PTW0_OUT, 0, PTW0_IN }
1713 },
1714 { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
1715 PTX7_FN, PTX7_OUT, 0, PTX7_IN,
1716 PTX6_FN, PTX6_OUT, 0, PTX6_IN,
1717 PTX5_FN, PTX5_OUT, 0, PTX5_IN,
1718 PTX4_FN, PTX4_OUT, 0, PTX4_IN,
1719 PTX3_FN, PTX3_OUT, 0, PTX3_IN,
1720 PTX2_FN, PTX2_OUT, 0, PTX2_IN,
1721 PTX1_FN, PTX1_OUT, 0, PTX1_IN,
1722 PTX0_FN, PTX0_OUT, 0, PTX0_IN }
1723 },
1724 { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
1725 PTY7_FN, PTY7_OUT, 0, PTY7_IN,
1726 PTY6_FN, PTY6_OUT, 0, PTY6_IN,
1727 PTY5_FN, PTY5_OUT, 0, PTY5_IN,
1728 PTY4_FN, PTY4_OUT, 0, PTY4_IN,
1729 PTY3_FN, PTY3_OUT, 0, PTY3_IN,
1730 PTY2_FN, PTY2_OUT, 0, PTY2_IN,
1731 PTY1_FN, PTY1_OUT, 0, PTY1_IN,
1732 PTY0_FN, PTY0_OUT, 0, PTY0_IN }
1733 },
1734 { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
1735 PTZ7_FN, PTZ7_OUT, 0, PTZ7_IN,
1736 PTZ6_FN, PTZ6_OUT, 0, PTZ6_IN,
1737 PTZ5_FN, PTZ5_OUT, 0, PTZ5_IN,
1738 PTZ4_FN, PTZ4_OUT, 0, PTZ4_IN,
1739 PTZ3_FN, PTZ3_OUT, 0, PTZ3_IN,
1740 PTZ2_FN, PTZ2_OUT, 0, PTZ2_IN,
1741 PTZ1_FN, PTZ1_OUT, 0, PTZ1_IN,
1742 PTZ0_FN, PTZ0_OUT, 0, PTZ0_IN }
1743 },
1744 { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 2) {
1745 PSA15_PSA14_FN1, PSA15_PSA14_FN2, 0, 0,
1746 PSA13_PSA12_FN1, PSA13_PSA12_FN2, 0, 0,
1747 PSA11_PSA10_FN1, PSA11_PSA10_FN2, 0, 0,
1748 0, 0, 0, 0,
1749 0, 0, 0, 0,
1750 PSA5_PSA4_FN1, PSA5_PSA4_FN2, PSA5_PSA4_FN3, 0,
1751 PSA3_PSA2_FN1, PSA3_PSA2_FN2, 0, 0,
1752 0, 0, 0, 0 }
1753 },
1754 { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 2) {
1755 PSB15_PSB14_FN1, PSB15_PSB14_FN2, 0, 0,
1756 PSB13_PSB12_LCDC_RGB, PSB13_PSB12_LCDC_SYS, 0, 0,
1757 0, 0, 0, 0,
1758 PSB9_PSB8_FN1, PSB9_PSB8_FN2, PSB9_PSB8_FN3, 0,
1759 PSB7_PSB6_FN1, PSB7_PSB6_FN2, 0, 0,
1760 PSB5_PSB4_FN1, PSB5_PSB4_FN2, 0, 0,
1761 PSB3_PSB2_FN1, PSB3_PSB2_FN2, 0, 0,
1762 0, 0, 0, 0 }
1763 },
1764 { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 2) {
1765 PSC15_PSC14_FN1, PSC15_PSC14_FN2, 0, 0,
1766 PSC13_PSC12_FN1, PSC13_PSC12_FN2, 0, 0,
1767 PSC11_PSC10_FN1, PSC11_PSC10_FN2, PSC11_PSC10_FN3, 0,
1768 PSC9_PSC8_FN1, PSC9_PSC8_FN2, 0, 0,
1769 PSC7_PSC6_FN1, PSC7_PSC6_FN2, PSC7_PSC6_FN3, 0,
1770 0, 0, 0, 0,
1771 0, 0, 0, 0,
1772 0, 0, 0, 0 }
1773 },
1774 { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 2) {
1775 PSD15_PSD14_FN1, PSD15_PSD14_FN2, 0, 0,
1776 PSD13_PSD12_FN1, PSD13_PSD12_FN2, 0, 0,
1777 PSD11_PSD10_FN1, PSD11_PSD10_FN2, PSD11_PSD10_FN3, 0,
1778 PSD9_PSD8_FN1, PSD9_PSD8_FN2, 0, 0,
1779 PSD7_PSD6_FN1, PSD7_PSD6_FN2, 0, 0,
1780 PSD5_PSD4_FN1, PSD5_PSD4_FN2, 0, 0,
1781 PSD3_PSD2_FN1, PSD3_PSD2_FN2, 0, 0,
1782 PSD1_PSD0_FN1, PSD1_PSD0_FN2, 0, 0 }
1783 },
1784 {}
1785};
1786
1787static struct pinmux_data_reg pinmux_data_regs[] = {
1788 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
1789 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
1790 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
1791 },
1792 { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
1793 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
1794 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
1795 },
1796 { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
1797 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
1798 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
1799 },
1800 { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
1801 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
1802 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
1803 },
1804 { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
1805 0, 0, PTE5_DATA, PTE4_DATA,
1806 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
1807 },
1808 { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
1809 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
1810 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
1811 },
1812 { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
1813 0, 0, PTG5_DATA, PTG4_DATA,
1814 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
1815 },
1816 { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
1817 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
1818 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
1819 },
1820 { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
1821 PTJ7_DATA, 0, PTJ5_DATA, 0,
1822 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
1823 },
1824 { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
1825 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
1826 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
1827 },
1828 { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
1829 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
1830 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
1831 },
1832 { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
1833 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
1834 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
1835 },
1836 { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
1837 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
1838 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
1839 },
1840 { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
1841 0, 0, 0, 0,
1842 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
1843 },
1844 { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
1845 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
1846 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
1847 },
1848 { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
1849 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
1850 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
1851 },
1852 { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
1853 0, 0, PTT5_DATA, PTT4_DATA,
1854 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
1855 },
1856 { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
1857 0, 0, PTU5_DATA, PTU4_DATA,
1858 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
1859 },
1860 { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
1861 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
1862 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
1863 },
1864 { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
1865 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
1866 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
1867 },
1868 { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
1869 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
1870 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
1871 },
1872 { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
1873 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
1874 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
1875 },
1876 { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
1877 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
1878 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
1879 },
1880 { },
1881};
1882
1883static struct pinmux_info sh7723_pinmux_info = {
1884 .name = "sh7723_pfc",
1885 .reserved_id = PINMUX_RESERVED,
1886 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1887 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1888 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1889 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1890 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1891 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1892
1893 .first_gpio = GPIO_PTA7,
1894 .last_gpio = GPIO_FN_IDEA0,
1895
1896 .gpios = pinmux_gpios,
1897 .cfg_regs = pinmux_config_regs,
1898 .data_regs = pinmux_data_regs,
1899
1900 .gpio_data = pinmux_data,
1901 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1902};
1903
1904static int __init plat_pinmux_setup(void)
1905{
1906 return register_pinmux(&sh7723_pinmux_info);
1907}
1908
1909arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
index e5e06845fa43..b8869aa20dec 100644
--- a/arch/sh/kernel/cpu/sh4a/smp-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH-X3 SMP 2 * SH-X3 SMP
3 * 3 *
4 * Copyright (C) 2007 Paul Mundt 4 * Copyright (C) 2007 - 2008 Paul Mundt
5 * Copyright (C) 2007 Magnus Damm 5 * Copyright (C) 2007 Magnus Damm
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
@@ -14,6 +14,22 @@
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/io.h> 15#include <linux/io.h>
16 16
17static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
18{
19 unsigned int message = (unsigned int)(long)arg;
20 unsigned int cpu = hard_smp_processor_id();
21 unsigned int offs = 4 * cpu;
22 unsigned int x;
23
24 x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
25 x &= (1 << (message << 2));
26 ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
27
28 smp_message_recv(message);
29
30 return IRQ_HANDLED;
31}
32
17void __init plat_smp_setup(void) 33void __init plat_smp_setup(void)
18{ 34{
19 unsigned int cpu = 0; 35 unsigned int cpu = 0;
@@ -40,6 +56,13 @@ void __init plat_smp_setup(void)
40 56
41void __init plat_prepare_cpus(unsigned int max_cpus) 57void __init plat_prepare_cpus(unsigned int max_cpus)
42{ 58{
59 int i;
60
61 BUILD_BUG_ON(SMP_MSG_NR >= 8);
62
63 for (i = 0; i < SMP_MSG_NR; i++)
64 request_irq(104 + i, ipi_interrupt_handler, IRQF_DISABLED,
65 "IPI", (void *)(long)i);
43} 66}
44 67
45#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12)) 68#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
@@ -59,7 +82,7 @@ void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
59 ctrl_outl(STBCR_MSTP, STBCR_REG(cpu)); 82 ctrl_outl(STBCR_MSTP, STBCR_REG(cpu));
60 83
61 while (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP)) 84 while (!(ctrl_inl(STBCR_REG(cpu)) & STBCR_MSTP))
62 ; 85 cpu_relax();
63 86
64 /* Start up secondary processor by sending a reset */ 87 /* Start up secondary processor by sending a reset */
65 ctrl_outl(STBCR_AP_VAL, STBCR_REG(cpu)); 88 ctrl_outl(STBCR_AP_VAL, STBCR_REG(cpu));
@@ -75,46 +98,6 @@ void plat_send_ipi(unsigned int cpu, unsigned int message)
75 unsigned long addr = 0xfe410070 + (cpu * 4); 98 unsigned long addr = 0xfe410070 + (cpu * 4);
76 99
77 BUG_ON(cpu >= 4); 100 BUG_ON(cpu >= 4);
78 BUG_ON(message >= SMP_MSG_NR);
79 101
80 ctrl_outl(1 << (message << 2), addr); /* C0INTICI..CnINTICI */ 102 ctrl_outl(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
81} 103}
82
83struct ipi_data {
84 void (*handler)(void *);
85 void *arg;
86 unsigned int message;
87};
88
89static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
90{
91 struct ipi_data *id = arg;
92 unsigned int cpu = hard_smp_processor_id();
93 unsigned int offs = 4 * cpu;
94 unsigned int x;
95
96 x = ctrl_inl(0xfe410070 + offs); /* C0INITICI..CnINTICI */
97 x &= (1 << (id->message << 2));
98 ctrl_outl(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */
99
100 id->handler(id->arg);
101
102 return IRQ_HANDLED;
103}
104
105static struct ipi_data ipi_handlers[SMP_MSG_NR];
106
107int plat_register_ipi_handler(unsigned int message,
108 void (*handler)(void *), void *arg)
109{
110 struct ipi_data *id = &ipi_handlers[message];
111
112 BUG_ON(SMP_MSG_NR >= 8);
113 BUG_ON(message >= SMP_MSG_NR);
114
115 id->handler = handler;
116 id->arg = arg;
117 id->message = message;
118
119 return request_irq(104 + message, ipi_interrupt_handler, 0, "IPI", id);
120}
diff --git a/arch/sh/kernel/cpu/sh5/Makefile b/arch/sh/kernel/cpu/sh5/Makefile
index 8646363e9ded..ce4602ea23a8 100644
--- a/arch/sh/kernel/cpu/sh5/Makefile
+++ b/arch/sh/kernel/cpu/sh5/Makefile
@@ -5,3 +5,8 @@ obj-y := entry.o probe.o switchto.o
5 5
6obj-$(CONFIG_SH_FPU) += fpu.o 6obj-$(CONFIG_SH_FPU) += fpu.o
7obj-$(CONFIG_KALLSYMS) += unwind.o 7obj-$(CONFIG_KALLSYMS) += unwind.o
8
9# Primary on-chip clocks (common)
10clock-$(CONFIG_CPU_SH5) := clock-sh5.o
11
12obj-y += $(clock-y)
diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c
new file mode 100644
index 000000000000..52c49248833a
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c
@@ -0,0 +1,79 @@
1/*
2 * arch/sh/kernel/cpu/sh5/clock-sh5.c
3 *
4 * SH-5 support for the clock framework
5 *
6 * Copyright (C) 2008 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <asm/clock.h>
15#include <asm/io.h>
16
17static int ifc_table[] = { 2, 4, 6, 8, 10, 12, 16, 24 };
18
19/* Clock, Power and Reset Controller */
20#define CPRC_BLOCK_OFF 0x01010000
21#define CPRC_BASE (PHYS_PERIPHERAL_BLOCK + CPRC_BLOCK_OFF)
22
23static unsigned long cprc_base;
24
25static void master_clk_init(struct clk *clk)
26{
27 int idx = (ctrl_inl(cprc_base + 0x00) >> 6) & 0x0007;
28 clk->rate *= ifc_table[idx];
29}
30
31static struct clk_ops sh5_master_clk_ops = {
32 .init = master_clk_init,
33};
34
35static void module_clk_recalc(struct clk *clk)
36{
37 int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007;
38 clk->rate = clk->parent->rate / ifc_table[idx];
39}
40
41static struct clk_ops sh5_module_clk_ops = {
42 .recalc = module_clk_recalc,
43};
44
45static void bus_clk_recalc(struct clk *clk)
46{
47 int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007;
48 clk->rate = clk->parent->rate / ifc_table[idx];
49}
50
51static struct clk_ops sh5_bus_clk_ops = {
52 .recalc = bus_clk_recalc,
53};
54
55static void cpu_clk_recalc(struct clk *clk)
56{
57 int idx = (ctrl_inw(cprc_base) & 0x0007);
58 clk->rate = clk->parent->rate / ifc_table[idx];
59}
60
61static struct clk_ops sh5_cpu_clk_ops = {
62 .recalc = cpu_clk_recalc,
63};
64
65static struct clk_ops *sh5_clk_ops[] = {
66 &sh5_master_clk_ops,
67 &sh5_module_clk_ops,
68 &sh5_bus_clk_ops,
69 &sh5_cpu_clk_ops,
70};
71
72void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
73{
74 cprc_base = onchip_remap(CPRC_BASE, 1024, "CPRC");
75 BUG_ON(!cprc_base);
76
77 if (idx < ARRAY_SIZE(sh5_clk_ops))
78 *ops = sh5_clk_ops[idx];
79}
diff --git a/arch/sh/kernel/dump_task.c b/arch/sh/kernel/dump_task.c
deleted file mode 100644
index 1db7ce0f25d4..000000000000
--- a/arch/sh/kernel/dump_task.c
+++ /dev/null
@@ -1,32 +0,0 @@
1#include <linux/elfcore.h>
2#include <linux/sched.h>
3#include <asm/fpu.h>
4
5/*
6 * Capture the user space registers if the task is not running (in user space)
7 */
8int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
9{
10 struct pt_regs ptregs;
11
12 ptregs = *task_pt_regs(tsk);
13 elf_core_copy_regs(regs, &ptregs);
14
15 return 1;
16}
17
18int dump_task_fpu(struct task_struct *tsk, elf_fpregset_t *fpu)
19{
20 int fpvalid = 0;
21
22#if defined(CONFIG_SH_FPU)
23 fpvalid = !!tsk_used_math(tsk);
24 if (fpvalid) {
25 unlazy_fpu(tsk, task_pt_regs(tsk));
26 memcpy(fpu, &tsk->thread.fpu.hard, sizeof(*fpu));
27 }
28#endif
29
30 return fpvalid;
31}
32
diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S
index efbb4268875e..1a5cf9dd82de 100644
--- a/arch/sh/kernel/entry-common.S
+++ b/arch/sh/kernel/entry-common.S
@@ -371,3 +371,47 @@ syscall_exit:
371#endif 371#endif
3727: .long do_syscall_trace_enter 3727: .long do_syscall_trace_enter
3738: .long do_syscall_trace_leave 3738: .long do_syscall_trace_leave
374
375#ifdef CONFIG_FTRACE
376 .align 2
377 .globl _mcount
378 .type _mcount,@function
379 .globl mcount
380 .type mcount,@function
381_mcount:
382mcount:
383 mov.l r4, @-r15
384 mov.l r5, @-r15
385 mov.l r6, @-r15
386 mov.l r7, @-r15
387 sts.l pr, @-r15
388
389 mov.l @(20,r15),r4
390 sts pr, r5
391
392 mov.l 1f, r6
393 mov.l ftrace_stub, r7
394 cmp/eq r6, r7
395 bt skip_trace
396
397 mov.l @r6, r6
398 jsr @r6
399 nop
400
401skip_trace:
402
403 lds.l @r15+, pr
404 mov.l @r15+, r7
405 mov.l @r15+, r6
406 mov.l @r15+, r5
407 rts
408 mov.l @r15+, r4
409
410 .align 2
4111: .long ftrace_trace_function
412
413 .globl ftrace_stub
414ftrace_stub:
415 rts
416 nop
417#endif /* CONFIG_FTRACE */
diff --git a/arch/sh/kernel/gpio.c b/arch/sh/kernel/gpio.c
new file mode 100644
index 000000000000..bb8b812c6895
--- /dev/null
+++ b/arch/sh/kernel/gpio.c
@@ -0,0 +1,498 @@
1/*
2 * Pinmuxed GPIO support for SuperH.
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/errno.h>
12#include <linux/kernel.h>
13#include <linux/list.h>
14#include <linux/module.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/bitops.h>
20#include <linux/gpio.h>
21
22static struct pinmux_info *registered_gpio;
23
24static struct pinmux_info *gpio_controller(unsigned gpio)
25{
26 if (!registered_gpio)
27 return NULL;
28
29 if (gpio < registered_gpio->first_gpio)
30 return NULL;
31
32 if (gpio > registered_gpio->last_gpio)
33 return NULL;
34
35 return registered_gpio;
36}
37
38static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
39{
40 if (enum_id < r->begin)
41 return 0;
42
43 if (enum_id > r->end)
44 return 0;
45
46 return 1;
47}
48
49static int read_write_reg(unsigned long reg, unsigned long reg_width,
50 unsigned long field_width, unsigned long in_pos,
51 unsigned long value, int do_write)
52{
53 unsigned long data, mask, pos;
54
55 data = 0;
56 mask = (1 << field_width) - 1;
57 pos = reg_width - ((in_pos + 1) * field_width);
58
59#ifdef DEBUG
60 pr_info("%s, addr = %lx, value = %ld, pos = %ld, "
61 "r_width = %ld, f_width = %ld\n",
62 do_write ? "write" : "read", reg, value, pos,
63 reg_width, field_width);
64#endif
65
66 switch (reg_width) {
67 case 8:
68 data = ctrl_inb(reg);
69 break;
70 case 16:
71 data = ctrl_inw(reg);
72 break;
73 case 32:
74 data = ctrl_inl(reg);
75 break;
76 }
77
78 if (!do_write)
79 return (data >> pos) & mask;
80
81 data &= ~(mask << pos);
82 data |= value << pos;
83
84 switch (reg_width) {
85 case 8:
86 ctrl_outb(data, reg);
87 break;
88 case 16:
89 ctrl_outw(data, reg);
90 break;
91 case 32:
92 ctrl_outl(data, reg);
93 break;
94 }
95 return 0;
96}
97
98static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
99 struct pinmux_data_reg **drp, int *bitp)
100{
101 pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
102 struct pinmux_data_reg *data_reg;
103 int k, n;
104
105 if (!enum_in_range(enum_id, &gpioc->data))
106 return -1;
107
108 k = 0;
109 while (1) {
110 data_reg = gpioc->data_regs + k;
111
112 if (!data_reg->reg_width)
113 break;
114
115 for (n = 0; n < data_reg->reg_width; n++) {
116 if (data_reg->enum_ids[n] == enum_id) {
117 *drp = data_reg;
118 *bitp = n;
119 return 0;
120
121 }
122 }
123 k++;
124 }
125
126 return -1;
127}
128
129static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
130 struct pinmux_cfg_reg **crp, int *indexp,
131 unsigned long **cntp)
132{
133 struct pinmux_cfg_reg *config_reg;
134 unsigned long r_width, f_width;
135 int k, n;
136
137 k = 0;
138 while (1) {
139 config_reg = gpioc->cfg_regs + k;
140
141 r_width = config_reg->reg_width;
142 f_width = config_reg->field_width;
143
144 if (!r_width)
145 break;
146 for (n = 0; n < (r_width / f_width) * 1 << f_width; n++) {
147 if (config_reg->enum_ids[n] == enum_id) {
148 *crp = config_reg;
149 *indexp = n;
150 *cntp = &config_reg->cnt[n / (1 << f_width)];
151 return 0;
152 }
153 }
154 k++;
155 }
156
157 return -1;
158}
159
160static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
161 int pos, pinmux_enum_t *enum_idp)
162{
163 pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
164 pinmux_enum_t *data = gpioc->gpio_data;
165 int k;
166
167 if (!enum_in_range(enum_id, &gpioc->data)) {
168 if (!enum_in_range(enum_id, &gpioc->mark)) {
169 pr_err("non data/mark enum_id for gpio %d\n", gpio);
170 return -1;
171 }
172 }
173
174 if (pos) {
175 *enum_idp = data[pos + 1];
176 return pos + 1;
177 }
178
179 for (k = 0; k < gpioc->gpio_data_size; k++) {
180 if (data[k] == enum_id) {
181 *enum_idp = data[k + 1];
182 return k + 1;
183 }
184 }
185
186 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
187 return -1;
188}
189
190static int write_config_reg(struct pinmux_info *gpioc,
191 struct pinmux_cfg_reg *crp,
192 int index)
193{
194 unsigned long ncomb, pos, value;
195
196 ncomb = 1 << crp->field_width;
197 pos = index / ncomb;
198 value = index % ncomb;
199
200 return read_write_reg(crp->reg, crp->reg_width,
201 crp->field_width, pos, value, 1);
202}
203
204static int check_config_reg(struct pinmux_info *gpioc,
205 struct pinmux_cfg_reg *crp,
206 int index)
207{
208 unsigned long ncomb, pos, value;
209
210 ncomb = 1 << crp->field_width;
211 pos = index / ncomb;
212 value = index % ncomb;
213
214 if (read_write_reg(crp->reg, crp->reg_width,
215 crp->field_width, pos, 0, 0) == value)
216 return 0;
217
218 return -1;
219}
220
221enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
222
223int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
224 int pinmux_type, int cfg_mode)
225{
226 struct pinmux_cfg_reg *cr = NULL;
227 pinmux_enum_t enum_id;
228 struct pinmux_range *range;
229 int in_range, pos, index;
230 unsigned long *cntp;
231
232 switch (pinmux_type) {
233
234 case PINMUX_TYPE_FUNCTION:
235 range = NULL;
236 break;
237
238 case PINMUX_TYPE_OUTPUT:
239 range = &gpioc->output;
240 break;
241
242 case PINMUX_TYPE_INPUT:
243 range = &gpioc->input;
244 break;
245
246 case PINMUX_TYPE_INPUT_PULLUP:
247 range = &gpioc->input_pu;
248 break;
249
250 case PINMUX_TYPE_INPUT_PULLDOWN:
251 range = &gpioc->input_pd;
252 break;
253
254 default:
255 goto out_err;
256 }
257
258 pos = 0;
259 enum_id = 0;
260 index = 0;
261 while (1) {
262 pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
263 if (pos <= 0)
264 goto out_err;
265
266 if (!enum_id)
267 break;
268
269 in_range = enum_in_range(enum_id, &gpioc->function);
270 if (!in_range && range)
271 in_range = enum_in_range(enum_id, range);
272
273 if (!in_range)
274 continue;
275
276 if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0)
277 goto out_err;
278
279 switch (cfg_mode) {
280 case GPIO_CFG_DRYRUN:
281 if (!*cntp || !check_config_reg(gpioc, cr, index))
282 continue;
283 break;
284
285 case GPIO_CFG_REQ:
286 if (write_config_reg(gpioc, cr, index) != 0)
287 goto out_err;
288 *cntp = *cntp + 1;
289 break;
290
291 case GPIO_CFG_FREE:
292 *cntp = *cntp - 1;
293 break;
294 }
295 }
296
297 return 0;
298 out_err:
299 return -1;
300}
301
302static DEFINE_SPINLOCK(gpio_lock);
303
304int __gpio_request(unsigned gpio)
305{
306 struct pinmux_info *gpioc = gpio_controller(gpio);
307 struct pinmux_data_reg *dummy;
308 unsigned long flags;
309 int i, ret, pinmux_type;
310
311 ret = -EINVAL;
312
313 if (!gpioc)
314 goto err_out;
315
316 spin_lock_irqsave(&gpio_lock, flags);
317
318 if ((gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
319 goto err_unlock;
320
321 /* setup pin function here if no data is associated with pin */
322
323 if (get_data_reg(gpioc, gpio, &dummy, &i) != 0)
324 pinmux_type = PINMUX_TYPE_FUNCTION;
325 else
326 pinmux_type = PINMUX_TYPE_GPIO;
327
328 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
329 if (pinmux_config_gpio(gpioc, gpio,
330 pinmux_type,
331 GPIO_CFG_DRYRUN) != 0)
332 goto err_unlock;
333
334 if (pinmux_config_gpio(gpioc, gpio,
335 pinmux_type,
336 GPIO_CFG_REQ) != 0)
337 BUG();
338 }
339
340 gpioc->gpios[gpio].flags = pinmux_type;
341
342 ret = 0;
343 err_unlock:
344 spin_unlock_irqrestore(&gpio_lock, flags);
345 err_out:
346 return ret;
347}
348EXPORT_SYMBOL(__gpio_request);
349
350void gpio_free(unsigned gpio)
351{
352 struct pinmux_info *gpioc = gpio_controller(gpio);
353 unsigned long flags;
354 int pinmux_type;
355
356 if (!gpioc)
357 return;
358
359 spin_lock_irqsave(&gpio_lock, flags);
360
361 pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
362 pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
363 gpioc->gpios[gpio].flags = PINMUX_TYPE_NONE;
364
365 spin_unlock_irqrestore(&gpio_lock, flags);
366}
367EXPORT_SYMBOL(gpio_free);
368
369static int pinmux_direction(struct pinmux_info *gpioc,
370 unsigned gpio, int new_pinmux_type)
371{
372 int ret, pinmux_type;
373
374 ret = -EINVAL;
375 pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
376
377 switch (pinmux_type) {
378 case PINMUX_TYPE_GPIO:
379 break;
380 case PINMUX_TYPE_OUTPUT:
381 case PINMUX_TYPE_INPUT:
382 case PINMUX_TYPE_INPUT_PULLUP:
383 case PINMUX_TYPE_INPUT_PULLDOWN:
384 pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
385 break;
386 default:
387 goto err_out;
388 }
389
390 if (pinmux_config_gpio(gpioc, gpio,
391 new_pinmux_type,
392 GPIO_CFG_DRYRUN) != 0)
393 goto err_out;
394
395 if (pinmux_config_gpio(gpioc, gpio,
396 new_pinmux_type,
397 GPIO_CFG_REQ) != 0)
398 BUG();
399
400 gpioc->gpios[gpio].flags = new_pinmux_type;
401
402 ret = 0;
403 err_out:
404 return ret;
405}
406
407int gpio_direction_input(unsigned gpio)
408{
409 struct pinmux_info *gpioc = gpio_controller(gpio);
410 unsigned long flags;
411 int ret = -EINVAL;
412
413 if (!gpioc)
414 goto err_out;
415
416 spin_lock_irqsave(&gpio_lock, flags);
417 ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_INPUT);
418 spin_unlock_irqrestore(&gpio_lock, flags);
419 err_out:
420 return ret;
421}
422EXPORT_SYMBOL(gpio_direction_input);
423
424static int __gpio_get_set_value(struct pinmux_info *gpioc,
425 unsigned gpio, int value,
426 int do_write)
427{
428 struct pinmux_data_reg *dr = NULL;
429 int bit = 0;
430
431 if (get_data_reg(gpioc, gpio, &dr, &bit) != 0)
432 BUG();
433 else
434 value = read_write_reg(dr->reg, dr->reg_width,
435 1, bit, value, do_write);
436
437 return value;
438}
439
440int gpio_direction_output(unsigned gpio, int value)
441{
442 struct pinmux_info *gpioc = gpio_controller(gpio);
443 unsigned long flags;
444 int ret = -EINVAL;
445
446 if (!gpioc)
447 goto err_out;
448
449 spin_lock_irqsave(&gpio_lock, flags);
450 __gpio_get_set_value(gpioc, gpio, value, 1);
451 ret = pinmux_direction(gpioc, gpio, PINMUX_TYPE_OUTPUT);
452 spin_unlock_irqrestore(&gpio_lock, flags);
453 err_out:
454 return ret;
455}
456EXPORT_SYMBOL(gpio_direction_output);
457
458int gpio_get_value(unsigned gpio)
459{
460 struct pinmux_info *gpioc = gpio_controller(gpio);
461 unsigned long flags;
462 int value = 0;
463
464 if (!gpioc)
465 BUG();
466 else {
467 spin_lock_irqsave(&gpio_lock, flags);
468 value = __gpio_get_set_value(gpioc, gpio, 0, 0);
469 spin_unlock_irqrestore(&gpio_lock, flags);
470 }
471
472 return value;
473}
474EXPORT_SYMBOL(gpio_get_value);
475
476void gpio_set_value(unsigned gpio, int value)
477{
478 struct pinmux_info *gpioc = gpio_controller(gpio);
479 unsigned long flags;
480
481 if (!gpioc)
482 BUG();
483 else {
484 spin_lock_irqsave(&gpio_lock, flags);
485 __gpio_get_set_value(gpioc, gpio, value, 1);
486 spin_unlock_irqrestore(&gpio_lock, flags);
487 }
488}
489EXPORT_SYMBOL(gpio_set_value);
490
491int register_pinmux(struct pinmux_info *pip)
492{
493 registered_gpio = pip;
494 pr_info("pinmux: %s handling gpio %d -> %d\n",
495 pip->name, pip->first_gpio, pip->last_gpio);
496
497 return 0;
498}
diff --git a/arch/sh/kernel/io.c b/arch/sh/kernel/io.c
index 2b8991229900..29cf4588fc05 100644
--- a/arch/sh/kernel/io.c
+++ b/arch/sh/kernel/io.c
@@ -19,12 +19,12 @@
19 * Copy data from IO memory space to "real" memory space. 19 * Copy data from IO memory space to "real" memory space.
20 * This needs to be optimized. 20 * This needs to be optimized.
21 */ 21 */
22void memcpy_fromio(void *to, volatile void __iomem *from, unsigned long count) 22void memcpy_fromio(void *to, const volatile void __iomem *from, unsigned long count)
23{ 23{
24 char *p = to; 24 unsigned char *p = to;
25 while (count) { 25 while (count) {
26 count--; 26 count--;
27 *p = readb((void __iomem *)from); 27 *p = readb(from);
28 p++; 28 p++;
29 from++; 29 from++;
30 } 30 }
@@ -37,10 +37,10 @@ EXPORT_SYMBOL(memcpy_fromio);
37 */ 37 */
38void memcpy_toio(volatile void __iomem *to, const void *from, unsigned long count) 38void memcpy_toio(volatile void __iomem *to, const void *from, unsigned long count)
39{ 39{
40 const char *p = from; 40 const unsigned char *p = from;
41 while (count) { 41 while (count) {
42 count--; 42 count--;
43 writeb(*p, (void __iomem *)to); 43 writeb(*p, to);
44 p++; 44 p++;
45 to++; 45 to++;
46 } 46 }
@@ -55,7 +55,7 @@ void memset_io(volatile void __iomem *dst, int c, unsigned long count)
55{ 55{
56 while (count) { 56 while (count) {
57 count--; 57 count--;
58 writeb(c, (void __iomem *)dst); 58 writeb(c, dst);
59 dst++; 59 dst++;
60 } 60 }
61} 61}
diff --git a/arch/sh/kernel/io_generic.c b/arch/sh/kernel/io_generic.c
index db769449f5a7..5a7f554d9ca1 100644
--- a/arch/sh/kernel/io_generic.c
+++ b/arch/sh/kernel/io_generic.c
@@ -19,38 +19,33 @@
19/* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a 19/* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a
20 * workaround. */ 20 * workaround. */
21/* I'm not sure SH7709 has this kind of bug */ 21/* I'm not sure SH7709 has this kind of bug */
22#define dummy_read() ctrl_inb(0xba000000) 22#define dummy_read() __raw_readb(0xba000000)
23#else 23#else
24#define dummy_read() 24#define dummy_read()
25#endif 25#endif
26 26
27unsigned long generic_io_base; 27unsigned long generic_io_base;
28 28
29static inline void delay(void)
30{
31 ctrl_inw(0xa0000000);
32}
33
34u8 generic_inb(unsigned long port) 29u8 generic_inb(unsigned long port)
35{ 30{
36 return ctrl_inb((unsigned long __force)__ioport_map(port, 1)); 31 return __raw_readb(__ioport_map(port, 1));
37} 32}
38 33
39u16 generic_inw(unsigned long port) 34u16 generic_inw(unsigned long port)
40{ 35{
41 return ctrl_inw((unsigned long __force)__ioport_map(port, 2)); 36 return __raw_readw(__ioport_map(port, 2));
42} 37}
43 38
44u32 generic_inl(unsigned long port) 39u32 generic_inl(unsigned long port)
45{ 40{
46 return ctrl_inl((unsigned long __force)__ioport_map(port, 4)); 41 return __raw_readl(__ioport_map(port, 4));
47} 42}
48 43
49u8 generic_inb_p(unsigned long port) 44u8 generic_inb_p(unsigned long port)
50{ 45{
51 unsigned long v = generic_inb(port); 46 unsigned long v = generic_inb(port);
52 47
53 delay(); 48 ctrl_delay();
54 return v; 49 return v;
55} 50}
56 51
@@ -58,7 +53,7 @@ u16 generic_inw_p(unsigned long port)
58{ 53{
59 unsigned long v = generic_inw(port); 54 unsigned long v = generic_inw(port);
60 55
61 delay(); 56 ctrl_delay();
62 return v; 57 return v;
63} 58}
64 59
@@ -66,7 +61,7 @@ u32 generic_inl_p(unsigned long port)
66{ 61{
67 unsigned long v = generic_inl(port); 62 unsigned long v = generic_inl(port);
68 63
69 delay(); 64 ctrl_delay();
70 return v; 65 return v;
71} 66}
72 67
@@ -81,7 +76,7 @@ void generic_insb(unsigned long port, void *dst, unsigned long count)
81 volatile u8 *port_addr; 76 volatile u8 *port_addr;
82 u8 *buf = dst; 77 u8 *buf = dst;
83 78
84 port_addr = (volatile u8 *)__ioport_map(port, 1); 79 port_addr = (volatile u8 __force *)__ioport_map(port, 1);
85 while (count--) 80 while (count--)
86 *buf++ = *port_addr; 81 *buf++ = *port_addr;
87} 82}
@@ -91,7 +86,7 @@ void generic_insw(unsigned long port, void *dst, unsigned long count)
91 volatile u16 *port_addr; 86 volatile u16 *port_addr;
92 u16 *buf = dst; 87 u16 *buf = dst;
93 88
94 port_addr = (volatile u16 *)__ioport_map(port, 2); 89 port_addr = (volatile u16 __force *)__ioport_map(port, 2);
95 while (count--) 90 while (count--)
96 *buf++ = *port_addr; 91 *buf++ = *port_addr;
97 92
@@ -103,7 +98,7 @@ void generic_insl(unsigned long port, void *dst, unsigned long count)
103 volatile u32 *port_addr; 98 volatile u32 *port_addr;
104 u32 *buf = dst; 99 u32 *buf = dst;
105 100
106 port_addr = (volatile u32 *)__ioport_map(port, 4); 101 port_addr = (volatile u32 __force *)__ioport_map(port, 4);
107 while (count--) 102 while (count--)
108 *buf++ = *port_addr; 103 *buf++ = *port_addr;
109 104
@@ -112,35 +107,35 @@ void generic_insl(unsigned long port, void *dst, unsigned long count)
112 107
113void generic_outb(u8 b, unsigned long port) 108void generic_outb(u8 b, unsigned long port)
114{ 109{
115 ctrl_outb(b, (unsigned long __force)__ioport_map(port, 1)); 110 __raw_writeb(b, __ioport_map(port, 1));
116} 111}
117 112
118void generic_outw(u16 b, unsigned long port) 113void generic_outw(u16 b, unsigned long port)
119{ 114{
120 ctrl_outw(b, (unsigned long __force)__ioport_map(port, 2)); 115 __raw_writew(b, __ioport_map(port, 2));
121} 116}
122 117
123void generic_outl(u32 b, unsigned long port) 118void generic_outl(u32 b, unsigned long port)
124{ 119{
125 ctrl_outl(b, (unsigned long __force)__ioport_map(port, 4)); 120 __raw_writel(b, __ioport_map(port, 4));
126} 121}
127 122
128void generic_outb_p(u8 b, unsigned long port) 123void generic_outb_p(u8 b, unsigned long port)
129{ 124{
130 generic_outb(b, port); 125 generic_outb(b, port);
131 delay(); 126 ctrl_delay();
132} 127}
133 128
134void generic_outw_p(u16 b, unsigned long port) 129void generic_outw_p(u16 b, unsigned long port)
135{ 130{
136 generic_outw(b, port); 131 generic_outw(b, port);
137 delay(); 132 ctrl_delay();
138} 133}
139 134
140void generic_outl_p(u32 b, unsigned long port) 135void generic_outl_p(u32 b, unsigned long port)
141{ 136{
142 generic_outl(b, port); 137 generic_outl(b, port);
143 delay(); 138 ctrl_delay();
144} 139}
145 140
146/* 141/*
@@ -184,36 +179,6 @@ void generic_outsl(unsigned long port, const void *src, unsigned long count)
184 dummy_read(); 179 dummy_read();
185} 180}
186 181
187u8 generic_readb(void __iomem *addr)
188{
189 return ctrl_inb((unsigned long __force)addr);
190}
191
192u16 generic_readw(void __iomem *addr)
193{
194 return ctrl_inw((unsigned long __force)addr);
195}
196
197u32 generic_readl(void __iomem *addr)
198{
199 return ctrl_inl((unsigned long __force)addr);
200}
201
202void generic_writeb(u8 b, void __iomem *addr)
203{
204 ctrl_outb(b, (unsigned long __force)addr);
205}
206
207void generic_writew(u16 b, void __iomem *addr)
208{
209 ctrl_outw(b, (unsigned long __force)addr);
210}
211
212void generic_writel(u32 b, void __iomem *addr)
213{
214 ctrl_outl(b, (unsigned long __force)addr);
215}
216
217void __iomem *generic_ioport_map(unsigned long addr, unsigned int size) 182void __iomem *generic_ioport_map(unsigned long addr, unsigned int size)
218{ 183{
219 return (void __iomem *)(addr + generic_io_base); 184 return (void __iomem *)(addr + generic_io_base);
diff --git a/arch/sh/kernel/kprobes.c b/arch/sh/kernel/kprobes.c
new file mode 100644
index 000000000000..c96850b061fb
--- /dev/null
+++ b/arch/sh/kernel/kprobes.c
@@ -0,0 +1,584 @@
1/*
2 * Kernel probes (kprobes) for SuperH
3 *
4 * Copyright (C) 2007 Chris Smith <chris.smith@st.com>
5 * Copyright (C) 2006 Lineo Solutions, Inc.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/kprobes.h>
12#include <linux/module.h>
13#include <linux/ptrace.h>
14#include <linux/preempt.h>
15#include <linux/kdebug.h>
16#include <asm/cacheflush.h>
17#include <asm/uaccess.h>
18
19DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL;
20DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
21
22static struct kprobe saved_current_opcode;
23static struct kprobe saved_next_opcode;
24static struct kprobe saved_next_opcode2;
25
26#define OPCODE_JMP(x) (((x) & 0xF0FF) == 0x402b)
27#define OPCODE_JSR(x) (((x) & 0xF0FF) == 0x400b)
28#define OPCODE_BRA(x) (((x) & 0xF000) == 0xa000)
29#define OPCODE_BRAF(x) (((x) & 0xF0FF) == 0x0023)
30#define OPCODE_BSR(x) (((x) & 0xF000) == 0xb000)
31#define OPCODE_BSRF(x) (((x) & 0xF0FF) == 0x0003)
32
33#define OPCODE_BF_S(x) (((x) & 0xFF00) == 0x8f00)
34#define OPCODE_BT_S(x) (((x) & 0xFF00) == 0x8d00)
35
36#define OPCODE_BF(x) (((x) & 0xFF00) == 0x8b00)
37#define OPCODE_BT(x) (((x) & 0xFF00) == 0x8900)
38
39#define OPCODE_RTS(x) (((x) & 0x000F) == 0x000b)
40#define OPCODE_RTE(x) (((x) & 0xFFFF) == 0x002b)
41
42int __kprobes arch_prepare_kprobe(struct kprobe *p)
43{
44 kprobe_opcode_t opcode = *(kprobe_opcode_t *) (p->addr);
45
46 if (OPCODE_RTE(opcode))
47 return -EFAULT; /* Bad breakpoint */
48
49 p->opcode = opcode;
50
51 return 0;
52}
53
54void __kprobes arch_copy_kprobe(struct kprobe *p)
55{
56 memcpy(p->ainsn.insn, p->addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
57 p->opcode = *p->addr;
58}
59
60void __kprobes arch_arm_kprobe(struct kprobe *p)
61{
62 *p->addr = BREAKPOINT_INSTRUCTION;
63 flush_icache_range((unsigned long)p->addr,
64 (unsigned long)p->addr + sizeof(kprobe_opcode_t));
65}
66
67void __kprobes arch_disarm_kprobe(struct kprobe *p)
68{
69 *p->addr = p->opcode;
70 flush_icache_range((unsigned long)p->addr,
71 (unsigned long)p->addr + sizeof(kprobe_opcode_t));
72}
73
74int __kprobes arch_trampoline_kprobe(struct kprobe *p)
75{
76 if (*p->addr == BREAKPOINT_INSTRUCTION)
77 return 1;
78
79 return 0;
80}
81
82/**
83 * If an illegal slot instruction exception occurs for an address
84 * containing a kprobe, remove the probe.
85 *
86 * Returns 0 if the exception was handled successfully, 1 otherwise.
87 */
88int __kprobes kprobe_handle_illslot(unsigned long pc)
89{
90 struct kprobe *p = get_kprobe((kprobe_opcode_t *) pc + 1);
91
92 if (p != NULL) {
93 printk("Warning: removing kprobe from delay slot: 0x%.8x\n",
94 (unsigned int)pc + 2);
95 unregister_kprobe(p);
96 return 0;
97 }
98
99 return 1;
100}
101
102void __kprobes arch_remove_kprobe(struct kprobe *p)
103{
104 if (saved_next_opcode.addr != 0x0) {
105 arch_disarm_kprobe(p);
106 arch_disarm_kprobe(&saved_next_opcode);
107 saved_next_opcode.addr = 0x0;
108 saved_next_opcode.opcode = 0x0;
109
110 if (saved_next_opcode2.addr != 0x0) {
111 arch_disarm_kprobe(&saved_next_opcode2);
112 saved_next_opcode2.addr = 0x0;
113 saved_next_opcode2.opcode = 0x0;
114 }
115 }
116}
117
118static void __kprobes save_previous_kprobe(struct kprobe_ctlblk *kcb)
119{
120 kcb->prev_kprobe.kp = kprobe_running();
121 kcb->prev_kprobe.status = kcb->kprobe_status;
122}
123
124static void __kprobes restore_previous_kprobe(struct kprobe_ctlblk *kcb)
125{
126 __get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp;
127 kcb->kprobe_status = kcb->prev_kprobe.status;
128}
129
130static void __kprobes set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
131 struct kprobe_ctlblk *kcb)
132{
133 __get_cpu_var(current_kprobe) = p;
134}
135
136/*
137 * Singlestep is implemented by disabling the current kprobe and setting one
138 * on the next instruction, following branches. Two probes are set if the
139 * branch is conditional.
140 */
141static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
142{
143 kprobe_opcode_t *addr = NULL;
144 saved_current_opcode.addr = (kprobe_opcode_t *) (regs->pc);
145 addr = saved_current_opcode.addr;
146
147 if (p != NULL) {
148 arch_disarm_kprobe(p);
149
150 if (OPCODE_JSR(p->opcode) || OPCODE_JMP(p->opcode)) {
151 unsigned int reg_nr = ((p->opcode >> 8) & 0x000F);
152 saved_next_opcode.addr =
153 (kprobe_opcode_t *) regs->regs[reg_nr];
154 } else if (OPCODE_BRA(p->opcode) || OPCODE_BSR(p->opcode)) {
155 unsigned long disp = (p->opcode & 0x0FFF);
156 saved_next_opcode.addr =
157 (kprobe_opcode_t *) (regs->pc + 4 + disp * 2);
158
159 } else if (OPCODE_BRAF(p->opcode) || OPCODE_BSRF(p->opcode)) {
160 unsigned int reg_nr = ((p->opcode >> 8) & 0x000F);
161 saved_next_opcode.addr =
162 (kprobe_opcode_t *) (regs->pc + 4 +
163 regs->regs[reg_nr]);
164
165 } else if (OPCODE_RTS(p->opcode)) {
166 saved_next_opcode.addr = (kprobe_opcode_t *) regs->pr;
167
168 } else if (OPCODE_BF(p->opcode) || OPCODE_BT(p->opcode)) {
169 unsigned long disp = (p->opcode & 0x00FF);
170 /* case 1 */
171 saved_next_opcode.addr = p->addr + 1;
172 /* case 2 */
173 saved_next_opcode2.addr =
174 (kprobe_opcode_t *) (regs->pc + 4 + disp * 2);
175 saved_next_opcode2.opcode = *(saved_next_opcode2.addr);
176 arch_arm_kprobe(&saved_next_opcode2);
177
178 } else if (OPCODE_BF_S(p->opcode) || OPCODE_BT_S(p->opcode)) {
179 unsigned long disp = (p->opcode & 0x00FF);
180 /* case 1 */
181 saved_next_opcode.addr = p->addr + 2;
182 /* case 2 */
183 saved_next_opcode2.addr =
184 (kprobe_opcode_t *) (regs->pc + 4 + disp * 2);
185 saved_next_opcode2.opcode = *(saved_next_opcode2.addr);
186 arch_arm_kprobe(&saved_next_opcode2);
187
188 } else {
189 saved_next_opcode.addr = p->addr + 1;
190 }
191
192 saved_next_opcode.opcode = *(saved_next_opcode.addr);
193 arch_arm_kprobe(&saved_next_opcode);
194 }
195}
196
197/* Called with kretprobe_lock held */
198void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
199 struct pt_regs *regs)
200{
201 ri->ret_addr = (kprobe_opcode_t *) regs->pr;
202
203 /* Replace the return addr with trampoline addr */
204 regs->pr = (unsigned long)kretprobe_trampoline;
205}
206
207static int __kprobes kprobe_handler(struct pt_regs *regs)
208{
209 struct kprobe *p;
210 int ret = 0;
211 kprobe_opcode_t *addr = NULL;
212 struct kprobe_ctlblk *kcb;
213
214 /*
215 * We don't want to be preempted for the entire
216 * duration of kprobe processing
217 */
218 preempt_disable();
219 kcb = get_kprobe_ctlblk();
220
221 addr = (kprobe_opcode_t *) (regs->pc);
222
223 /* Check we're not actually recursing */
224 if (kprobe_running()) {
225 p = get_kprobe(addr);
226 if (p) {
227 if (kcb->kprobe_status == KPROBE_HIT_SS &&
228 *p->ainsn.insn == BREAKPOINT_INSTRUCTION) {
229 goto no_kprobe;
230 }
231 /* We have reentered the kprobe_handler(), since
232 * another probe was hit while within the handler.
233 * We here save the original kprobes variables and
234 * just single step on the instruction of the new probe
235 * without calling any user handlers.
236 */
237 save_previous_kprobe(kcb);
238 set_current_kprobe(p, regs, kcb);
239 kprobes_inc_nmissed_count(p);
240 prepare_singlestep(p, regs);
241 kcb->kprobe_status = KPROBE_REENTER;
242 return 1;
243 } else {
244 p = __get_cpu_var(current_kprobe);
245 if (p->break_handler && p->break_handler(p, regs)) {
246 goto ss_probe;
247 }
248 }
249 goto no_kprobe;
250 }
251
252 p = get_kprobe(addr);
253 if (!p) {
254 /* Not one of ours: let kernel handle it */
255 if (*(kprobe_opcode_t *)addr != BREAKPOINT_INSTRUCTION) {
256 /*
257 * The breakpoint instruction was removed right
258 * after we hit it. Another cpu has removed
259 * either a probepoint or a debugger breakpoint
260 * at this address. In either case, no further
261 * handling of this interrupt is appropriate.
262 */
263 ret = 1;
264 }
265
266 goto no_kprobe;
267 }
268
269 set_current_kprobe(p, regs, kcb);
270 kcb->kprobe_status = KPROBE_HIT_ACTIVE;
271
272 if (p->pre_handler && p->pre_handler(p, regs))
273 /* handler has already set things up, so skip ss setup */
274 return 1;
275
276ss_probe:
277 prepare_singlestep(p, regs);
278 kcb->kprobe_status = KPROBE_HIT_SS;
279 return 1;
280
281no_kprobe:
282 preempt_enable_no_resched();
283 return ret;
284}
285
286/*
287 * For function-return probes, init_kprobes() establishes a probepoint
288 * here. When a retprobed function returns, this probe is hit and
289 * trampoline_probe_handler() runs, calling the kretprobe's handler.
290 */
291static void __used kretprobe_trampoline_holder(void)
292{
293 asm volatile (".globl kretprobe_trampoline\n"
294 "kretprobe_trampoline:\n\t"
295 "nop\n");
296}
297
298/*
299 * Called when we hit the probe point at kretprobe_trampoline
300 */
301int __kprobes trampoline_probe_handler(struct kprobe *p, struct pt_regs *regs)
302{
303 struct kretprobe_instance *ri = NULL;
304 struct hlist_head *head, empty_rp;
305 struct hlist_node *node, *tmp;
306 unsigned long flags, orig_ret_address = 0;
307 unsigned long trampoline_address = (unsigned long)&kretprobe_trampoline;
308
309 INIT_HLIST_HEAD(&empty_rp);
310 kretprobe_hash_lock(current, &head, &flags);
311
312 /*
313 * It is possible to have multiple instances associated with a given
314 * task either because an multiple functions in the call path
315 * have a return probe installed on them, and/or more then one return
316 * return probe was registered for a target function.
317 *
318 * We can handle this because:
319 * - instances are always inserted at the head of the list
320 * - when multiple return probes are registered for the same
321 * function, the first instance's ret_addr will point to the
322 * real return address, and all the rest will point to
323 * kretprobe_trampoline
324 */
325 hlist_for_each_entry_safe(ri, node, tmp, head, hlist) {
326 if (ri->task != current)
327 /* another task is sharing our hash bucket */
328 continue;
329
330 if (ri->rp && ri->rp->handler) {
331 __get_cpu_var(current_kprobe) = &ri->rp->kp;
332 ri->rp->handler(ri, regs);
333 __get_cpu_var(current_kprobe) = NULL;
334 }
335
336 orig_ret_address = (unsigned long)ri->ret_addr;
337 recycle_rp_inst(ri, &empty_rp);
338
339 if (orig_ret_address != trampoline_address)
340 /*
341 * This is the real return address. Any other
342 * instances associated with this task are for
343 * other calls deeper on the call stack
344 */
345 break;
346 }
347
348 kretprobe_assert(ri, orig_ret_address, trampoline_address);
349
350 regs->pc = orig_ret_address;
351 kretprobe_hash_unlock(current, &flags);
352
353 preempt_enable_no_resched();
354
355 hlist_for_each_entry_safe(ri, node, tmp, &empty_rp, hlist) {
356 hlist_del(&ri->hlist);
357 kfree(ri);
358 }
359
360 return orig_ret_address;
361}
362
363static int __kprobes post_kprobe_handler(struct pt_regs *regs)
364{
365 struct kprobe *cur = kprobe_running();
366 struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
367 kprobe_opcode_t *addr = NULL;
368 struct kprobe *p = NULL;
369
370 if (!cur)
371 return 0;
372
373 if ((kcb->kprobe_status != KPROBE_REENTER) && cur->post_handler) {
374 kcb->kprobe_status = KPROBE_HIT_SSDONE;
375 cur->post_handler(cur, regs, 0);
376 }
377
378 if (saved_next_opcode.addr != 0x0) {
379 arch_disarm_kprobe(&saved_next_opcode);
380 saved_next_opcode.addr = 0x0;
381 saved_next_opcode.opcode = 0x0;
382
383 addr = saved_current_opcode.addr;
384 saved_current_opcode.addr = 0x0;
385
386 p = get_kprobe(addr);
387 arch_arm_kprobe(p);
388
389 if (saved_next_opcode2.addr != 0x0) {
390 arch_disarm_kprobe(&saved_next_opcode2);
391 saved_next_opcode2.addr = 0x0;
392 saved_next_opcode2.opcode = 0x0;
393 }
394 }
395
396 /* Restore back the original saved kprobes variables and continue. */
397 if (kcb->kprobe_status == KPROBE_REENTER) {
398 restore_previous_kprobe(kcb);
399 goto out;
400 }
401
402 reset_current_kprobe();
403
404out:
405 preempt_enable_no_resched();
406
407 return 1;
408}
409
410int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr)
411{
412 struct kprobe *cur = kprobe_running();
413 struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
414 const struct exception_table_entry *entry;
415
416 switch (kcb->kprobe_status) {
417 case KPROBE_HIT_SS:
418 case KPROBE_REENTER:
419 /*
420 * We are here because the instruction being single
421 * stepped caused a page fault. We reset the current
422 * kprobe, point the pc back to the probe address
423 * and allow the page fault handler to continue as a
424 * normal page fault.
425 */
426 regs->pc = (unsigned long)cur->addr;
427 if (kcb->kprobe_status == KPROBE_REENTER)
428 restore_previous_kprobe(kcb);
429 else
430 reset_current_kprobe();
431 preempt_enable_no_resched();
432 break;
433 case KPROBE_HIT_ACTIVE:
434 case KPROBE_HIT_SSDONE:
435 /*
436 * We increment the nmissed count for accounting,
437 * we can also use npre/npostfault count for accounting
438 * these specific fault cases.
439 */
440 kprobes_inc_nmissed_count(cur);
441
442 /*
443 * We come here because instructions in the pre/post
444 * handler caused the page_fault, this could happen
445 * if handler tries to access user space by
446 * copy_from_user(), get_user() etc. Let the
447 * user-specified handler try to fix it first.
448 */
449 if (cur->fault_handler && cur->fault_handler(cur, regs, trapnr))
450 return 1;
451
452 /*
453 * In case the user-specified fault handler returned
454 * zero, try to fix up.
455 */
456 if ((entry = search_exception_tables(regs->pc)) != NULL) {
457 regs->pc = entry->fixup;
458 return 1;
459 }
460
461 /*
462 * fixup_exception() could not handle it,
463 * Let do_page_fault() fix it.
464 */
465 break;
466 default:
467 break;
468 }
469
470 return 0;
471}
472
473/*
474 * Wrapper routine to for handling exceptions.
475 */
476int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
477 unsigned long val, void *data)
478{
479 struct kprobe *p = NULL;
480 struct die_args *args = (struct die_args *)data;
481 int ret = NOTIFY_DONE;
482 kprobe_opcode_t *addr = NULL;
483 struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
484
485 addr = (kprobe_opcode_t *) (args->regs->pc);
486 if (val == DIE_TRAP) {
487 if (!kprobe_running()) {
488 if (kprobe_handler(args->regs)) {
489 ret = NOTIFY_STOP;
490 } else {
491 /* Not a kprobe trap */
492 ret = NOTIFY_DONE;
493 }
494 } else {
495 p = get_kprobe(addr);
496 if ((kcb->kprobe_status == KPROBE_HIT_SS) ||
497 (kcb->kprobe_status == KPROBE_REENTER)) {
498 if (post_kprobe_handler(args->regs))
499 ret = NOTIFY_STOP;
500 } else {
501 if (kprobe_handler(args->regs)) {
502 ret = NOTIFY_STOP;
503 } else {
504 p = __get_cpu_var(current_kprobe);
505 if (p->break_handler &&
506 p->break_handler(p, args->regs))
507 ret = NOTIFY_STOP;
508 }
509 }
510 }
511 }
512
513 return ret;
514}
515
516int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
517{
518 struct jprobe *jp = container_of(p, struct jprobe, kp);
519 unsigned long addr;
520 struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
521
522 kcb->jprobe_saved_regs = *regs;
523 kcb->jprobe_saved_r15 = regs->regs[15];
524 addr = kcb->jprobe_saved_r15;
525
526 /*
527 * TBD: As Linus pointed out, gcc assumes that the callee
528 * owns the argument space and could overwrite it, e.g.
529 * tailcall optimization. So, to be absolutely safe
530 * we also save and restore enough stack bytes to cover
531 * the argument area.
532 */
533 memcpy(kcb->jprobes_stack, (kprobe_opcode_t *) addr,
534 MIN_STACK_SIZE(addr));
535
536 regs->pc = (unsigned long)(jp->entry);
537
538 return 1;
539}
540
541void __kprobes jprobe_return(void)
542{
543 asm volatile ("trapa #0x3a\n\t" "jprobe_return_end:\n\t" "nop\n\t");
544}
545
546int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
547{
548 struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
549 unsigned long stack_addr = kcb->jprobe_saved_r15;
550 u8 *addr = (u8 *)regs->pc;
551
552 if ((addr >= (u8 *)jprobe_return) &&
553 (addr <= (u8 *)jprobe_return_end)) {
554 *regs = kcb->jprobe_saved_regs;
555
556 memcpy((kprobe_opcode_t *)stack_addr, kcb->jprobes_stack,
557 MIN_STACK_SIZE(stack_addr));
558
559 kcb->kprobe_status = KPROBE_HIT_SS;
560 preempt_enable_no_resched();
561 return 1;
562 }
563
564 return 0;
565}
566
567static struct kprobe trampoline_p = {
568 .addr = (kprobe_opcode_t *)&kretprobe_trampoline,
569 .pre_handler = trampoline_probe_handler
570};
571
572int __init arch_init_kprobes(void)
573{
574 saved_next_opcode.addr = 0x0;
575 saved_next_opcode.opcode = 0x0;
576
577 saved_current_opcode.addr = 0x0;
578 saved_current_opcode.opcode = 0x0;
579
580 saved_next_opcode2.addr = 0x0;
581 saved_next_opcode2.opcode = 0x0;
582
583 return register_kprobe(&trampoline_p);
584}
diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c
index 129b2cfd18a8..c1ea41e5812a 100644
--- a/arch/sh/kernel/machvec.c
+++ b/arch/sh/kernel/machvec.c
@@ -14,6 +14,7 @@
14#include <linux/string.h> 14#include <linux/string.h>
15#include <asm/machvec.h> 15#include <asm/machvec.h>
16#include <asm/sections.h> 16#include <asm/sections.h>
17#include <asm/setup.h>
17#include <asm/io.h> 18#include <asm/io.h>
18#include <asm/irq.h> 19#include <asm/irq.h>
19 20
@@ -125,9 +126,6 @@ void __init sh_mv_setup(void)
125 mv_set(insb); mv_set(insw); mv_set(insl); 126 mv_set(insb); mv_set(insw); mv_set(insl);
126 mv_set(outsb); mv_set(outsw); mv_set(outsl); 127 mv_set(outsb); mv_set(outsw); mv_set(outsl);
127 128
128 mv_set(readb); mv_set(readw); mv_set(readl);
129 mv_set(writeb); mv_set(writew); mv_set(writel);
130
131 mv_set(ioport_map); 129 mv_set(ioport_map);
132 mv_set(ioport_unmap); 130 mv_set(ioport_unmap);
133 mv_set(irq_demux); 131 mv_set(irq_demux);
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index 3326a45749d9..b965f0282c7d 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -7,7 +7,11 @@
7 * 7 *
8 * SuperH version: Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima 8 * SuperH version: Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
9 * Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC 9 * Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
10 * Copyright (C) 2002 - 2007 Paul Mundt 10 * Copyright (C) 2002 - 2008 Paul Mundt
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
11 */ 15 */
12#include <linux/module.h> 16#include <linux/module.h>
13#include <linux/mm.h> 17#include <linux/mm.h>
@@ -26,6 +30,7 @@
26#include <asm/system.h> 30#include <asm/system.h>
27#include <asm/ubc.h> 31#include <asm/ubc.h>
28#include <asm/fpu.h> 32#include <asm/fpu.h>
33#include <asm/syscalls.h>
29 34
30static int hlt_counter; 35static int hlt_counter;
31int ubc_usercnt = 0; 36int ubc_usercnt = 0;
@@ -111,15 +116,21 @@ void show_regs(struct pt_regs * regs)
111{ 116{
112 printk("\n"); 117 printk("\n");
113 printk("Pid : %d, Comm: %20s\n", task_pid_nr(current), current->comm); 118 printk("Pid : %d, Comm: %20s\n", task_pid_nr(current), current->comm);
119 printk("CPU : %d %s (%s %.*s)\n",
120 smp_processor_id(), print_tainted(), init_utsname()->release,
121 (int)strcspn(init_utsname()->version, " "),
122 init_utsname()->version);
123
114 print_symbol("PC is at %s\n", instruction_pointer(regs)); 124 print_symbol("PC is at %s\n", instruction_pointer(regs));
125 print_symbol("PR is at %s\n", regs->pr);
126
115 printk("PC : %08lx SP : %08lx SR : %08lx ", 127 printk("PC : %08lx SP : %08lx SR : %08lx ",
116 regs->pc, regs->regs[15], regs->sr); 128 regs->pc, regs->regs[15], regs->sr);
117#ifdef CONFIG_MMU 129#ifdef CONFIG_MMU
118 printk("TEA : %08x ", ctrl_inl(MMU_TEA)); 130 printk("TEA : %08x\n", ctrl_inl(MMU_TEA));
119#else 131#else
120 printk(" "); 132 printk("\n");
121#endif 133#endif
122 printk("%s\n", print_tainted());
123 134
124 printk("R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n", 135 printk("R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
125 regs->regs[0],regs->regs[1], 136 regs->regs[0],regs->regs[1],
@@ -162,6 +173,7 @@ __asm__(".align 5\n"
162int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) 173int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
163{ 174{
164 struct pt_regs regs; 175 struct pt_regs regs;
176 int pid;
165 177
166 memset(&regs, 0, sizeof(regs)); 178 memset(&regs, 0, sizeof(regs));
167 regs.regs[4] = (unsigned long)arg; 179 regs.regs[4] = (unsigned long)arg;
@@ -171,8 +183,12 @@ int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
171 regs.sr = (1 << 30); 183 regs.sr = (1 << 30);
172 184
173 /* Ok, create the new process.. */ 185 /* Ok, create the new process.. */
174 return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, 186 pid = do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0,
175 &regs, 0, NULL, NULL); 187 &regs, 0, NULL, NULL);
188
189 trace_mark(kernel_arch_kthread_create, "pid %d fn %p", pid, fn);
190
191 return pid;
176} 192}
177 193
178/* 194/*
@@ -210,10 +226,10 @@ int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu)
210 struct task_struct *tsk = current; 226 struct task_struct *tsk = current;
211 227
212 fpvalid = !!tsk_used_math(tsk); 228 fpvalid = !!tsk_used_math(tsk);
213 if (fpvalid) { 229 if (fpvalid)
214 unlazy_fpu(tsk, regs); 230 fpvalid = !fpregs_get(tsk, NULL, 0,
215 memcpy(fpu, &tsk->thread.fpu.hard, sizeof(*fpu)); 231 sizeof(struct user_fpu_struct),
216 } 232 fpu, NULL);
217#endif 233#endif
218 234
219 return fpvalid; 235 return fpvalid;
diff --git a/arch/sh/kernel/process_64.c b/arch/sh/kernel/process_64.c
index b9dbd2d3b4a5..b7aa09235b51 100644
--- a/arch/sh/kernel/process_64.c
+++ b/arch/sh/kernel/process_64.c
@@ -25,6 +25,7 @@
25#include <linux/module.h> 25#include <linux/module.h>
26#include <linux/proc_fs.h> 26#include <linux/proc_fs.h>
27#include <linux/io.h> 27#include <linux/io.h>
28#include <asm/syscalls.h>
28#include <asm/uaccess.h> 29#include <asm/uaccess.h>
29#include <asm/pgtable.h> 30#include <asm/pgtable.h>
30#include <asm/mmu_context.h> 31#include <asm/mmu_context.h>
@@ -395,6 +396,7 @@ ATTRIB_NORET void kernel_thread_helper(void *arg, int (*fn)(void *))
395int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags) 396int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
396{ 397{
397 struct pt_regs regs; 398 struct pt_regs regs;
399 int pid;
398 400
399 memset(&regs, 0, sizeof(regs)); 401 memset(&regs, 0, sizeof(regs));
400 regs.regs[2] = (unsigned long)arg; 402 regs.regs[2] = (unsigned long)arg;
@@ -403,8 +405,13 @@ int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
403 regs.pc = (unsigned long)kernel_thread_helper; 405 regs.pc = (unsigned long)kernel_thread_helper;
404 regs.sr = (1 << 30); 406 regs.sr = (1 << 30);
405 407
406 return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, 408 /* Ok, create the new process.. */
407 &regs, 0, NULL, NULL); 409 pid = do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0,
410 &regs, 0, NULL, NULL);
411
412 trace_mark(kernel_arch_kthread_create, "pid %d fn %p", pid, fn);
413
414 return pid;
408} 415}
409 416
410/* 417/*
diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c
index 035cb300d3dc..29ca09d24ef8 100644
--- a/arch/sh/kernel/ptrace_32.c
+++ b/arch/sh/kernel/ptrace_32.c
@@ -1,12 +1,14 @@
1/* 1/*
2 * linux/arch/sh/kernel/ptrace.c 2 * SuperH process tracing
3 * 3 *
4 * Original x86 implementation: 4 * Copyright (C) 1999, 2000 Kaz Kojima & Niibe Yutaka
5 * By Ross Biro 1/23/92 5 * Copyright (C) 2002 - 2008 Paul Mundt
6 * edited by Linus Torvalds
7 * 6 *
8 * SuperH version: Copyright (C) 1999, 2000 Kaz Kojima & Niibe Yutaka 7 * Audit support by Yuichi Nakamura <ynakam@hitachisoft.jp>
9 * Audit support: Yuichi Nakamura <ynakam@hitachisoft.jp> 8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
10 */ 12 */
11#include <linux/kernel.h> 13#include <linux/kernel.h>
12#include <linux/sched.h> 14#include <linux/sched.h>
@@ -22,16 +24,15 @@
22#include <linux/audit.h> 24#include <linux/audit.h>
23#include <linux/seccomp.h> 25#include <linux/seccomp.h>
24#include <linux/tracehook.h> 26#include <linux/tracehook.h>
27#include <linux/elf.h>
28#include <linux/regset.h>
25#include <asm/uaccess.h> 29#include <asm/uaccess.h>
26#include <asm/pgtable.h> 30#include <asm/pgtable.h>
27#include <asm/system.h> 31#include <asm/system.h>
28#include <asm/processor.h> 32#include <asm/processor.h>
29#include <asm/mmu_context.h> 33#include <asm/mmu_context.h>
30 34#include <asm/syscalls.h>
31/* 35#include <asm/fpu.h>
32 * does not yet catch signals sent when the child dies.
33 * in exit.c or in signal.c.
34 */
35 36
36/* 37/*
37 * This routine will get a word off of the process kernel stack. 38 * This routine will get a word off of the process kernel stack.
@@ -61,16 +62,12 @@ static inline int put_stack_long(struct task_struct *task, int offset,
61 62
62void user_enable_single_step(struct task_struct *child) 63void user_enable_single_step(struct task_struct *child)
63{ 64{
64 struct pt_regs *regs = task_pt_regs(child);
65 long pc;
66
67 pc = get_stack_long(child, (long)&regs->pc);
68
69 /* Next scheduling will set up UBC */ 65 /* Next scheduling will set up UBC */
70 if (child->thread.ubc_pc == 0) 66 if (child->thread.ubc_pc == 0)
71 ubc_usercnt += 1; 67 ubc_usercnt += 1;
72 68
73 child->thread.ubc_pc = pc; 69 child->thread.ubc_pc = get_stack_long(child,
70 offsetof(struct pt_regs, pc));
74 71
75 set_tsk_thread_flag(child, TIF_SINGLESTEP); 72 set_tsk_thread_flag(child, TIF_SINGLESTEP);
76} 73}
@@ -102,9 +99,213 @@ void ptrace_disable(struct task_struct *child)
102 user_disable_single_step(child); 99 user_disable_single_step(child);
103} 100}
104 101
102static int genregs_get(struct task_struct *target,
103 const struct user_regset *regset,
104 unsigned int pos, unsigned int count,
105 void *kbuf, void __user *ubuf)
106{
107 const struct pt_regs *regs = task_pt_regs(target);
108 int ret;
109
110 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
111 regs->regs,
112 0, 16 * sizeof(unsigned long));
113 if (!ret)
114 /* PC, PR, SR, GBR, MACH, MACL, TRA */
115 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
116 &regs->pc,
117 offsetof(struct pt_regs, pc),
118 sizeof(struct pt_regs));
119 if (!ret)
120 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
121 sizeof(struct pt_regs), -1);
122
123 return ret;
124}
125
126static int genregs_set(struct task_struct *target,
127 const struct user_regset *regset,
128 unsigned int pos, unsigned int count,
129 const void *kbuf, const void __user *ubuf)
130{
131 struct pt_regs *regs = task_pt_regs(target);
132 int ret;
133
134 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
135 regs->regs,
136 0, 16 * sizeof(unsigned long));
137 if (!ret && count > 0)
138 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
139 &regs->pc,
140 offsetof(struct pt_regs, pc),
141 sizeof(struct pt_regs));
142 if (!ret)
143 ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
144 sizeof(struct pt_regs), -1);
145
146 return ret;
147}
148
149#ifdef CONFIG_SH_FPU
150int fpregs_get(struct task_struct *target,
151 const struct user_regset *regset,
152 unsigned int pos, unsigned int count,
153 void *kbuf, void __user *ubuf)
154{
155 int ret;
156
157 ret = init_fpu(target);
158 if (ret)
159 return ret;
160
161 if ((boot_cpu_data.flags & CPU_HAS_FPU))
162 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
163 &target->thread.fpu.hard, 0, -1);
164
165 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
166 &target->thread.fpu.soft, 0, -1);
167}
168
169static int fpregs_set(struct task_struct *target,
170 const struct user_regset *regset,
171 unsigned int pos, unsigned int count,
172 const void *kbuf, const void __user *ubuf)
173{
174 int ret;
175
176 ret = init_fpu(target);
177 if (ret)
178 return ret;
179
180 set_stopped_child_used_math(target);
181
182 if ((boot_cpu_data.flags & CPU_HAS_FPU))
183 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
184 &target->thread.fpu.hard, 0, -1);
185
186 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
187 &target->thread.fpu.soft, 0, -1);
188}
189
190static int fpregs_active(struct task_struct *target,
191 const struct user_regset *regset)
192{
193 return tsk_used_math(target) ? regset->n : 0;
194}
195#endif
196
197#ifdef CONFIG_SH_DSP
198static int dspregs_get(struct task_struct *target,
199 const struct user_regset *regset,
200 unsigned int pos, unsigned int count,
201 void *kbuf, void __user *ubuf)
202{
203 const struct pt_dspregs *regs = task_pt_dspregs(target);
204 int ret;
205
206 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, regs,
207 0, sizeof(struct pt_dspregs));
208 if (!ret)
209 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
210 sizeof(struct pt_dspregs), -1);
211
212 return ret;
213}
214
215static int dspregs_set(struct task_struct *target,
216 const struct user_regset *regset,
217 unsigned int pos, unsigned int count,
218 const void *kbuf, const void __user *ubuf)
219{
220 struct pt_dspregs *regs = task_pt_dspregs(target);
221 int ret;
222
223 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, regs,
224 0, sizeof(struct pt_dspregs));
225 if (!ret)
226 ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
227 sizeof(struct pt_dspregs), -1);
228
229 return ret;
230}
231
232static int dspregs_active(struct task_struct *target,
233 const struct user_regset *regset)
234{
235 struct pt_regs *regs = task_pt_regs(target);
236
237 return regs->sr & SR_DSP ? regset->n : 0;
238}
239#endif
240
241/*
242 * These are our native regset flavours.
243 */
244enum sh_regset {
245 REGSET_GENERAL,
246#ifdef CONFIG_SH_FPU
247 REGSET_FPU,
248#endif
249#ifdef CONFIG_SH_DSP
250 REGSET_DSP,
251#endif
252};
253
254static const struct user_regset sh_regsets[] = {
255 /*
256 * Format is:
257 * R0 --> R15
258 * PC, PR, SR, GBR, MACH, MACL, TRA
259 */
260 [REGSET_GENERAL] = {
261 .core_note_type = NT_PRSTATUS,
262 .n = ELF_NGREG,
263 .size = sizeof(long),
264 .align = sizeof(long),
265 .get = genregs_get,
266 .set = genregs_set,
267 },
268
269#ifdef CONFIG_SH_FPU
270 [REGSET_FPU] = {
271 .core_note_type = NT_PRFPREG,
272 .n = sizeof(struct user_fpu_struct) / sizeof(long),
273 .size = sizeof(long),
274 .align = sizeof(long),
275 .get = fpregs_get,
276 .set = fpregs_set,
277 .active = fpregs_active,
278 },
279#endif
280
281#ifdef CONFIG_SH_DSP
282 [REGSET_DSP] = {
283 .n = sizeof(struct pt_dspregs) / sizeof(long),
284 .size = sizeof(long),
285 .align = sizeof(long),
286 .get = dspregs_get,
287 .set = dspregs_set,
288 .active = dspregs_active,
289 },
290#endif
291};
292
293static const struct user_regset_view user_sh_native_view = {
294 .name = "sh",
295 .e_machine = EM_SH,
296 .regsets = sh_regsets,
297 .n = ARRAY_SIZE(sh_regsets),
298};
299
300const struct user_regset_view *task_user_regset_view(struct task_struct *task)
301{
302 return &user_sh_native_view;
303}
304
105long arch_ptrace(struct task_struct *child, long request, long addr, long data) 305long arch_ptrace(struct task_struct *child, long request, long addr, long data)
106{ 306{
107 struct user * dummy = NULL; 307 struct user * dummy = NULL;
308 unsigned long __user *datap = (unsigned long __user *)data;
108 int ret; 309 int ret;
109 310
110 switch (request) { 311 switch (request) {
@@ -133,7 +334,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
133 tmp = !!tsk_used_math(child); 334 tmp = !!tsk_used_math(child);
134 else 335 else
135 tmp = 0; 336 tmp = 0;
136 ret = put_user(tmp, (unsigned long __user *)data); 337 ret = put_user(tmp, datap);
137 break; 338 break;
138 } 339 }
139 340
@@ -157,34 +358,39 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
157 } 358 }
158 break; 359 break;
159 360
361 case PTRACE_GETREGS:
362 return copy_regset_to_user(child, &user_sh_native_view,
363 REGSET_GENERAL,
364 0, sizeof(struct pt_regs),
365 (void __user *)data);
366 case PTRACE_SETREGS:
367 return copy_regset_from_user(child, &user_sh_native_view,
368 REGSET_GENERAL,
369 0, sizeof(struct pt_regs),
370 (const void __user *)data);
371#ifdef CONFIG_SH_FPU
372 case PTRACE_GETFPREGS:
373 return copy_regset_to_user(child, &user_sh_native_view,
374 REGSET_FPU,
375 0, sizeof(struct user_fpu_struct),
376 (void __user *)data);
377 case PTRACE_SETFPREGS:
378 return copy_regset_from_user(child, &user_sh_native_view,
379 REGSET_FPU,
380 0, sizeof(struct user_fpu_struct),
381 (const void __user *)data);
382#endif
160#ifdef CONFIG_SH_DSP 383#ifdef CONFIG_SH_DSP
161 case PTRACE_GETDSPREGS: { 384 case PTRACE_GETDSPREGS:
162 unsigned long dp; 385 return copy_regset_to_user(child, &user_sh_native_view,
163 386 REGSET_DSP,
164 ret = -EIO; 387 0, sizeof(struct pt_dspregs),
165 dp = ((unsigned long) child) + THREAD_SIZE - 388 (void __user *)data);
166 sizeof(struct pt_dspregs); 389 case PTRACE_SETDSPREGS:
167 if (*((int *) (dp - 4)) == SR_FD) { 390 return copy_regset_from_user(child, &user_sh_native_view,
168 copy_to_user((void *)addr, (void *) dp, 391 REGSET_DSP,
169 sizeof(struct pt_dspregs)); 392 0, sizeof(struct pt_dspregs),
170 ret = 0; 393 (const void __user *)data);
171 }
172 break;
173 }
174
175 case PTRACE_SETDSPREGS: {
176 unsigned long dp;
177
178 ret = -EIO;
179 dp = ((unsigned long) child) + THREAD_SIZE -
180 sizeof(struct pt_dspregs);
181 if (*((int *) (dp - 4)) == SR_FD) {
182 copy_from_user((void *) dp, (void *)addr,
183 sizeof(struct pt_dspregs));
184 ret = 0;
185 }
186 break;
187 }
188#endif 394#endif
189#ifdef CONFIG_BINFMT_ELF_FDPIC 395#ifdef CONFIG_BINFMT_ELF_FDPIC
190 case PTRACE_GETFDPIC: { 396 case PTRACE_GETFDPIC: {
@@ -202,7 +408,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
202 } 408 }
203 409
204 ret = 0; 410 ret = 0;
205 if (put_user(tmp, (unsigned long *) data)) { 411 if (put_user(tmp, datap)) {
206 ret = -EFAULT; 412 ret = -EFAULT;
207 break; 413 break;
208 } 414 }
diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c
index 9c6424892bd3..e15b099c1f06 100644
--- a/arch/sh/kernel/ptrace_64.c
+++ b/arch/sh/kernel/ptrace_64.c
@@ -35,6 +35,7 @@
35#include <asm/system.h> 35#include <asm/system.h>
36#include <asm/processor.h> 36#include <asm/processor.h>
37#include <asm/mmu_context.h> 37#include <asm/mmu_context.h>
38#include <asm/syscalls.h>
38#include <asm/fpu.h> 39#include <asm/fpu.h>
39 40
40/* This mask defines the bits of the SR which the user is not allowed to 41/* This mask defines the bits of the SR which the user is not allowed to
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index de832056bf1b..e7152cc6930e 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -26,6 +26,9 @@
26#include <linux/err.h> 26#include <linux/err.h>
27#include <linux/debugfs.h> 27#include <linux/debugfs.h>
28#include <linux/crash_dump.h> 28#include <linux/crash_dump.h>
29#include <linux/mmzone.h>
30#include <linux/clk.h>
31#include <linux/delay.h>
29#include <asm/uaccess.h> 32#include <asm/uaccess.h>
30#include <asm/io.h> 33#include <asm/io.h>
31#include <asm/page.h> 34#include <asm/page.h>
@@ -144,6 +147,7 @@ static void __init reserve_crashkernel(void)
144{ 147{
145 unsigned long long free_mem; 148 unsigned long long free_mem;
146 unsigned long long crash_size, crash_base; 149 unsigned long long crash_size, crash_base;
150 void *vp;
147 int ret; 151 int ret;
148 152
149 free_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT; 153 free_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
@@ -152,12 +156,14 @@ static void __init reserve_crashkernel(void)
152 &crash_size, &crash_base); 156 &crash_size, &crash_base);
153 if (ret == 0 && crash_size) { 157 if (ret == 0 && crash_size) {
154 if (crash_base <= 0) { 158 if (crash_base <= 0) {
155 printk(KERN_INFO "crashkernel reservation failed - " 159 vp = alloc_bootmem_nopanic(crash_size);
156 "you have to specify a base address\n"); 160 if (!vp) {
157 return; 161 printk(KERN_INFO "crashkernel allocation "
158 } 162 "failed\n");
159 163 return;
160 if (reserve_bootmem(crash_base, crash_size, 164 }
165 crash_base = __pa(vp);
166 } else if (reserve_bootmem(crash_base, crash_size,
161 BOOTMEM_EXCLUSIVE) < 0) { 167 BOOTMEM_EXCLUSIVE) < 0) {
162 printk(KERN_INFO "crashkernel reservation failed - " 168 printk(KERN_INFO "crashkernel reservation failed - "
163 "memory is in use\n"); 169 "memory is in use\n");
@@ -179,6 +185,24 @@ static inline void __init reserve_crashkernel(void)
179{} 185{}
180#endif 186#endif
181 187
188#ifndef CONFIG_GENERIC_CALIBRATE_DELAY
189void __cpuinit calibrate_delay(void)
190{
191 struct clk *clk = clk_get(NULL, "cpu_clk");
192
193 if (IS_ERR(clk))
194 panic("Need a sane CPU clock definition!");
195
196 loops_per_jiffy = (clk_get_rate(clk) >> 1) / HZ;
197
198 printk(KERN_INFO "Calibrating delay loop (skipped)... "
199 "%lu.%02lu BogoMIPS PRESET (lpj=%lu)\n",
200 loops_per_jiffy/(500000/HZ),
201 (loops_per_jiffy/(5000/HZ)) % 100,
202 loops_per_jiffy);
203}
204#endif
205
182void __init __add_active_range(unsigned int nid, unsigned long start_pfn, 206void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
183 unsigned long end_pfn) 207 unsigned long end_pfn)
184{ 208{
@@ -232,15 +256,17 @@ void __init setup_bootmem_allocator(unsigned long free_pfn)
232 * case of us accidentally initializing the bootmem allocator with 256 * case of us accidentally initializing the bootmem allocator with
233 * an invalid RAM area. 257 * an invalid RAM area.
234 */ 258 */
235 reserve_bootmem(__MEMORY_START+PAGE_SIZE, 259 reserve_bootmem(__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET,
236 (PFN_PHYS(free_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START, 260 (PFN_PHYS(free_pfn) + bootmap_size + PAGE_SIZE - 1) -
237 BOOTMEM_DEFAULT); 261 (__MEMORY_START + CONFIG_ZERO_PAGE_OFFSET),
262 BOOTMEM_DEFAULT);
238 263
239 /* 264 /*
240 * reserve physical page 0 - it's a special BIOS page on many boxes, 265 * reserve physical page 0 - it's a special BIOS page on many boxes,
241 * enabling clean reboots, SMP operation, laptop functions. 266 * enabling clean reboots, SMP operation, laptop functions.
242 */ 267 */
243 reserve_bootmem(__MEMORY_START, PAGE_SIZE, BOOTMEM_DEFAULT); 268 reserve_bootmem(__MEMORY_START, CONFIG_ZERO_PAGE_OFFSET,
269 BOOTMEM_DEFAULT);
244 270
245 sparse_memory_present_with_active_regions(0); 271 sparse_memory_present_with_active_regions(0);
246 272
@@ -248,17 +274,18 @@ void __init setup_bootmem_allocator(unsigned long free_pfn)
248 ROOT_DEV = Root_RAM0; 274 ROOT_DEV = Root_RAM0;
249 275
250 if (LOADER_TYPE && INITRD_START) { 276 if (LOADER_TYPE && INITRD_START) {
251 if (INITRD_START + INITRD_SIZE <= (max_low_pfn << PAGE_SHIFT)) { 277 unsigned long initrd_start_phys = INITRD_START + __MEMORY_START;
252 reserve_bootmem(INITRD_START + __MEMORY_START, 278
253 INITRD_SIZE, BOOTMEM_DEFAULT); 279 if (initrd_start_phys + INITRD_SIZE <= PFN_PHYS(max_low_pfn)) {
254 initrd_start = INITRD_START + PAGE_OFFSET + 280 reserve_bootmem(initrd_start_phys, INITRD_SIZE,
255 __MEMORY_START; 281 BOOTMEM_DEFAULT);
282 initrd_start = (unsigned long)__va(initrd_start_phys);
256 initrd_end = initrd_start + INITRD_SIZE; 283 initrd_end = initrd_start + INITRD_SIZE;
257 } else { 284 } else {
258 printk("initrd extends beyond end of memory " 285 printk("initrd extends beyond end of memory "
259 "(0x%08lx > 0x%08lx)\ndisabling initrd\n", 286 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
260 INITRD_START + INITRD_SIZE, 287 initrd_start_phys + INITRD_SIZE,
261 max_low_pfn << PAGE_SHIFT); 288 (unsigned long)PFN_PHYS(max_low_pfn));
262 initrd_start = 0; 289 initrd_start = 0;
263 } 290 }
264 } 291 }
@@ -530,6 +557,8 @@ struct dentry *sh_debugfs_root;
530static int __init sh_debugfs_init(void) 557static int __init sh_debugfs_init(void)
531{ 558{
532 sh_debugfs_root = debugfs_create_dir("sh", NULL); 559 sh_debugfs_root = debugfs_create_dir("sh", NULL);
560 if (!sh_debugfs_root)
561 return -ENOMEM;
533 if (IS_ERR(sh_debugfs_root)) 562 if (IS_ERR(sh_debugfs_root))
534 return PTR_ERR(sh_debugfs_root); 563 return PTR_ERR(sh_debugfs_root);
535 564
diff --git a/arch/sh/kernel/sh_ksyms_32.c b/arch/sh/kernel/sh_ksyms_32.c
index 6e1b1c271658..d917b7b4042b 100644
--- a/arch/sh/kernel/sh_ksyms_32.c
+++ b/arch/sh/kernel/sh_ksyms_32.c
@@ -16,6 +16,7 @@
16#include <asm/delay.h> 16#include <asm/delay.h>
17#include <asm/tlbflush.h> 17#include <asm/tlbflush.h>
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/ftrace.h>
19 20
20extern int dump_fpu(struct pt_regs *, elf_fpregset_t *); 21extern int dump_fpu(struct pt_regs *, elf_fpregset_t *);
21extern struct hw_interrupt_type no_irq_type; 22extern struct hw_interrupt_type no_irq_type;
@@ -133,6 +134,9 @@ EXPORT_SYMBOL(__flush_purge_region);
133EXPORT_SYMBOL(clear_user_page); 134EXPORT_SYMBOL(clear_user_page);
134#endif 135#endif
135 136
137#ifdef CONFIG_FTRACE
138EXPORT_SYMBOL(mcount);
139#endif
136EXPORT_SYMBOL(csum_partial); 140EXPORT_SYMBOL(csum_partial);
137EXPORT_SYMBOL(csum_partial_copy_generic); 141EXPORT_SYMBOL(csum_partial_copy_generic);
138#ifdef CONFIG_IPV6 142#ifdef CONFIG_IPV6
diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c
index 51689d29ad45..69d09c0b3498 100644
--- a/arch/sh/kernel/signal_32.c
+++ b/arch/sh/kernel/signal_32.c
@@ -30,6 +30,7 @@
30#include <asm/uaccess.h> 30#include <asm/uaccess.h>
31#include <asm/pgtable.h> 31#include <asm/pgtable.h>
32#include <asm/cacheflush.h> 32#include <asm/cacheflush.h>
33#include <asm/syscalls.h>
33#include <asm/fpu.h> 34#include <asm/fpu.h>
34 35
35#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) 36#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
@@ -215,6 +216,9 @@ asmlinkage int sys_sigreturn(unsigned long r4, unsigned long r5,
215 sigset_t set; 216 sigset_t set;
216 int r0; 217 int r0;
217 218
219 /* Always make any pending restarted system calls return -EINTR */
220 current_thread_info()->restart_block.fn = do_no_restart_syscall;
221
218 if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) 222 if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
219 goto badframe; 223 goto badframe;
220 224
@@ -247,9 +251,11 @@ asmlinkage int sys_rt_sigreturn(unsigned long r4, unsigned long r5,
247 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 251 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
248 struct rt_sigframe __user *frame = (struct rt_sigframe __user *)regs->regs[15]; 252 struct rt_sigframe __user *frame = (struct rt_sigframe __user *)regs->regs[15];
249 sigset_t set; 253 sigset_t set;
250 stack_t st;
251 int r0; 254 int r0;
252 255
256 /* Always make any pending restarted system calls return -EINTR */
257 current_thread_info()->restart_block.fn = do_no_restart_syscall;
258
253 if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) 259 if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
254 goto badframe; 260 goto badframe;
255 261
@@ -265,11 +271,9 @@ asmlinkage int sys_rt_sigreturn(unsigned long r4, unsigned long r5,
265 if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0)) 271 if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0))
266 goto badframe; 272 goto badframe;
267 273
268 if (__copy_from_user(&st, &frame->uc.uc_stack, sizeof(st))) 274 if (do_sigaltstack(&frame->uc.uc_stack, NULL,
275 regs->regs[15]) == -EFAULT)
269 goto badframe; 276 goto badframe;
270 /* It is more difficult to avoid calling this function than to
271 call it and ignore errors. */
272 do_sigaltstack((const stack_t __user *)&st, NULL, (unsigned long)frame);
273 277
274 return r0; 278 return r0;
275 279
@@ -429,7 +433,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
429 433
430 /* Create the ucontext. */ 434 /* Create the ucontext. */
431 err |= __put_user(0, &frame->uc.uc_flags); 435 err |= __put_user(0, &frame->uc.uc_flags);
432 err |= __put_user(0, &frame->uc.uc_link); 436 err |= __put_user(NULL, &frame->uc.uc_link);
433 err |= __put_user((void *)current->sas_ss_sp, 437 err |= __put_user((void *)current->sas_ss_sp,
434 &frame->uc.uc_stack.ss_sp); 438 &frame->uc.uc_stack.ss_sp);
435 err |= __put_user(sas_ss_flags(regs->regs[15]), 439 err |= __put_user(sas_ss_flags(regs->regs[15]),
@@ -492,37 +496,43 @@ give_sigsegv:
492 return -EFAULT; 496 return -EFAULT;
493} 497}
494 498
499static inline void
500handle_syscall_restart(unsigned long save_r0, struct pt_regs *regs,
501 struct sigaction *sa)
502{
503 /* If we're not from a syscall, bail out */
504 if (regs->tra < 0)
505 return;
506
507 /* check for system call restart.. */
508 switch (regs->regs[0]) {
509 case -ERESTART_RESTARTBLOCK:
510 case -ERESTARTNOHAND:
511 no_system_call_restart:
512 regs->regs[0] = -EINTR;
513 regs->sr |= 1;
514 break;
515
516 case -ERESTARTSYS:
517 if (!(sa->sa_flags & SA_RESTART))
518 goto no_system_call_restart;
519 /* fallthrough */
520 case -ERESTARTNOINTR:
521 regs->regs[0] = save_r0;
522 regs->pc -= instruction_size(ctrl_inw(regs->pc - 4));
523 break;
524 }
525}
526
495/* 527/*
496 * OK, we're invoking a handler 528 * OK, we're invoking a handler
497 */ 529 */
498
499static int 530static int
500handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info, 531handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
501 sigset_t *oldset, struct pt_regs *regs, unsigned int save_r0) 532 sigset_t *oldset, struct pt_regs *regs, unsigned int save_r0)
502{ 533{
503 int ret; 534 int ret;
504 535
505 /* Are we from a system call? */
506 if (regs->tra >= 0) {
507 /* If so, check system call restarting.. */
508 switch (regs->regs[0]) {
509 case -ERESTART_RESTARTBLOCK:
510 case -ERESTARTNOHAND:
511 no_system_call_restart:
512 regs->regs[0] = -EINTR;
513 break;
514
515 case -ERESTARTSYS:
516 if (!(ka->sa.sa_flags & SA_RESTART))
517 goto no_system_call_restart;
518 /* fallthrough */
519 case -ERESTARTNOINTR:
520 regs->regs[0] = save_r0;
521 regs->pc -= instruction_size(
522 ctrl_inw(regs->pc - 4));
523 break;
524 }
525 }
526 536
527 /* Set up the stack frame */ 537 /* Set up the stack frame */
528 if (ka->sa.sa_flags & SA_SIGINFO) 538 if (ka->sa.sa_flags & SA_SIGINFO)
@@ -580,6 +590,9 @@ static void do_signal(struct pt_regs *regs, unsigned int save_r0)
580 590
581 signr = get_signal_to_deliver(&info, &ka, regs, NULL); 591 signr = get_signal_to_deliver(&info, &ka, regs, NULL);
582 if (signr > 0) { 592 if (signr > 0) {
593 if (regs->sr & 1)
594 handle_syscall_restart(save_r0, regs, &ka.sa);
595
583 /* Whee! Actually deliver the signal. */ 596 /* Whee! Actually deliver the signal. */
584 if (handle_signal(signr, &ka, &info, oldset, 597 if (handle_signal(signr, &ka, &info, oldset,
585 regs, save_r0) == 0) { 598 regs, save_r0) == 0) {
diff --git a/arch/sh/kernel/signal_64.c b/arch/sh/kernel/signal_64.c
index 1d62dfef77f1..ce3e851dffcb 100644
--- a/arch/sh/kernel/signal_64.c
+++ b/arch/sh/kernel/signal_64.c
@@ -43,6 +43,10 @@
43 43
44#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP))) 44#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
45 45
46static void
47handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
48 sigset_t *oldset, struct pt_regs * regs);
49
46/* 50/*
47 * Note that 'init' is a special process: it doesn't get signals it doesn't 51 * Note that 'init' is a special process: it doesn't get signals it doesn't
48 * want to handle. Thus you cannot kill init even with a SIGKILL even by 52 * want to handle. Thus you cannot kill init even with a SIGKILL even by
@@ -371,6 +375,9 @@ asmlinkage int sys_sigreturn(unsigned long r2, unsigned long r3,
371 sigset_t set; 375 sigset_t set;
372 long long ret; 376 long long ret;
373 377
378 /* Always make any pending restarted system calls return -EINTR */
379 current_thread_info()->restart_block.fn = do_no_restart_syscall;
380
374 if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) 381 if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
375 goto badframe; 382 goto badframe;
376 383
@@ -408,6 +415,9 @@ asmlinkage int sys_rt_sigreturn(unsigned long r2, unsigned long r3,
408 stack_t __user st; 415 stack_t __user st;
409 long long ret; 416 long long ret;
410 417
418 /* Always make any pending restarted system calls return -EINTR */
419 current_thread_info()->restart_block.fn = do_no_restart_syscall;
420
411 if (!access_ok(VERIFY_READ, frame, sizeof(*frame))) 421 if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
412 goto badframe; 422 goto badframe;
413 423
@@ -535,7 +545,7 @@ static void setup_frame(int sig, struct k_sigaction *ka,
535 * On SH5 all edited pointers are subject to NEFF 545 * On SH5 all edited pointers are subject to NEFF
536 */ 546 */
537 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? 547 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ?
538 (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; 548 (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR;
539 } else { 549 } else {
540 /* 550 /*
541 * Different approach on SH5. 551 * Different approach on SH5.
@@ -550,10 +560,10 @@ static void setup_frame(int sig, struct k_sigaction *ka,
550 */ 560 */
551 DEREF_REG_PR = (unsigned long) frame->retcode | 0x01; 561 DEREF_REG_PR = (unsigned long) frame->retcode | 0x01;
552 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? 562 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ?
553 (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; 563 (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR;
554 564
555 if (__copy_to_user(frame->retcode, 565 if (__copy_to_user(frame->retcode,
556 (unsigned long long)sa_default_restorer & (~1), 16) != 0) 566 (void *)((unsigned long)sa_default_restorer & (~1)), 16) != 0)
557 goto give_sigsegv; 567 goto give_sigsegv;
558 568
559 /* Cohere the trampoline with the I-cache. */ 569 /* Cohere the trampoline with the I-cache. */
@@ -566,7 +576,7 @@ static void setup_frame(int sig, struct k_sigaction *ka,
566 */ 576 */
567 regs->regs[REG_SP] = (unsigned long) frame; 577 regs->regs[REG_SP] = (unsigned long) frame;
568 regs->regs[REG_SP] = (regs->regs[REG_SP] & NEFF_SIGN) ? 578 regs->regs[REG_SP] = (regs->regs[REG_SP] & NEFF_SIGN) ?
569 (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP]; 579 (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP];
570 regs->regs[REG_ARG1] = signal; /* Arg for signal handler */ 580 regs->regs[REG_ARG1] = signal; /* Arg for signal handler */
571 581
572 /* FIXME: 582 /* FIXME:
@@ -652,7 +662,7 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
652 * On SH5 all edited pointers are subject to NEFF 662 * On SH5 all edited pointers are subject to NEFF
653 */ 663 */
654 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? 664 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ?
655 (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; 665 (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR;
656 } else { 666 } else {
657 /* 667 /*
658 * Different approach on SH5. 668 * Different approach on SH5.
@@ -668,10 +678,10 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
668 678
669 DEREF_REG_PR = (unsigned long) frame->retcode | 0x01; 679 DEREF_REG_PR = (unsigned long) frame->retcode | 0x01;
670 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ? 680 DEREF_REG_PR = (DEREF_REG_PR & NEFF_SIGN) ?
671 (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR; 681 (DEREF_REG_PR | NEFF_MASK) : DEREF_REG_PR;
672 682
673 if (__copy_to_user(frame->retcode, 683 if (__copy_to_user(frame->retcode,
674 (unsigned long long)sa_default_rt_restorer & (~1), 16) != 0) 684 (void *)((unsigned long)sa_default_rt_restorer & (~1)), 16) != 0)
675 goto give_sigsegv; 685 goto give_sigsegv;
676 686
677 flush_icache_range(DEREF_REG_PR-1, DEREF_REG_PR-1+15); 687 flush_icache_range(DEREF_REG_PR-1, DEREF_REG_PR-1+15);
@@ -683,7 +693,7 @@ static void setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
683 */ 693 */
684 regs->regs[REG_SP] = (unsigned long) frame; 694 regs->regs[REG_SP] = (unsigned long) frame;
685 regs->regs[REG_SP] = (regs->regs[REG_SP] & NEFF_SIGN) ? 695 regs->regs[REG_SP] = (regs->regs[REG_SP] & NEFF_SIGN) ?
686 (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP]; 696 (regs->regs[REG_SP] | NEFF_MASK) : regs->regs[REG_SP];
687 regs->regs[REG_ARG1] = signal; /* Arg for signal handler */ 697 regs->regs[REG_ARG1] = signal; /* Arg for signal handler */
688 regs->regs[REG_ARG2] = (unsigned long long)(unsigned long)(signed long)&frame->info; 698 regs->regs[REG_ARG2] = (unsigned long long)(unsigned long)(signed long)&frame->info;
689 regs->regs[REG_ARG3] = (unsigned long long)(unsigned long)(signed long)&frame->uc.uc_mcontext; 699 regs->regs[REG_ARG3] = (unsigned long long)(unsigned long)(signed long)&frame->uc.uc_mcontext;
diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c
index 001778f9adaf..508dfb023628 100644
--- a/arch/sh/kernel/smp.c
+++ b/arch/sh/kernel/smp.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * SMP support for the SuperH processors. 4 * SMP support for the SuperH processors.
5 * 5 *
6 * Copyright (C) 2002 - 2007 Paul Mundt 6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Copyright (C) 2006 - 2007 Akio Idehara 7 * Copyright (C) 2006 - 2007 Akio Idehara
8 * 8 *
9 * This file is subject to the terms and conditions of the GNU General Public 9 * This file is subject to the terms and conditions of the GNU General Public
@@ -86,9 +86,12 @@ asmlinkage void __cpuinit start_secondary(void)
86 86
87 local_irq_enable(); 87 local_irq_enable();
88 88
89 cpu = smp_processor_id();
90
91 /* Enable local timers */
92 local_timer_setup(cpu);
89 calibrate_delay(); 93 calibrate_delay();
90 94
91 cpu = smp_processor_id();
92 smp_store_cpu_info(cpu); 95 smp_store_cpu_info(cpu);
93 96
94 cpu_set(cpu, cpu_online_map); 97 cpu_set(cpu, cpu_online_map);
@@ -186,6 +189,42 @@ void arch_send_call_function_single_ipi(int cpu)
186 plat_send_ipi(cpu, SMP_MSG_FUNCTION_SINGLE); 189 plat_send_ipi(cpu, SMP_MSG_FUNCTION_SINGLE);
187} 190}
188 191
192void smp_timer_broadcast(cpumask_t mask)
193{
194 int cpu;
195
196 for_each_cpu_mask(cpu, mask)
197 plat_send_ipi(cpu, SMP_MSG_TIMER);
198}
199
200static void ipi_timer(void)
201{
202 irq_enter();
203 local_timer_interrupt();
204 irq_exit();
205}
206
207void smp_message_recv(unsigned int msg)
208{
209 switch (msg) {
210 case SMP_MSG_FUNCTION:
211 generic_smp_call_function_interrupt();
212 break;
213 case SMP_MSG_RESCHEDULE:
214 break;
215 case SMP_MSG_FUNCTION_SINGLE:
216 generic_smp_call_function_single_interrupt();
217 break;
218 case SMP_MSG_TIMER:
219 ipi_timer();
220 break;
221 default:
222 printk(KERN_WARNING "SMP %d: %s(): unknown IPI %d\n",
223 smp_processor_id(), __func__, msg);
224 break;
225 }
226}
227
189/* Not really SMP stuff ... */ 228/* Not really SMP stuff ... */
190int setup_profiling_timer(unsigned int multiplier) 229int setup_profiling_timer(unsigned int multiplier)
191{ 230{
diff --git a/arch/sh/kernel/stacktrace.c b/arch/sh/kernel/stacktrace.c
index 54d1f61aa007..1a2a5eb76e41 100644
--- a/arch/sh/kernel/stacktrace.c
+++ b/arch/sh/kernel/stacktrace.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Stack trace management functions 4 * Stack trace management functions
5 * 5 *
6 * Copyright (C) 2006 Paul Mundt 6 * Copyright (C) 2006 - 2008 Paul Mundt
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -36,3 +36,24 @@ void save_stack_trace(struct stack_trace *trace)
36 } 36 }
37} 37}
38EXPORT_SYMBOL_GPL(save_stack_trace); 38EXPORT_SYMBOL_GPL(save_stack_trace);
39
40void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
41{
42 unsigned long *sp = (unsigned long *)tsk->thread.sp;
43
44 while (!kstack_end(sp)) {
45 unsigned long addr = *sp++;
46
47 if (__kernel_text_address(addr)) {
48 if (in_sched_functions(addr))
49 break;
50 if (trace->skip > 0)
51 trace->skip--;
52 else
53 trace->entries[trace->nr_entries++] = addr;
54 if (trace->nr_entries >= trace->max_entries)
55 break;
56 }
57 }
58}
59EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
diff --git a/arch/sh/kernel/sys_sh.c b/arch/sh/kernel/sys_sh.c
index 9061b86d73fa..38f098c9c72d 100644
--- a/arch/sh/kernel/sys_sh.c
+++ b/arch/sh/kernel/sys_sh.c
@@ -23,6 +23,7 @@
23#include <linux/fs.h> 23#include <linux/fs.h>
24#include <linux/ipc.h> 24#include <linux/ipc.h>
25#include <asm/cacheflush.h> 25#include <asm/cacheflush.h>
26#include <asm/syscalls.h>
26#include <asm/uaccess.h> 27#include <asm/uaccess.h>
27#include <asm/unistd.h> 28#include <asm/unistd.h>
28 29
@@ -170,6 +171,8 @@ asmlinkage int sys_ipc(uint call, int first, int second,
170 version = call >> 16; /* hack for backward compatibility */ 171 version = call >> 16; /* hack for backward compatibility */
171 call &= 0xffff; 172 call &= 0xffff;
172 173
174 trace_mark(kernel_arch_ipc_call, "call %u first %d", call, first);
175
173 if (call <= SEMTIMEDOP) 176 if (call <= SEMTIMEDOP)
174 switch (call) { 177 switch (call) {
175 case SEMOP: 178 case SEMOP:
@@ -186,7 +189,7 @@ asmlinkage int sys_ipc(uint call, int first, int second,
186 union semun fourth; 189 union semun fourth;
187 if (!ptr) 190 if (!ptr)
188 return -EINVAL; 191 return -EINVAL;
189 if (get_user(fourth.__pad, (void * __user *) ptr)) 192 if (get_user(fourth.__pad, (void __user * __user *) ptr))
190 return -EFAULT; 193 return -EFAULT;
191 return sys_semctl (first, second, third, fourth); 194 return sys_semctl (first, second, third, fourth);
192 } 195 }
@@ -261,13 +264,13 @@ asmlinkage int sys_ipc(uint call, int first, int second,
261 return -EINVAL; 264 return -EINVAL;
262} 265}
263 266
264asmlinkage int sys_uname(struct old_utsname * name) 267asmlinkage int sys_uname(struct old_utsname __user *name)
265{ 268{
266 int err; 269 int err;
267 if (!name) 270 if (!name)
268 return -EFAULT; 271 return -EFAULT;
269 down_read(&uts_sem); 272 down_read(&uts_sem);
270 err = copy_to_user(name, utsname(), sizeof (*name)); 273 err = copy_to_user(name, utsname(), sizeof(*name));
271 up_read(&uts_sem); 274 up_read(&uts_sem);
272 return err?-EFAULT:0; 275 return err?-EFAULT:0;
273} 276}
diff --git a/arch/sh/kernel/sys_sh32.c b/arch/sh/kernel/sys_sh32.c
index f0aa5c398656..dbba1e1833d4 100644
--- a/arch/sh/kernel/sys_sh32.c
+++ b/arch/sh/kernel/sys_sh32.c
@@ -16,6 +16,7 @@
16#include <asm/cacheflush.h> 16#include <asm/cacheflush.h>
17#include <asm/uaccess.h> 17#include <asm/uaccess.h>
18#include <asm/unistd.h> 18#include <asm/unistd.h>
19#include <asm/syscalls.h>
19 20
20/* 21/*
21 * sys_pipe() is the normal C calling standard for creating 22 * sys_pipe() is the normal C calling standard for creating
@@ -37,13 +38,13 @@ asmlinkage int sys_pipe(unsigned long r4, unsigned long r5,
37 return error; 38 return error;
38} 39}
39 40
40asmlinkage ssize_t sys_pread_wrapper(unsigned int fd, char * buf, 41asmlinkage ssize_t sys_pread_wrapper(unsigned int fd, char __user *buf,
41 size_t count, long dummy, loff_t pos) 42 size_t count, long dummy, loff_t pos)
42{ 43{
43 return sys_pread64(fd, buf, count, pos); 44 return sys_pread64(fd, buf, count, pos);
44} 45}
45 46
46asmlinkage ssize_t sys_pwrite_wrapper(unsigned int fd, const char * buf, 47asmlinkage ssize_t sys_pwrite_wrapper(unsigned int fd, const char __user *buf,
47 size_t count, long dummy, loff_t pos) 48 size_t count, long dummy, loff_t pos)
48{ 49{
49 return sys_pwrite64(fd, buf, count, pos); 50 return sys_pwrite64(fd, buf, count, pos);
diff --git a/arch/sh/kernel/time_32.c b/arch/sh/kernel/time_32.c
index 0758b5ee8180..23ca711c27d2 100644
--- a/arch/sh/kernel/time_32.c
+++ b/arch/sh/kernel/time_32.c
@@ -1,9 +1,9 @@
1/* 1/*
2 * arch/sh/kernel/time.c 2 * arch/sh/kernel/time_32.c
3 * 3 *
4 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka 4 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
5 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> 5 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
6 * Copyright (C) 2002 - 2007 Paul Mundt 6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org> 7 * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
8 * 8 *
9 * Some code taken from i386 version. 9 * Some code taken from i386 version.
@@ -16,6 +16,8 @@
16#include <linux/timex.h> 16#include <linux/timex.h>
17#include <linux/sched.h> 17#include <linux/sched.h>
18#include <linux/clockchips.h> 18#include <linux/clockchips.h>
19#include <linux/mc146818rtc.h> /* for rtc_lock */
20#include <linux/smp.h>
19#include <asm/clock.h> 21#include <asm/clock.h>
20#include <asm/rtc.h> 22#include <asm/rtc.h>
21#include <asm/timer.h> 23#include <asm/timer.h>
@@ -253,6 +255,10 @@ void __init time_init(void)
253 set_normalized_timespec(&wall_to_monotonic, 255 set_normalized_timespec(&wall_to_monotonic,
254 -xtime.tv_sec, -xtime.tv_nsec); 256 -xtime.tv_sec, -xtime.tv_nsec);
255 257
258#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
259 local_timer_setup(smp_processor_id());
260#endif
261
256 /* 262 /*
257 * Find the timer to use as the system timer, it will be 263 * Find the timer to use as the system timer, it will be
258 * initialized for us. 264 * initialized for us.
@@ -260,6 +266,7 @@ void __init time_init(void)
260 sys_timer = get_sys_timer(); 266 sys_timer = get_sys_timer();
261 printk(KERN_INFO "Using %s for system timer\n", sys_timer->name); 267 printk(KERN_INFO "Using %s for system timer\n", sys_timer->name);
262 268
269
263 if (sys_timer->ops->read) 270 if (sys_timer->ops->read)
264 clocksource_sh.read = sys_timer->ops->read; 271 clocksource_sh.read = sys_timer->ops->read;
265 272
diff --git a/arch/sh/kernel/time_64.c b/arch/sh/kernel/time_64.c
index 791edabf7d83..bbb2af1004d9 100644
--- a/arch/sh/kernel/time_64.c
+++ b/arch/sh/kernel/time_64.c
@@ -39,6 +39,7 @@
39#include <asm/processor.h> 39#include <asm/processor.h>
40#include <asm/uaccess.h> 40#include <asm/uaccess.h>
41#include <asm/delay.h> 41#include <asm/delay.h>
42#include <asm/clock.h>
42 43
43#define TMU_TOCR_INIT 0x00 44#define TMU_TOCR_INIT 0x00
44#define TMU0_TCR_INIT 0x0020 45#define TMU0_TCR_INIT 0x0020
@@ -51,14 +52,6 @@
51#define RTC_RCR1_CIE 0x10 /* Carry Interrupt Enable */ 52#define RTC_RCR1_CIE 0x10 /* Carry Interrupt Enable */
52#define RTC_RCR1 (rtc_base + 0x38) 53#define RTC_RCR1 (rtc_base + 0x38)
53 54
54/* Clock, Power and Reset Controller */
55#define CPRC_BLOCK_OFF 0x01010000
56#define CPRC_BASE PHYS_PERIPHERAL_BLOCK + CPRC_BLOCK_OFF
57
58#define FRQCR (cprc_base+0x0)
59#define WTCSR (cprc_base+0x0018)
60#define STBCR (cprc_base+0x0030)
61
62/* Time Management Unit */ 55/* Time Management Unit */
63#define TMU_BLOCK_OFF 0x01020000 56#define TMU_BLOCK_OFF 0x01020000
64#define TMU_BASE PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF 57#define TMU_BASE PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF
@@ -293,103 +286,17 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
293 return IRQ_HANDLED; 286 return IRQ_HANDLED;
294} 287}
295 288
296
297static __init unsigned int get_cpu_hz(void)
298{
299 unsigned int count;
300 unsigned long __dummy;
301 unsigned long ctc_val_init, ctc_val;
302
303 /*
304 ** Regardless the toolchain, force the compiler to use the
305 ** arbitrary register r3 as a clock tick counter.
306 ** NOTE: r3 must be in accordance with sh64_rtc_interrupt()
307 */
308 register unsigned long long __rtc_irq_flag __asm__ ("r3");
309
310 local_irq_enable();
311 do {} while (ctrl_inb(rtc_base) != 0);
312 ctrl_outb(RTC_RCR1_CIE, RTC_RCR1); /* Enable carry interrupt */
313
314 /*
315 * r3 is arbitrary. CDC does not support "=z".
316 */
317 ctc_val_init = 0xffffffff;
318 ctc_val = ctc_val_init;
319
320 asm volatile("gettr tr0, %1\n\t"
321 "putcon %0, " __CTC "\n\t"
322 "and %2, r63, %2\n\t"
323 "pta $+4, tr0\n\t"
324 "beq/l %2, r63, tr0\n\t"
325 "ptabs %1, tr0\n\t"
326 "getcon " __CTC ", %0\n\t"
327 : "=r"(ctc_val), "=r" (__dummy), "=r" (__rtc_irq_flag)
328 : "0" (0));
329 local_irq_disable();
330 /*
331 * SH-3:
332 * CPU clock = 4 stages * loop
333 * tst rm,rm if id ex
334 * bt/s 1b if id ex
335 * add #1,rd if id ex
336 * (if) pipe line stole
337 * tst rm,rm if id ex
338 * ....
339 *
340 *
341 * SH-4:
342 * CPU clock = 6 stages * loop
343 * I don't know why.
344 * ....
345 *
346 * SH-5:
347 * Use CTC register to count. This approach returns the right value
348 * even if the I-cache is disabled (e.g. whilst debugging.)
349 *
350 */
351
352 count = ctc_val_init - ctc_val; /* CTC counts down */
353
354 /*
355 * This really is count by the number of clock cycles
356 * by the ratio between a complete R64CNT
357 * wrap-around (128) and CUI interrupt being raised (64).
358 */
359 return count*2;
360}
361
362static irqreturn_t sh64_rtc_interrupt(int irq, void *dev_id)
363{
364 struct pt_regs *regs = get_irq_regs();
365
366 ctrl_outb(0, RTC_RCR1); /* Disable Carry Interrupts */
367 regs->regs[3] = 1; /* Using r3 */
368
369 return IRQ_HANDLED;
370}
371
372static struct irqaction irq0 = { 289static struct irqaction irq0 = {
373 .handler = timer_interrupt, 290 .handler = timer_interrupt,
374 .flags = IRQF_DISABLED, 291 .flags = IRQF_DISABLED,
375 .mask = CPU_MASK_NONE, 292 .mask = CPU_MASK_NONE,
376 .name = "timer", 293 .name = "timer",
377}; 294};
378static struct irqaction irq1 = {
379 .handler = sh64_rtc_interrupt,
380 .flags = IRQF_DISABLED,
381 .mask = CPU_MASK_NONE,
382 .name = "rtc",
383};
384 295
385void __init time_init(void) 296void __init time_init(void)
386{ 297{
387 unsigned int cpu_clock, master_clock, bus_clock, module_clock;
388 unsigned long interval; 298 unsigned long interval;
389 unsigned long frqcr, ifc, pfc; 299 struct clk *clk;
390 static int ifc_table[] = { 2, 4, 6, 8, 10, 12, 16, 24 };
391#define bfc_table ifc_table /* Same */
392#define pfc_table ifc_table /* Same */
393 300
394 tmu_base = onchip_remap(TMU_BASE, 1024, "TMU"); 301 tmu_base = onchip_remap(TMU_BASE, 1024, "TMU");
395 if (!tmu_base) { 302 if (!tmu_base) {
@@ -401,50 +308,19 @@ void __init time_init(void)
401 panic("Unable to remap RTC\n"); 308 panic("Unable to remap RTC\n");
402 } 309 }
403 310
404 cprc_base = onchip_remap(CPRC_BASE, 1024, "CPRC"); 311 clk = clk_get(NULL, "cpu_clk");
405 if (!cprc_base) { 312 scaled_recip_ctc_ticks_per_jiffy = ((1ULL << CTC_JIFFY_SCALE_SHIFT) /
406 panic("Unable to remap CPRC\n"); 313 (unsigned long long)(clk_get_rate(clk) / HZ));
407 }
408 314
409 rtc_sh_get_time(&xtime); 315 rtc_sh_get_time(&xtime);
410 316
411 setup_irq(TIMER_IRQ, &irq0); 317 setup_irq(TIMER_IRQ, &irq0);
412 setup_irq(RTC_IRQ, &irq1);
413
414 /* Check how fast it is.. */
415 cpu_clock = get_cpu_hz();
416
417 /* Note careful order of operations to maintain reasonable precision and avoid overflow. */
418 scaled_recip_ctc_ticks_per_jiffy = ((1ULL << CTC_JIFFY_SCALE_SHIFT) / (unsigned long long)(cpu_clock / HZ));
419
420 free_irq(RTC_IRQ, NULL);
421
422 printk("CPU clock: %d.%02dMHz\n",
423 (cpu_clock / 1000000), (cpu_clock % 1000000)/10000);
424 {
425 unsigned short bfc;
426 frqcr = ctrl_inl(FRQCR);
427 ifc = ifc_table[(frqcr>> 6) & 0x0007];
428 bfc = bfc_table[(frqcr>> 3) & 0x0007];
429 pfc = pfc_table[(frqcr>> 12) & 0x0007];
430 master_clock = cpu_clock * ifc;
431 bus_clock = master_clock/bfc;
432 }
433 318
434 printk("Bus clock: %d.%02dMHz\n", 319 clk = clk_get(NULL, "module_clk");
435 (bus_clock/1000000), (bus_clock % 1000000)/10000); 320 interval = (clk_get_rate(clk)/(HZ*4));
436 module_clock = master_clock/pfc;
437 printk("Module clock: %d.%02dMHz\n",
438 (module_clock/1000000), (module_clock % 1000000)/10000);
439 interval = (module_clock/(HZ*4));
440 321
441 printk("Interval = %ld\n", interval); 322 printk("Interval = %ld\n", interval);
442 323
443 current_cpu_data.cpu_clock = cpu_clock;
444 current_cpu_data.master_clock = master_clock;
445 current_cpu_data.bus_clock = bus_clock;
446 current_cpu_data.module_clock = module_clock;
447
448 /* Start TMU0 */ 324 /* Start TMU0 */
449 ctrl_outb(TMU_TSTR_OFF, TMU_TSTR); 325 ctrl_outb(TMU_TSTR_OFF, TMU_TSTR);
450 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR); 326 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
@@ -454,36 +330,6 @@ void __init time_init(void)
454 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR); 330 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
455} 331}
456 332
457void enter_deep_standby(void)
458{
459 /* Disable watchdog timer */
460 ctrl_outl(0xa5000000, WTCSR);
461 /* Configure deep standby on sleep */
462 ctrl_outl(0x03, STBCR);
463
464#ifdef CONFIG_SH_ALPHANUMERIC
465 {
466 extern void mach_alphanum(int position, unsigned char value);
467 extern void mach_alphanum_brightness(int setting);
468 char halted[] = "Halted. ";
469 int i;
470 mach_alphanum_brightness(6); /* dimmest setting above off */
471 for (i=0; i<8; i++) {
472 mach_alphanum(i, halted[i]);
473 }
474 asm __volatile__ ("synco");
475 }
476#endif
477
478 asm __volatile__ ("sleep");
479 asm __volatile__ ("synci");
480 asm __volatile__ ("nop");
481 asm __volatile__ ("nop");
482 asm __volatile__ ("nop");
483 asm __volatile__ ("nop");
484 panic("Unexpected wakeup!\n");
485}
486
487static struct resource rtc_resources[] = { 333static struct resource rtc_resources[] = {
488 [0] = { 334 [0] = {
489 /* RTC base, filled in by rtc_init */ 335 /* RTC base, filled in by rtc_init */
diff --git a/arch/sh/kernel/timers/Makefile b/arch/sh/kernel/timers/Makefile
index bcf244ff6a12..0b7f8577193f 100644
--- a/arch/sh/kernel/timers/Makefile
+++ b/arch/sh/kernel/timers/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_SH_TMU) += timer-tmu.o
8obj-$(CONFIG_SH_MTU2) += timer-mtu2.o 8obj-$(CONFIG_SH_MTU2) += timer-mtu2.o
9obj-$(CONFIG_SH_CMT) += timer-cmt.o 9obj-$(CONFIG_SH_CMT) += timer-cmt.o
10 10
11obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += timer-broadcast.o
diff --git a/arch/sh/kernel/timers/timer-broadcast.c b/arch/sh/kernel/timers/timer-broadcast.c
new file mode 100644
index 000000000000..c2317635230f
--- /dev/null
+++ b/arch/sh/kernel/timers/timer-broadcast.c
@@ -0,0 +1,57 @@
1/*
2 * Dummy local timer
3 *
4 * Copyright (C) 2008 Paul Mundt
5 *
6 * cloned from:
7 *
8 * linux/arch/arm/mach-realview/localtimer.c
9 *
10 * Copyright (C) 2002 ARM Ltd.
11 * All Rights Reserved
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/delay.h>
20#include <linux/device.h>
21#include <linux/smp.h>
22#include <linux/jiffies.h>
23#include <linux/percpu.h>
24#include <linux/clockchips.h>
25#include <linux/irq.h>
26
27static DEFINE_PER_CPU(struct clock_event_device, local_clockevent);
28
29/*
30 * Used on SMP for either the local timer or SMP_MSG_TIMER
31 */
32void local_timer_interrupt(void)
33{
34 struct clock_event_device *clk = &__get_cpu_var(local_clockevent);
35
36 clk->event_handler(clk);
37}
38
39static void dummy_timer_set_mode(enum clock_event_mode mode,
40 struct clock_event_device *clk)
41{
42}
43
44void __cpuinit local_timer_setup(unsigned int cpu)
45{
46 struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
47
48 clk->name = "dummy_timer";
49 clk->features = CLOCK_EVT_FEAT_DUMMY;
50 clk->rating = 200;
51 clk->mult = 1;
52 clk->set_mode = dummy_timer_set_mode;
53 clk->broadcast = smp_timer_broadcast;
54 clk->cpumask = cpumask_of_cpu(cpu);
55
56 clockevents_register_device(clk);
57}
diff --git a/arch/sh/kernel/timers/timer-cmt.c b/arch/sh/kernel/timers/timer-cmt.c
index d20c8c375881..c127293271e1 100644
--- a/arch/sh/kernel/timers/timer-cmt.c
+++ b/arch/sh/kernel/timers/timer-cmt.c
@@ -174,7 +174,7 @@ static int cmt_timer_init(void)
174 return 0; 174 return 0;
175} 175}
176 176
177struct sys_timer_ops cmt_timer_ops = { 177static struct sys_timer_ops cmt_timer_ops = {
178 .init = cmt_timer_init, 178 .init = cmt_timer_init,
179 .start = cmt_timer_start, 179 .start = cmt_timer_start,
180 .stop = cmt_timer_stop, 180 .stop = cmt_timer_stop,
diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c
index 1ca9ad49b541..aaaf90d06b85 100644
--- a/arch/sh/kernel/timers/timer-tmu.c
+++ b/arch/sh/kernel/timers/timer-tmu.c
@@ -28,43 +28,90 @@
28#define TMU_TOCR_INIT 0x00 28#define TMU_TOCR_INIT 0x00
29#define TMU_TCR_INIT 0x0020 29#define TMU_TCR_INIT 0x0020
30 30
31static int tmu_timer_start(void) 31#define TMU0 (0)
32#define TMU1 (1)
33
34static inline void _tmu_start(int tmu_num)
32{ 35{
33 ctrl_outb(ctrl_inb(TMU_012_TSTR) | 0x3, TMU_012_TSTR); 36 ctrl_outb(ctrl_inb(TMU_012_TSTR) | (0x1<<tmu_num), TMU_012_TSTR);
34 return 0;
35} 37}
36 38
37static void tmu0_timer_set_interval(unsigned long interval, unsigned int reload) 39static inline void _tmu_set_irq(int tmu_num, int enabled)
38{ 40{
39 ctrl_outl(interval, TMU0_TCNT); 41 register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
42 ctrl_outw( (enabled ? ctrl_inw(tmu_tcr) | (1<<5) : ctrl_inw(tmu_tcr) & ~(1<<5)), tmu_tcr);
43}
40 44
41 /* 45static inline void _tmu_stop(int tmu_num)
42 * TCNT reloads from TCOR on underflow, clear it if we don't 46{
43 * intend to auto-reload 47 ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~(0x1<<tmu_num), TMU_012_TSTR);
44 */ 48}
45 if (reload) 49
46 ctrl_outl(interval, TMU0_TCOR); 50static inline void _tmu_clear_status(int tmu_num)
47 else 51{
48 ctrl_outl(0, TMU0_TCOR); 52 register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
53 /* Clear UNF bit */
54 ctrl_outw(ctrl_inw(tmu_tcr) & ~0x100, tmu_tcr);
55}
49 56
50 tmu_timer_start(); 57static inline unsigned long _tmu_read(int tmu_num)
58{
59 return ctrl_inl(TMU0_TCNT+0xC*tmu_num);
60}
61
62static int tmu_timer_start(void)
63{
64 _tmu_start(TMU0);
65 _tmu_start(TMU1);
66 _tmu_set_irq(TMU0,1);
67 return 0;
51} 68}
52 69
53static int tmu_timer_stop(void) 70static int tmu_timer_stop(void)
54{ 71{
55 ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~0x3, TMU_012_TSTR); 72 _tmu_stop(TMU0);
73 _tmu_stop(TMU1);
74 _tmu_clear_status(TMU0);
56 return 0; 75 return 0;
57} 76}
58 77
78/*
79 * also when the module_clk is scaled the TMU1
80 * will show the same frequency
81 */
82static int tmus_are_scaled;
83
59static cycle_t tmu_timer_read(void) 84static cycle_t tmu_timer_read(void)
60{ 85{
61 return ~ctrl_inl(TMU1_TCNT); 86 return ((cycle_t)(~_tmu_read(TMU1)))<<tmus_are_scaled;
87}
88
89
90static unsigned long tmu_latest_interval[3];
91static void tmu_timer_set_interval(int tmu_num, unsigned long interval, unsigned int reload)
92{
93 unsigned long tmu_tcnt = TMU0_TCNT + tmu_num*0xC;
94 unsigned long tmu_tcor = TMU0_TCOR + tmu_num*0xC;
95
96 _tmu_stop(tmu_num);
97
98 ctrl_outl(interval, tmu_tcnt);
99 tmu_latest_interval[tmu_num] = interval;
100
101 /*
102 * TCNT reloads from TCOR on underflow, clear it if we don't
103 * intend to auto-reload
104 */
105 ctrl_outl( reload ? interval : 0 , tmu_tcor);
106
107 _tmu_start(tmu_num);
62} 108}
63 109
64static int tmu_set_next_event(unsigned long cycles, 110static int tmu_set_next_event(unsigned long cycles,
65 struct clock_event_device *evt) 111 struct clock_event_device *evt)
66{ 112{
67 tmu0_timer_set_interval(cycles, 1); 113 tmu_timer_set_interval(TMU0,cycles, evt->mode == CLOCK_EVT_MODE_PERIODIC);
114 _tmu_set_irq(TMU0,1);
68 return 0; 115 return 0;
69} 116}
70 117
@@ -96,12 +143,8 @@ static struct clock_event_device tmu0_clockevent = {
96static irqreturn_t tmu_timer_interrupt(int irq, void *dummy) 143static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
97{ 144{
98 struct clock_event_device *evt = &tmu0_clockevent; 145 struct clock_event_device *evt = &tmu0_clockevent;
99 unsigned long timer_status; 146 _tmu_clear_status(TMU0);
100 147 _tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT);
101 /* Clear UNF bit */
102 timer_status = ctrl_inw(TMU0_TCR);
103 timer_status &= ~0x100;
104 ctrl_outw(timer_status, TMU0_TCR);
105 148
106 evt->event_handler(evt); 149 evt->event_handler(evt);
107 150
@@ -109,56 +152,73 @@ static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
109} 152}
110 153
111static struct irqaction tmu0_irq = { 154static struct irqaction tmu0_irq = {
112 .name = "periodic timer", 155 .name = "periodic/oneshot timer",
113 .handler = tmu_timer_interrupt, 156 .handler = tmu_timer_interrupt,
114 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 157 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
115 .mask = CPU_MASK_NONE, 158 .mask = CPU_MASK_NONE,
116}; 159};
117 160
118static void tmu0_clk_init(struct clk *clk) 161static void __init tmu_clk_init(struct clk *clk)
119{ 162{
120 u8 divisor = TMU_TCR_INIT & 0x7; 163 u8 divisor = TMU_TCR_INIT & 0x7;
121 ctrl_outw(TMU_TCR_INIT, TMU0_TCR); 164 int tmu_num = clk->name[3]-'0';
122 clk->rate = clk->parent->rate / (4 << (divisor << 1)); 165 ctrl_outw(TMU_TCR_INIT, TMU0_TCR+(tmu_num*0xC));
166 clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
123} 167}
124 168
125static void tmu0_clk_recalc(struct clk *clk) 169static void tmu_clk_recalc(struct clk *clk)
126{ 170{
127 u8 divisor = ctrl_inw(TMU0_TCR) & 0x7; 171 int tmu_num = clk->name[3]-'0';
128 clk->rate = clk->parent->rate / (4 << (divisor << 1)); 172 unsigned long prev_rate = clk_get_rate(clk);
129} 173 unsigned long flags;
174 u8 divisor = ctrl_inw(TMU0_TCR+tmu_num*0xC) & 0x7;
175 clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
130 176
131static struct clk_ops tmu0_clk_ops = { 177 if(prev_rate==clk_get_rate(clk))
132 .init = tmu0_clk_init, 178 return;
133 .recalc = tmu0_clk_recalc,
134};
135 179
136static struct clk tmu0_clk = { 180 if(tmu_num)
137 .name = "tmu0_clk", 181 return; /* No more work on TMU1 */
138 .ops = &tmu0_clk_ops,
139};
140 182
141static void tmu1_clk_init(struct clk *clk) 183 local_irq_save(flags);
142{ 184 tmus_are_scaled = (prev_rate > clk->rate);
143 u8 divisor = TMU_TCR_INIT & 0x7;
144 ctrl_outw(divisor, TMU1_TCR);
145 clk->rate = clk->parent->rate / (4 << (divisor << 1));
146}
147 185
148static void tmu1_clk_recalc(struct clk *clk) 186 _tmu_stop(TMU0);
149{ 187
150 u8 divisor = ctrl_inw(TMU1_TCR) & 0x7; 188 tmu0_clockevent.mult = div_sc(clk->rate, NSEC_PER_SEC,
151 clk->rate = clk->parent->rate / (4 << (divisor << 1)); 189 tmu0_clockevent.shift);
190 tmu0_clockevent.max_delta_ns =
191 clockevent_delta2ns(-1, &tmu0_clockevent);
192 tmu0_clockevent.min_delta_ns =
193 clockevent_delta2ns(1, &tmu0_clockevent);
194
195 if (tmus_are_scaled)
196 tmu_latest_interval[TMU0] >>= 1;
197 else
198 tmu_latest_interval[TMU0] <<= 1;
199
200 tmu_timer_set_interval(TMU0,
201 tmu_latest_interval[TMU0],
202 tmu0_clockevent.mode == CLOCK_EVT_MODE_PERIODIC);
203
204 _tmu_start(TMU0);
205
206 local_irq_restore(flags);
152} 207}
153 208
154static struct clk_ops tmu1_clk_ops = { 209static struct clk_ops tmu_clk_ops = {
155 .init = tmu1_clk_init, 210 .init = tmu_clk_init,
156 .recalc = tmu1_clk_recalc, 211 .recalc = tmu_clk_recalc,
212};
213
214static struct clk tmu0_clk = {
215 .name = "tmu0_clk",
216 .ops = &tmu_clk_ops,
157}; 217};
158 218
159static struct clk tmu1_clk = { 219static struct clk tmu1_clk = {
160 .name = "tmu1_clk", 220 .name = "tmu1_clk",
161 .ops = &tmu1_clk_ops, 221 .ops = &tmu_clk_ops,
162}; 222};
163 223
164static int tmu_timer_init(void) 224static int tmu_timer_init(void)
@@ -189,11 +249,12 @@ static int tmu_timer_init(void)
189 frequency = clk_get_rate(&tmu0_clk); 249 frequency = clk_get_rate(&tmu0_clk);
190 interval = (frequency + HZ / 2) / HZ; 250 interval = (frequency + HZ / 2) / HZ;
191 251
192 sh_hpt_frequency = clk_get_rate(&tmu1_clk); 252 tmu_timer_set_interval(TMU0,interval, 1);
193 ctrl_outl(~0, TMU1_TCNT); 253 tmu_timer_set_interval(TMU1,~0,1);
194 ctrl_outl(~0, TMU1_TCOR);
195 254
196 tmu0_timer_set_interval(interval, 1); 255 _tmu_start(TMU1);
256
257 sh_hpt_frequency = clk_get_rate(&tmu1_clk);
197 258
198 tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC, 259 tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
199 tmu0_clockevent.shift); 260 tmu0_clockevent.shift);
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index 511a9426cec5..b359b08a8e33 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -26,6 +26,7 @@
26#include <asm/system.h> 26#include <asm/system.h>
27#include <asm/uaccess.h> 27#include <asm/uaccess.h>
28#include <asm/fpu.h> 28#include <asm/fpu.h>
29#include <asm/kprobes.h>
29 30
30#ifdef CONFIG_SH_KGDB 31#ifdef CONFIG_SH_KGDB
31#include <asm/kgdb.h> 32#include <asm/kgdb.h>
@@ -192,6 +193,7 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
192 int ret, index, count; 193 int ret, index, count;
193 unsigned long *rm, *rn; 194 unsigned long *rm, *rn;
194 unsigned char *src, *dst; 195 unsigned char *src, *dst;
196 unsigned char __user *srcu, *dstu;
195 197
196 index = (instruction>>8)&15; /* 0x0F00 */ 198 index = (instruction>>8)&15; /* 0x0F00 */
197 rn = &regs->regs[index]; 199 rn = &regs->regs[index];
@@ -206,28 +208,28 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
206 case 0: /* mov.[bwl] to/from memory via r0+rn */ 208 case 0: /* mov.[bwl] to/from memory via r0+rn */
207 if (instruction & 8) { 209 if (instruction & 8) {
208 /* from memory */ 210 /* from memory */
209 src = (unsigned char*) *rm; 211 srcu = (unsigned char __user *)*rm;
210 src += regs->regs[0]; 212 srcu += regs->regs[0];
211 dst = (unsigned char*) rn; 213 dst = (unsigned char *)rn;
212 *(unsigned long*)dst = 0; 214 *(unsigned long *)dst = 0;
213 215
214#if !defined(__LITTLE_ENDIAN__) 216#if !defined(__LITTLE_ENDIAN__)
215 dst += 4-count; 217 dst += 4-count;
216#endif 218#endif
217 if (ma->from(dst, src, count)) 219 if (ma->from(dst, srcu, count))
218 goto fetch_fault; 220 goto fetch_fault;
219 221
220 sign_extend(count, dst); 222 sign_extend(count, dst);
221 } else { 223 } else {
222 /* to memory */ 224 /* to memory */
223 src = (unsigned char*) rm; 225 src = (unsigned char *)rm;
224#if !defined(__LITTLE_ENDIAN__) 226#if !defined(__LITTLE_ENDIAN__)
225 src += 4-count; 227 src += 4-count;
226#endif 228#endif
227 dst = (unsigned char*) *rn; 229 dstu = (unsigned char __user *)*rn;
228 dst += regs->regs[0]; 230 dstu += regs->regs[0];
229 231
230 if (ma->to(dst, src, count)) 232 if (ma->to(dstu, src, count))
231 goto fetch_fault; 233 goto fetch_fault;
232 } 234 }
233 ret = 0; 235 ret = 0;
@@ -235,10 +237,10 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
235 237
236 case 1: /* mov.l Rm,@(disp,Rn) */ 238 case 1: /* mov.l Rm,@(disp,Rn) */
237 src = (unsigned char*) rm; 239 src = (unsigned char*) rm;
238 dst = (unsigned char*) *rn; 240 dstu = (unsigned char __user *)*rn;
239 dst += (instruction&0x000F)<<2; 241 dstu += (instruction&0x000F)<<2;
240 242
241 if (ma->to(dst, src, 4)) 243 if (ma->to(dstu, src, 4))
242 goto fetch_fault; 244 goto fetch_fault;
243 ret = 0; 245 ret = 0;
244 break; 246 break;
@@ -247,28 +249,28 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
247 if (instruction & 4) 249 if (instruction & 4)
248 *rn -= count; 250 *rn -= count;
249 src = (unsigned char*) rm; 251 src = (unsigned char*) rm;
250 dst = (unsigned char*) *rn; 252 dstu = (unsigned char __user *)*rn;
251#if !defined(__LITTLE_ENDIAN__) 253#if !defined(__LITTLE_ENDIAN__)
252 src += 4-count; 254 src += 4-count;
253#endif 255#endif
254 if (ma->to(dst, src, count)) 256 if (ma->to(dstu, src, count))
255 goto fetch_fault; 257 goto fetch_fault;
256 ret = 0; 258 ret = 0;
257 break; 259 break;
258 260
259 case 5: /* mov.l @(disp,Rm),Rn */ 261 case 5: /* mov.l @(disp,Rm),Rn */
260 src = (unsigned char*) *rm; 262 srcu = (unsigned char __user *)*rm;
261 src += (instruction&0x000F)<<2; 263 srcu += (instruction & 0x000F) << 2;
262 dst = (unsigned char*) rn; 264 dst = (unsigned char *)rn;
263 *(unsigned long*)dst = 0; 265 *(unsigned long *)dst = 0;
264 266
265 if (ma->from(dst, src, 4)) 267 if (ma->from(dst, srcu, 4))
266 goto fetch_fault; 268 goto fetch_fault;
267 ret = 0; 269 ret = 0;
268 break; 270 break;
269 271
270 case 6: /* mov.[bwl] from memory, possibly with post-increment */ 272 case 6: /* mov.[bwl] from memory, possibly with post-increment */
271 src = (unsigned char*) *rm; 273 srcu = (unsigned char __user *)*rm;
272 if (instruction & 4) 274 if (instruction & 4)
273 *rm += count; 275 *rm += count;
274 dst = (unsigned char*) rn; 276 dst = (unsigned char*) rn;
@@ -277,7 +279,7 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
277#if !defined(__LITTLE_ENDIAN__) 279#if !defined(__LITTLE_ENDIAN__)
278 dst += 4-count; 280 dst += 4-count;
279#endif 281#endif
280 if (ma->from(dst, src, count)) 282 if (ma->from(dst, srcu, count))
281 goto fetch_fault; 283 goto fetch_fault;
282 sign_extend(count, dst); 284 sign_extend(count, dst);
283 ret = 0; 285 ret = 0;
@@ -286,28 +288,28 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
286 case 8: 288 case 8:
287 switch ((instruction&0xFF00)>>8) { 289 switch ((instruction&0xFF00)>>8) {
288 case 0x81: /* mov.w R0,@(disp,Rn) */ 290 case 0x81: /* mov.w R0,@(disp,Rn) */
289 src = (unsigned char*) &regs->regs[0]; 291 src = (unsigned char *) &regs->regs[0];
290#if !defined(__LITTLE_ENDIAN__) 292#if !defined(__LITTLE_ENDIAN__)
291 src += 2; 293 src += 2;
292#endif 294#endif
293 dst = (unsigned char*) *rm; /* called Rn in the spec */ 295 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
294 dst += (instruction&0x000F)<<1; 296 dstu += (instruction & 0x000F) << 1;
295 297
296 if (ma->to(dst, src, 2)) 298 if (ma->to(dstu, src, 2))
297 goto fetch_fault; 299 goto fetch_fault;
298 ret = 0; 300 ret = 0;
299 break; 301 break;
300 302
301 case 0x85: /* mov.w @(disp,Rm),R0 */ 303 case 0x85: /* mov.w @(disp,Rm),R0 */
302 src = (unsigned char*) *rm; 304 srcu = (unsigned char __user *)*rm;
303 src += (instruction&0x000F)<<1; 305 srcu += (instruction & 0x000F) << 1;
304 dst = (unsigned char*) &regs->regs[0]; 306 dst = (unsigned char *) &regs->regs[0];
305 *(unsigned long*)dst = 0; 307 *(unsigned long *)dst = 0;
306 308
307#if !defined(__LITTLE_ENDIAN__) 309#if !defined(__LITTLE_ENDIAN__)
308 dst += 2; 310 dst += 2;
309#endif 311#endif
310 if (ma->from(dst, src, 2)) 312 if (ma->from(dst, srcu, 2))
311 goto fetch_fault; 313 goto fetch_fault;
312 sign_extend(2, dst); 314 sign_extend(2, dst);
313 ret = 0; 315 ret = 0;
@@ -333,7 +335,8 @@ static inline int handle_delayslot(struct pt_regs *regs,
333 struct mem_access *ma) 335 struct mem_access *ma)
334{ 336{
335 opcode_t instruction; 337 opcode_t instruction;
336 void *addr = (void *)(regs->pc + instruction_size(old_instruction)); 338 void __user *addr = (void __user *)(regs->pc +
339 instruction_size(old_instruction));
337 340
338 if (copy_from_user(&instruction, addr, sizeof(instruction))) { 341 if (copy_from_user(&instruction, addr, sizeof(instruction))) {
339 /* the instruction-fetch faulted */ 342 /* the instruction-fetch faulted */
@@ -511,14 +514,6 @@ int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs,
511 return ret; 514 return ret;
512} 515}
513 516
514#ifdef CONFIG_CPU_HAS_SR_RB
515#define lookup_exception_vector(x) \
516 __asm__ __volatile__ ("stc r2_bank, %0\n\t" : "=r" ((x)))
517#else
518#define lookup_exception_vector(x) \
519 __asm__ __volatile__ ("mov r4, %0\n\t" : "=r" ((x)))
520#endif
521
522/* 517/*
523 * Handle various address error exceptions: 518 * Handle various address error exceptions:
524 * - instruction address error: 519 * - instruction address error:
@@ -542,7 +537,7 @@ asmlinkage void do_address_error(struct pt_regs *regs,
542 537
543 /* Intentional ifdef */ 538 /* Intentional ifdef */
544#ifdef CONFIG_CPU_HAS_SR_RB 539#ifdef CONFIG_CPU_HAS_SR_RB
545 lookup_exception_vector(error_code); 540 error_code = lookup_exception_vector();
546#endif 541#endif
547 542
548 oldfs = get_fs(); 543 oldfs = get_fs();
@@ -559,7 +554,7 @@ asmlinkage void do_address_error(struct pt_regs *regs,
559 } 554 }
560 555
561 set_fs(USER_DS); 556 set_fs(USER_DS);
562 if (copy_from_user(&instruction, (void *)(regs->pc), 557 if (copy_from_user(&instruction, (void __user *)(regs->pc),
563 sizeof(instruction))) { 558 sizeof(instruction))) {
564 /* Argh. Fault on the instruction itself. 559 /* Argh. Fault on the instruction itself.
565 This should never happen non-SMP 560 This should never happen non-SMP
@@ -589,7 +584,7 @@ uspace_segv:
589 die("unaligned program counter", regs, error_code); 584 die("unaligned program counter", regs, error_code);
590 585
591 set_fs(KERNEL_DS); 586 set_fs(KERNEL_DS);
592 if (copy_from_user(&instruction, (void *)(regs->pc), 587 if (copy_from_user(&instruction, (void __user *)(regs->pc),
593 sizeof(instruction))) { 588 sizeof(instruction))) {
594 /* Argh. Fault on the instruction itself. 589 /* Argh. Fault on the instruction itself.
595 This should never happen non-SMP 590 This should never happen non-SMP
@@ -683,7 +678,7 @@ asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
683 } 678 }
684#endif 679#endif
685 680
686 lookup_exception_vector(error_code); 681 error_code = lookup_exception_vector();
687 682
688 local_irq_enable(); 683 local_irq_enable();
689 CHK_REMOTE_DEBUG(regs); 684 CHK_REMOTE_DEBUG(regs);
@@ -739,11 +734,13 @@ asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
739 struct pt_regs __regs) 734 struct pt_regs __regs)
740{ 735{
741 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 736 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
742 unsigned long error_code; 737 unsigned long inst;
743 struct task_struct *tsk = current; 738 struct task_struct *tsk = current;
744#ifdef CONFIG_SH_FPU_EMU
745 unsigned short inst = 0;
746 739
740 if (kprobe_handle_illslot(regs->pc) == 0)
741 return;
742
743#ifdef CONFIG_SH_FPU_EMU
747 get_user(inst, (unsigned short *)regs->pc + 1); 744 get_user(inst, (unsigned short *)regs->pc + 1);
748 if (!do_fpu_inst(inst, regs)) { 745 if (!do_fpu_inst(inst, regs)) {
749 get_user(inst, (unsigned short *)regs->pc); 746 get_user(inst, (unsigned short *)regs->pc);
@@ -754,12 +751,12 @@ asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
754 /* not a FPU inst. */ 751 /* not a FPU inst. */
755#endif 752#endif
756 753
757 lookup_exception_vector(error_code); 754 inst = lookup_exception_vector();
758 755
759 local_irq_enable(); 756 local_irq_enable();
760 CHK_REMOTE_DEBUG(regs); 757 CHK_REMOTE_DEBUG(regs);
761 force_sig(SIGILL, tsk); 758 force_sig(SIGILL, tsk);
762 die_if_no_fixup("illegal slot instruction", regs, error_code); 759 die_if_no_fixup("illegal slot instruction", regs, inst);
763} 760}
764 761
765asmlinkage void do_exception_error(unsigned long r4, unsigned long r5, 762asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
@@ -769,7 +766,7 @@ asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
769 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); 766 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
770 long ex; 767 long ex;
771 768
772 lookup_exception_vector(ex); 769 ex = lookup_exception_vector();
773 die_if_kernel("exception", regs, ex); 770 die_if_kernel("exception", regs, ex);
774} 771}
775 772
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-09 09:23:18 -0400