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authorLinus Torvalds <torvalds@g5.osdl.org>2006-10-12 11:33:23 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-10-12 11:33:23 -0400
commit9eb200748878751310cd9848c5dd4d467960beec (patch)
tree16458876279abbc597843a7c1bb8216474691380 /arch/sh/kernel
parent8770c018da7bbaa3b41371abc401b2aa7e76a71a (diff)
parent8ae91b9ad88a130cd50fc0b78b16e7b9510b8067 (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: sh: SH-4A UBC support sh: interrupt exception handling rework sh: Default enable R7780RP IRQs. sh: Zero-out coherent buffer in consistent_alloc(). sh: Convert IPR-IRQ to IRQ chip. sh: Convert INTC2 IRQ handler to irq_chip. sh: Fix pr_debug statements for sh4 sh: Convert r7780rp IRQ handler to IRQ chip. sh: Updates for IRQ handler changes. sh: Kill off timer_ops get_frequency(). sh: First step at generic timeofday support.
Diffstat (limited to 'arch/sh/kernel')
-rw-r--r--arch/sh/kernel/cpu/irq/intc2.c138
-rw-r--r--arch/sh/kernel/cpu/irq/ipr.c102
-rw-r--r--arch/sh/kernel/cpu/sh3/ex.S195
-rw-r--r--arch/sh/kernel/cpu/sh4/ex.S500
-rw-r--r--arch/sh/kernel/entry.S43
-rw-r--r--arch/sh/kernel/irq.c42
-rw-r--r--arch/sh/kernel/process.c30
-rw-r--r--arch/sh/kernel/time.c9
-rw-r--r--arch/sh/kernel/timers/timer-tmu.c63
9 files changed, 144 insertions, 978 deletions
diff --git a/arch/sh/kernel/cpu/irq/intc2.c b/arch/sh/kernel/cpu/irq/intc2.c
index e30e4b7aa70e..d4b2bb7e08c7 100644
--- a/arch/sh/kernel/cpu/irq/intc2.c
+++ b/arch/sh/kernel/cpu/irq/intc2.c
@@ -10,93 +10,32 @@
10 * These are the "new Hitachi style" interrupts, as present on the 10 * These are the "new Hitachi style" interrupts, as present on the
11 * Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780. 11 * Hitachi 7751, the STM ST40 STB1, SH7760, and SH7780.
12 */ 12 */
13
14#include <linux/kernel.h> 13#include <linux/kernel.h>
15#include <linux/init.h> 14#include <linux/init.h>
16#include <linux/irq.h> 15#include <linux/irq.h>
17#include <asm/system.h> 16#include <asm/system.h>
18#include <asm/io.h> 17#include <asm/io.h>
19#include <asm/machvec.h>
20
21struct intc2_data {
22 unsigned char msk_offset;
23 unsigned char msk_shift;
24
25 int (*clear_irq) (int);
26};
27
28static struct intc2_data intc2_data[NR_INTC2_IRQS];
29
30static void enable_intc2_irq(unsigned int irq);
31static void disable_intc2_irq(unsigned int irq);
32
33/* shutdown is same as "disable" */
34#define shutdown_intc2_irq disable_intc2_irq
35
36static void mask_and_ack_intc2(unsigned int);
37static void end_intc2_irq(unsigned int irq);
38
39static unsigned int startup_intc2_irq(unsigned int irq)
40{
41 enable_intc2_irq(irq);
42 return 0; /* never anything pending */
43}
44
45static struct hw_interrupt_type intc2_irq_type = {
46 .typename = "INTC2-IRQ",
47 .startup = startup_intc2_irq,
48 .shutdown = shutdown_intc2_irq,
49 .enable = enable_intc2_irq,
50 .disable = disable_intc2_irq,
51 .ack = mask_and_ack_intc2,
52 .end = end_intc2_irq
53};
54 18
55static void disable_intc2_irq(unsigned int irq) 19static void disable_intc2_irq(unsigned int irq)
56{ 20{
57 int irq_offset = irq - INTC2_FIRST_IRQ; 21 struct intc2_data *p = get_irq_chip_data(irq);
58 int msk_shift, msk_offset; 22 ctrl_outl(1 << p->msk_shift,
59 23 INTC2_BASE + INTC2_INTMSK_OFFSET + p->msk_offset);
60 /* Sanity check */
61 if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))
62 return;
63
64 msk_shift = intc2_data[irq_offset].msk_shift;
65 msk_offset = intc2_data[irq_offset].msk_offset;
66
67 ctrl_outl(1 << msk_shift,
68 INTC2_BASE + INTC2_INTMSK_OFFSET + msk_offset);
69} 24}
70 25
71static void enable_intc2_irq(unsigned int irq) 26static void enable_intc2_irq(unsigned int irq)
72{ 27{
73 int irq_offset = irq - INTC2_FIRST_IRQ; 28 struct intc2_data *p = get_irq_chip_data(irq);
74 int msk_shift, msk_offset; 29 ctrl_outl(1 << p->msk_shift,
75 30 INTC2_BASE + INTC2_INTMSKCLR_OFFSET + p->msk_offset);
76 /* Sanity check */
77 if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS))
78 return;
79
80 msk_shift = intc2_data[irq_offset].msk_shift;
81 msk_offset = intc2_data[irq_offset].msk_offset;
82
83 ctrl_outl(1 << msk_shift,
84 INTC2_BASE + INTC2_INTMSKCLR_OFFSET + msk_offset);
85}
86
87static void mask_and_ack_intc2(unsigned int irq)
88{
89 disable_intc2_irq(irq);
90} 31}
91 32
92static void end_intc2_irq(unsigned int irq) 33static struct irq_chip intc2_irq_chip = {
93{ 34 .typename = "intc2",
94 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 35 .mask = disable_intc2_irq,
95 enable_intc2_irq(irq); 36 .unmask = enable_intc2_irq,
96 37 .mask_ack = disable_intc2_irq,
97 if (unlikely(intc2_data[irq - INTC2_FIRST_IRQ].clear_irq)) 38};
98 intc2_data[irq - INTC2_FIRST_IRQ].clear_irq(irq);
99}
100 39
101/* 40/*
102 * Setup an INTC2 style interrupt. 41 * Setup an INTC2 style interrupt.
@@ -108,46 +47,30 @@ static void end_intc2_irq(unsigned int irq)
108 * | | | | 47 * | | | |
109 * make_intc2_irq(84, 0, 16, 0, 13); 48 * make_intc2_irq(84, 0, 16, 0, 13);
110 */ 49 */
111void make_intc2_irq(unsigned int irq, 50void make_intc2_irq(struct intc2_data *p)
112 unsigned int ipr_offset, unsigned int ipr_shift,
113 unsigned int msk_offset, unsigned int msk_shift,
114 unsigned int priority)
115{ 51{
116 int irq_offset = irq - INTC2_FIRST_IRQ;
117 unsigned int flags; 52 unsigned int flags;
118 unsigned long ipr; 53 unsigned long ipr;
119 54
120 if (unlikely(irq_offset < 0 || irq_offset >= NR_INTC2_IRQS)) 55 disable_irq_nosync(p->irq);
121 return;
122
123 disable_irq_nosync(irq);
124
125 /* Fill the data we need */
126 intc2_data[irq_offset].msk_offset = msk_offset;
127 intc2_data[irq_offset].msk_shift = msk_shift;
128 intc2_data[irq_offset].clear_irq = NULL;
129 56
130 /* Set the priority level */ 57 /* Set the priority level */
131 local_irq_save(flags); 58 local_irq_save(flags);
132 59
133 ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + ipr_offset); 60 ipr = ctrl_inl(INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
134 ipr &= ~(0xf << ipr_shift); 61 ipr &= ~(0xf << p->ipr_shift);
135 ipr |= priority << ipr_shift; 62 ipr |= p->priority << p->ipr_shift;
136 ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + ipr_offset); 63 ctrl_outl(ipr, INTC2_BASE + INTC2_INTPRI_OFFSET + p->ipr_offset);
137 64
138 local_irq_restore(flags); 65 local_irq_restore(flags);
139 66
140 irq_desc[irq].chip = &intc2_irq_type; 67 set_irq_chip_and_handler(p->irq, &intc2_irq_chip, handle_level_irq);
68 set_irq_chip_data(p->irq, p);
141 69
142 disable_intc2_irq(irq); 70 enable_intc2_irq(p->irq);
143} 71}
144 72
145static struct intc2_init { 73static struct intc2_data intc2_irq_table[] = {
146 unsigned short irq;
147 unsigned char ipr_offset, ipr_shift;
148 unsigned char msk_offset, msk_shift;
149 unsigned char priority;
150} intc2_init_data[] __initdata = {
151#if defined(CONFIG_CPU_SUBTYPE_ST40) 74#if defined(CONFIG_CPU_SUBTYPE_ST40)
152 {64, 0, 0, 0, 0, 13}, /* PCI serr */ 75 {64, 0, 0, 0, 0, 13}, /* PCI serr */
153 {65, 0, 4, 0, 1, 13}, /* PCI err */ 76 {65, 0, 4, 0, 1, 13}, /* PCI err */
@@ -266,19 +189,6 @@ void __init init_IRQ_intc2(void)
266{ 189{
267 int i; 190 int i;
268 191
269 for (i = 0; i < ARRAY_SIZE(intc2_init_data); i++) { 192 for (i = 0; i < ARRAY_SIZE(intc2_irq_table); i++)
270 struct intc2_init *p = intc2_init_data + i; 193 make_intc2_irq(intc2_irq_table + i);
271 make_intc2_irq(p->irq, p->ipr_offset, p->ipr_shift,
272 p-> msk_offset, p->msk_shift, p->priority);
273 }
274}
275
276/* Adds a termination callback to the interrupt */
277void intc2_add_clear_irq(int irq, int (*fn)(int))
278{
279 if (unlikely(irq < INTC2_FIRST_IRQ))
280 return;
281
282 intc2_data[irq - INTC2_FIRST_IRQ].clear_irq = fn;
283} 194}
284
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index f785822cd5de..8944abdf6e1c 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -1,11 +1,10 @@
1/* 1/*
2 * arch/sh/kernel/cpu/irq/ipr.c 2 * Interrupt handling for IPR-based IRQ.
3 * 3 *
4 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi 4 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
5 * Copyright (C) 2000 Kazumoto Kojima 5 * Copyright (C) 2000 Kazumoto Kojima
6 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> 6 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
7 * 7 * Copyright (C) 2006 Paul Mundt
8 * Interrupt handling for IPR-based IRQ.
9 * 8 *
10 * Supported system: 9 * Supported system:
11 * On-chip supporting modules (TMU, RTC, etc.). 10 * On-chip supporting modules (TMU, RTC, etc.).
@@ -13,12 +12,13 @@
13 * Hitachi SolutionEngine external I/O: 12 * Hitachi SolutionEngine external I/O:
14 * MS7709SE01, MS7709ASE01, and MS7750SE01 13 * MS7709SE01, MS7709ASE01, and MS7750SE01
15 * 14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details.
16 */ 18 */
17
18#include <linux/init.h> 19#include <linux/init.h>
19#include <linux/irq.h> 20#include <linux/irq.h>
20#include <linux/module.h> 21#include <linux/module.h>
21
22#include <asm/system.h> 22#include <asm/system.h>
23#include <asm/io.h> 23#include <asm/io.h>
24#include <asm/machvec.h> 24#include <asm/machvec.h>
@@ -28,93 +28,45 @@ struct ipr_data {
28 int shift; /* Shifts of the 16-bit data */ 28 int shift; /* Shifts of the 16-bit data */
29 int priority; /* The priority */ 29 int priority; /* The priority */
30}; 30};
31static struct ipr_data ipr_data[NR_IRQS];
32
33static void enable_ipr_irq(unsigned int irq);
34static void disable_ipr_irq(unsigned int irq);
35
36/* shutdown is same as "disable" */
37#define shutdown_ipr_irq disable_ipr_irq
38
39static void mask_and_ack_ipr(unsigned int);
40static void end_ipr_irq(unsigned int irq);
41
42static unsigned int startup_ipr_irq(unsigned int irq)
43{
44 enable_ipr_irq(irq);
45 return 0; /* never anything pending */
46}
47
48static struct hw_interrupt_type ipr_irq_type = {
49 .typename = "IPR-IRQ",
50 .startup = startup_ipr_irq,
51 .shutdown = shutdown_ipr_irq,
52 .enable = enable_ipr_irq,
53 .disable = disable_ipr_irq,
54 .ack = mask_and_ack_ipr,
55 .end = end_ipr_irq
56};
57 31
58static void disable_ipr_irq(unsigned int irq) 32static void disable_ipr_irq(unsigned int irq)
59{ 33{
60 unsigned long val; 34 struct ipr_data *p = get_irq_chip_data(irq);
61 unsigned int addr = ipr_data[irq].addr;
62 unsigned short mask = 0xffff ^ (0x0f << ipr_data[irq].shift);
63
64 /* Set the priority in IPR to 0 */ 35 /* Set the priority in IPR to 0 */
65 val = ctrl_inw(addr); 36 ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr);
66 val &= mask;
67 ctrl_outw(val, addr);
68} 37}
69 38
70static void enable_ipr_irq(unsigned int irq) 39static void enable_ipr_irq(unsigned int irq)
71{ 40{
72 unsigned long val; 41 struct ipr_data *p = get_irq_chip_data(irq);
73 unsigned int addr = ipr_data[irq].addr;
74 int priority = ipr_data[irq].priority;
75 unsigned short value = (priority << ipr_data[irq].shift);
76
77 /* Set priority in IPR back to original value */ 42 /* Set priority in IPR back to original value */
78 val = ctrl_inw(addr); 43 ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr);
79 val |= value;
80 ctrl_outw(val, addr);
81} 44}
82 45
83static void mask_and_ack_ipr(unsigned int irq) 46static struct irq_chip ipr_irq_chip = {
84{ 47 .name = "ipr",
85 disable_ipr_irq(irq); 48 .mask = disable_ipr_irq,
86 49 .unmask = enable_ipr_irq,
87#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 50 .mask_ack = disable_ipr_irq,
88 defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 51};
89 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
90 /* This is needed when we use edge triggered setting */
91 /* XXX: Is it really needed? */
92 if (IRQ0_IRQ <= irq && irq <= IRQ5_IRQ) {
93 /* Clear external interrupt request */
94 int a = ctrl_inb(INTC_IRR0);
95 a &= ~(1 << (irq - IRQ0_IRQ));
96 ctrl_outb(a, INTC_IRR0);
97 }
98#endif
99}
100
101static void end_ipr_irq(unsigned int irq)
102{
103 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
104 enable_ipr_irq(irq);
105}
106 52
107void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority) 53void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
108{ 54{
55 struct ipr_data ipr_data;
56
109 disable_irq_nosync(irq); 57 disable_irq_nosync(irq);
110 ipr_data[irq].addr = addr;
111 ipr_data[irq].shift = pos*4; /* POSition (0-3) x 4 means shift */
112 ipr_data[irq].priority = priority;
113 58
114 irq_desc[irq].chip = &ipr_irq_type; 59 ipr_data.addr = addr;
115 disable_ipr_irq(irq); 60 ipr_data.shift = pos*4; /* POSition (0-3) x 4 means shift */
61 ipr_data.priority = priority;
62
63 set_irq_chip_and_handler(irq, &ipr_irq_chip, handle_level_irq);
64 set_irq_chip_data(irq, &ipr_data);
65
66 enable_ipr_irq(irq);
116} 67}
117 68
69/* XXX: This needs to die a horrible death.. */
118void __init init_IRQ(void) 70void __init init_IRQ(void)
119{ 71{
120#ifndef CONFIG_CPU_SUBTYPE_SH7780 72#ifndef CONFIG_CPU_SUBTYPE_SH7780
diff --git a/arch/sh/kernel/cpu/sh3/ex.S b/arch/sh/kernel/cpu/sh3/ex.S
index 44daf44833f9..6be46f0686b7 100644
--- a/arch/sh/kernel/cpu/sh3/ex.S
+++ b/arch/sh/kernel/cpu/sh3/ex.S
@@ -49,198 +49,3 @@ ENTRY(nmi_slot)
49#endif 49#endif
50ENTRY(user_break_point_trap) 50ENTRY(user_break_point_trap)
51 .long break_point_trap /* 1E0 */ 51 .long break_point_trap /* 1E0 */
52ENTRY(interrupt_table)
53 ! external hardware
54 .long do_IRQ ! 0000 /* 200 */
55 .long do_IRQ ! 0001
56 .long do_IRQ ! 0010
57 .long do_IRQ ! 0011
58 .long do_IRQ ! 0100
59 .long do_IRQ ! 0101
60 .long do_IRQ ! 0110
61 .long do_IRQ ! 0111
62 .long do_IRQ ! 1000 /* 300 */
63 .long do_IRQ ! 1001
64 .long do_IRQ ! 1010
65 .long do_IRQ ! 1011
66 .long do_IRQ ! 1100
67 .long do_IRQ ! 1101
68 .long do_IRQ ! 1110
69 .long exception_error
70 ! Internal hardware
71 .long do_IRQ ! TMU0 tuni0 /* 400 */
72 .long do_IRQ ! TMU1 tuni1
73 .long do_IRQ ! TMU2 tuni2
74 .long do_IRQ ! ticpi2
75 .long do_IRQ ! RTC ati
76 .long do_IRQ ! pri
77 .long do_IRQ ! cui
78 .long do_IRQ ! SCI eri
79 .long do_IRQ ! rxi /* 500 */
80 .long do_IRQ ! txi
81 .long do_IRQ ! tei
82 .long do_IRQ ! WDT iti /* 560 */
83 .long do_IRQ ! REF rcmi
84 .long do_IRQ ! rovi
85 .long do_IRQ
86 .long do_IRQ /* 5E0 */
87#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
88 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
89 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
90 defined(CONFIG_CPU_SUBTYPE_SH7300) || \
91 defined(CONFIG_CPU_SUBTYPE_SH7705) || \
92 defined(CONFIG_CPU_SUBTYPE_SH7710)
93 .long do_IRQ ! 32 IRQ irq0 /* 600 */
94 .long do_IRQ ! 33 irq1
95 .long do_IRQ ! 34 irq2
96 .long do_IRQ ! 35 irq3
97 .long do_IRQ ! 36 irq4
98 .long do_IRQ ! 37 irq5
99 .long do_IRQ ! 38
100 .long do_IRQ ! 39
101 .long do_IRQ ! 40 PINT pint0-7 /* 700 */
102 .long do_IRQ ! 41 pint8-15
103 .long do_IRQ ! 42
104 .long do_IRQ ! 43
105 .long do_IRQ ! 44
106 .long do_IRQ ! 45
107 .long do_IRQ ! 46
108 .long do_IRQ ! 47
109 .long do_IRQ ! 48 DMAC dei0 /* 800 */
110 .long do_IRQ ! 49 dei1
111 .long do_IRQ ! 50 dei2
112 .long do_IRQ ! 51 dei3
113 .long do_IRQ ! 52 IrDA eri1
114 .long do_IRQ ! 53 rxi1
115 .long do_IRQ ! 54 bri1
116 .long do_IRQ ! 55 txi1
117 .long do_IRQ ! 56 SCIF eri2
118 .long do_IRQ ! 57 rxi2
119 .long do_IRQ ! 58 bri2
120 .long do_IRQ ! 59 txi2
121 .long do_IRQ ! 60 ADC adi /* 980 */
122#if defined(CONFIG_CPU_SUBTYPE_SH7705)
123 .long exception_none ! 61 /* 9A0 */
124 .long exception_none ! 62
125 .long exception_none ! 63
126 .long exception_none ! 64 /* A00 */
127 .long do_IRQ ! 65 USB usi0
128 .long do_IRQ ! 66 usi1
129 .long exception_none ! 67
130 .long exception_none ! 68
131 .long exception_none ! 69
132 .long exception_none ! 70
133 .long exception_none ! 71
134 .long exception_none ! 72 /* B00 */
135 .long exception_none ! 73
136 .long exception_none ! 74
137 .long exception_none ! 75
138 .long exception_none ! 76
139 .long exception_none ! 77
140 .long exception_none ! 78
141 .long exception_none ! 79
142 .long do_IRQ ! 80 TPU0 tpi0 /* C00 */
143 .long do_IRQ ! 81 TPU1 tpi1
144 .long exception_none ! 82
145 .long exception_none ! 83
146 .long do_IRQ ! 84 TPU2 tpi2
147 .long do_IRQ ! 85 TPU3 tpi3 /* CA0 */
148#endif
149#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7300)
150 .long do_IRQ ! 61 LCDC lcdi /* 9A0 */
151 .long do_IRQ ! 62 PCC pcc0i
152 .long do_IRQ ! 63 pcc1i /* 9E0 */
153#endif
154#if defined(CONFIG_CPU_SUBTYPE_SH7710)
155 .long exception_none ! 61 /* 9A0 */
156 .long exception_none ! 62
157 .long exception_none ! 63
158 .long exception_none ! 64 /* A00 */
159 .long exception_none ! 65
160 .long exception_none ! 66
161 .long exception_none ! 67
162 .long exception_none ! 68
163 .long exception_none ! 69
164 .long exception_none ! 70
165 .long exception_none ! 71
166 .long exception_none ! 72 /* B00 */
167 .long exception_none ! 73
168 .long exception_none ! 74
169 .long exception_none ! 75
170 .long do_IRQ ! 76 DMAC2 dei4 /* B80 */
171 .long do_IRQ ! 77 DMAC2 dei5
172 .long exception_none ! 78
173 .long do_IRQ ! 79 IPSEC ipseci /* BE0 */
174 .long do_IRQ ! 80 EDMAC eint0 /* C00 */
175 .long do_IRQ ! 81 EDMAC eint1
176 .long do_IRQ ! 82 EDMAC eint2
177 .long exception_none ! 83 /* C60 */
178 .long exception_none ! 84
179 .long exception_none ! 85
180 .long exception_none ! 86
181 .long exception_none ! 87
182 .long exception_none ! 88 /* D00 */
183 .long exception_none ! 89
184 .long exception_none ! 90
185 .long exception_none ! 91
186 .long exception_none ! 92
187 .long exception_none ! 93
188 .long exception_none ! 94
189 .long exception_none ! 95
190 .long do_IRQ ! 96 SIOF eri0 /* E00 */
191 .long do_IRQ ! 97 txi0
192 .long do_IRQ ! 98 rxi0
193 .long do_IRQ ! 99 cci0
194 .long do_IRQ ! 100 eri1 /* E80 */
195 .long do_IRQ ! 101 txi1
196 .long do_IRQ ! 102 rxi2
197 .long do_IRQ ! 103 cci3
198#endif
199#if defined(CONFIG_CPU_SUBTYPE_SH7300)
200 .long do_IRQ ! 64
201 .long do_IRQ ! 65
202 .long do_IRQ ! 66
203 .long do_IRQ ! 67
204 .long do_IRQ ! 68
205 .long do_IRQ ! 69
206 .long do_IRQ ! 70
207 .long do_IRQ ! 71
208 .long do_IRQ ! 72
209 .long do_IRQ ! 73
210 .long do_IRQ ! 74
211 .long do_IRQ ! 75
212 .long do_IRQ ! 76
213 .long do_IRQ ! 77
214 .long do_IRQ ! 78
215 .long do_IRQ ! 79
216 .long do_IRQ ! 80 SCIF0(SH7300)
217 .long do_IRQ ! 81
218 .long do_IRQ ! 82
219 .long do_IRQ ! 83
220 .long do_IRQ ! 84
221 .long do_IRQ ! 85
222 .long do_IRQ ! 86
223 .long do_IRQ ! 87
224 .long do_IRQ ! 88
225 .long do_IRQ ! 89
226 .long do_IRQ ! 90
227 .long do_IRQ ! 91
228 .long do_IRQ ! 92
229 .long do_IRQ ! 93
230 .long do_IRQ ! 94
231 .long do_IRQ ! 95
232 .long do_IRQ ! 96
233 .long do_IRQ ! 97
234 .long do_IRQ ! 98
235 .long do_IRQ ! 99
236 .long do_IRQ ! 100
237 .long do_IRQ ! 101
238 .long do_IRQ ! 102
239 .long do_IRQ ! 103
240 .long do_IRQ ! 104
241 .long do_IRQ ! 105
242 .long do_IRQ ! 106
243 .long do_IRQ ! 107
244 .long do_IRQ ! 108
245#endif
246#endif
diff --git a/arch/sh/kernel/cpu/sh4/ex.S b/arch/sh/kernel/cpu/sh4/ex.S
index 7146893a6cca..3f4cd043e900 100644
--- a/arch/sh/kernel/cpu/sh4/ex.S
+++ b/arch/sh/kernel/cpu/sh4/ex.S
@@ -53,503 +53,3 @@ ENTRY(nmi_slot)
53#endif 53#endif
54ENTRY(user_break_point_trap) 54ENTRY(user_break_point_trap)
55 .long break_point_trap /* 1E0 */ 55 .long break_point_trap /* 1E0 */
56ENTRY(interrupt_table)
57 ! external hardware
58 .long do_IRQ ! 0000 /* 200 */
59 .long do_IRQ ! 0001
60 .long do_IRQ ! 0010
61 .long do_IRQ ! 0011
62 .long do_IRQ ! 0100
63 .long do_IRQ ! 0101
64 .long do_IRQ ! 0110
65 .long do_IRQ ! 0111
66 .long do_IRQ ! 1000 /* 300 */
67 .long do_IRQ ! 1001
68 .long do_IRQ ! 1010
69 .long do_IRQ ! 1011
70 .long do_IRQ ! 1100
71 .long do_IRQ ! 1101
72 .long do_IRQ ! 1110
73 .long exception_error
74 ! Internal hardware
75#ifndef CONFIG_CPU_SUBTYPE_SH7780
76 .long do_IRQ ! TMU0 tuni0 /* 400 */
77 .long do_IRQ ! TMU1 tuni1
78 .long do_IRQ ! TMU2 tuni2
79 .long do_IRQ ! ticpi2
80#if defined(CONFIG_CPU_SUBTYPE_SH7760)
81 .long exception_error
82 .long exception_error
83 .long exception_error
84 .long exception_error
85 .long exception_error /* 500 */
86 .long exception_error
87 .long exception_error
88#else
89 .long do_IRQ ! RTC ati
90 .long do_IRQ ! pri
91 .long do_IRQ ! cui
92 .long do_IRQ ! SCI eri
93 .long do_IRQ ! rxi /* 500 */
94 .long do_IRQ ! txi
95 .long do_IRQ ! tei
96#endif
97 .long do_IRQ ! WDT iti /* 560 */
98 .long do_IRQ ! REF rcmi
99 .long do_IRQ ! rovi
100 .long do_IRQ
101 .long do_IRQ /* 5E0 */
102 .long do_IRQ ! 32 Hitachi UDI /* 600 */
103 .long do_IRQ ! 33 GPIO
104 .long do_IRQ ! 34 DMAC dmte0
105 .long do_IRQ ! 35 dmte1
106 .long do_IRQ ! 36 dmte2
107 .long do_IRQ ! 37 dmte3
108 .long do_IRQ ! 38 dmae
109 .long exception_error ! 39 /* 6E0 */
110#if defined(CONFIG_CPU_SUBTYPE_SH7760)
111 .long exception_error /* 700 */
112 .long exception_error
113 .long exception_error
114 .long exception_error /* 760 */
115#else
116 .long do_IRQ ! 40 SCIF eri /* 700 */
117 .long do_IRQ ! 41 rxi
118 .long do_IRQ ! 42 bri
119 .long do_IRQ ! 43 txi
120#endif
121#if CONFIG_NR_ONCHIP_DMA_CHANNELS == 8
122 .long do_IRQ ! 44 DMAC dmte4 /* 780 */
123 .long do_IRQ ! 45 dmte5
124 .long do_IRQ ! 46 dmte6
125 .long do_IRQ ! 47 dmte7 /* 7E0 */
126#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
127 .long do_IRQ ! 44 IIC1 ali /* 780 */
128 .long do_IRQ ! 45 tacki
129 .long do_IRQ ! 46 waiti
130 .long do_IRQ ! 47 dtei /* 7E0 */
131 .long do_IRQ ! 48 DMAC dei0 /* 800 */
132 .long do_IRQ ! 49 dei1 /* 820 */
133#else
134 .long exception_error ! 44 /* 780 */
135 .long exception_error ! 45
136 .long exception_error ! 46
137 .long exception_error ! 47
138#endif
139#if defined(CONFIG_SH_FPU)
140 .long do_fpu_state_restore ! 48 /* 800 */
141 .long do_fpu_state_restore ! 49 /* 820 */
142#elif !defined(CONFIG_CPU_SUBTYPE_SH7343) && \
143 !defined(CONFIG_CPU_SUBTYPE_SH73180)
144 .long exception_error
145 .long exception_error
146#endif
147#if defined(CONFIG_CPU_SUBTYPE_SH7751)
148 .long exception_error /* 840 */
149 .long exception_error
150 .long exception_error
151 .long exception_error
152 .long exception_error
153 .long exception_error
154 .long exception_error /* 900 */
155 .long exception_error
156 .long exception_error
157 .long exception_error
158 .long exception_error
159 .long exception_error
160 .long exception_error
161 .long exception_error
162 .long do_IRQ ! PCI serr /* A00 */
163 .long do_IRQ ! dma3
164 .long do_IRQ ! dma2
165 .long do_IRQ ! dma1
166 .long do_IRQ ! dma0
167 .long do_IRQ ! pwon
168 .long do_IRQ ! pwdwn
169 .long do_IRQ ! err
170 .long do_IRQ ! TMU3 tuni3 /* B00 */
171 .long exception_error
172 .long exception_error
173 .long exception_error
174 .long do_IRQ ! TMU4 tuni4 /* B80 */
175#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
176 .long do_IRQ ! IRQ irq6 /* 840 */
177 .long do_IRQ ! irq7
178 .long do_IRQ ! SCIF eri0
179 .long do_IRQ ! rxi0
180 .long do_IRQ ! bri0
181 .long do_IRQ ! txi0
182 .long do_IRQ ! HCAN2 cani0 /* 900 */
183 .long do_IRQ ! cani1
184 .long do_IRQ ! SSI ssii0
185 .long do_IRQ ! ssii1
186 .long do_IRQ ! HAC haci0
187 .long do_IRQ ! haci1
188 .long do_IRQ ! IIC iici0
189 .long do_IRQ ! iici1
190 .long do_IRQ ! USB usbi /* A00 */
191 .long do_IRQ ! LCDC vint
192 .long exception_error
193 .long exception_error
194 .long do_IRQ ! DMABRG dmabrgi0
195 .long do_IRQ ! dmabrgi1
196 .long do_IRQ ! dmabrgi2
197 .long exception_error
198 .long do_IRQ ! SCIF eri1 /* B00 */
199 .long do_IRQ ! rxi1
200 .long do_IRQ ! bri1
201 .long do_IRQ ! txi1
202 .long do_IRQ ! eri2
203 .long do_IRQ ! rxi2
204 .long do_IRQ ! bri2
205 .long do_IRQ ! txi2
206 .long do_IRQ ! SIM simeri /* C00 */
207 .long do_IRQ ! simrxi
208 .long do_IRQ ! simtxi
209 .long do_IRQ ! simtei
210 .long do_IRQ ! HSPI spii
211 .long exception_error
212 .long exception_error
213 .long exception_error
214 .long do_IRQ ! MMCIF mmci0 /* D00 */
215 .long do_IRQ ! mmci1
216 .long do_IRQ ! mmci2
217 .long do_IRQ ! mmci3
218 .long exception_error
219 .long exception_error
220 .long exception_error
221 .long exception_error
222 .long exception_error /* E00 */
223 .long exception_error
224 .long exception_error
225 .long exception_error
226 .long do_IRQ ! MFI mfii
227 .long exception_error
228 .long exception_error
229 .long exception_error
230 .long exception_error /* F00 */
231 .long exception_error
232 .long exception_error
233 .long exception_error
234 .long do_IRQ ! ADC adi
235 .long do_IRQ ! CMT cmti /* FA0 */
236#elif defined(CONFIG_CPU_SUBTYPE_SH73180) || defined(CONFIG_CPU_SUBTYPE_SH7343)
237 .long do_IRQ ! 50 0x840
238 .long do_IRQ ! 51 0x860
239 .long do_IRQ ! 52 0x880
240 .long do_IRQ ! 53 0x8a0
241 .long do_IRQ ! 54 0x8c0
242 .long do_IRQ ! 55 0x8e0
243 .long do_IRQ ! 56 0x900
244 .long do_IRQ ! 57 0x920
245 .long do_IRQ ! 58 0x940
246 .long do_IRQ ! 59 0x960
247 .long do_IRQ ! 60 0x980
248 .long do_IRQ ! 61 0x9a0
249 .long do_IRQ ! 62 0x9c0
250 .long do_IRQ ! 63 0x9e0
251 .long do_IRQ ! 64 0xa00
252 .long do_IRQ ! 65 0xa20
253 .long do_IRQ ! 66 0xa40
254 .long do_IRQ ! 67 0xa60
255 .long do_IRQ ! 68 0xa80
256 .long do_IRQ ! 69 0xaa0
257 .long do_IRQ ! 70 0xac0
258 .long do_IRQ ! 71 0xae0
259 .long do_IRQ ! 72 0xb00
260 .long do_IRQ ! 73 0xb20
261 .long do_IRQ ! 74 0xb40
262 .long do_IRQ ! 75 0xb60
263 .long do_IRQ ! 76 0xb80
264 .long do_IRQ ! 77 0xba0
265 .long do_IRQ ! 78 0xbc0
266 .long do_IRQ ! 79 0xbe0
267 .long do_IRQ ! 80 0xc00
268 .long do_IRQ ! 81 0xc20
269 .long do_IRQ ! 82 0xc40
270 .long do_IRQ ! 83 0xc60
271 .long do_IRQ ! 84 0xc80
272 .long do_IRQ ! 85 0xca0
273 .long do_IRQ ! 86 0xcc0
274 .long do_IRQ ! 87 0xce0
275 .long do_IRQ ! 88 0xd00
276 .long do_IRQ ! 89 0xd20
277 .long do_IRQ ! 90 0xd40
278 .long do_IRQ ! 91 0xd60
279 .long do_IRQ ! 92 0xd80
280 .long do_IRQ ! 93 0xda0
281 .long do_IRQ ! 94 0xdc0
282 .long do_IRQ ! 95 0xde0
283 .long do_IRQ ! 96 0xe00
284 .long do_IRQ ! 97 0xe20
285 .long do_IRQ ! 98 0xe40
286 .long do_IRQ ! 99 0xe60
287 .long do_IRQ ! 100 0xe80
288 .long do_IRQ ! 101 0xea0
289 .long do_IRQ ! 102 0xec0
290 .long do_IRQ ! 103 0xee0
291 .long do_IRQ ! 104 0xf00
292 .long do_IRQ ! 105 0xf20
293 .long do_IRQ ! 106 0xf40
294 .long do_IRQ ! 107 0xf60
295 .long do_IRQ ! 108 0xf80
296#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
297 .long exception_error ! 50 0x840
298 .long exception_error ! 51 0x860
299 .long exception_error ! 52 0x880
300 .long exception_error ! 53 0x8a0
301 .long exception_error ! 54 0x8c0
302 .long exception_error ! 55 0x8e0
303 .long exception_error ! 56 0x900
304 .long exception_error ! 57 0x920
305 .long exception_error ! 58 0x940
306 .long exception_error ! 59 0x960
307 .long exception_error ! 60 0x980
308 .long exception_error ! 61 0x9a0
309 .long exception_error ! 62 0x9c0
310 .long exception_error ! 63 0x9e0
311 .long do_IRQ ! 64 0xa00 PCI serr
312 .long do_IRQ ! 65 0xa20 err
313 .long do_IRQ ! 66 0xa40 ad
314 .long do_IRQ ! 67 0xa60 pwr_dwn
315 .long exception_error ! 68 0xa80
316 .long exception_error ! 69 0xaa0
317 .long exception_error ! 70 0xac0
318 .long exception_error ! 71 0xae0
319 .long do_IRQ ! 72 0xb00 DMA INT0
320 .long do_IRQ ! 73 0xb20 INT1
321 .long do_IRQ ! 74 0xb40 INT2
322 .long do_IRQ ! 75 0xb60 INT3
323 .long do_IRQ ! 76 0xb80 INT4
324 .long exception_error ! 77 0xba0
325 .long do_IRQ ! 78 0xbc0 DMA ERR
326 .long exception_error ! 79 0xbe0
327 .long do_IRQ ! 80 0xc00 PIO0
328 .long do_IRQ ! 81 0xc20 PIO1
329 .long do_IRQ ! 82 0xc40 PIO2
330 .long exception_error ! 83 0xc60
331 .long exception_error ! 84 0xc80
332 .long exception_error ! 85 0xca0
333 .long exception_error ! 86 0xcc0
334 .long exception_error ! 87 0xce0
335 .long exception_error ! 88 0xd00
336 .long exception_error ! 89 0xd20
337 .long exception_error ! 90 0xd40
338 .long exception_error ! 91 0xd60
339 .long exception_error ! 92 0xd80
340 .long exception_error ! 93 0xda0
341 .long exception_error ! 94 0xdc0
342 .long exception_error ! 95 0xde0
343 .long exception_error ! 96 0xe00
344 .long exception_error ! 97 0xe20
345 .long exception_error ! 98 0xe40
346 .long exception_error ! 99 0xe60
347 .long exception_error ! 100 0xe80
348 .long exception_error ! 101 0xea0
349 .long exception_error ! 102 0xec0
350 .long exception_error ! 103 0xee0
351 .long exception_error ! 104 0xf00
352 .long exception_error ! 105 0xf20
353 .long exception_error ! 106 0xf40
354 .long exception_error ! 107 0xf60
355 .long exception_error ! 108 0xf80
356 .long exception_error ! 109 0xfa0
357 .long exception_error ! 110 0xfc0
358 .long exception_error ! 111 0xfe0
359 .long do_IRQ ! 112 0x1000 Mailbox
360 .long exception_error ! 113 0x1020
361 .long exception_error ! 114 0x1040
362 .long exception_error ! 115 0x1060
363 .long exception_error ! 116 0x1080
364 .long exception_error ! 117 0x10a0
365 .long exception_error ! 118 0x10c0
366 .long exception_error ! 119 0x10e0
367 .long exception_error ! 120 0x1100
368 .long exception_error ! 121 0x1120
369 .long exception_error ! 122 0x1140
370 .long exception_error ! 123 0x1160
371 .long exception_error ! 124 0x1180
372 .long exception_error ! 125 0x11a0
373 .long exception_error ! 126 0x11c0
374 .long exception_error ! 127 0x11e0
375 .long exception_error ! 128 0x1200
376 .long exception_error ! 129 0x1220
377 .long exception_error ! 130 0x1240
378 .long exception_error ! 131 0x1260
379 .long exception_error ! 132 0x1280
380 .long exception_error ! 133 0x12a0
381 .long exception_error ! 134 0x12c0
382 .long exception_error ! 135 0x12e0
383 .long exception_error ! 136 0x1300
384 .long exception_error ! 137 0x1320
385 .long exception_error ! 138 0x1340
386 .long exception_error ! 139 0x1360
387 .long do_IRQ ! 140 0x1380 EMPI INV_ADDR
388 .long exception_error ! 141 0x13a0
389 .long exception_error ! 142 0x13c0
390 .long exception_error ! 143 0x13e0
391#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
392 .long do_IRQ ! 50 0x840
393 .long do_IRQ ! 51 0x860
394 .long do_IRQ ! 52 0x880
395 .long do_IRQ ! 53 0x8a0
396 .long do_IRQ ! 54 0x8c0
397 .long do_IRQ ! 55 0x8e0
398 .long do_IRQ ! 56 0x900
399 .long do_IRQ ! 57 0x920
400 .long do_IRQ ! 58 0x940
401 .long do_IRQ ! 59 0x960
402 .long do_IRQ ! 60 0x980
403 .long do_IRQ ! 61 0x9a0
404 .long do_IRQ ! 62 0x9c0
405 .long do_IRQ ! 63 0x9e0
406 .long do_IRQ ! 64 0xa00
407 .long do_IRQ ! 65 0xa20
408 .long do_IRQ ! 66 0xa4d
409 .long do_IRQ ! 67 0xa60
410 .long do_IRQ ! 68 0xa80
411 .long do_IRQ ! 69 0xaa0
412 .long do_IRQ ! 70 0xac0
413 .long do_IRQ ! 71 0xae0
414 .long do_IRQ ! 72 0xb00
415 .long do_IRQ ! 73 0xb20
416 .long do_IRQ ! 74 0xb40
417 .long do_IRQ ! 75 0xb60
418 .long do_IRQ ! 76 0xb80
419 .long do_IRQ ! 77 0xba0
420 .long do_IRQ ! 78 0xbc0
421 .long do_IRQ ! 79 0xbe0
422 .long do_IRQ ! 80 0xc00
423 .long do_IRQ ! 81 0xc20
424 .long do_IRQ ! 82 0xc40
425 .long do_IRQ ! 83 0xc60
426 .long do_IRQ ! 84 0xc80
427 .long do_IRQ ! 85 0xca0
428 .long do_IRQ ! 86 0xcc0
429 .long do_IRQ ! 87 0xce0
430 .long do_IRQ ! 88 0xd00
431 .long do_IRQ ! 89 0xd20
432 .long do_IRQ ! 90 0xd40
433 .long do_IRQ ! 91 0xd60
434 .long do_IRQ ! 92 0xd80
435 .long do_IRQ ! 93 0xda0
436 .long do_IRQ ! 94 0xdc0
437 .long do_IRQ ! 95 0xde0
438 .long do_IRQ ! 96 0xe00
439 .long do_IRQ ! 97 0xe20
440 .long do_IRQ ! 98 0xe40
441 .long do_IRQ ! 99 0xe60
442 .long do_IRQ ! 100 0xe80
443 .long do_IRQ ! 101 0xea0
444 .long do_IRQ ! 102 0xec0
445 .long do_IRQ ! 103 0xee0
446 .long do_IRQ ! 104 0xf00
447 .long do_IRQ ! 105 0xf20
448 .long do_IRQ ! 106 0xf40
449 .long do_IRQ ! 107 0xf60
450 .long do_IRQ ! 108 0xf80
451#endif
452#else
453 .long exception_error /* 400 */
454 .long exception_error
455 .long exception_error
456 .long exception_error
457 .long do_IRQ ! RTC ati
458 .long do_IRQ ! pri
459 .long do_IRQ ! cui
460 .long exception_error
461 .long exception_error /* 500 */
462 .long exception_error
463 .long exception_error
464 .long do_IRQ ! WDT iti /* 560 */
465 .long do_IRQ ! TMU-ch0
466 .long do_IRQ ! TMU-ch1
467 .long do_IRQ ! TMU-ch2
468 .long do_IRQ ! ticpi2 /* 5E0 */
469 .long do_IRQ ! 32 Hitachi UDI /* 600 */
470 .long exception_error
471 .long do_IRQ ! 34 DMAC dmte0
472 .long do_IRQ ! 35 dmte1
473 .long do_IRQ ! 36 dmte2
474 .long do_IRQ ! 37 dmte3
475 .long do_IRQ ! 38 dmae
476 .long exception_error ! 39 /* 6E0 */
477 .long do_IRQ ! 40 SCIF-ch0 eri /* 700 */
478 .long do_IRQ ! 41 rxi
479 .long do_IRQ ! 42 bri
480 .long do_IRQ ! 43 txi
481 .long do_IRQ ! 44 DMAC dmte4 /* 780 */
482 .long do_IRQ ! 45 dmte5
483 .long do_IRQ ! 46 dmte6
484 .long do_IRQ ! 47 dmte7 /* 7E0 */
485#if defined(CONFIG_SH_FPU)
486 .long do_fpu_state_restore ! 48 /* 800 */
487 .long do_fpu_state_restore ! 49 /* 820 */
488#else
489 .long exception_error
490 .long exception_error
491#endif
492 .long exception_error /* 840 */
493 .long exception_error
494 .long exception_error
495 .long exception_error
496 .long exception_error
497 .long exception_error
498 .long do_IRQ ! 56 CMT /* 900 */
499 .long exception_error
500 .long exception_error
501 .long exception_error
502 .long do_IRQ ! 60 HAC
503 .long exception_error
504 .long exception_error
505 .long exception_error
506 .long do_IRQ ! PCI serr /* A00 */
507 .long do_IRQ ! INTA
508 .long do_IRQ ! INTB
509 .long do_IRQ ! INTC
510 .long do_IRQ ! INTD
511 .long do_IRQ ! err
512 .long do_IRQ ! pwd3
513 .long do_IRQ ! pwd2
514 .long do_IRQ ! pwd1 /* B00 */
515 .long do_IRQ ! pwd0
516 .long exception_error
517 .long exception_error
518 .long do_IRQ ! SCIF-ch1 eri /* B80 */
519 .long do_IRQ ! rxi
520 .long do_IRQ ! bri
521 .long do_IRQ ! txi
522 .long do_IRQ ! SIOF /* C00 */
523 .long exception_error
524 .long exception_error
525 .long exception_error
526 .long do_IRQ ! HSPI /* C80 */
527 .long exception_error
528 .long exception_error
529 .long exception_error
530 .long do_IRQ ! MMCIF fatat /* D00 */
531 .long do_IRQ ! tran
532 .long do_IRQ ! err
533 .long do_IRQ ! frdy
534 .long do_IRQ ! DMAC dmint8 /* D80 */
535 .long do_IRQ ! dmint9
536 .long do_IRQ ! dmint10
537 .long do_IRQ ! dmint11
538 .long do_IRQ ! TMU-ch3 /* E00 */
539 .long do_IRQ ! TMU-ch4
540 .long do_IRQ ! TMU-ch5
541 .long exception_error
542 .long do_IRQ ! SSI
543 .long exception_error
544 .long exception_error
545 .long exception_error
546 .long do_IRQ ! FLCTL flste /* F00 */
547 .long do_IRQ ! fltend
548 .long do_IRQ ! fltrq0
549 .long do_IRQ ! fltrq1
550 .long do_IRQ ! GPIO gpioi0 /* F80 */
551 .long do_IRQ ! gpioi1
552 .long do_IRQ ! gpioi2
553 .long do_IRQ ! gpioi3
554#endif
555
diff --git a/arch/sh/kernel/entry.S b/arch/sh/kernel/entry.S
index 97c571fbcdf1..39aaefb2d83f 100644
--- a/arch/sh/kernel/entry.S
+++ b/arch/sh/kernel/entry.S
@@ -1,9 +1,8 @@
1/* $Id: entry.S,v 1.37 2004/06/11 13:02:46 doyu Exp $ 1/*
2 *
3 * linux/arch/sh/entry.S 2 * linux/arch/sh/entry.S
4 * 3 *
5 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka 4 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
6 * Copyright (C) 2003 Paul Mundt 5 * Copyright (C) 2003 - 2006 Paul Mundt
7 * 6 *
8 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
@@ -78,7 +77,6 @@ OFF_TRA = (16*4+6*4)
78#define k3 r3 77#define k3 r3
79#define k4 r4 78#define k4 r4
80 79
81#define k_ex_code r2_bank /* r2_bank1 */
82#define g_imask r6 /* r6_bank1 */ 80#define g_imask r6 /* r6_bank1 */
83#define k_g_imask r6_bank /* r6_bank1 */ 81#define k_g_imask r6_bank /* r6_bank1 */
84#define current r7 /* r7_bank1 */ 82#define current r7 /* r7_bank1 */
@@ -691,7 +689,7 @@ interrupt:
6910: 6890:
692#endif /* defined(CONFIG_KGDB_NMI) */ 690#endif /* defined(CONFIG_KGDB_NMI) */
693 bra handle_exception 691 bra handle_exception
694 mov.l @k2, k2 692 mov #-1, k2 ! interrupt exception marker
695 693
696 .align 2 694 .align 2
6971: .long EXPEVT 6951: .long EXPEVT
@@ -717,8 +715,7 @@ ENTRY(handle_exception)
717 add current, k1 715 add current, k1
718 mov k1, r15 ! change to kernel stack 716 mov k1, r15 ! change to kernel stack
719 ! 717 !
7201: mov #-1, k4 7181: mov.l 2f, k1
721 mov.l 2f, k1
722 ! 719 !
723#ifdef CONFIG_SH_DSP 720#ifdef CONFIG_SH_DSP
724 mov.l r2, @-r15 ! Save r2, we need another reg 721 mov.l r2, @-r15 ! Save r2, we need another reg
@@ -763,6 +760,8 @@ skip_save:
763#endif 760#endif
764 ! Save the user registers on the stack. 761 ! Save the user registers on the stack.
765 mov.l k2, @-r15 ! EXPEVT 762 mov.l k2, @-r15 ! EXPEVT
763
764 mov #-1, k4
766 mov.l k4, @-r15 ! set TRA (default: -1) 765 mov.l k4, @-r15 ! set TRA (default: -1)
767 ! 766 !
768 sts.l macl, @-r15 767 sts.l macl, @-r15
@@ -797,8 +796,21 @@ skip_save:
797 mov.l r2, @-r15 796 mov.l r2, @-r15
798 mov.l r1, @-r15 797 mov.l r1, @-r15
799 mov.l r0, @-r15 798 mov.l r0, @-r15
800 ! Then, dispatch to the handler, according to the exception code. 799
801 stc k_ex_code, r8 800 /*
801 * This gets a bit tricky.. in the INTEVT case we don't want to use
802 * the VBR offset as a destination in the jump call table, since all
803 * of the destinations are the same. In this case, (interrupt) sets
804 * a marker in r2 (now r2_bank since SR.RB changed), which we check
805 * to determine the exception type. For all other exceptions, we
806 * forcibly read EXPEVT from memory and fix up the jump address, in
807 * the interrupt exception case we jump to do_IRQ() and defer the
808 * INTEVT read until there. As a bonus, we can also clean up the SR.RB
809 * checks that do_IRQ() was doing..
810 */
811 stc r2_bank, r8
812 cmp/pz r8
813 bf interrupt_exception
802 shlr2 r8 814 shlr2 r8
803 shlr r8 815 shlr r8
804 mov.l 4f, r9 816 mov.l 4f, r9
@@ -806,6 +818,8 @@ skip_save:
806 mov.l @r9, r9 818 mov.l @r9, r9
807 jmp @r9 819 jmp @r9
808 nop 820 nop
821 rts
822 nop
809 823
810 .align 2 824 .align 2
8111: .long 0x00001000 ! DSP=1 8251: .long 0x00001000 ! DSP=1
@@ -813,8 +827,17 @@ skip_save:
8133: .long 0xcfffffff ! RB=0, BL=0 8273: .long 0xcfffffff ! RB=0, BL=0
8144: .long exception_handling_table 8284: .long exception_handling_table
815 829
830interrupt_exception:
831 mov.l 1f, r9
832 jmp @r9
833 nop
834 rts
835 nop
836
837 .align 2
8381: .long do_IRQ
839
816 .align 2 840 .align 2
817ENTRY(exception_none) 841ENTRY(exception_none)
818 rts 842 rts
819 nop 843 nop
820
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index c7ebd6aec951..acf2602569c4 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -11,12 +11,15 @@
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/kernel_stat.h> 12#include <linux/kernel_stat.h>
13#include <linux/seq_file.h> 13#include <linux/seq_file.h>
14#include <linux/io.h>
14#include <asm/irq.h> 15#include <asm/irq.h>
15#include <asm/processor.h> 16#include <asm/processor.h>
16#include <asm/uaccess.h> 17#include <asm/uaccess.h>
17#include <asm/thread_info.h> 18#include <asm/thread_info.h>
18#include <asm/cpu/mmu_context.h> 19#include <asm/cpu/mmu_context.h>
19 20
21atomic_t irq_err_count;
22
20/* 23/*
21 * 'what should we do if we get a hw irq event on an illegal vector'. 24 * 'what should we do if we get a hw irq event on an illegal vector'.
22 * each architecture has to answer this themselves, it doesn't deserve 25 * each architecture has to answer this themselves, it doesn't deserve
@@ -24,6 +27,7 @@
24 */ 27 */
25void ack_bad_irq(unsigned int irq) 28void ack_bad_irq(unsigned int irq)
26{ 29{
30 atomic_inc(&irq_err_count);
27 printk("unexpected IRQ trap at vector %02x\n", irq); 31 printk("unexpected IRQ trap at vector %02x\n", irq);
28} 32}
29 33
@@ -47,8 +51,10 @@ int show_interrupts(struct seq_file *p, void *v)
47 if (!action) 51 if (!action)
48 goto unlock; 52 goto unlock;
49 seq_printf(p, "%3d: ",i); 53 seq_printf(p, "%3d: ",i);
50 seq_printf(p, "%10u ", kstat_irqs(i)); 54 for_each_online_cpu(j)
51 seq_printf(p, " %14s", irq_desc[i].chip->typename); 55 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
56 seq_printf(p, " %14s", irq_desc[i].chip->name);
57 seq_printf(p, "-%s", handle_irq_name(irq_desc[i].handle_irq));
52 seq_printf(p, " %s", action->name); 58 seq_printf(p, " %s", action->name);
53 59
54 for (action=action->next; action; action = action->next) 60 for (action=action->next; action; action = action->next)
@@ -56,7 +62,9 @@ int show_interrupts(struct seq_file *p, void *v)
56 seq_putc(p, '\n'); 62 seq_putc(p, '\n');
57unlock: 63unlock:
58 spin_unlock_irqrestore(&irq_desc[i].lock, flags); 64 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
59 } 65 } else if (i == NR_IRQS)
66 seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count));
67
60 return 0; 68 return 0;
61} 69}
62#endif 70#endif
@@ -78,7 +86,8 @@ asmlinkage int do_IRQ(unsigned long r4, unsigned long r5,
78 unsigned long r6, unsigned long r7, 86 unsigned long r6, unsigned long r7,
79 struct pt_regs regs) 87 struct pt_regs regs)
80{ 88{
81 int irq = r4; 89 struct pt_regs *old_regs = set_irq_regs(&regs);
90 int irq;
82#ifdef CONFIG_4KSTACKS 91#ifdef CONFIG_4KSTACKS
83 union irq_ctx *curctx, *irqctx; 92 union irq_ctx *curctx, *irqctx;
84#endif 93#endif
@@ -102,20 +111,9 @@ asmlinkage int do_IRQ(unsigned long r4, unsigned long r5,
102#endif 111#endif
103 112
104#ifdef CONFIG_CPU_HAS_INTEVT 113#ifdef CONFIG_CPU_HAS_INTEVT
105 __asm__ __volatile__ ( 114 irq = (ctrl_inl(INTEVT) >> 5) - 16;
106#ifdef CONFIG_CPU_HAS_SR_RB
107 "stc r2_bank, %0\n\t"
108#else 115#else
109 "mov.l @%1, %0\n\t" 116 irq = r4;
110#endif
111 "shlr2 %0\n\t"
112 "shlr2 %0\n\t"
113 "shlr %0\n\t"
114 "add #-16, %0\n\t"
115 : "=z" (irq), "=r" (r4)
116 : "1" (INTEVT)
117 : "memory"
118 );
119#endif 117#endif
120 118
121 irq = irq_demux(irq); 119 irq = irq_demux(irq);
@@ -139,25 +137,25 @@ asmlinkage int do_IRQ(unsigned long r4, unsigned long r5,
139 137
140 __asm__ __volatile__ ( 138 __asm__ __volatile__ (
141 "mov %0, r4 \n" 139 "mov %0, r4 \n"
142 "mov %1, r5 \n"
143 "mov r15, r9 \n" 140 "mov r15, r9 \n"
144 "jsr @%2 \n" 141 "jsr @%1 \n"
145 /* swith to the irq stack */ 142 /* swith to the irq stack */
146 " mov %3, r15 \n" 143 " mov %2, r15 \n"
147 /* restore the stack (ring zero) */ 144 /* restore the stack (ring zero) */
148 "mov r9, r15 \n" 145 "mov r9, r15 \n"
149 : /* no outputs */ 146 : /* no outputs */
150 : "r" (irq), "r" (&regs), "r" (__do_IRQ), "r" (isp) 147 : "r" (irq), "r" (generic_handle_irq), "r" (isp)
151 /* XXX: A somewhat excessive clobber list? -PFM */ 148 /* XXX: A somewhat excessive clobber list? -PFM */
152 : "memory", "r0", "r1", "r2", "r3", "r4", 149 : "memory", "r0", "r1", "r2", "r3", "r4",
153 "r5", "r6", "r7", "r8", "t", "pr" 150 "r5", "r6", "r7", "r8", "t", "pr"
154 ); 151 );
155 } else 152 } else
156#endif 153#endif
157 __do_IRQ(irq, &regs); 154 generic_handle_irq(irq);
158 155
159 irq_exit(); 156 irq_exit();
160 157
158 set_irq_regs(old_regs);
161 return 1; 159 return 1;
162} 160}
163 161
diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c
index 0b1d5dd7a93b..91516dca4a85 100644
--- a/arch/sh/kernel/process.c
+++ b/arch/sh/kernel/process.c
@@ -5,6 +5,7 @@
5 * Copyright (C) 1995 Linus Torvalds 5 * Copyright (C) 1995 Linus Torvalds
6 * 6 *
7 * SuperH version: Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima 7 * SuperH version: Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
8 * Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
8 */ 9 */
9 10
10/* 11/*
@@ -290,6 +291,24 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
290static void 291static void
291ubc_set_tracing(int asid, unsigned long pc) 292ubc_set_tracing(int asid, unsigned long pc)
292{ 293{
294#if defined(CONFIG_CPU_SH4A)
295 unsigned long val;
296
297 val = (UBC_CBR_ID_INST | UBC_CBR_RW_READ | UBC_CBR_CE);
298 val |= (UBC_CBR_AIE | UBC_CBR_AIV_SET(asid));
299
300 ctrl_outl(val, UBC_CBR0);
301 ctrl_outl(pc, UBC_CAR0);
302 ctrl_outl(0x0, UBC_CAMR0);
303 ctrl_outl(0x0, UBC_CBCR);
304
305 val = (UBC_CRR_RES | UBC_CRR_PCB | UBC_CRR_BIE);
306 ctrl_outl(val, UBC_CRR0);
307
308 /* Read UBC register that we writed last. For chekking UBC Register changed */
309 val = ctrl_inl(UBC_CRR0);
310
311#else /* CONFIG_CPU_SH4A */
293 ctrl_outl(pc, UBC_BARA); 312 ctrl_outl(pc, UBC_BARA);
294 313
295#ifdef CONFIG_MMU 314#ifdef CONFIG_MMU
@@ -307,6 +326,7 @@ ubc_set_tracing(int asid, unsigned long pc)
307 ctrl_outw(BBR_INST | BBR_READ, UBC_BBRA); 326 ctrl_outw(BBR_INST | BBR_READ, UBC_BBRA);
308 ctrl_outw(BRCR_PCBA, UBC_BRCR); 327 ctrl_outw(BRCR_PCBA, UBC_BRCR);
309 } 328 }
329#endif /* CONFIG_CPU_SH4A */
310} 330}
311 331
312/* 332/*
@@ -359,8 +379,13 @@ struct task_struct *__switch_to(struct task_struct *prev, struct task_struct *ne
359#endif 379#endif
360 ubc_set_tracing(asid, next->thread.ubc_pc); 380 ubc_set_tracing(asid, next->thread.ubc_pc);
361 } else { 381 } else {
382#if defined(CONFIG_CPU_SH4A)
383 ctrl_outl(UBC_CBR_INIT, UBC_CBR0);
384 ctrl_outl(UBC_CRR_INIT, UBC_CRR0);
385#else
362 ctrl_outw(0, UBC_BBRA); 386 ctrl_outw(0, UBC_BBRA);
363 ctrl_outw(0, UBC_BBRB); 387 ctrl_outw(0, UBC_BBRB);
388#endif
364 } 389 }
365 390
366 return prev; 391 return prev;
@@ -460,8 +485,13 @@ asmlinkage void break_point_trap(unsigned long r4, unsigned long r5,
460 struct pt_regs regs) 485 struct pt_regs regs)
461{ 486{
462 /* Clear tracing. */ 487 /* Clear tracing. */
488#if defined(CONFIG_CPU_SH4A)
489 ctrl_outl(UBC_CBR_INIT, UBC_CBR0);
490 ctrl_outl(UBC_CRR_INIT, UBC_CRR0);
491#else
463 ctrl_outw(0, UBC_BBRA); 492 ctrl_outw(0, UBC_BBRA);
464 ctrl_outw(0, UBC_BBRB); 493 ctrl_outw(0, UBC_BBRB);
494#endif
465 current->thread.ubc_pc = 0; 495 current->thread.ubc_pc = 0;
466 ubc_usercnt -= 1; 496 ubc_usercnt -= 1;
467 497
diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c
index 450c68f1df05..57e708d7b52d 100644
--- a/arch/sh/kernel/time.c
+++ b/arch/sh/kernel/time.c
@@ -47,6 +47,7 @@ unsigned long long __attribute__ ((weak)) sched_clock(void)
47 return (unsigned long long)jiffies * (1000000000 / HZ); 47 return (unsigned long long)jiffies * (1000000000 / HZ);
48} 48}
49 49
50#ifndef CONFIG_GENERIC_TIME
50void do_gettimeofday(struct timeval *tv) 51void do_gettimeofday(struct timeval *tv)
51{ 52{
52 unsigned long seq; 53 unsigned long seq;
@@ -99,6 +100,7 @@ int do_settimeofday(struct timespec *tv)
99 return 0; 100 return 0;
100} 101}
101EXPORT_SYMBOL(do_settimeofday); 102EXPORT_SYMBOL(do_settimeofday);
103#endif /* !CONFIG_GENERIC_TIME */
102 104
103/* last time the RTC clock got updated */ 105/* last time the RTC clock got updated */
104static long last_rtc_update; 106static long last_rtc_update;
@@ -107,13 +109,14 @@ static long last_rtc_update;
107 * handle_timer_tick() needs to keep up the real-time clock, 109 * handle_timer_tick() needs to keep up the real-time clock,
108 * as well as call the "do_timer()" routine every clocktick 110 * as well as call the "do_timer()" routine every clocktick
109 */ 111 */
110void handle_timer_tick(struct pt_regs *regs) 112void handle_timer_tick(void)
111{ 113{
112 do_timer(1); 114 do_timer(1);
113#ifndef CONFIG_SMP 115#ifndef CONFIG_SMP
114 update_process_times(user_mode(regs)); 116 update_process_times(user_mode(get_irq_regs()));
115#endif 117#endif
116 profile_tick(CPU_PROFILING, regs); 118 if (current->pid)
119 profile_tick(CPU_PROFILING);
117 120
118#ifdef CONFIG_HEARTBEAT 121#ifdef CONFIG_HEARTBEAT
119 if (sh_mv.mv_heartbeat != NULL) 122 if (sh_mv.mv_heartbeat != NULL)
diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c
index 205816fcf0da..24927015dc31 100644
--- a/arch/sh/kernel/timers/timer-tmu.c
+++ b/arch/sh/kernel/timers/timer-tmu.c
@@ -80,8 +80,7 @@ static unsigned long tmu_timer_get_offset(void)
80 return count; 80 return count;
81} 81}
82 82
83static irqreturn_t tmu_timer_interrupt(int irq, void *dev_id, 83static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
84 struct pt_regs *regs)
85{ 84{
86 unsigned long timer_status; 85 unsigned long timer_status;
87 86
@@ -98,7 +97,7 @@ static irqreturn_t tmu_timer_interrupt(int irq, void *dev_id,
98 * locally disabled. -arca 97 * locally disabled. -arca
99 */ 98 */
100 write_seqlock(&xtime_lock); 99 write_seqlock(&xtime_lock);
101 handle_timer_tick(regs); 100 handle_timer_tick();
102 write_sequnlock(&xtime_lock); 101 write_sequnlock(&xtime_lock);
103 102
104 return IRQ_HANDLED; 103 return IRQ_HANDLED;
@@ -111,60 +110,6 @@ static struct irqaction tmu_irq = {
111 .mask = CPU_MASK_NONE, 110 .mask = CPU_MASK_NONE,
112}; 111};
113 112
114/*
115 * Hah! We'll see if this works (switching from usecs to nsecs).
116 */
117static unsigned long tmu_timer_get_frequency(void)
118{
119 u32 freq;
120 struct timespec ts1, ts2;
121 unsigned long diff_nsec;
122 unsigned long factor;
123
124 /* Setup the timer: We don't want to generate interrupts, just
125 * have it count down at its natural rate.
126 */
127 ctrl_outb(0, TMU_TSTR);
128#if !defined(CONFIG_CPU_SUBTYPE_SH7300) && !defined(CONFIG_CPU_SUBTYPE_SH7760)
129 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
130#endif
131 ctrl_outw(TMU0_TCR_CALIB, TMU0_TCR);
132 ctrl_outl(0xffffffff, TMU0_TCOR);
133 ctrl_outl(0xffffffff, TMU0_TCNT);
134
135 rtc_sh_get_time(&ts2);
136
137 do {
138 rtc_sh_get_time(&ts1);
139 } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
140
141 /* actually start the timer */
142 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
143
144 do {
145 rtc_sh_get_time(&ts2);
146 } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
147
148 freq = 0xffffffff - ctrl_inl(TMU0_TCNT);
149 if (ts2.tv_nsec < ts1.tv_nsec) {
150 ts2.tv_nsec += 1000000000;
151 ts2.tv_sec--;
152 }
153
154 diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec);
155
156 /* this should work well if the RTC has a precision of n Hz, where
157 * n is an integer. I don't think we have to worry about the other
158 * cases. */
159 factor = (1000000000 + diff_nsec/2) / diff_nsec;
160
161 if (factor * diff_nsec > 1100000000 ||
162 factor * diff_nsec < 900000000)
163 panic("weird RTC (diff_nsec %ld)", diff_nsec);
164
165 return freq * factor;
166}
167
168static void tmu_clk_init(struct clk *clk) 113static void tmu_clk_init(struct clk *clk)
169{ 114{
170 u8 divisor = TMU0_TCR_INIT & 0x7; 115 u8 divisor = TMU0_TCR_INIT & 0x7;
@@ -232,12 +177,12 @@ struct sys_timer_ops tmu_timer_ops = {
232 .init = tmu_timer_init, 177 .init = tmu_timer_init,
233 .start = tmu_timer_start, 178 .start = tmu_timer_start,
234 .stop = tmu_timer_stop, 179 .stop = tmu_timer_stop,
235 .get_frequency = tmu_timer_get_frequency, 180#ifndef CONFIG_GENERIC_TIME
236 .get_offset = tmu_timer_get_offset, 181 .get_offset = tmu_timer_get_offset,
182#endif
237}; 183};
238 184
239struct sys_timer tmu_timer = { 185struct sys_timer tmu_timer = {
240 .name = "tmu", 186 .name = "tmu",
241 .ops = &tmu_timer_ops, 187 .ops = &tmu_timer_ops,
242}; 188};
243
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