diff options
author | Magnus Damm <damm@opensource.se> | 2010-05-11 05:35:27 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2010-05-13 04:36:13 -0400 |
commit | 00522ac3b11f52cce6358516dd8695a588082a73 (patch) | |
tree | 2cf94d2421abcefc43abf687b428eb223ec62034 /arch/sh/kernel | |
parent | b3f9f630d35f7eeec49221690991e834d7b27e05 (diff) |
sh: switch sh7723 to clkdev
This patch converts the remaining sh7723 clocks
to use clkdev for lookup. The now unused name
and id from struct clk are also removed.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel')
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7723.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c index 7685504369cc..d3938f0d3702 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c | |||
@@ -38,8 +38,6 @@ | |||
38 | 38 | ||
39 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ | 39 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ |
40 | static struct clk r_clk = { | 40 | static struct clk r_clk = { |
41 | .name = "rclk", | ||
42 | .id = -1, | ||
43 | .rate = 32768, | 41 | .rate = 32768, |
44 | }; | 42 | }; |
45 | 43 | ||
@@ -48,8 +46,6 @@ static struct clk r_clk = { | |||
48 | * from the platform code. | 46 | * from the platform code. |
49 | */ | 47 | */ |
50 | struct clk extal_clk = { | 48 | struct clk extal_clk = { |
51 | .name = "extal", | ||
52 | .id = -1, | ||
53 | .rate = 33333333, | 49 | .rate = 33333333, |
54 | }; | 50 | }; |
55 | 51 | ||
@@ -71,8 +67,6 @@ static struct clk_ops dll_clk_ops = { | |||
71 | }; | 67 | }; |
72 | 68 | ||
73 | static struct clk dll_clk = { | 69 | static struct clk dll_clk = { |
74 | .name = "dll_clk", | ||
75 | .id = -1, | ||
76 | .ops = &dll_clk_ops, | 70 | .ops = &dll_clk_ops, |
77 | .parent = &r_clk, | 71 | .parent = &r_clk, |
78 | .flags = CLK_ENABLE_ON_INIT, | 72 | .flags = CLK_ENABLE_ON_INIT, |
@@ -96,8 +90,6 @@ static struct clk_ops pll_clk_ops = { | |||
96 | }; | 90 | }; |
97 | 91 | ||
98 | static struct clk pll_clk = { | 92 | static struct clk pll_clk = { |
99 | .name = "pll_clk", | ||
100 | .id = -1, | ||
101 | .ops = &pll_clk_ops, | 93 | .ops = &pll_clk_ops, |
102 | .flags = CLK_ENABLE_ON_INIT, | 94 | .flags = CLK_ENABLE_ON_INIT, |
103 | }; | 95 | }; |
@@ -211,6 +203,12 @@ static struct clk mstp_clks[] = { | |||
211 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | 203 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
212 | 204 | ||
213 | static struct clk_lookup lookups[] = { | 205 | static struct clk_lookup lookups[] = { |
206 | /* main clocks */ | ||
207 | CLKDEV_CON_ID("rclk", &r_clk), | ||
208 | CLKDEV_CON_ID("extal", &extal_clk), | ||
209 | CLKDEV_CON_ID("dll_clk", &dll_clk), | ||
210 | CLKDEV_CON_ID("pll_clk", &pll_clk), | ||
211 | |||
214 | /* DIV4 clocks */ | 212 | /* DIV4 clocks */ |
215 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | 213 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), |
216 | CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), | 214 | CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), |