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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2013-12-06 04:59:48 -0500
committerSimon Horman <horms+renesas@verge.net.au>2013-12-24 07:49:43 -0500
commitd850acf975bee46e43c3cd80d2d287010195c63b (patch)
tree0d61e0af191f2b3d818d93de29353c97deb34c43 /arch/sh/kernel/cpu
parentec09c5eb491834d4011c72538e58d8b7096076bd (diff)
sh: Declare SCIF register base and IRQ as resources
Passing the register base address and IRQ through platform data is deprecated. Use resources instead. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/sh/kernel/cpu')
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c27
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c9
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c72
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c36
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c36
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7264.c96
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7269.c96
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c18
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c27
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c18
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c18
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh4-202.c15
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c18
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c58
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c36
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c9
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c27
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c54
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c54
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7734.c66
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c27
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c27
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c90
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c18
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c54
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c82
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c45
-rw-r--r--arch/sh/kernel/cpu/sh5/setup-sh5.c11
28 files changed, 883 insertions, 261 deletions
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 4df4d4ffe39b..1a4fe7c0e548 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -61,51 +61,66 @@ static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
61 NULL, prio_registers, NULL); 61 NULL, prio_registers, NULL);
62 62
63static struct plat_sci_port scif0_platform_data = { 63static struct plat_sci_port scif0_platform_data = {
64 .mapbase = 0xf8400000,
65 .flags = UPF_BOOT_AUTOCONF, 64 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 65 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2, 66 .scbrr_algo_id = SCBRR_ALGO_2,
68 .type = PORT_SCIF, 67 .type = PORT_SCIF,
69 .irqs = SCIx_IRQ_MUXED(88), 68};
69
70static struct resource scif0_resources[] = {
71 DEFINE_RES_MEM(0xf8400000, 0x100),
72 DEFINE_RES_IRQ(88),
70}; 73};
71 74
72static struct platform_device scif0_device = { 75static struct platform_device scif0_device = {
73 .name = "sh-sci", 76 .name = "sh-sci",
74 .id = 0, 77 .id = 0,
78 .resource = scif0_resources,
79 .num_resources = ARRAY_SIZE(scif0_resources),
75 .dev = { 80 .dev = {
76 .platform_data = &scif0_platform_data, 81 .platform_data = &scif0_platform_data,
77 }, 82 },
78}; 83};
79 84
80static struct plat_sci_port scif1_platform_data = { 85static struct plat_sci_port scif1_platform_data = {
81 .mapbase = 0xf8410000,
82 .flags = UPF_BOOT_AUTOCONF, 86 .flags = UPF_BOOT_AUTOCONF,
83 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 87 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
84 .scbrr_algo_id = SCBRR_ALGO_2, 88 .scbrr_algo_id = SCBRR_ALGO_2,
85 .type = PORT_SCIF, 89 .type = PORT_SCIF,
86 .irqs = SCIx_IRQ_MUXED(92), 90};
91
92static struct resource scif1_resources[] = {
93 DEFINE_RES_MEM(0xf8410000, 0x100),
94 DEFINE_RES_IRQ(92),
87}; 95};
88 96
89static struct platform_device scif1_device = { 97static struct platform_device scif1_device = {
90 .name = "sh-sci", 98 .name = "sh-sci",
91 .id = 1, 99 .id = 1,
100 .resource = scif1_resources,
101 .num_resources = ARRAY_SIZE(scif1_resources),
92 .dev = { 102 .dev = {
93 .platform_data = &scif1_platform_data, 103 .platform_data = &scif1_platform_data,
94 }, 104 },
95}; 105};
96 106
97static struct plat_sci_port scif2_platform_data = { 107static struct plat_sci_port scif2_platform_data = {
98 .mapbase = 0xf8420000,
99 .flags = UPF_BOOT_AUTOCONF, 108 .flags = UPF_BOOT_AUTOCONF,
100 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 109 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
101 .scbrr_algo_id = SCBRR_ALGO_2, 110 .scbrr_algo_id = SCBRR_ALGO_2,
102 .type = PORT_SCIF, 111 .type = PORT_SCIF,
103 .irqs = SCIx_IRQ_MUXED(96), 112};
113
114static struct resource scif2_resources[] = {
115 DEFINE_RES_MEM(0xf8420000, 0x100),
116 DEFINE_RES_IRQ(96),
104}; 117};
105 118
106static struct platform_device scif2_device = { 119static struct platform_device scif2_device = {
107 .name = "sh-sci", 120 .name = "sh-sci",
108 .id = 2, 121 .id = 2,
122 .resource = scif2_resources,
123 .num_resources = ARRAY_SIZE(scif2_resources),
109 .dev = { 124 .dev = {
110 .platform_data = &scif2_platform_data, 125 .platform_data = &scif2_platform_data,
111 }, 126 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index f7f1cf2af302..9bdc61143f40 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -199,17 +199,22 @@ static struct platform_device mtu2_2_device = {
199}; 199};
200 200
201static struct plat_sci_port scif0_platform_data = { 201static struct plat_sci_port scif0_platform_data = {
202 .mapbase = 0xff804000,
203 .flags = UPF_BOOT_AUTOCONF, 202 .flags = UPF_BOOT_AUTOCONF,
204 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 203 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
205 .scbrr_algo_id = SCBRR_ALGO_2, 204 .scbrr_algo_id = SCBRR_ALGO_2,
206 .type = PORT_SCIF, 205 .type = PORT_SCIF,
207 .irqs = SCIx_IRQ_MUXED(220), 206};
207
208static struct resource scif0_resources[] = {
209 DEFINE_RES_MEM(0xff804000, 0x100),
210 DEFINE_RES_IRQ(220),
208}; 211};
209 212
210static struct platform_device scif0_device = { 213static struct platform_device scif0_device = {
211 .name = "sh-sci", 214 .name = "sh-sci",
212 .id = 0, 215 .id = 0,
216 .resource = scif0_resources,
217 .num_resources = ARRAY_SIZE(scif0_resources),
213 .dev = { 218 .dev = {
214 .platform_data = &scif0_platform_data, 219 .platform_data = &scif0_platform_data,
215 }, 220 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 7b84785b8962..7585c4ed7c5c 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -178,136 +178,176 @@ static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
178 mask_registers, prio_registers, NULL); 178 mask_registers, prio_registers, NULL);
179 179
180static struct plat_sci_port scif0_platform_data = { 180static struct plat_sci_port scif0_platform_data = {
181 .mapbase = 0xfffe8000,
182 .flags = UPF_BOOT_AUTOCONF, 181 .flags = UPF_BOOT_AUTOCONF,
183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 182 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
184 .scbrr_algo_id = SCBRR_ALGO_2, 183 .scbrr_algo_id = SCBRR_ALGO_2,
185 .type = PORT_SCIF, 184 .type = PORT_SCIF,
186 .irqs = SCIx_IRQ_MUXED(180), 185};
186
187static struct resource scif0_resources[] = {
188 DEFINE_RES_MEM(0xfffe8000, 0x100),
189 DEFINE_RES_IRQ(180),
187}; 190};
188 191
189static struct platform_device scif0_device = { 192static struct platform_device scif0_device = {
190 .name = "sh-sci", 193 .name = "sh-sci",
191 .id = 0, 194 .id = 0,
195 .resource = scif0_resources,
196 .num_resources = ARRAY_SIZE(scif0_resources),
192 .dev = { 197 .dev = {
193 .platform_data = &scif0_platform_data, 198 .platform_data = &scif0_platform_data,
194 }, 199 },
195}; 200};
196 201
197static struct plat_sci_port scif1_platform_data = { 202static struct plat_sci_port scif1_platform_data = {
198 .mapbase = 0xfffe8800,
199 .flags = UPF_BOOT_AUTOCONF, 203 .flags = UPF_BOOT_AUTOCONF,
200 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 204 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
201 .scbrr_algo_id = SCBRR_ALGO_2, 205 .scbrr_algo_id = SCBRR_ALGO_2,
202 .type = PORT_SCIF, 206 .type = PORT_SCIF,
203 .irqs = SCIx_IRQ_MUXED(184), 207};
208
209static struct resource scif1_resources[] = {
210 DEFINE_RES_MEM(0xfffe8800, 0x100),
211 DEFINE_RES_IRQ(184),
204}; 212};
205 213
206static struct platform_device scif1_device = { 214static struct platform_device scif1_device = {
207 .name = "sh-sci", 215 .name = "sh-sci",
208 .id = 1, 216 .id = 1,
217 .resource = scif1_resources,
218 .num_resources = ARRAY_SIZE(scif1_resources),
209 .dev = { 219 .dev = {
210 .platform_data = &scif1_platform_data, 220 .platform_data = &scif1_platform_data,
211 }, 221 },
212}; 222};
213 223
214static struct plat_sci_port scif2_platform_data = { 224static struct plat_sci_port scif2_platform_data = {
215 .mapbase = 0xfffe9000,
216 .flags = UPF_BOOT_AUTOCONF, 225 .flags = UPF_BOOT_AUTOCONF,
217 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 226 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
218 .scbrr_algo_id = SCBRR_ALGO_2, 227 .scbrr_algo_id = SCBRR_ALGO_2,
219 .type = PORT_SCIF, 228 .type = PORT_SCIF,
220 .irqs = SCIx_IRQ_MUXED(188), 229};
230
231static struct resource scif2_resources[] = {
232 DEFINE_RES_MEM(0xfffe9000, 0x100),
233 DEFINE_RES_IRQ(188),
221}; 234};
222 235
223static struct platform_device scif2_device = { 236static struct platform_device scif2_device = {
224 .name = "sh-sci", 237 .name = "sh-sci",
225 .id = 2, 238 .id = 2,
239 .resource = scif2_resources,
240 .num_resources = ARRAY_SIZE(scif2_resources),
226 .dev = { 241 .dev = {
227 .platform_data = &scif2_platform_data, 242 .platform_data = &scif2_platform_data,
228 }, 243 },
229}; 244};
230 245
231static struct plat_sci_port scif3_platform_data = { 246static struct plat_sci_port scif3_platform_data = {
232 .mapbase = 0xfffe9800,
233 .flags = UPF_BOOT_AUTOCONF, 247 .flags = UPF_BOOT_AUTOCONF,
234 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 248 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
235 .scbrr_algo_id = SCBRR_ALGO_2, 249 .scbrr_algo_id = SCBRR_ALGO_2,
236 .type = PORT_SCIF, 250 .type = PORT_SCIF,
237 .irqs = SCIx_IRQ_MUXED(192), 251};
252
253static struct resource scif3_resources[] = {
254 DEFINE_RES_MEM(0xfffe9800, 0x100),
255 DEFINE_RES_IRQ(192),
238}; 256};
239 257
240static struct platform_device scif3_device = { 258static struct platform_device scif3_device = {
241 .name = "sh-sci", 259 .name = "sh-sci",
242 .id = 3, 260 .id = 3,
261 .resource = scif3_resources,
262 .num_resources = ARRAY_SIZE(scif3_resources),
243 .dev = { 263 .dev = {
244 .platform_data = &scif3_platform_data, 264 .platform_data = &scif3_platform_data,
245 }, 265 },
246}; 266};
247 267
248static struct plat_sci_port scif4_platform_data = { 268static struct plat_sci_port scif4_platform_data = {
249 .mapbase = 0xfffea000,
250 .flags = UPF_BOOT_AUTOCONF, 269 .flags = UPF_BOOT_AUTOCONF,
251 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 270 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
252 .scbrr_algo_id = SCBRR_ALGO_2, 271 .scbrr_algo_id = SCBRR_ALGO_2,
253 .type = PORT_SCIF, 272 .type = PORT_SCIF,
254 .irqs = SCIx_IRQ_MUXED(196), 273};
274
275static struct resource scif4_resources[] = {
276 DEFINE_RES_MEM(0xfffea000, 0x100),
277 DEFINE_RES_IRQ(196),
255}; 278};
256 279
257static struct platform_device scif4_device = { 280static struct platform_device scif4_device = {
258 .name = "sh-sci", 281 .name = "sh-sci",
259 .id = 4, 282 .id = 4,
283 .resource = scif4_resources,
284 .num_resources = ARRAY_SIZE(scif4_resources),
260 .dev = { 285 .dev = {
261 .platform_data = &scif4_platform_data, 286 .platform_data = &scif4_platform_data,
262 }, 287 },
263}; 288};
264 289
265static struct plat_sci_port scif5_platform_data = { 290static struct plat_sci_port scif5_platform_data = {
266 .mapbase = 0xfffea800,
267 .flags = UPF_BOOT_AUTOCONF, 291 .flags = UPF_BOOT_AUTOCONF,
268 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 292 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
269 .scbrr_algo_id = SCBRR_ALGO_2, 293 .scbrr_algo_id = SCBRR_ALGO_2,
270 .type = PORT_SCIF, 294 .type = PORT_SCIF,
271 .irqs = SCIx_IRQ_MUXED(200), 295};
296
297static struct resource scif5_resources[] = {
298 DEFINE_RES_MEM(0xfffea800, 0x100),
299 DEFINE_RES_IRQ(200),
272}; 300};
273 301
274static struct platform_device scif5_device = { 302static struct platform_device scif5_device = {
275 .name = "sh-sci", 303 .name = "sh-sci",
276 .id = 5, 304 .id = 5,
305 .resource = scif5_resources,
306 .num_resources = ARRAY_SIZE(scif5_resources),
277 .dev = { 307 .dev = {
278 .platform_data = &scif5_platform_data, 308 .platform_data = &scif5_platform_data,
279 }, 309 },
280}; 310};
281 311
282static struct plat_sci_port scif6_platform_data = { 312static struct plat_sci_port scif6_platform_data = {
283 .mapbase = 0xfffeb000,
284 .flags = UPF_BOOT_AUTOCONF, 313 .flags = UPF_BOOT_AUTOCONF,
285 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 314 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
286 .scbrr_algo_id = SCBRR_ALGO_2, 315 .scbrr_algo_id = SCBRR_ALGO_2,
287 .type = PORT_SCIF, 316 .type = PORT_SCIF,
288 .irqs = SCIx_IRQ_MUXED(204), 317};
318
319static struct resource scif6_resources[] = {
320 DEFINE_RES_MEM(0xfffeb000, 0x100),
321 DEFINE_RES_IRQ(204),
289}; 322};
290 323
291static struct platform_device scif6_device = { 324static struct platform_device scif6_device = {
292 .name = "sh-sci", 325 .name = "sh-sci",
293 .id = 6, 326 .id = 6,
327 .resource = scif6_resources,
328 .num_resources = ARRAY_SIZE(scif6_resources),
294 .dev = { 329 .dev = {
295 .platform_data = &scif6_platform_data, 330 .platform_data = &scif6_platform_data,
296 }, 331 },
297}; 332};
298 333
299static struct plat_sci_port scif7_platform_data = { 334static struct plat_sci_port scif7_platform_data = {
300 .mapbase = 0xfffeb800,
301 .flags = UPF_BOOT_AUTOCONF, 335 .flags = UPF_BOOT_AUTOCONF,
302 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 336 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
303 .scbrr_algo_id = SCBRR_ALGO_2, 337 .scbrr_algo_id = SCBRR_ALGO_2,
304 .type = PORT_SCIF, 338 .type = PORT_SCIF,
305 .irqs = SCIx_IRQ_MUXED(208), 339};
340
341static struct resource scif7_resources[] = {
342 DEFINE_RES_MEM(0xfffeb800, 0x100),
343 DEFINE_RES_IRQ(208),
306}; 344};
307 345
308static struct platform_device scif7_device = { 346static struct platform_device scif7_device = {
309 .name = "sh-sci", 347 .name = "sh-sci",
310 .id = 7, 348 .id = 7,
349 .resource = scif7_resources,
350 .num_resources = ARRAY_SIZE(scif7_resources),
311 .dev = { 351 .dev = {
312 .platform_data = &scif7_platform_data, 352 .platform_data = &scif7_platform_data,
313 }, 353 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index bfc33f6a28c3..f2a9baaa541b 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -174,76 +174,96 @@ static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
174 mask_registers, prio_registers, NULL); 174 mask_registers, prio_registers, NULL);
175 175
176static struct plat_sci_port scif0_platform_data = { 176static struct plat_sci_port scif0_platform_data = {
177 .mapbase = 0xfffe8000,
178 .flags = UPF_BOOT_AUTOCONF, 177 .flags = UPF_BOOT_AUTOCONF,
179 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 178 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
180 SCSCR_REIE, 179 SCSCR_REIE,
181 .scbrr_algo_id = SCBRR_ALGO_2, 180 .scbrr_algo_id = SCBRR_ALGO_2,
182 .type = PORT_SCIF, 181 .type = PORT_SCIF,
183 .irqs = SCIx_IRQ_MUXED(192),
184 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 182 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
185}; 183};
186 184
185static struct resource scif0_resources[] = {
186 DEFINE_RES_MEM(0xfffe8000, 0x100),
187 DEFINE_RES_IRQ(192),
188};
189
187static struct platform_device scif0_device = { 190static struct platform_device scif0_device = {
188 .name = "sh-sci", 191 .name = "sh-sci",
189 .id = 0, 192 .id = 0,
193 .resource = scif0_resources,
194 .num_resources = ARRAY_SIZE(scif0_resources),
190 .dev = { 195 .dev = {
191 .platform_data = &scif0_platform_data, 196 .platform_data = &scif0_platform_data,
192 }, 197 },
193}; 198};
194 199
195static struct plat_sci_port scif1_platform_data = { 200static struct plat_sci_port scif1_platform_data = {
196 .mapbase = 0xfffe8800,
197 .flags = UPF_BOOT_AUTOCONF, 201 .flags = UPF_BOOT_AUTOCONF,
198 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 202 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
199 SCSCR_REIE, 203 SCSCR_REIE,
200 .scbrr_algo_id = SCBRR_ALGO_2, 204 .scbrr_algo_id = SCBRR_ALGO_2,
201 .type = PORT_SCIF, 205 .type = PORT_SCIF,
202 .irqs = SCIx_IRQ_MUXED(196),
203 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 206 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
204}; 207};
205 208
209static struct resource scif1_resources[] = {
210 DEFINE_RES_MEM(0xfffe8800, 0x100),
211 DEFINE_RES_IRQ(196),
212};
213
206static struct platform_device scif1_device = { 214static struct platform_device scif1_device = {
207 .name = "sh-sci", 215 .name = "sh-sci",
208 .id = 1, 216 .id = 1,
217 .resource = scif1_resources,
218 .num_resources = ARRAY_SIZE(scif1_resources),
209 .dev = { 219 .dev = {
210 .platform_data = &scif1_platform_data, 220 .platform_data = &scif1_platform_data,
211 }, 221 },
212}; 222};
213 223
214static struct plat_sci_port scif2_platform_data = { 224static struct plat_sci_port scif2_platform_data = {
215 .mapbase = 0xfffe9000,
216 .flags = UPF_BOOT_AUTOCONF, 225 .flags = UPF_BOOT_AUTOCONF,
217 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 226 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
218 SCSCR_REIE, 227 SCSCR_REIE,
219 .scbrr_algo_id = SCBRR_ALGO_2, 228 .scbrr_algo_id = SCBRR_ALGO_2,
220 .type = PORT_SCIF, 229 .type = PORT_SCIF,
221 .irqs = SCIx_IRQ_MUXED(200),
222 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 230 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
223}; 231};
224 232
233static struct resource scif2_resources[] = {
234 DEFINE_RES_MEM(0xfffe9000, 0x100),
235 DEFINE_RES_IRQ(200),
236};
237
225static struct platform_device scif2_device = { 238static struct platform_device scif2_device = {
226 .name = "sh-sci", 239 .name = "sh-sci",
227 .id = 2, 240 .id = 2,
241 .resource = scif2_resources,
242 .num_resources = ARRAY_SIZE(scif2_resources),
228 .dev = { 243 .dev = {
229 .platform_data = &scif2_platform_data, 244 .platform_data = &scif2_platform_data,
230 }, 245 },
231}; 246};
232 247
233static struct plat_sci_port scif3_platform_data = { 248static struct plat_sci_port scif3_platform_data = {
234 .mapbase = 0xfffe9800,
235 .flags = UPF_BOOT_AUTOCONF, 249 .flags = UPF_BOOT_AUTOCONF,
236 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 250 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
237 SCSCR_REIE, 251 SCSCR_REIE,
238 .scbrr_algo_id = SCBRR_ALGO_2, 252 .scbrr_algo_id = SCBRR_ALGO_2,
239 .type = PORT_SCIF, 253 .type = PORT_SCIF,
240 .irqs = SCIx_IRQ_MUXED(204),
241 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 254 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
242}; 255};
243 256
257static struct resource scif3_resources[] = {
258 DEFINE_RES_MEM(0xfffe9800, 0x100),
259 DEFINE_RES_IRQ(204),
260};
261
244static struct platform_device scif3_device = { 262static struct platform_device scif3_device = {
245 .name = "sh-sci", 263 .name = "sh-sci",
246 .id = 3, 264 .id = 3,
265 .resource = scif3_resources,
266 .num_resources = ARRAY_SIZE(scif3_resources),
247 .dev = { 267 .dev = {
248 .platform_data = &scif3_platform_data, 268 .platform_data = &scif3_platform_data,
249 }, 269 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index a5010741de85..fc7cacd36729 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -134,68 +134,88 @@ static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
134 mask_registers, prio_registers, NULL); 134 mask_registers, prio_registers, NULL);
135 135
136static struct plat_sci_port scif0_platform_data = { 136static struct plat_sci_port scif0_platform_data = {
137 .mapbase = 0xfffe8000,
138 .flags = UPF_BOOT_AUTOCONF, 137 .flags = UPF_BOOT_AUTOCONF,
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 138 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
140 .scbrr_algo_id = SCBRR_ALGO_2, 139 .scbrr_algo_id = SCBRR_ALGO_2,
141 .type = PORT_SCIF, 140 .type = PORT_SCIF,
142 .irqs = SCIx_IRQ_MUXED(240), 141};
142
143static struct resource scif0_resources[] = {
144 DEFINE_RES_MEM(0xfffe8000, 0x100),
145 DEFINE_RES_IRQ(240),
143}; 146};
144 147
145static struct platform_device scif0_device = { 148static struct platform_device scif0_device = {
146 .name = "sh-sci", 149 .name = "sh-sci",
147 .id = 0, 150 .id = 0,
151 .resource = scif0_resources,
152 .num_resources = ARRAY_SIZE(scif0_resources),
148 .dev = { 153 .dev = {
149 .platform_data = &scif0_platform_data, 154 .platform_data = &scif0_platform_data,
150 }, 155 },
151}; 156};
152 157
153static struct plat_sci_port scif1_platform_data = { 158static struct plat_sci_port scif1_platform_data = {
154 .mapbase = 0xfffe8800,
155 .flags = UPF_BOOT_AUTOCONF, 159 .flags = UPF_BOOT_AUTOCONF,
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 160 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
157 .scbrr_algo_id = SCBRR_ALGO_2, 161 .scbrr_algo_id = SCBRR_ALGO_2,
158 .type = PORT_SCIF, 162 .type = PORT_SCIF,
159 .irqs = SCIx_IRQ_MUXED(244), 163};
164
165static struct resource scif1_resources[] = {
166 DEFINE_RES_MEM(0xfffe8800, 0x100),
167 DEFINE_RES_IRQ(244),
160}; 168};
161 169
162static struct platform_device scif1_device = { 170static struct platform_device scif1_device = {
163 .name = "sh-sci", 171 .name = "sh-sci",
164 .id = 1, 172 .id = 1,
173 .resource = scif1_resources,
174 .num_resources = ARRAY_SIZE(scif1_resources),
165 .dev = { 175 .dev = {
166 .platform_data = &scif1_platform_data, 176 .platform_data = &scif1_platform_data,
167 }, 177 },
168}; 178};
169 179
170static struct plat_sci_port scif2_platform_data = { 180static struct plat_sci_port scif2_platform_data = {
171 .mapbase = 0xfffe9000,
172 .flags = UPF_BOOT_AUTOCONF, 181 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 182 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
174 .scbrr_algo_id = SCBRR_ALGO_2, 183 .scbrr_algo_id = SCBRR_ALGO_2,
175 .type = PORT_SCIF, 184 .type = PORT_SCIF,
176 .irqs = SCIx_IRQ_MUXED(248), 185};
186
187static struct resource scif2_resources[] = {
188 DEFINE_RES_MEM(0xfffe9000, 0x100),
189 DEFINE_RES_IRQ(248),
177}; 190};
178 191
179static struct platform_device scif2_device = { 192static struct platform_device scif2_device = {
180 .name = "sh-sci", 193 .name = "sh-sci",
181 .id = 2, 194 .id = 2,
195 .resource = scif2_resources,
196 .num_resources = ARRAY_SIZE(scif2_resources),
182 .dev = { 197 .dev = {
183 .platform_data = &scif2_platform_data, 198 .platform_data = &scif2_platform_data,
184 }, 199 },
185}; 200};
186 201
187static struct plat_sci_port scif3_platform_data = { 202static struct plat_sci_port scif3_platform_data = {
188 .mapbase = 0xfffe9800,
189 .flags = UPF_BOOT_AUTOCONF, 203 .flags = UPF_BOOT_AUTOCONF,
190 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 204 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
191 .scbrr_algo_id = SCBRR_ALGO_2, 205 .scbrr_algo_id = SCBRR_ALGO_2,
192 .type = PORT_SCIF, 206 .type = PORT_SCIF,
193 .irqs = SCIx_IRQ_MUXED(252), 207};
208
209static struct resource scif3_resources[] = {
210 DEFINE_RES_MEM(0xfffe9800, 0x100),
211 DEFINE_RES_IRQ(252),
194}; 212};
195 213
196static struct platform_device scif3_device = { 214static struct platform_device scif3_device = {
197 .name = "sh-sci", 215 .name = "sh-sci",
198 .id = 3, 216 .id = 3,
217 .resource = scif3_resources,
218 .num_resources = ARRAY_SIZE(scif3_resources),
199 .dev = { 219 .dev = {
200 .platform_data = &scif3_platform_data, 220 .platform_data = &scif3_platform_data,
201 }, 221 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
index ce5c1b5aebfa..00edbdabcaa1 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
@@ -226,152 +226,216 @@ static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups,
226 mask_registers, prio_registers, NULL); 226 mask_registers, prio_registers, NULL);
227 227
228static struct plat_sci_port scif0_platform_data = { 228static struct plat_sci_port scif0_platform_data = {
229 .mapbase = 0xfffe8000,
230 .flags = UPF_BOOT_AUTOCONF, 229 .flags = UPF_BOOT_AUTOCONF,
231 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 230 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
232 SCSCR_REIE | SCSCR_TOIE, 231 SCSCR_REIE | SCSCR_TOIE,
233 .scbrr_algo_id = SCBRR_ALGO_2, 232 .scbrr_algo_id = SCBRR_ALGO_2,
234 .type = PORT_SCIF, 233 .type = PORT_SCIF,
235 .irqs = { 233, 234, 235, 232 },
236 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 234 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
237}; 235};
238 236
237static struct resource scif0_resources[] = {
238 DEFINE_RES_MEM(0xfffe8000, 0x100),
239 DEFINE_RES_IRQ(233),
240 DEFINE_RES_IRQ(234),
241 DEFINE_RES_IRQ(235),
242 DEFINE_RES_IRQ(232),
243};
244
239static struct platform_device scif0_device = { 245static struct platform_device scif0_device = {
240 .name = "sh-sci", 246 .name = "sh-sci",
241 .id = 0, 247 .id = 0,
248 .resource = scif0_resources,
249 .num_resources = ARRAY_SIZE(scif0_resources),
242 .dev = { 250 .dev = {
243 .platform_data = &scif0_platform_data, 251 .platform_data = &scif0_platform_data,
244 }, 252 },
245}; 253};
246 254
247static struct plat_sci_port scif1_platform_data = { 255static struct plat_sci_port scif1_platform_data = {
248 .mapbase = 0xfffe8800,
249 .flags = UPF_BOOT_AUTOCONF, 256 .flags = UPF_BOOT_AUTOCONF,
250 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 257 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
251 SCSCR_REIE | SCSCR_TOIE, 258 SCSCR_REIE | SCSCR_TOIE,
252 .scbrr_algo_id = SCBRR_ALGO_2, 259 .scbrr_algo_id = SCBRR_ALGO_2,
253 .type = PORT_SCIF, 260 .type = PORT_SCIF,
254 .irqs = { 237, 238, 239, 236 },
255 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 261 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
256}; 262};
257 263
264static struct resource scif1_resources[] = {
265 DEFINE_RES_MEM(0xfffe8800, 0x100),
266 DEFINE_RES_IRQ(237),
267 DEFINE_RES_IRQ(238),
268 DEFINE_RES_IRQ(239),
269 DEFINE_RES_IRQ(236),
270};
271
258static struct platform_device scif1_device = { 272static struct platform_device scif1_device = {
259 .name = "sh-sci", 273 .name = "sh-sci",
260 .id = 1, 274 .id = 1,
275 .resource = scif1_resources,
276 .num_resources = ARRAY_SIZE(scif1_resources),
261 .dev = { 277 .dev = {
262 .platform_data = &scif1_platform_data, 278 .platform_data = &scif1_platform_data,
263 }, 279 },
264}; 280};
265 281
266static struct plat_sci_port scif2_platform_data = { 282static struct plat_sci_port scif2_platform_data = {
267 .mapbase = 0xfffe9000,
268 .flags = UPF_BOOT_AUTOCONF, 283 .flags = UPF_BOOT_AUTOCONF,
269 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 284 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
270 SCSCR_REIE | SCSCR_TOIE, 285 SCSCR_REIE | SCSCR_TOIE,
271 .scbrr_algo_id = SCBRR_ALGO_2, 286 .scbrr_algo_id = SCBRR_ALGO_2,
272 .type = PORT_SCIF, 287 .type = PORT_SCIF,
273 .irqs = { 241, 242, 243, 240 },
274 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 288 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
275}; 289};
276 290
291static struct resource scif2_resources[] = {
292 DEFINE_RES_MEM(0xfffe9000, 0x100),
293 DEFINE_RES_IRQ(241),
294 DEFINE_RES_IRQ(242),
295 DEFINE_RES_IRQ(243),
296 DEFINE_RES_IRQ(240),
297};
298
277static struct platform_device scif2_device = { 299static struct platform_device scif2_device = {
278 .name = "sh-sci", 300 .name = "sh-sci",
279 .id = 2, 301 .id = 2,
302 .resource = scif2_resources,
303 .num_resources = ARRAY_SIZE(scif2_resources),
280 .dev = { 304 .dev = {
281 .platform_data = &scif2_platform_data, 305 .platform_data = &scif2_platform_data,
282 }, 306 },
283}; 307};
284 308
285static struct plat_sci_port scif3_platform_data = { 309static struct plat_sci_port scif3_platform_data = {
286 .mapbase = 0xfffe9800,
287 .flags = UPF_BOOT_AUTOCONF, 310 .flags = UPF_BOOT_AUTOCONF,
288 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 311 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
289 SCSCR_REIE | SCSCR_TOIE, 312 SCSCR_REIE | SCSCR_TOIE,
290 .scbrr_algo_id = SCBRR_ALGO_2, 313 .scbrr_algo_id = SCBRR_ALGO_2,
291 .type = PORT_SCIF, 314 .type = PORT_SCIF,
292 .irqs = { 245, 246, 247, 244 },
293 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 315 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
294}; 316};
295 317
318static struct resource scif3_resources[] = {
319 DEFINE_RES_MEM(0xfffe9800, 0x100),
320 DEFINE_RES_IRQ(245),
321 DEFINE_RES_IRQ(246),
322 DEFINE_RES_IRQ(247),
323 DEFINE_RES_IRQ(244),
324};
325
296static struct platform_device scif3_device = { 326static struct platform_device scif3_device = {
297 .name = "sh-sci", 327 .name = "sh-sci",
298 .id = 3, 328 .id = 3,
329 .resource = scif3_resources,
330 .num_resources = ARRAY_SIZE(scif3_resources),
299 .dev = { 331 .dev = {
300 .platform_data = &scif3_platform_data, 332 .platform_data = &scif3_platform_data,
301 }, 333 },
302}; 334};
303 335
304static struct plat_sci_port scif4_platform_data = { 336static struct plat_sci_port scif4_platform_data = {
305 .mapbase = 0xfffea000,
306 .flags = UPF_BOOT_AUTOCONF, 337 .flags = UPF_BOOT_AUTOCONF,
307 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 338 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
308 SCSCR_REIE | SCSCR_TOIE, 339 SCSCR_REIE | SCSCR_TOIE,
309 .scbrr_algo_id = SCBRR_ALGO_2, 340 .scbrr_algo_id = SCBRR_ALGO_2,
310 .type = PORT_SCIF, 341 .type = PORT_SCIF,
311 .irqs = { 249, 250, 251, 248 },
312 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 342 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
313}; 343};
314 344
345static struct resource scif4_resources[] = {
346 DEFINE_RES_MEM(0xfffea000, 0x100),
347 DEFINE_RES_IRQ(249),
348 DEFINE_RES_IRQ(250),
349 DEFINE_RES_IRQ(251),
350 DEFINE_RES_IRQ(248),
351};
352
315static struct platform_device scif4_device = { 353static struct platform_device scif4_device = {
316 .name = "sh-sci", 354 .name = "sh-sci",
317 .id = 4, 355 .id = 4,
356 .resource = scif4_resources,
357 .num_resources = ARRAY_SIZE(scif4_resources),
318 .dev = { 358 .dev = {
319 .platform_data = &scif4_platform_data, 359 .platform_data = &scif4_platform_data,
320 }, 360 },
321}; 361};
322 362
323static struct plat_sci_port scif5_platform_data = { 363static struct plat_sci_port scif5_platform_data = {
324 .mapbase = 0xfffea800,
325 .flags = UPF_BOOT_AUTOCONF, 364 .flags = UPF_BOOT_AUTOCONF,
326 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 365 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
327 SCSCR_REIE | SCSCR_TOIE, 366 SCSCR_REIE | SCSCR_TOIE,
328 .scbrr_algo_id = SCBRR_ALGO_2, 367 .scbrr_algo_id = SCBRR_ALGO_2,
329 .type = PORT_SCIF, 368 .type = PORT_SCIF,
330 .irqs = { 253, 254, 255, 252 },
331 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 369 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
332}; 370};
333 371
372static struct resource scif5_resources[] = {
373 DEFINE_RES_MEM(0xfffea800, 0x100),
374 DEFINE_RES_IRQ(253),
375 DEFINE_RES_IRQ(254),
376 DEFINE_RES_IRQ(255),
377 DEFINE_RES_IRQ(252),
378};
379
334static struct platform_device scif5_device = { 380static struct platform_device scif5_device = {
335 .name = "sh-sci", 381 .name = "sh-sci",
336 .id = 5, 382 .id = 5,
383 .resource = scif5_resources,
384 .num_resources = ARRAY_SIZE(scif5_resources),
337 .dev = { 385 .dev = {
338 .platform_data = &scif5_platform_data, 386 .platform_data = &scif5_platform_data,
339 }, 387 },
340}; 388};
341 389
342static struct plat_sci_port scif6_platform_data = { 390static struct plat_sci_port scif6_platform_data = {
343 .mapbase = 0xfffeb000,
344 .flags = UPF_BOOT_AUTOCONF, 391 .flags = UPF_BOOT_AUTOCONF,
345 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 392 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
346 SCSCR_REIE | SCSCR_TOIE, 393 SCSCR_REIE | SCSCR_TOIE,
347 .scbrr_algo_id = SCBRR_ALGO_2, 394 .scbrr_algo_id = SCBRR_ALGO_2,
348 .type = PORT_SCIF, 395 .type = PORT_SCIF,
349 .irqs = { 257, 258, 259, 256 },
350 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 396 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
351}; 397};
352 398
399static struct resource scif6_resources[] = {
400 DEFINE_RES_MEM(0xfffeb000, 0x100),
401 DEFINE_RES_IRQ(257),
402 DEFINE_RES_IRQ(258),
403 DEFINE_RES_IRQ(259),
404 DEFINE_RES_IRQ(256),
405};
406
353static struct platform_device scif6_device = { 407static struct platform_device scif6_device = {
354 .name = "sh-sci", 408 .name = "sh-sci",
355 .id = 6, 409 .id = 6,
410 .resource = scif6_resources,
411 .num_resources = ARRAY_SIZE(scif6_resources),
356 .dev = { 412 .dev = {
357 .platform_data = &scif6_platform_data, 413 .platform_data = &scif6_platform_data,
358 }, 414 },
359}; 415};
360 416
361static struct plat_sci_port scif7_platform_data = { 417static struct plat_sci_port scif7_platform_data = {
362 .mapbase = 0xfffeb800,
363 .flags = UPF_BOOT_AUTOCONF, 418 .flags = UPF_BOOT_AUTOCONF,
364 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 419 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
365 SCSCR_REIE | SCSCR_TOIE, 420 SCSCR_REIE | SCSCR_TOIE,
366 .scbrr_algo_id = SCBRR_ALGO_2, 421 .scbrr_algo_id = SCBRR_ALGO_2,
367 .type = PORT_SCIF, 422 .type = PORT_SCIF,
368 .irqs = { 261, 262, 263, 260 },
369 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 423 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
370}; 424};
371 425
426static struct resource scif7_resources[] = {
427 DEFINE_RES_MEM(0xfffeb800, 0x100),
428 DEFINE_RES_IRQ(261),
429 DEFINE_RES_IRQ(262),
430 DEFINE_RES_IRQ(263),
431 DEFINE_RES_IRQ(260),
432};
433
372static struct platform_device scif7_device = { 434static struct platform_device scif7_device = {
373 .name = "sh-sci", 435 .name = "sh-sci",
374 .id = 7, 436 .id = 7,
437 .resource = scif7_resources,
438 .num_resources = ARRAY_SIZE(scif7_resources),
375 .dev = { 439 .dev = {
376 .platform_data = &scif7_platform_data, 440 .platform_data = &scif7_platform_data,
377 }, 441 },
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c
index e82ae9d8d3bc..5cdbaac322a0 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c
@@ -248,152 +248,216 @@ static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups,
248 mask_registers, prio_registers, NULL); 248 mask_registers, prio_registers, NULL);
249 249
250static struct plat_sci_port scif0_platform_data = { 250static struct plat_sci_port scif0_platform_data = {
251 .mapbase = 0xe8007000,
252 .flags = UPF_BOOT_AUTOCONF, 251 .flags = UPF_BOOT_AUTOCONF,
253 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 252 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
254 SCSCR_REIE | SCSCR_TOIE, 253 SCSCR_REIE | SCSCR_TOIE,
255 .scbrr_algo_id = SCBRR_ALGO_2, 254 .scbrr_algo_id = SCBRR_ALGO_2,
256 .type = PORT_SCIF, 255 .type = PORT_SCIF,
257 .irqs = { 259, 260, 261, 258 },
258 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 256 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
259}; 257};
260 258
259static struct resource scif0_resources[] = {
260 DEFINE_RES_MEM(0xe8007000, 0x100),
261 DEFINE_RES_IRQ(259),
262 DEFINE_RES_IRQ(260),
263 DEFINE_RES_IRQ(261),
264 DEFINE_RES_IRQ(258),
265};
266
261static struct platform_device scif0_device = { 267static struct platform_device scif0_device = {
262 .name = "sh-sci", 268 .name = "sh-sci",
263 .id = 0, 269 .id = 0,
270 .resource = scif0_resources,
271 .num_resources = ARRAY_SIZE(scif0_resources),
264 .dev = { 272 .dev = {
265 .platform_data = &scif0_platform_data, 273 .platform_data = &scif0_platform_data,
266 }, 274 },
267}; 275};
268 276
269static struct plat_sci_port scif1_platform_data = { 277static struct plat_sci_port scif1_platform_data = {
270 .mapbase = 0xe8007800,
271 .flags = UPF_BOOT_AUTOCONF, 278 .flags = UPF_BOOT_AUTOCONF,
272 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 279 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
273 SCSCR_REIE | SCSCR_TOIE, 280 SCSCR_REIE | SCSCR_TOIE,
274 .scbrr_algo_id = SCBRR_ALGO_2, 281 .scbrr_algo_id = SCBRR_ALGO_2,
275 .type = PORT_SCIF, 282 .type = PORT_SCIF,
276 .irqs = { 263, 264, 265, 262 },
277 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 283 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
278}; 284};
279 285
286static struct resource scif1_resources[] = {
287 DEFINE_RES_MEM(0xe8007800, 0x100),
288 DEFINE_RES_IRQ(263),
289 DEFINE_RES_IRQ(264),
290 DEFINE_RES_IRQ(265),
291 DEFINE_RES_IRQ(262),
292};
293
280static struct platform_device scif1_device = { 294static struct platform_device scif1_device = {
281 .name = "sh-sci", 295 .name = "sh-sci",
282 .id = 1, 296 .id = 1,
297 .resource = scif1_resources,
298 .num_resources = ARRAY_SIZE(scif1_resources),
283 .dev = { 299 .dev = {
284 .platform_data = &scif1_platform_data, 300 .platform_data = &scif1_platform_data,
285 }, 301 },
286}; 302};
287 303
288static struct plat_sci_port scif2_platform_data = { 304static struct plat_sci_port scif2_platform_data = {
289 .mapbase = 0xe8008000,
290 .flags = UPF_BOOT_AUTOCONF, 305 .flags = UPF_BOOT_AUTOCONF,
291 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 306 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
292 SCSCR_REIE | SCSCR_TOIE, 307 SCSCR_REIE | SCSCR_TOIE,
293 .scbrr_algo_id = SCBRR_ALGO_2, 308 .scbrr_algo_id = SCBRR_ALGO_2,
294 .type = PORT_SCIF, 309 .type = PORT_SCIF,
295 .irqs = { 267, 268, 269, 266 },
296 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 310 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
297}; 311};
298 312
313static struct resource scif2_resources[] = {
314 DEFINE_RES_MEM(0xe8008000, 0x100),
315 DEFINE_RES_IRQ(267),
316 DEFINE_RES_IRQ(268),
317 DEFINE_RES_IRQ(269),
318 DEFINE_RES_IRQ(266),
319};
320
299static struct platform_device scif2_device = { 321static struct platform_device scif2_device = {
300 .name = "sh-sci", 322 .name = "sh-sci",
301 .id = 2, 323 .id = 2,
324 .resource = scif2_resources,
325 .num_resources = ARRAY_SIZE(scif2_resources),
302 .dev = { 326 .dev = {
303 .platform_data = &scif2_platform_data, 327 .platform_data = &scif2_platform_data,
304 }, 328 },
305}; 329};
306 330
307static struct plat_sci_port scif3_platform_data = { 331static struct plat_sci_port scif3_platform_data = {
308 .mapbase = 0xe8008800,
309 .flags = UPF_BOOT_AUTOCONF, 332 .flags = UPF_BOOT_AUTOCONF,
310 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 333 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
311 SCSCR_REIE | SCSCR_TOIE, 334 SCSCR_REIE | SCSCR_TOIE,
312 .scbrr_algo_id = SCBRR_ALGO_2, 335 .scbrr_algo_id = SCBRR_ALGO_2,
313 .type = PORT_SCIF, 336 .type = PORT_SCIF,
314 .irqs = { 271, 272, 273, 270 },
315 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 337 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
316}; 338};
317 339
340static struct resource scif3_resources[] = {
341 DEFINE_RES_MEM(0xe8008800, 0x100),
342 DEFINE_RES_IRQ(271),
343 DEFINE_RES_IRQ(272),
344 DEFINE_RES_IRQ(273),
345 DEFINE_RES_IRQ(270),
346};
347
318static struct platform_device scif3_device = { 348static struct platform_device scif3_device = {
319 .name = "sh-sci", 349 .name = "sh-sci",
320 .id = 3, 350 .id = 3,
351 .resource = scif3_resources,
352 .num_resources = ARRAY_SIZE(scif3_resources),
321 .dev = { 353 .dev = {
322 .platform_data = &scif3_platform_data, 354 .platform_data = &scif3_platform_data,
323 }, 355 },
324}; 356};
325 357
326static struct plat_sci_port scif4_platform_data = { 358static struct plat_sci_port scif4_platform_data = {
327 .mapbase = 0xe8009000,
328 .flags = UPF_BOOT_AUTOCONF, 359 .flags = UPF_BOOT_AUTOCONF,
329 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 360 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
330 SCSCR_REIE | SCSCR_TOIE, 361 SCSCR_REIE | SCSCR_TOIE,
331 .scbrr_algo_id = SCBRR_ALGO_2, 362 .scbrr_algo_id = SCBRR_ALGO_2,
332 .type = PORT_SCIF, 363 .type = PORT_SCIF,
333 .irqs = { 275, 276, 277, 274 },
334 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 364 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
335}; 365};
336 366
367static struct resource scif4_resources[] = {
368 DEFINE_RES_MEM(0xe8009000, 0x100),
369 DEFINE_RES_IRQ(275),
370 DEFINE_RES_IRQ(276),
371 DEFINE_RES_IRQ(277),
372 DEFINE_RES_IRQ(274),
373};
374
337static struct platform_device scif4_device = { 375static struct platform_device scif4_device = {
338 .name = "sh-sci", 376 .name = "sh-sci",
339 .id = 4, 377 .id = 4,
378 .resource = scif4_resources,
379 .num_resources = ARRAY_SIZE(scif4_resources),
340 .dev = { 380 .dev = {
341 .platform_data = &scif4_platform_data, 381 .platform_data = &scif4_platform_data,
342 }, 382 },
343}; 383};
344 384
345static struct plat_sci_port scif5_platform_data = { 385static struct plat_sci_port scif5_platform_data = {
346 .mapbase = 0xe8009800,
347 .flags = UPF_BOOT_AUTOCONF, 386 .flags = UPF_BOOT_AUTOCONF,
348 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 387 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
349 SCSCR_REIE | SCSCR_TOIE, 388 SCSCR_REIE | SCSCR_TOIE,
350 .scbrr_algo_id = SCBRR_ALGO_2, 389 .scbrr_algo_id = SCBRR_ALGO_2,
351 .type = PORT_SCIF, 390 .type = PORT_SCIF,
352 .irqs = { 279, 280, 281, 278 },
353 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 391 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
354}; 392};
355 393
394static struct resource scif5_resources[] = {
395 DEFINE_RES_MEM(0xe8009800, 0x100),
396 DEFINE_RES_IRQ(279),
397 DEFINE_RES_IRQ(280),
398 DEFINE_RES_IRQ(281),
399 DEFINE_RES_IRQ(278),
400};
401
356static struct platform_device scif5_device = { 402static struct platform_device scif5_device = {
357 .name = "sh-sci", 403 .name = "sh-sci",
358 .id = 5, 404 .id = 5,
405 .resource = scif5_resources,
406 .num_resources = ARRAY_SIZE(scif5_resources),
359 .dev = { 407 .dev = {
360 .platform_data = &scif5_platform_data, 408 .platform_data = &scif5_platform_data,
361 }, 409 },
362}; 410};
363 411
364static struct plat_sci_port scif6_platform_data = { 412static struct plat_sci_port scif6_platform_data = {
365 .mapbase = 0xe800a000,
366 .flags = UPF_BOOT_AUTOCONF, 413 .flags = UPF_BOOT_AUTOCONF,
367 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 414 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
368 SCSCR_REIE | SCSCR_TOIE, 415 SCSCR_REIE | SCSCR_TOIE,
369 .scbrr_algo_id = SCBRR_ALGO_2, 416 .scbrr_algo_id = SCBRR_ALGO_2,
370 .type = PORT_SCIF, 417 .type = PORT_SCIF,
371 .irqs = { 283, 284, 285, 282 },
372 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 418 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
373}; 419};
374 420
421static struct resource scif6_resources[] = {
422 DEFINE_RES_MEM(0xe800a000, 0x100),
423 DEFINE_RES_IRQ(283),
424 DEFINE_RES_IRQ(284),
425 DEFINE_RES_IRQ(285),
426 DEFINE_RES_IRQ(282),
427};
428
375static struct platform_device scif6_device = { 429static struct platform_device scif6_device = {
376 .name = "sh-sci", 430 .name = "sh-sci",
377 .id = 6, 431 .id = 6,
432 .resource = scif6_resources,
433 .num_resources = ARRAY_SIZE(scif6_resources),
378 .dev = { 434 .dev = {
379 .platform_data = &scif6_platform_data, 435 .platform_data = &scif6_platform_data,
380 }, 436 },
381}; 437};
382 438
383static struct plat_sci_port scif7_platform_data = { 439static struct plat_sci_port scif7_platform_data = {
384 .mapbase = 0xe800a800,
385 .flags = UPF_BOOT_AUTOCONF, 440 .flags = UPF_BOOT_AUTOCONF,
386 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | 441 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
387 SCSCR_REIE | SCSCR_TOIE, 442 SCSCR_REIE | SCSCR_TOIE,
388 .scbrr_algo_id = SCBRR_ALGO_2, 443 .scbrr_algo_id = SCBRR_ALGO_2,
389 .type = PORT_SCIF, 444 .type = PORT_SCIF,
390 .irqs = { 287, 288, 289, 286 },
391 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, 445 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
392}; 446};
393 447
448static struct resource scif7_resources[] = {
449 DEFINE_RES_MEM(0xe800a800, 0x100),
450 DEFINE_RES_IRQ(287),
451 DEFINE_RES_IRQ(288),
452 DEFINE_RES_IRQ(289),
453 DEFINE_RES_IRQ(286),
454};
455
394static struct platform_device scif7_device = { 456static struct platform_device scif7_device = {
395 .name = "sh-sci", 457 .name = "sh-sci",
396 .id = 7, 458 .id = 7,
459 .resource = scif7_resources,
460 .num_resources = ARRAY_SIZE(scif7_resources),
397 .dev = { 461 .dev = {
398 .platform_data = &scif7_platform_data, 462 .platform_data = &scif7_platform_data,
399 }, 463 },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 03e4c96f2b11..10dd0a01d5f8 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -70,39 +70,49 @@ static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
70 NULL, prio_registers, NULL); 70 NULL, prio_registers, NULL);
71 71
72static struct plat_sci_port scif0_platform_data = { 72static struct plat_sci_port scif0_platform_data = {
73 .mapbase = 0xa4410000,
74 .flags = UPF_BOOT_AUTOCONF, 73 .flags = UPF_BOOT_AUTOCONF,
75 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | 74 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE |
76 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, 75 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
77 .scbrr_algo_id = SCBRR_ALGO_4, 76 .scbrr_algo_id = SCBRR_ALGO_4,
78 .type = PORT_SCIF, 77 .type = PORT_SCIF,
79 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
80 .ops = &sh770x_sci_port_ops, 78 .ops = &sh770x_sci_port_ops,
81 .regtype = SCIx_SH7705_SCIF_REGTYPE, 79 .regtype = SCIx_SH7705_SCIF_REGTYPE,
82}; 80};
83 81
82static struct resource scif0_resources[] = {
83 DEFINE_RES_MEM(0xa4410000, 0x100),
84 DEFINE_RES_IRQ(evt2irq(0x900)),
85};
86
84static struct platform_device scif0_device = { 87static struct platform_device scif0_device = {
85 .name = "sh-sci", 88 .name = "sh-sci",
86 .id = 0, 89 .id = 0,
90 .resource = scif0_resources,
91 .num_resources = ARRAY_SIZE(scif0_resources),
87 .dev = { 92 .dev = {
88 .platform_data = &scif0_platform_data, 93 .platform_data = &scif0_platform_data,
89 }, 94 },
90}; 95};
91 96
92static struct plat_sci_port scif1_platform_data = { 97static struct plat_sci_port scif1_platform_data = {
93 .mapbase = 0xa4400000,
94 .flags = UPF_BOOT_AUTOCONF, 98 .flags = UPF_BOOT_AUTOCONF,
95 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, 99 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
96 .scbrr_algo_id = SCBRR_ALGO_4, 100 .scbrr_algo_id = SCBRR_ALGO_4,
97 .type = PORT_SCIF, 101 .type = PORT_SCIF,
98 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
99 .ops = &sh770x_sci_port_ops, 102 .ops = &sh770x_sci_port_ops,
100 .regtype = SCIx_SH7705_SCIF_REGTYPE, 103 .regtype = SCIx_SH7705_SCIF_REGTYPE,
101}; 104};
102 105
106static struct resource scif1_resources[] = {
107 DEFINE_RES_MEM(0xa4400000, 0x100),
108 DEFINE_RES_IRQ(evt2irq(0x880)),
109};
110
103static struct platform_device scif1_device = { 111static struct platform_device scif1_device = {
104 .name = "sh-sci", 112 .name = "sh-sci",
105 .id = 1, 113 .id = 1,
114 .resource = scif1_resources,
115 .num_resources = ARRAY_SIZE(scif1_resources),
106 .dev = { 116 .dev = {
107 .platform_data = &scif1_platform_data, 117 .platform_data = &scif1_platform_data,
108 }, 118 },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index ba26cd9ce69b..d5541b0a6dc5 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -109,20 +109,25 @@ static struct platform_device rtc_device = {
109}; 109};
110 110
111static struct plat_sci_port scif0_platform_data = { 111static struct plat_sci_port scif0_platform_data = {
112 .mapbase = 0xfffffe80,
113 .port_reg = 0xa4000136, 112 .port_reg = 0xa4000136,
114 .flags = UPF_BOOT_AUTOCONF, 113 .flags = UPF_BOOT_AUTOCONF,
115 .scscr = SCSCR_TE | SCSCR_RE, 114 .scscr = SCSCR_TE | SCSCR_RE,
116 .scbrr_algo_id = SCBRR_ALGO_2, 115 .scbrr_algo_id = SCBRR_ALGO_2,
117 .type = PORT_SCI, 116 .type = PORT_SCI,
118 .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)),
119 .ops = &sh770x_sci_port_ops, 117 .ops = &sh770x_sci_port_ops,
120 .regshift = 1, 118 .regshift = 1,
121}; 119};
122 120
121static struct resource scif0_resources[] = {
122 DEFINE_RES_MEM(0xfffffe80, 0x100),
123 DEFINE_RES_IRQ(evt2irq(0x4e0)),
124};
125
123static struct platform_device scif0_device = { 126static struct platform_device scif0_device = {
124 .name = "sh-sci", 127 .name = "sh-sci",
125 .id = 0, 128 .id = 0,
129 .resource = scif0_resources,
130 .num_resources = ARRAY_SIZE(scif0_resources),
126 .dev = { 131 .dev = {
127 .platform_data = &scif0_platform_data, 132 .platform_data = &scif0_platform_data,
128 }, 133 },
@@ -131,19 +136,24 @@ static struct platform_device scif0_device = {
131 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 136 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
132 defined(CONFIG_CPU_SUBTYPE_SH7709) 137 defined(CONFIG_CPU_SUBTYPE_SH7709)
133static struct plat_sci_port scif1_platform_data = { 138static struct plat_sci_port scif1_platform_data = {
134 .mapbase = 0xa4000150,
135 .flags = UPF_BOOT_AUTOCONF, 139 .flags = UPF_BOOT_AUTOCONF,
136 .scscr = SCSCR_TE | SCSCR_RE, 140 .scscr = SCSCR_TE | SCSCR_RE,
137 .scbrr_algo_id = SCBRR_ALGO_2, 141 .scbrr_algo_id = SCBRR_ALGO_2,
138 .type = PORT_SCIF, 142 .type = PORT_SCIF,
139 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
140 .ops = &sh770x_sci_port_ops, 143 .ops = &sh770x_sci_port_ops,
141 .regtype = SCIx_SH3_SCIF_REGTYPE, 144 .regtype = SCIx_SH3_SCIF_REGTYPE,
142}; 145};
143 146
147static struct resource scif1_resources[] = {
148 DEFINE_RES_MEM(0xa4000150, 0x100),
149 DEFINE_RES_IRQ(evt2irq(0x900)),
150};
151
144static struct platform_device scif1_device = { 152static struct platform_device scif1_device = {
145 .name = "sh-sci", 153 .name = "sh-sci",
146 .id = 1, 154 .id = 1,
155 .resource = scif1_resources,
156 .num_resources = ARRAY_SIZE(scif1_resources),
147 .dev = { 157 .dev = {
148 .platform_data = &scif1_platform_data, 158 .platform_data = &scif1_platform_data,
149 }, 159 },
@@ -152,20 +162,25 @@ static struct platform_device scif1_device = {
152#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 162#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
153 defined(CONFIG_CPU_SUBTYPE_SH7709) 163 defined(CONFIG_CPU_SUBTYPE_SH7709)
154static struct plat_sci_port scif2_platform_data = { 164static struct plat_sci_port scif2_platform_data = {
155 .mapbase = 0xa4000140,
156 .port_reg = SCIx_NOT_SUPPORTED, 165 .port_reg = SCIx_NOT_SUPPORTED,
157 .flags = UPF_BOOT_AUTOCONF, 166 .flags = UPF_BOOT_AUTOCONF,
158 .scscr = SCSCR_TE | SCSCR_RE, 167 .scscr = SCSCR_TE | SCSCR_RE,
159 .scbrr_algo_id = SCBRR_ALGO_2, 168 .scbrr_algo_id = SCBRR_ALGO_2,
160 .type = PORT_IRDA, 169 .type = PORT_IRDA,
161 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
162 .ops = &sh770x_sci_port_ops, 170 .ops = &sh770x_sci_port_ops,
163 .regshift = 1, 171 .regshift = 1,
164}; 172};
165 173
174static struct resource scif2_resources[] = {
175 DEFINE_RES_MEM(0xa4000140, 0x100),
176 DEFINE_RES_IRQ(evt2irq(0x880)),
177};
178
166static struct platform_device scif2_device = { 179static struct platform_device scif2_device = {
167 .name = "sh-sci", 180 .name = "sh-sci",
168 .id = 2, 181 .id = 2,
182 .resource = scif2_resources,
183 .num_resources = ARRAY_SIZE(scif2_resources),
169 .dev = { 184 .dev = {
170 .platform_data = &scif2_platform_data, 185 .platform_data = &scif2_platform_data,
171 }, 186 },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 93c9c5e24a7a..de229f5c6b1e 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -98,36 +98,46 @@ static struct platform_device rtc_device = {
98}; 98};
99 99
100static struct plat_sci_port scif0_platform_data = { 100static struct plat_sci_port scif0_platform_data = {
101 .mapbase = 0xa4400000,
102 .flags = UPF_BOOT_AUTOCONF, 101 .flags = UPF_BOOT_AUTOCONF,
103 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | 102 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
104 SCSCR_CKE1 | SCSCR_CKE0, 103 SCSCR_CKE1 | SCSCR_CKE0,
105 .scbrr_algo_id = SCBRR_ALGO_2, 104 .scbrr_algo_id = SCBRR_ALGO_2,
106 .type = PORT_SCIF, 105 .type = PORT_SCIF,
107 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), 106};
107
108static struct resource scif0_resources[] = {
109 DEFINE_RES_MEM(0xa4400000, 0x100),
110 DEFINE_RES_IRQ(evt2irq(0x880)),
108}; 111};
109 112
110static struct platform_device scif0_device = { 113static struct platform_device scif0_device = {
111 .name = "sh-sci", 114 .name = "sh-sci",
112 .id = 0, 115 .id = 0,
116 .resource = scif0_resources,
117 .num_resources = ARRAY_SIZE(scif0_resources),
113 .dev = { 118 .dev = {
114 .platform_data = &scif0_platform_data, 119 .platform_data = &scif0_platform_data,
115 }, 120 },
116}; 121};
117 122
118static struct plat_sci_port scif1_platform_data = { 123static struct plat_sci_port scif1_platform_data = {
119 .mapbase = 0xa4410000,
120 .flags = UPF_BOOT_AUTOCONF, 124 .flags = UPF_BOOT_AUTOCONF,
121 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | 125 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE |
122 SCSCR_CKE1 | SCSCR_CKE0, 126 SCSCR_CKE1 | SCSCR_CKE0,
123 .scbrr_algo_id = SCBRR_ALGO_2, 127 .scbrr_algo_id = SCBRR_ALGO_2,
124 .type = PORT_SCIF, 128 .type = PORT_SCIF,
125 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), 129};
130
131static struct resource scif1_resources[] = {
132 DEFINE_RES_MEM(0xa4410000, 0x100),
133 DEFINE_RES_IRQ(evt2irq(0x900)),
126}; 134};
127 135
128static struct platform_device scif1_device = { 136static struct platform_device scif1_device = {
129 .name = "sh-sci", 137 .name = "sh-sci",
130 .id = 1, 138 .id = 1,
139 .resource = scif1_resources,
140 .num_resources = ARRAY_SIZE(scif1_resources),
131 .dev = { 141 .dev = {
132 .platform_data = &scif1_platform_data, 142 .platform_data = &scif1_platform_data,
133 }, 143 },
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 42d991f632b1..ca835819357b 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -52,38 +52,48 @@ static struct platform_device rtc_device = {
52}; 52};
53 53
54static struct plat_sci_port scif0_platform_data = { 54static struct plat_sci_port scif0_platform_data = {
55 .mapbase = 0xa4430000,
56 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE, 56 .scscr = SCSCR_RE | SCSCR_TE,
58 .scbrr_algo_id = SCBRR_ALGO_4, 57 .scbrr_algo_id = SCBRR_ALGO_4,
59 .type = PORT_SCIF, 58 .type = PORT_SCIF,
60 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
61 .ops = &sh7720_sci_port_ops, 59 .ops = &sh7720_sci_port_ops,
62 .regtype = SCIx_SH7705_SCIF_REGTYPE, 60 .regtype = SCIx_SH7705_SCIF_REGTYPE,
63}; 61};
64 62
63static struct resource scif0_resources[] = {
64 DEFINE_RES_MEM(0xa4430000, 0x100),
65 DEFINE_RES_IRQ(evt2irq(0xc00)),
66};
67
65static struct platform_device scif0_device = { 68static struct platform_device scif0_device = {
66 .name = "sh-sci", 69 .name = "sh-sci",
67 .id = 0, 70 .id = 0,
71 .resource = scif0_resources,
72 .num_resources = ARRAY_SIZE(scif0_resources),
68 .dev = { 73 .dev = {
69 .platform_data = &scif0_platform_data, 74 .platform_data = &scif0_platform_data,
70 }, 75 },
71}; 76};
72 77
73static struct plat_sci_port scif1_platform_data = { 78static struct plat_sci_port scif1_platform_data = {
74 .mapbase = 0xa4438000,
75 .flags = UPF_BOOT_AUTOCONF, 79 .flags = UPF_BOOT_AUTOCONF,
76 .scscr = SCSCR_RE | SCSCR_TE, 80 .scscr = SCSCR_RE | SCSCR_TE,
77 .scbrr_algo_id = SCBRR_ALGO_4, 81 .scbrr_algo_id = SCBRR_ALGO_4,
78 .type = PORT_SCIF, 82 .type = PORT_SCIF,
79 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
80 .ops = &sh7720_sci_port_ops, 83 .ops = &sh7720_sci_port_ops,
81 .regtype = SCIx_SH7705_SCIF_REGTYPE, 84 .regtype = SCIx_SH7705_SCIF_REGTYPE,
82}; 85};
83 86
87static struct resource scif1_resources[] = {
88 DEFINE_RES_MEM(0xa4438000, 0x100),
89 DEFINE_RES_IRQ(evt2irq(0xc20)),
90};
91
84static struct platform_device scif1_device = { 92static struct platform_device scif1_device = {
85 .name = "sh-sci", 93 .name = "sh-sci",
86 .id = 1, 94 .id = 1,
95 .resource = scif1_resources,
96 .num_resources = ARRAY_SIZE(scif1_resources),
87 .dev = { 97 .dev = {
88 .platform_data = &scif1_platform_data, 98 .platform_data = &scif1_platform_data,
89 }, 99 },
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index 2a5320aa73bb..0fc6a105144a 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -17,20 +17,25 @@
17#include <linux/io.h> 17#include <linux/io.h>
18 18
19static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = 0xffe80000,
21 .flags = UPF_BOOT_AUTOCONF, 20 .flags = UPF_BOOT_AUTOCONF,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2, 22 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 23 .type = PORT_SCIF,
25 .irqs = { evt2irq(0x700), 24};
26 evt2irq(0x720), 25
27 evt2irq(0x760), 26static struct resource scif0_resources[] = {
28 evt2irq(0x740) }, 27 DEFINE_RES_MEM(0xffe80000, 0x100),
28 DEFINE_RES_IRQ(evt2irq(0x700)),
29 DEFINE_RES_IRQ(evt2irq(0x720)),
30 DEFINE_RES_IRQ(evt2irq(0x760)),
31 DEFINE_RES_IRQ(evt2irq(0x740)),
29}; 32};
30 33
31static struct platform_device scif0_device = { 34static struct platform_device scif0_device = {
32 .name = "sh-sci", 35 .name = "sh-sci",
33 .id = 0, 36 .id = 0,
37 .resource = scif0_resources,
38 .num_resources = ARRAY_SIZE(scif0_resources),
34 .dev = { 39 .dev = {
35 .platform_data = &scif0_platform_data, 40 .platform_data = &scif0_platform_data,
36 }, 41 },
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index 04a45512596f..5613c15d8163 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -38,36 +38,46 @@ static struct platform_device rtc_device = {
38}; 38};
39 39
40static struct plat_sci_port sci_platform_data = { 40static struct plat_sci_port sci_platform_data = {
41 .mapbase = 0xffe00000,
42 .port_reg = 0xffe0001C, 41 .port_reg = 0xffe0001C,
43 .flags = UPF_BOOT_AUTOCONF, 42 .flags = UPF_BOOT_AUTOCONF,
44 .scscr = SCSCR_TE | SCSCR_RE, 43 .scscr = SCSCR_TE | SCSCR_RE,
45 .scbrr_algo_id = SCBRR_ALGO_2, 44 .scbrr_algo_id = SCBRR_ALGO_2,
46 .type = PORT_SCI, 45 .type = PORT_SCI,
47 .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)),
48 .regshift = 2, 46 .regshift = 2,
49}; 47};
50 48
49static struct resource sci_resources[] = {
50 DEFINE_RES_MEM(0xffe00000, 0x100),
51 DEFINE_RES_IRQ(evt2irq(0x4e0)),
52};
53
51static struct platform_device sci_device = { 54static struct platform_device sci_device = {
52 .name = "sh-sci", 55 .name = "sh-sci",
53 .id = 0, 56 .id = 0,
57 .resource = sci_resources,
58 .num_resources = ARRAY_SIZE(sci_resources),
54 .dev = { 59 .dev = {
55 .platform_data = &sci_platform_data, 60 .platform_data = &sci_platform_data,
56 }, 61 },
57}; 62};
58 63
59static struct plat_sci_port scif_platform_data = { 64static struct plat_sci_port scif_platform_data = {
60 .mapbase = 0xffe80000,
61 .flags = UPF_BOOT_AUTOCONF, 65 .flags = UPF_BOOT_AUTOCONF,
62 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, 66 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
63 .scbrr_algo_id = SCBRR_ALGO_2, 67 .scbrr_algo_id = SCBRR_ALGO_2,
64 .type = PORT_SCIF, 68 .type = PORT_SCIF,
65 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), 69};
70
71static struct resource scif_resources[] = {
72 DEFINE_RES_MEM(0xffe80000, 0x100),
73 DEFINE_RES_IRQ(evt2irq(0x700)),
66}; 74};
67 75
68static struct platform_device scif_device = { 76static struct platform_device scif_device = {
69 .name = "sh-sci", 77 .name = "sh-sci",
70 .id = 1, 78 .id = 1,
79 .resource = scif_resources,
80 .num_resources = ARRAY_SIZE(scif_resources),
71 .dev = { 81 .dev = {
72 .platform_data = &scif_platform_data, 82 .platform_data = &scif_platform_data,
73 }, 83 },
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 98e075ada44e..a83e6f5a42d0 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -128,83 +128,103 @@ static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups,
128 mask_registers, prio_registers, NULL); 128 mask_registers, prio_registers, NULL);
129 129
130static struct plat_sci_port scif0_platform_data = { 130static struct plat_sci_port scif0_platform_data = {
131 .mapbase = 0xfe600000,
132 .flags = UPF_BOOT_AUTOCONF, 131 .flags = UPF_BOOT_AUTOCONF,
133 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 132 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
134 .scbrr_algo_id = SCBRR_ALGO_2, 133 .scbrr_algo_id = SCBRR_ALGO_2,
135 .type = PORT_SCIF, 134 .type = PORT_SCIF,
136 .irqs = { evt2irq(0x880),
137 evt2irq(0x8a0),
138 evt2irq(0x8e0),
139 evt2irq(0x8c0) },
140 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 135 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
141}; 136};
142 137
138static struct resource scif0_resources[] = {
139 DEFINE_RES_MEM(0xfe600000, 0x100),
140 DEFINE_RES_IRQ(evt2irq(0x880)),
141 DEFINE_RES_IRQ(evt2irq(0x8a0)),
142 DEFINE_RES_IRQ(evt2irq(0x8e0)),
143 DEFINE_RES_IRQ(evt2irq(0x8c0)),
144};
145
143static struct platform_device scif0_device = { 146static struct platform_device scif0_device = {
144 .name = "sh-sci", 147 .name = "sh-sci",
145 .id = 0, 148 .id = 0,
149 .resource = scif0_resources,
150 .num_resources = ARRAY_SIZE(scif0_resources),
146 .dev = { 151 .dev = {
147 .platform_data = &scif0_platform_data, 152 .platform_data = &scif0_platform_data,
148 }, 153 },
149}; 154};
150 155
151static struct plat_sci_port scif1_platform_data = { 156static struct plat_sci_port scif1_platform_data = {
152 .mapbase = 0xfe610000,
153 .flags = UPF_BOOT_AUTOCONF, 157 .flags = UPF_BOOT_AUTOCONF,
154 .type = PORT_SCIF, 158 .type = PORT_SCIF,
155 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 159 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
156 .scbrr_algo_id = SCBRR_ALGO_2, 160 .scbrr_algo_id = SCBRR_ALGO_2,
157 .irqs = { evt2irq(0xb00),
158 evt2irq(0xb20),
159 evt2irq(0xb60),
160 evt2irq(0xb40) },
161 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 161 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
162}; 162};
163 163
164static struct resource scif1_resources[] = {
165 DEFINE_RES_MEM(0xfe610000, 0x100),
166 DEFINE_RES_IRQ(evt2irq(0xb00)),
167 DEFINE_RES_IRQ(evt2irq(0xb20)),
168 DEFINE_RES_IRQ(evt2irq(0xb60)),
169 DEFINE_RES_IRQ(evt2irq(0xb40)),
170};
171
164static struct platform_device scif1_device = { 172static struct platform_device scif1_device = {
165 .name = "sh-sci", 173 .name = "sh-sci",
166 .id = 1, 174 .id = 1,
175 .resource = scif1_resources,
176 .num_resources = ARRAY_SIZE(scif1_resources),
167 .dev = { 177 .dev = {
168 .platform_data = &scif1_platform_data, 178 .platform_data = &scif1_platform_data,
169 }, 179 },
170}; 180};
171 181
172static struct plat_sci_port scif2_platform_data = { 182static struct plat_sci_port scif2_platform_data = {
173 .mapbase = 0xfe620000,
174 .flags = UPF_BOOT_AUTOCONF, 183 .flags = UPF_BOOT_AUTOCONF,
175 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 184 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
176 .scbrr_algo_id = SCBRR_ALGO_2, 185 .scbrr_algo_id = SCBRR_ALGO_2,
177 .type = PORT_SCIF, 186 .type = PORT_SCIF,
178 .irqs = { evt2irq(0xb80),
179 evt2irq(0xba0),
180 evt2irq(0xbe0),
181 evt2irq(0xbc0) },
182 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 187 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
183}; 188};
184 189
190static struct resource scif2_resources[] = {
191 DEFINE_RES_MEM(0xfe620000, 0x100),
192 DEFINE_RES_IRQ(evt2irq(0xb80)),
193 DEFINE_RES_IRQ(evt2irq(0xba0)),
194 DEFINE_RES_IRQ(evt2irq(0xbe0)),
195 DEFINE_RES_IRQ(evt2irq(0xbc0)),
196};
197
185static struct platform_device scif2_device = { 198static struct platform_device scif2_device = {
186 .name = "sh-sci", 199 .name = "sh-sci",
187 .id = 2, 200 .id = 2,
201 .resource = scif2_resources,
202 .num_resources = ARRAY_SIZE(scif2_resources),
188 .dev = { 203 .dev = {
189 .platform_data = &scif2_platform_data, 204 .platform_data = &scif2_platform_data,
190 }, 205 },
191}; 206};
192 207
193static struct plat_sci_port scif3_platform_data = { 208static struct plat_sci_port scif3_platform_data = {
194 .mapbase = 0xfe480000,
195 .flags = UPF_BOOT_AUTOCONF, 209 .flags = UPF_BOOT_AUTOCONF,
196 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 210 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
197 .scbrr_algo_id = SCBRR_ALGO_2, 211 .scbrr_algo_id = SCBRR_ALGO_2,
198 .type = PORT_SCI, 212 .type = PORT_SCI,
199 .irqs = { evt2irq(0xc00),
200 evt2irq(0xc20),
201 evt2irq(0xc40), },
202 .regshift = 2, 213 .regshift = 2,
203}; 214};
204 215
216static struct resource scif3_resources[] = {
217 DEFINE_RES_MEM(0xfe480000, 0x100),
218 DEFINE_RES_IRQ(evt2irq(0xc00)),
219 DEFINE_RES_IRQ(evt2irq(0xc20)),
220 DEFINE_RES_IRQ(evt2irq(0xc40)),
221};
222
205static struct platform_device scif3_device = { 223static struct platform_device scif3_device = {
206 .name = "sh-sci", 224 .name = "sh-sci",
207 .id = 3, 225 .id = 3,
226 .resource = scif3_resources,
227 .num_resources = ARRAY_SIZE(scif3_resources),
208 .dev = { 228 .dev = {
209 .platform_data = &scif3_platform_data, 229 .platform_data = &scif3_platform_data,
210 }, 230 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index b91ea8300a3e..8b45f672448d 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -18,68 +18,88 @@
18 18
19/* Serial */ 19/* Serial */
20static struct plat_sci_port scif0_platform_data = { 20static struct plat_sci_port scif0_platform_data = {
21 .mapbase = 0xffe00000,
22 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
24 .scbrr_algo_id = SCBRR_ALGO_2, 23 .scbrr_algo_id = SCBRR_ALGO_2,
25 .type = PORT_SCIF, 24 .type = PORT_SCIF,
26 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), 25};
26
27static struct resource scif0_resources[] = {
28 DEFINE_RES_MEM(0xffe00000, 0x100),
29 DEFINE_RES_IRQ(evt2irq(0xc00)),
27}; 30};
28 31
29static struct platform_device scif0_device = { 32static struct platform_device scif0_device = {
30 .name = "sh-sci", 33 .name = "sh-sci",
31 .id = 0, 34 .id = 0,
35 .resource = scif0_resources,
36 .num_resources = ARRAY_SIZE(scif0_resources),
32 .dev = { 37 .dev = {
33 .platform_data = &scif0_platform_data, 38 .platform_data = &scif0_platform_data,
34 }, 39 },
35}; 40};
36 41
37static struct plat_sci_port scif1_platform_data = { 42static struct plat_sci_port scif1_platform_data = {
38 .mapbase = 0xffe10000,
39 .flags = UPF_BOOT_AUTOCONF, 43 .flags = UPF_BOOT_AUTOCONF,
40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 44 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
41 .scbrr_algo_id = SCBRR_ALGO_2, 45 .scbrr_algo_id = SCBRR_ALGO_2,
42 .type = PORT_SCIF, 46 .type = PORT_SCIF,
43 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), 47};
48
49static struct resource scif1_resources[] = {
50 DEFINE_RES_MEM(0xffe10000, 0x100),
51 DEFINE_RES_IRQ(evt2irq(0xc20)),
44}; 52};
45 53
46static struct platform_device scif1_device = { 54static struct platform_device scif1_device = {
47 .name = "sh-sci", 55 .name = "sh-sci",
48 .id = 1, 56 .id = 1,
57 .resource = scif1_resources,
58 .num_resources = ARRAY_SIZE(scif1_resources),
49 .dev = { 59 .dev = {
50 .platform_data = &scif1_platform_data, 60 .platform_data = &scif1_platform_data,
51 }, 61 },
52}; 62};
53 63
54static struct plat_sci_port scif2_platform_data = { 64static struct plat_sci_port scif2_platform_data = {
55 .mapbase = 0xffe20000,
56 .flags = UPF_BOOT_AUTOCONF, 65 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
58 .scbrr_algo_id = SCBRR_ALGO_2, 67 .scbrr_algo_id = SCBRR_ALGO_2,
59 .type = PORT_SCIF, 68 .type = PORT_SCIF,
60 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), 69};
70
71static struct resource scif2_resources[] = {
72 DEFINE_RES_MEM(0xffe20000, 0x100),
73 DEFINE_RES_IRQ(evt2irq(0xc40)),
61}; 74};
62 75
63static struct platform_device scif2_device = { 76static struct platform_device scif2_device = {
64 .name = "sh-sci", 77 .name = "sh-sci",
65 .id = 2, 78 .id = 2,
79 .resource = scif2_resources,
80 .num_resources = ARRAY_SIZE(scif2_resources),
66 .dev = { 81 .dev = {
67 .platform_data = &scif2_platform_data, 82 .platform_data = &scif2_platform_data,
68 }, 83 },
69}; 84};
70 85
71static struct plat_sci_port scif3_platform_data = { 86static struct plat_sci_port scif3_platform_data = {
72 .mapbase = 0xffe30000,
73 .flags = UPF_BOOT_AUTOCONF, 87 .flags = UPF_BOOT_AUTOCONF,
74 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 88 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
75 .scbrr_algo_id = SCBRR_ALGO_2, 89 .scbrr_algo_id = SCBRR_ALGO_2,
76 .type = PORT_SCIF, 90 .type = PORT_SCIF,
77 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc60)), 91};
92
93static struct resource scif3_resources[] = {
94 DEFINE_RES_MEM(0xffe30000, 0x100),
95 DEFINE_RES_IRQ(evt2irq(0xc60)),
78}; 96};
79 97
80static struct platform_device scif3_device = { 98static struct platform_device scif3_device = {
81 .name = "sh-sci", 99 .name = "sh-sci",
82 .id = 3, 100 .id = 3,
101 .resource = scif3_resources,
102 .num_resources = ARRAY_SIZE(scif3_resources),
83 .dev = { 103 .dev = {
84 .platform_data = &scif3_platform_data, 104 .platform_data = &scif3_platform_data,
85 }, 105 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 0bd09d51419f..317f710a5b2b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -20,18 +20,23 @@
20#include <asm/clock.h> 20#include <asm/clock.h>
21 21
22static struct plat_sci_port scif0_platform_data = { 22static struct plat_sci_port scif0_platform_data = {
23 .mapbase = 0xffe00000,
24 .port_reg = 0xa405013e, 23 .port_reg = 0xa405013e,
25 .flags = UPF_BOOT_AUTOCONF, 24 .flags = UPF_BOOT_AUTOCONF,
26 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
27 .scbrr_algo_id = SCBRR_ALGO_2, 26 .scbrr_algo_id = SCBRR_ALGO_2,
28 .type = PORT_SCIF, 27 .type = PORT_SCIF,
29 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), 28};
29
30static struct resource scif0_resources[] = {
31 DEFINE_RES_MEM(0xffe00000, 0x100),
32 DEFINE_RES_IRQ(evt2irq(0xc00)),
30}; 33};
31 34
32static struct platform_device scif0_device = { 35static struct platform_device scif0_device = {
33 .name = "sh-sci", 36 .name = "sh-sci",
34 .id = 0, 37 .id = 0,
38 .resource = scif0_resources,
39 .num_resources = ARRAY_SIZE(scif0_resources),
35 .dev = { 40 .dev = {
36 .platform_data = &scif0_platform_data, 41 .platform_data = &scif0_platform_data,
37 }, 42 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 6a868b091c2d..6aeebb5299f6 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -179,57 +179,72 @@ struct platform_device dma_device = {
179 179
180/* Serial */ 180/* Serial */
181static struct plat_sci_port scif0_platform_data = { 181static struct plat_sci_port scif0_platform_data = {
182 .mapbase = 0xffe00000,
183 .flags = UPF_BOOT_AUTOCONF, 182 .flags = UPF_BOOT_AUTOCONF,
184 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
185 .scbrr_algo_id = SCBRR_ALGO_2, 184 .scbrr_algo_id = SCBRR_ALGO_2,
186 .type = PORT_SCIF, 185 .type = PORT_SCIF,
187 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
188 .ops = &sh7722_sci_port_ops, 186 .ops = &sh7722_sci_port_ops,
189 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 187 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
190}; 188};
191 189
190static struct resource scif0_resources[] = {
191 DEFINE_RES_MEM(0xffe00000, 0x100),
192 DEFINE_RES_IRQ(evt2irq(0xc00)),
193};
194
192static struct platform_device scif0_device = { 195static struct platform_device scif0_device = {
193 .name = "sh-sci", 196 .name = "sh-sci",
194 .id = 0, 197 .id = 0,
198 .resource = scif0_resources,
199 .num_resources = ARRAY_SIZE(scif0_resources),
195 .dev = { 200 .dev = {
196 .platform_data = &scif0_platform_data, 201 .platform_data = &scif0_platform_data,
197 }, 202 },
198}; 203};
199 204
200static struct plat_sci_port scif1_platform_data = { 205static struct plat_sci_port scif1_platform_data = {
201 .mapbase = 0xffe10000,
202 .flags = UPF_BOOT_AUTOCONF, 206 .flags = UPF_BOOT_AUTOCONF,
203 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 207 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
204 .scbrr_algo_id = SCBRR_ALGO_2, 208 .scbrr_algo_id = SCBRR_ALGO_2,
205 .type = PORT_SCIF, 209 .type = PORT_SCIF,
206 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
207 .ops = &sh7722_sci_port_ops, 210 .ops = &sh7722_sci_port_ops,
208 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 211 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
209}; 212};
210 213
214static struct resource scif1_resources[] = {
215 DEFINE_RES_MEM(0xffe10000, 0x100),
216 DEFINE_RES_IRQ(evt2irq(0xc20)),
217};
218
211static struct platform_device scif1_device = { 219static struct platform_device scif1_device = {
212 .name = "sh-sci", 220 .name = "sh-sci",
213 .id = 1, 221 .id = 1,
222 .resource = scif1_resources,
223 .num_resources = ARRAY_SIZE(scif1_resources),
214 .dev = { 224 .dev = {
215 .platform_data = &scif1_platform_data, 225 .platform_data = &scif1_platform_data,
216 }, 226 },
217}; 227};
218 228
219static struct plat_sci_port scif2_platform_data = { 229static struct plat_sci_port scif2_platform_data = {
220 .mapbase = 0xffe20000,
221 .flags = UPF_BOOT_AUTOCONF, 230 .flags = UPF_BOOT_AUTOCONF,
222 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 231 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
223 .scbrr_algo_id = SCBRR_ALGO_2, 232 .scbrr_algo_id = SCBRR_ALGO_2,
224 .type = PORT_SCIF, 233 .type = PORT_SCIF,
225 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
226 .ops = &sh7722_sci_port_ops, 234 .ops = &sh7722_sci_port_ops,
227 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 235 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
228}; 236};
229 237
238static struct resource scif2_resources[] = {
239 DEFINE_RES_MEM(0xffe20000, 0x100),
240 DEFINE_RES_IRQ(evt2irq(0xc40)),
241};
242
230static struct platform_device scif2_device = { 243static struct platform_device scif2_device = {
231 .name = "sh-sci", 244 .name = "sh-sci",
232 .id = 2, 245 .id = 2,
246 .resource = scif2_resources,
247 .num_resources = ARRAY_SIZE(scif2_resources),
233 .dev = { 248 .dev = {
234 .platform_data = &scif2_platform_data, 249 .platform_data = &scif2_platform_data,
235 }, 250 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 28d6fd835fe0..521a09ef4ffe 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -23,111 +23,141 @@
23 23
24/* Serial */ 24/* Serial */
25static struct plat_sci_port scif0_platform_data = { 25static struct plat_sci_port scif0_platform_data = {
26 .mapbase = 0xffe00000,
27 .port_reg = 0xa4050160, 26 .port_reg = 0xa4050160,
28 .flags = UPF_BOOT_AUTOCONF, 27 .flags = UPF_BOOT_AUTOCONF,
29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
30 .scbrr_algo_id = SCBRR_ALGO_2, 29 .scbrr_algo_id = SCBRR_ALGO_2,
31 .type = PORT_SCIF, 30 .type = PORT_SCIF,
32 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
33 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 31 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
34}; 32};
35 33
34static struct resource scif0_resources[] = {
35 DEFINE_RES_MEM(0xffe00000, 0x100),
36 DEFINE_RES_IRQ(evt2irq(0xc00)),
37};
38
36static struct platform_device scif0_device = { 39static struct platform_device scif0_device = {
37 .name = "sh-sci", 40 .name = "sh-sci",
38 .id = 0, 41 .id = 0,
42 .resource = scif0_resources,
43 .num_resources = ARRAY_SIZE(scif0_resources),
39 .dev = { 44 .dev = {
40 .platform_data = &scif0_platform_data, 45 .platform_data = &scif0_platform_data,
41 }, 46 },
42}; 47};
43 48
44static struct plat_sci_port scif1_platform_data = { 49static struct plat_sci_port scif1_platform_data = {
45 .mapbase = 0xffe10000,
46 .port_reg = SCIx_NOT_SUPPORTED, 50 .port_reg = SCIx_NOT_SUPPORTED,
47 .flags = UPF_BOOT_AUTOCONF, 51 .flags = UPF_BOOT_AUTOCONF,
48 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 52 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
49 .scbrr_algo_id = SCBRR_ALGO_2, 53 .scbrr_algo_id = SCBRR_ALGO_2,
50 .type = PORT_SCIF, 54 .type = PORT_SCIF,
51 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
52 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 55 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
53}; 56};
54 57
58static struct resource scif1_resources[] = {
59 DEFINE_RES_MEM(0xffe10000, 0x100),
60 DEFINE_RES_IRQ(evt2irq(0xc20)),
61};
62
55static struct platform_device scif1_device = { 63static struct platform_device scif1_device = {
56 .name = "sh-sci", 64 .name = "sh-sci",
57 .id = 1, 65 .id = 1,
66 .resource = scif1_resources,
67 .num_resources = ARRAY_SIZE(scif1_resources),
58 .dev = { 68 .dev = {
59 .platform_data = &scif1_platform_data, 69 .platform_data = &scif1_platform_data,
60 }, 70 },
61}; 71};
62 72
63static struct plat_sci_port scif2_platform_data = { 73static struct plat_sci_port scif2_platform_data = {
64 .mapbase = 0xffe20000,
65 .port_reg = SCIx_NOT_SUPPORTED, 74 .port_reg = SCIx_NOT_SUPPORTED,
66 .flags = UPF_BOOT_AUTOCONF, 75 .flags = UPF_BOOT_AUTOCONF,
67 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 76 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
68 .scbrr_algo_id = SCBRR_ALGO_2, 77 .scbrr_algo_id = SCBRR_ALGO_2,
69 .type = PORT_SCIF, 78 .type = PORT_SCIF,
70 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
71 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 79 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
72}; 80};
73 81
82static struct resource scif2_resources[] = {
83 DEFINE_RES_MEM(0xffe20000, 0x100),
84 DEFINE_RES_IRQ(evt2irq(0xc40)),
85};
86
74static struct platform_device scif2_device = { 87static struct platform_device scif2_device = {
75 .name = "sh-sci", 88 .name = "sh-sci",
76 .id = 2, 89 .id = 2,
90 .resource = scif2_resources,
91 .num_resources = ARRAY_SIZE(scif2_resources),
77 .dev = { 92 .dev = {
78 .platform_data = &scif2_platform_data, 93 .platform_data = &scif2_platform_data,
79 }, 94 },
80}; 95};
81 96
82static struct plat_sci_port scif3_platform_data = { 97static struct plat_sci_port scif3_platform_data = {
83 .mapbase = 0xa4e30000,
84 .flags = UPF_BOOT_AUTOCONF, 98 .flags = UPF_BOOT_AUTOCONF,
85 .port_reg = SCIx_NOT_SUPPORTED, 99 .port_reg = SCIx_NOT_SUPPORTED,
86 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 100 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
87 .scbrr_algo_id = SCBRR_ALGO_3, 101 .scbrr_algo_id = SCBRR_ALGO_3,
88 .type = PORT_SCIFA, 102 .type = PORT_SCIFA,
89 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), 103};
104
105static struct resource scif3_resources[] = {
106 DEFINE_RES_MEM(0xa4e30000, 0x100),
107 DEFINE_RES_IRQ(evt2irq(0x900)),
90}; 108};
91 109
92static struct platform_device scif3_device = { 110static struct platform_device scif3_device = {
93 .name = "sh-sci", 111 .name = "sh-sci",
94 .id = 3, 112 .id = 3,
113 .resource = scif3_resources,
114 .num_resources = ARRAY_SIZE(scif3_resources),
95 .dev = { 115 .dev = {
96 .platform_data = &scif3_platform_data, 116 .platform_data = &scif3_platform_data,
97 }, 117 },
98}; 118};
99 119
100static struct plat_sci_port scif4_platform_data = { 120static struct plat_sci_port scif4_platform_data = {
101 .mapbase = 0xa4e40000,
102 .port_reg = SCIx_NOT_SUPPORTED, 121 .port_reg = SCIx_NOT_SUPPORTED,
103 .flags = UPF_BOOT_AUTOCONF, 122 .flags = UPF_BOOT_AUTOCONF,
104 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 123 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
105 .scbrr_algo_id = SCBRR_ALGO_3, 124 .scbrr_algo_id = SCBRR_ALGO_3,
106 .type = PORT_SCIFA, 125 .type = PORT_SCIFA,
107 .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), 126};
127
128static struct resource scif4_resources[] = {
129 DEFINE_RES_MEM(0xa4e40000, 0x100),
130 DEFINE_RES_IRQ(evt2irq(0xd00)),
108}; 131};
109 132
110static struct platform_device scif4_device = { 133static struct platform_device scif4_device = {
111 .name = "sh-sci", 134 .name = "sh-sci",
112 .id = 4, 135 .id = 4,
136 .resource = scif4_resources,
137 .num_resources = ARRAY_SIZE(scif4_resources),
113 .dev = { 138 .dev = {
114 .platform_data = &scif4_platform_data, 139 .platform_data = &scif4_platform_data,
115 }, 140 },
116}; 141};
117 142
118static struct plat_sci_port scif5_platform_data = { 143static struct plat_sci_port scif5_platform_data = {
119 .mapbase = 0xa4e50000,
120 .port_reg = SCIx_NOT_SUPPORTED, 144 .port_reg = SCIx_NOT_SUPPORTED,
121 .flags = UPF_BOOT_AUTOCONF, 145 .flags = UPF_BOOT_AUTOCONF,
122 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 146 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
123 .scbrr_algo_id = SCBRR_ALGO_3, 147 .scbrr_algo_id = SCBRR_ALGO_3,
124 .type = PORT_SCIFA, 148 .type = PORT_SCIFA,
125 .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), 149};
150
151static struct resource scif5_resources[] = {
152 DEFINE_RES_MEM(0xa4e50000, 0x100),
153 DEFINE_RES_IRQ(evt2irq(0xfa0)),
126}; 154};
127 155
128static struct platform_device scif5_device = { 156static struct platform_device scif5_device = {
129 .name = "sh-sci", 157 .name = "sh-sci",
130 .id = 5, 158 .id = 5,
159 .resource = scif5_resources,
160 .num_resources = ARRAY_SIZE(scif5_resources),
131 .dev = { 161 .dev = {
132 .platform_data = &scif5_platform_data, 162 .platform_data = &scif5_platform_data,
133 }, 163 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 26b74c2f9496..fb0a23749147 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -290,111 +290,141 @@ static struct platform_device dma1_device = {
290 290
291/* Serial */ 291/* Serial */
292static struct plat_sci_port scif0_platform_data = { 292static struct plat_sci_port scif0_platform_data = {
293 .mapbase = 0xffe00000,
294 .port_reg = SCIx_NOT_SUPPORTED, 293 .port_reg = SCIx_NOT_SUPPORTED,
295 .flags = UPF_BOOT_AUTOCONF, 294 .flags = UPF_BOOT_AUTOCONF,
296 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 295 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
297 .scbrr_algo_id = SCBRR_ALGO_2, 296 .scbrr_algo_id = SCBRR_ALGO_2,
298 .type = PORT_SCIF, 297 .type = PORT_SCIF,
299 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
300 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 298 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
301}; 299};
302 300
301static struct resource scif0_resources[] = {
302 DEFINE_RES_MEM(0xffe00000, 0x100),
303 DEFINE_RES_IRQ(evt2irq(0xc00)),
304};
305
303static struct platform_device scif0_device = { 306static struct platform_device scif0_device = {
304 .name = "sh-sci", 307 .name = "sh-sci",
305 .id = 0, 308 .id = 0,
309 .resource = scif0_resources,
310 .num_resources = ARRAY_SIZE(scif0_resources),
306 .dev = { 311 .dev = {
307 .platform_data = &scif0_platform_data, 312 .platform_data = &scif0_platform_data,
308 }, 313 },
309}; 314};
310 315
311static struct plat_sci_port scif1_platform_data = { 316static struct plat_sci_port scif1_platform_data = {
312 .mapbase = 0xffe10000,
313 .port_reg = SCIx_NOT_SUPPORTED, 317 .port_reg = SCIx_NOT_SUPPORTED,
314 .flags = UPF_BOOT_AUTOCONF, 318 .flags = UPF_BOOT_AUTOCONF,
315 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 319 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
316 .scbrr_algo_id = SCBRR_ALGO_2, 320 .scbrr_algo_id = SCBRR_ALGO_2,
317 .type = PORT_SCIF, 321 .type = PORT_SCIF,
318 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)),
319 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 322 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
320}; 323};
321 324
325static struct resource scif1_resources[] = {
326 DEFINE_RES_MEM(0xffe10000, 0x100),
327 DEFINE_RES_IRQ(evt2irq(0xc20)),
328};
329
322static struct platform_device scif1_device = { 330static struct platform_device scif1_device = {
323 .name = "sh-sci", 331 .name = "sh-sci",
324 .id = 1, 332 .id = 1,
333 .resource = scif1_resources,
334 .num_resources = ARRAY_SIZE(scif1_resources),
325 .dev = { 335 .dev = {
326 .platform_data = &scif1_platform_data, 336 .platform_data = &scif1_platform_data,
327 }, 337 },
328}; 338};
329 339
330static struct plat_sci_port scif2_platform_data = { 340static struct plat_sci_port scif2_platform_data = {
331 .mapbase = 0xffe20000,
332 .port_reg = SCIx_NOT_SUPPORTED, 341 .port_reg = SCIx_NOT_SUPPORTED,
333 .flags = UPF_BOOT_AUTOCONF, 342 .flags = UPF_BOOT_AUTOCONF,
334 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 343 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
335 .scbrr_algo_id = SCBRR_ALGO_2, 344 .scbrr_algo_id = SCBRR_ALGO_2,
336 .type = PORT_SCIF, 345 .type = PORT_SCIF,
337 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)),
338 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, 346 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
339}; 347};
340 348
349static struct resource scif2_resources[] = {
350 DEFINE_RES_MEM(0xffe20000, 0x100),
351 DEFINE_RES_IRQ(evt2irq(0xc40)),
352};
353
341static struct platform_device scif2_device = { 354static struct platform_device scif2_device = {
342 .name = "sh-sci", 355 .name = "sh-sci",
343 .id = 2, 356 .id = 2,
357 .resource = scif2_resources,
358 .num_resources = ARRAY_SIZE(scif2_resources),
344 .dev = { 359 .dev = {
345 .platform_data = &scif2_platform_data, 360 .platform_data = &scif2_platform_data,
346 }, 361 },
347}; 362};
348 363
349static struct plat_sci_port scif3_platform_data = { 364static struct plat_sci_port scif3_platform_data = {
350 .mapbase = 0xa4e30000,
351 .port_reg = SCIx_NOT_SUPPORTED, 365 .port_reg = SCIx_NOT_SUPPORTED,
352 .flags = UPF_BOOT_AUTOCONF, 366 .flags = UPF_BOOT_AUTOCONF,
353 .scscr = SCSCR_RE | SCSCR_TE, 367 .scscr = SCSCR_RE | SCSCR_TE,
354 .scbrr_algo_id = SCBRR_ALGO_3, 368 .scbrr_algo_id = SCBRR_ALGO_3,
355 .type = PORT_SCIFA, 369 .type = PORT_SCIFA,
356 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), 370};
371
372static struct resource scif3_resources[] = {
373 DEFINE_RES_MEM(0xa4e30000, 0x100),
374 DEFINE_RES_IRQ(evt2irq(0x900)),
357}; 375};
358 376
359static struct platform_device scif3_device = { 377static struct platform_device scif3_device = {
360 .name = "sh-sci", 378 .name = "sh-sci",
361 .id = 3, 379 .id = 3,
380 .resource = scif3_resources,
381 .num_resources = ARRAY_SIZE(scif3_resources),
362 .dev = { 382 .dev = {
363 .platform_data = &scif3_platform_data, 383 .platform_data = &scif3_platform_data,
364 }, 384 },
365}; 385};
366 386
367static struct plat_sci_port scif4_platform_data = { 387static struct plat_sci_port scif4_platform_data = {
368 .mapbase = 0xa4e40000,
369 .port_reg = SCIx_NOT_SUPPORTED, 388 .port_reg = SCIx_NOT_SUPPORTED,
370 .flags = UPF_BOOT_AUTOCONF, 389 .flags = UPF_BOOT_AUTOCONF,
371 .scscr = SCSCR_RE | SCSCR_TE, 390 .scscr = SCSCR_RE | SCSCR_TE,
372 .scbrr_algo_id = SCBRR_ALGO_3, 391 .scbrr_algo_id = SCBRR_ALGO_3,
373 .type = PORT_SCIFA, 392 .type = PORT_SCIFA,
374 .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), 393};
394
395static struct resource scif4_resources[] = {
396 DEFINE_RES_MEM(0xa4e40000, 0x100),
397 DEFINE_RES_IRQ(evt2irq(0xd00)),
375}; 398};
376 399
377static struct platform_device scif4_device = { 400static struct platform_device scif4_device = {
378 .name = "sh-sci", 401 .name = "sh-sci",
379 .id = 4, 402 .id = 4,
403 .resource = scif4_resources,
404 .num_resources = ARRAY_SIZE(scif4_resources),
380 .dev = { 405 .dev = {
381 .platform_data = &scif4_platform_data, 406 .platform_data = &scif4_platform_data,
382 }, 407 },
383}; 408};
384 409
385static struct plat_sci_port scif5_platform_data = { 410static struct plat_sci_port scif5_platform_data = {
386 .mapbase = 0xa4e50000,
387 .port_reg = SCIx_NOT_SUPPORTED, 411 .port_reg = SCIx_NOT_SUPPORTED,
388 .flags = UPF_BOOT_AUTOCONF, 412 .flags = UPF_BOOT_AUTOCONF,
389 .scscr = SCSCR_RE | SCSCR_TE, 413 .scscr = SCSCR_RE | SCSCR_TE,
390 .scbrr_algo_id = SCBRR_ALGO_3, 414 .scbrr_algo_id = SCBRR_ALGO_3,
391 .type = PORT_SCIFA, 415 .type = PORT_SCIFA,
392 .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), 416};
417
418static struct resource scif5_resources[] = {
419 DEFINE_RES_MEM(0xa4e50000, 0x100),
420 DEFINE_RES_IRQ(evt2irq(0xfa0)),
393}; 421};
394 422
395static struct platform_device scif5_device = { 423static struct platform_device scif5_device = {
396 .name = "sh-sci", 424 .name = "sh-sci",
397 .id = 5, 425 .id = 5,
426 .resource = scif5_resources,
427 .num_resources = ARRAY_SIZE(scif5_resources),
398 .dev = { 428 .dev = {
399 .platform_data = &scif5_platform_data, 429 .platform_data = &scif5_platform_data,
400 }, 430 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
index f799971d453c..bedf8fb5be6f 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c
@@ -25,108 +25,138 @@
25 25
26/* SCIF */ 26/* SCIF */
27static struct plat_sci_port scif0_platform_data = { 27static struct plat_sci_port scif0_platform_data = {
28 .mapbase = 0xFFE40000,
29 .flags = UPF_BOOT_AUTOCONF, 28 .flags = UPF_BOOT_AUTOCONF,
30 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
31 .scbrr_algo_id = SCBRR_ALGO_2, 30 .scbrr_algo_id = SCBRR_ALGO_2,
32 .type = PORT_SCIF, 31 .type = PORT_SCIF,
33 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8C0)),
34 .regtype = SCIx_SH4_SCIF_REGTYPE, 32 .regtype = SCIx_SH4_SCIF_REGTYPE,
35}; 33};
36 34
35static struct resource scif0_resources[] = {
36 DEFINE_RES_MEM(0xffe40000, 0x100),
37 DEFINE_RES_IRQ(evt2irq(0x8c0)),
38};
39
37static struct platform_device scif0_device = { 40static struct platform_device scif0_device = {
38 .name = "sh-sci", 41 .name = "sh-sci",
39 .id = 0, 42 .id = 0,
43 .resource = scif0_resources,
44 .num_resources = ARRAY_SIZE(scif0_resources),
40 .dev = { 45 .dev = {
41 .platform_data = &scif0_platform_data, 46 .platform_data = &scif0_platform_data,
42 }, 47 },
43}; 48};
44 49
45static struct plat_sci_port scif1_platform_data = { 50static struct plat_sci_port scif1_platform_data = {
46 .mapbase = 0xFFE41000,
47 .flags = UPF_BOOT_AUTOCONF, 51 .flags = UPF_BOOT_AUTOCONF,
48 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 52 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
49 .scbrr_algo_id = SCBRR_ALGO_2, 53 .scbrr_algo_id = SCBRR_ALGO_2,
50 .type = PORT_SCIF, 54 .type = PORT_SCIF,
51 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8E0)),
52 .regtype = SCIx_SH4_SCIF_REGTYPE, 55 .regtype = SCIx_SH4_SCIF_REGTYPE,
53}; 56};
54 57
58static struct resource scif1_resources[] = {
59 DEFINE_RES_MEM(0xffe41000, 0x100),
60 DEFINE_RES_IRQ(evt2irq(0x8e0)),
61};
62
55static struct platform_device scif1_device = { 63static struct platform_device scif1_device = {
56 .name = "sh-sci", 64 .name = "sh-sci",
57 .id = 1, 65 .id = 1,
66 .resource = scif1_resources,
67 .num_resources = ARRAY_SIZE(scif1_resources),
58 .dev = { 68 .dev = {
59 .platform_data = &scif1_platform_data, 69 .platform_data = &scif1_platform_data,
60 }, 70 },
61}; 71};
62 72
63static struct plat_sci_port scif2_platform_data = { 73static struct plat_sci_port scif2_platform_data = {
64 .mapbase = 0xFFE42000,
65 .flags = UPF_BOOT_AUTOCONF, 74 .flags = UPF_BOOT_AUTOCONF,
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 75 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
67 .scbrr_algo_id = SCBRR_ALGO_2, 76 .scbrr_algo_id = SCBRR_ALGO_2,
68 .type = PORT_SCIF, 77 .type = PORT_SCIF,
69 .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)),
70 .regtype = SCIx_SH4_SCIF_REGTYPE, 78 .regtype = SCIx_SH4_SCIF_REGTYPE,
71}; 79};
72 80
81static struct resource scif2_resources[] = {
82 DEFINE_RES_MEM(0xffe42000, 0x100),
83 DEFINE_RES_IRQ(evt2irq(0x900)),
84};
85
73static struct platform_device scif2_device = { 86static struct platform_device scif2_device = {
74 .name = "sh-sci", 87 .name = "sh-sci",
75 .id = 2, 88 .id = 2,
89 .resource = scif2_resources,
90 .num_resources = ARRAY_SIZE(scif2_resources),
76 .dev = { 91 .dev = {
77 .platform_data = &scif2_platform_data, 92 .platform_data = &scif2_platform_data,
78 }, 93 },
79}; 94};
80 95
81static struct plat_sci_port scif3_platform_data = { 96static struct plat_sci_port scif3_platform_data = {
82 .mapbase = 0xFFE43000,
83 .flags = UPF_BOOT_AUTOCONF, 97 .flags = UPF_BOOT_AUTOCONF,
84 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 98 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
85 .scbrr_algo_id = SCBRR_ALGO_2, 99 .scbrr_algo_id = SCBRR_ALGO_2,
86 .type = PORT_SCIF, 100 .type = PORT_SCIF,
87 .irqs = SCIx_IRQ_MUXED(evt2irq(0x920)),
88 .regtype = SCIx_SH4_SCIF_REGTYPE, 101 .regtype = SCIx_SH4_SCIF_REGTYPE,
89}; 102};
90 103
104static struct resource scif3_resources[] = {
105 DEFINE_RES_MEM(0xffe43000, 0x100),
106 DEFINE_RES_IRQ(evt2irq(0x920)),
107};
108
91static struct platform_device scif3_device = { 109static struct platform_device scif3_device = {
92 .name = "sh-sci", 110 .name = "sh-sci",
93 .id = 3, 111 .id = 3,
112 .resource = scif3_resources,
113 .num_resources = ARRAY_SIZE(scif3_resources),
94 .dev = { 114 .dev = {
95 .platform_data = &scif3_platform_data, 115 .platform_data = &scif3_platform_data,
96 }, 116 },
97}; 117};
98 118
99static struct plat_sci_port scif4_platform_data = { 119static struct plat_sci_port scif4_platform_data = {
100 .mapbase = 0xFFE44000,
101 .flags = UPF_BOOT_AUTOCONF, 120 .flags = UPF_BOOT_AUTOCONF,
102 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 121 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
103 .scbrr_algo_id = SCBRR_ALGO_2, 122 .scbrr_algo_id = SCBRR_ALGO_2,
104 .type = PORT_SCIF, 123 .type = PORT_SCIF,
105 .irqs = SCIx_IRQ_MUXED(evt2irq(0x940)),
106 .regtype = SCIx_SH4_SCIF_REGTYPE, 124 .regtype = SCIx_SH4_SCIF_REGTYPE,
107}; 125};
108 126
127static struct resource scif4_resources[] = {
128 DEFINE_RES_MEM(0xffe44000, 0x100),
129 DEFINE_RES_IRQ(evt2irq(0x940)),
130};
131
109static struct platform_device scif4_device = { 132static struct platform_device scif4_device = {
110 .name = "sh-sci", 133 .name = "sh-sci",
111 .id = 4, 134 .id = 4,
135 .resource = scif4_resources,
136 .num_resources = ARRAY_SIZE(scif4_resources),
112 .dev = { 137 .dev = {
113 .platform_data = &scif4_platform_data, 138 .platform_data = &scif4_platform_data,
114 }, 139 },
115}; 140};
116 141
117static struct plat_sci_port scif5_platform_data = { 142static struct plat_sci_port scif5_platform_data = {
118 .mapbase = 0xFFE43000,
119 .flags = UPF_BOOT_AUTOCONF, 143 .flags = UPF_BOOT_AUTOCONF,
120 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 144 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
121 .scbrr_algo_id = SCBRR_ALGO_2, 145 .scbrr_algo_id = SCBRR_ALGO_2,
122 .type = PORT_SCIF, 146 .type = PORT_SCIF,
123 .irqs = SCIx_IRQ_MUXED(evt2irq(0x960)),
124 .regtype = SCIx_SH4_SCIF_REGTYPE, 147 .regtype = SCIx_SH4_SCIF_REGTYPE,
125}; 148};
126 149
150static struct resource scif5_resources[] = {
151 DEFINE_RES_MEM(0xffe43000, 0x100),
152 DEFINE_RES_IRQ(evt2irq(0x960)),
153};
154
127static struct platform_device scif5_device = { 155static struct platform_device scif5_device = {
128 .name = "sh-sci", 156 .name = "sh-sci",
129 .id = 5, 157 .id = 5,
158 .resource = scif5_resources,
159 .num_resources = ARRAY_SIZE(scif5_resources),
130 .dev = { 160 .dev = {
131 .platform_data = &scif5_platform_data, 161 .platform_data = &scif5_platform_data,
132 }, 162 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 9079a0f9ea9b..6b8d0e61704c 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -24,51 +24,66 @@
24#include <cpu/sh7757.h> 24#include <cpu/sh7757.h>
25 25
26static struct plat_sci_port scif2_platform_data = { 26static struct plat_sci_port scif2_platform_data = {
27 .mapbase = 0xfe4b0000, /* SCIF2 */
28 .flags = UPF_BOOT_AUTOCONF, 27 .flags = UPF_BOOT_AUTOCONF,
29 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
30 .scbrr_algo_id = SCBRR_ALGO_2, 29 .scbrr_algo_id = SCBRR_ALGO_2,
31 .type = PORT_SCIF, 30 .type = PORT_SCIF,
32 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), 31};
32
33static struct resource scif2_resources[] = {
34 DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */
35 DEFINE_RES_IRQ(evt2irq(0x700)),
33}; 36};
34 37
35static struct platform_device scif2_device = { 38static struct platform_device scif2_device = {
36 .name = "sh-sci", 39 .name = "sh-sci",
37 .id = 0, 40 .id = 0,
41 .resource = scif2_resources,
42 .num_resources = ARRAY_SIZE(scif2_resources),
38 .dev = { 43 .dev = {
39 .platform_data = &scif2_platform_data, 44 .platform_data = &scif2_platform_data,
40 }, 45 },
41}; 46};
42 47
43static struct plat_sci_port scif3_platform_data = { 48static struct plat_sci_port scif3_platform_data = {
44 .mapbase = 0xfe4c0000, /* SCIF3 */
45 .flags = UPF_BOOT_AUTOCONF, 49 .flags = UPF_BOOT_AUTOCONF,
46 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 50 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
47 .scbrr_algo_id = SCBRR_ALGO_2, 51 .scbrr_algo_id = SCBRR_ALGO_2,
48 .type = PORT_SCIF, 52 .type = PORT_SCIF,
49 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), 53};
54
55static struct resource scif3_resources[] = {
56 DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */
57 DEFINE_RES_IRQ(evt2irq(0xb80)),
50}; 58};
51 59
52static struct platform_device scif3_device = { 60static struct platform_device scif3_device = {
53 .name = "sh-sci", 61 .name = "sh-sci",
54 .id = 1, 62 .id = 1,
63 .resource = scif3_resources,
64 .num_resources = ARRAY_SIZE(scif3_resources),
55 .dev = { 65 .dev = {
56 .platform_data = &scif3_platform_data, 66 .platform_data = &scif3_platform_data,
57 }, 67 },
58}; 68};
59 69
60static struct plat_sci_port scif4_platform_data = { 70static struct plat_sci_port scif4_platform_data = {
61 .mapbase = 0xfe4d0000, /* SCIF4 */
62 .flags = UPF_BOOT_AUTOCONF, 71 .flags = UPF_BOOT_AUTOCONF,
63 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 72 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
64 .scbrr_algo_id = SCBRR_ALGO_2, 73 .scbrr_algo_id = SCBRR_ALGO_2,
65 .type = PORT_SCIF, 74 .type = PORT_SCIF,
66 .irqs = SCIx_IRQ_MUXED(evt2irq(0xF00)), 75};
76
77static struct resource scif4_resources[] = {
78 DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */
79 DEFINE_RES_IRQ(evt2irq(0xf00)),
67}; 80};
68 81
69static struct platform_device scif4_device = { 82static struct platform_device scif4_device = {
70 .name = "sh-sci", 83 .name = "sh-sci",
71 .id = 2, 84 .id = 2,
85 .resource = scif4_resources,
86 .num_resources = ARRAY_SIZE(scif4_resources),
72 .dev = { 87 .dev = {
73 .platform_data = &scif4_platform_data, 88 .platform_data = &scif4_platform_data,
74 }, 89 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 1686acaaf45a..940505cec66f 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -19,54 +19,69 @@
19#include <linux/usb/ohci_pdriver.h> 19#include <linux/usb/ohci_pdriver.h>
20 20
21static struct plat_sci_port scif0_platform_data = { 21static struct plat_sci_port scif0_platform_data = {
22 .mapbase = 0xffe00000,
23 .flags = UPF_BOOT_AUTOCONF, 22 .flags = UPF_BOOT_AUTOCONF,
24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
25 .scbrr_algo_id = SCBRR_ALGO_2, 24 .scbrr_algo_id = SCBRR_ALGO_2,
26 .type = PORT_SCIF, 25 .type = PORT_SCIF,
27 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
28 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
29}; 27};
30 28
29static struct resource scif0_resources[] = {
30 DEFINE_RES_MEM(0xffe00000, 0x100),
31 DEFINE_RES_IRQ(evt2irq(0x700)),
32};
33
31static struct platform_device scif0_device = { 34static struct platform_device scif0_device = {
32 .name = "sh-sci", 35 .name = "sh-sci",
33 .id = 0, 36 .id = 0,
37 .resource = scif0_resources,
38 .num_resources = ARRAY_SIZE(scif0_resources),
34 .dev = { 39 .dev = {
35 .platform_data = &scif0_platform_data, 40 .platform_data = &scif0_platform_data,
36 }, 41 },
37}; 42};
38 43
39static struct plat_sci_port scif1_platform_data = { 44static struct plat_sci_port scif1_platform_data = {
40 .mapbase = 0xffe08000,
41 .flags = UPF_BOOT_AUTOCONF, 45 .flags = UPF_BOOT_AUTOCONF,
42 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 46 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
43 .scbrr_algo_id = SCBRR_ALGO_2, 47 .scbrr_algo_id = SCBRR_ALGO_2,
44 .type = PORT_SCIF, 48 .type = PORT_SCIF,
45 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)),
46 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 49 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
47}; 50};
48 51
52static struct resource scif1_resources[] = {
53 DEFINE_RES_MEM(0xffe08000, 0x100),
54 DEFINE_RES_IRQ(evt2irq(0xb80)),
55};
56
49static struct platform_device scif1_device = { 57static struct platform_device scif1_device = {
50 .name = "sh-sci", 58 .name = "sh-sci",
51 .id = 1, 59 .id = 1,
60 .resource = scif1_resources,
61 .num_resources = ARRAY_SIZE(scif1_resources),
52 .dev = { 62 .dev = {
53 .platform_data = &scif1_platform_data, 63 .platform_data = &scif1_platform_data,
54 }, 64 },
55}; 65};
56 66
57static struct plat_sci_port scif2_platform_data = { 67static struct plat_sci_port scif2_platform_data = {
58 .mapbase = 0xffe10000,
59 .flags = UPF_BOOT_AUTOCONF, 68 .flags = UPF_BOOT_AUTOCONF,
60 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 69 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
61 .scbrr_algo_id = SCBRR_ALGO_2, 70 .scbrr_algo_id = SCBRR_ALGO_2,
62 .type = PORT_SCIF, 71 .type = PORT_SCIF,
63 .irqs = SCIx_IRQ_MUXED(evt2irq(0xf00)),
64 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 72 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
65}; 73};
66 74
75static struct resource scif2_resources[] = {
76 DEFINE_RES_MEM(0xffe10000, 0x100),
77 DEFINE_RES_IRQ(evt2irq(0xf00)),
78};
79
67static struct platform_device scif2_device = { 80static struct platform_device scif2_device = {
68 .name = "sh-sci", 81 .name = "sh-sci",
69 .id = 2, 82 .id = 2,
83 .resource = scif2_resources,
84 .num_resources = ARRAY_SIZE(scif2_resources),
70 .dev = { 85 .dev = {
71 .platform_data = &scif2_platform_data, 86 .platform_data = &scif2_platform_data,
72 }, 87 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 256ea7a45164..f9c04dee4e82 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -16,170 +16,220 @@
16#include <linux/io.h> 16#include <linux/io.h>
17 17
18static struct plat_sci_port scif0_platform_data = { 18static struct plat_sci_port scif0_platform_data = {
19 .mapbase = 0xff923000,
20 .flags = UPF_BOOT_AUTOCONF, 19 .flags = UPF_BOOT_AUTOCONF,
21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 20 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
22 .scbrr_algo_id = SCBRR_ALGO_2, 21 .scbrr_algo_id = SCBRR_ALGO_2,
23 .type = PORT_SCIF, 22 .type = PORT_SCIF,
24 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)), 23};
24
25static struct resource scif0_resources[] = {
26 DEFINE_RES_MEM(0xff923000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0x9a0)),
25}; 28};
26 29
27static struct platform_device scif0_device = { 30static struct platform_device scif0_device = {
28 .name = "sh-sci", 31 .name = "sh-sci",
29 .id = 0, 32 .id = 0,
33 .resource = scif0_resources,
34 .num_resources = ARRAY_SIZE(scif0_resources),
30 .dev = { 35 .dev = {
31 .platform_data = &scif0_platform_data, 36 .platform_data = &scif0_platform_data,
32 }, 37 },
33}; 38};
34 39
35static struct plat_sci_port scif1_platform_data = { 40static struct plat_sci_port scif1_platform_data = {
36 .mapbase = 0xff924000,
37 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
38 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 42 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
39 .scbrr_algo_id = SCBRR_ALGO_2, 43 .scbrr_algo_id = SCBRR_ALGO_2,
40 .type = PORT_SCIF, 44 .type = PORT_SCIF,
41 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)), 45};
46
47static struct resource scif1_resources[] = {
48 DEFINE_RES_MEM(0xff924000, 0x100),
49 DEFINE_RES_IRQ(evt2irq(0x9c0)),
42}; 50};
43 51
44static struct platform_device scif1_device = { 52static struct platform_device scif1_device = {
45 .name = "sh-sci", 53 .name = "sh-sci",
46 .id = 1, 54 .id = 1,
55 .resource = scif1_resources,
56 .num_resources = ARRAY_SIZE(scif1_resources),
47 .dev = { 57 .dev = {
48 .platform_data = &scif1_platform_data, 58 .platform_data = &scif1_platform_data,
49 }, 59 },
50}; 60};
51 61
52static struct plat_sci_port scif2_platform_data = { 62static struct plat_sci_port scif2_platform_data = {
53 .mapbase = 0xff925000,
54 .flags = UPF_BOOT_AUTOCONF, 63 .flags = UPF_BOOT_AUTOCONF,
55 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 64 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
56 .scbrr_algo_id = SCBRR_ALGO_2, 65 .scbrr_algo_id = SCBRR_ALGO_2,
57 .type = PORT_SCIF, 66 .type = PORT_SCIF,
58 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)), 67};
68
69static struct resource scif2_resources[] = {
70 DEFINE_RES_MEM(0xff925000, 0x100),
71 DEFINE_RES_IRQ(evt2irq(0x9e0)),
59}; 72};
60 73
61static struct platform_device scif2_device = { 74static struct platform_device scif2_device = {
62 .name = "sh-sci", 75 .name = "sh-sci",
63 .id = 2, 76 .id = 2,
77 .resource = scif2_resources,
78 .num_resources = ARRAY_SIZE(scif2_resources),
64 .dev = { 79 .dev = {
65 .platform_data = &scif2_platform_data, 80 .platform_data = &scif2_platform_data,
66 }, 81 },
67}; 82};
68 83
69static struct plat_sci_port scif3_platform_data = { 84static struct plat_sci_port scif3_platform_data = {
70 .mapbase = 0xff926000,
71 .flags = UPF_BOOT_AUTOCONF, 85 .flags = UPF_BOOT_AUTOCONF,
72 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 86 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
73 .scbrr_algo_id = SCBRR_ALGO_2, 87 .scbrr_algo_id = SCBRR_ALGO_2,
74 .type = PORT_SCIF, 88 .type = PORT_SCIF,
75 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa00)), 89};
90
91static struct resource scif3_resources[] = {
92 DEFINE_RES_MEM(0xff926000, 0x100),
93 DEFINE_RES_IRQ(evt2irq(0xa00)),
76}; 94};
77 95
78static struct platform_device scif3_device = { 96static struct platform_device scif3_device = {
79 .name = "sh-sci", 97 .name = "sh-sci",
80 .id = 3, 98 .id = 3,
99 .resource = scif3_resources,
100 .num_resources = ARRAY_SIZE(scif3_resources),
81 .dev = { 101 .dev = {
82 .platform_data = &scif3_platform_data, 102 .platform_data = &scif3_platform_data,
83 }, 103 },
84}; 104};
85 105
86static struct plat_sci_port scif4_platform_data = { 106static struct plat_sci_port scif4_platform_data = {
87 .mapbase = 0xff927000,
88 .flags = UPF_BOOT_AUTOCONF, 107 .flags = UPF_BOOT_AUTOCONF,
89 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 108 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
90 .scbrr_algo_id = SCBRR_ALGO_2, 109 .scbrr_algo_id = SCBRR_ALGO_2,
91 .type = PORT_SCIF, 110 .type = PORT_SCIF,
92 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa20)), 111};
112
113static struct resource scif4_resources[] = {
114 DEFINE_RES_MEM(0xff927000, 0x100),
115 DEFINE_RES_IRQ(evt2irq(0xa20)),
93}; 116};
94 117
95static struct platform_device scif4_device = { 118static struct platform_device scif4_device = {
96 .name = "sh-sci", 119 .name = "sh-sci",
97 .id = 4, 120 .id = 4,
121 .resource = scif4_resources,
122 .num_resources = ARRAY_SIZE(scif4_resources),
98 .dev = { 123 .dev = {
99 .platform_data = &scif4_platform_data, 124 .platform_data = &scif4_platform_data,
100 }, 125 },
101}; 126};
102 127
103static struct plat_sci_port scif5_platform_data = { 128static struct plat_sci_port scif5_platform_data = {
104 .mapbase = 0xff928000,
105 .flags = UPF_BOOT_AUTOCONF, 129 .flags = UPF_BOOT_AUTOCONF,
106 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 130 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
107 .scbrr_algo_id = SCBRR_ALGO_2, 131 .scbrr_algo_id = SCBRR_ALGO_2,
108 .type = PORT_SCIF, 132 .type = PORT_SCIF,
109 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa40)), 133};
134
135static struct resource scif5_resources[] = {
136 DEFINE_RES_MEM(0xff928000, 0x100),
137 DEFINE_RES_IRQ(evt2irq(0xa40)),
110}; 138};
111 139
112static struct platform_device scif5_device = { 140static struct platform_device scif5_device = {
113 .name = "sh-sci", 141 .name = "sh-sci",
114 .id = 5, 142 .id = 5,
143 .resource = scif5_resources,
144 .num_resources = ARRAY_SIZE(scif5_resources),
115 .dev = { 145 .dev = {
116 .platform_data = &scif5_platform_data, 146 .platform_data = &scif5_platform_data,
117 }, 147 },
118}; 148};
119 149
120static struct plat_sci_port scif6_platform_data = { 150static struct plat_sci_port scif6_platform_data = {
121 .mapbase = 0xff929000,
122 .flags = UPF_BOOT_AUTOCONF, 151 .flags = UPF_BOOT_AUTOCONF,
123 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 152 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
124 .scbrr_algo_id = SCBRR_ALGO_2, 153 .scbrr_algo_id = SCBRR_ALGO_2,
125 .type = PORT_SCIF, 154 .type = PORT_SCIF,
126 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa60)), 155};
156
157static struct resource scif6_resources[] = {
158 DEFINE_RES_MEM(0xff929000, 0x100),
159 DEFINE_RES_IRQ(evt2irq(0xa60)),
127}; 160};
128 161
129static struct platform_device scif6_device = { 162static struct platform_device scif6_device = {
130 .name = "sh-sci", 163 .name = "sh-sci",
131 .id = 6, 164 .id = 6,
165 .resource = scif6_resources,
166 .num_resources = ARRAY_SIZE(scif6_resources),
132 .dev = { 167 .dev = {
133 .platform_data = &scif6_platform_data, 168 .platform_data = &scif6_platform_data,
134 }, 169 },
135}; 170};
136 171
137static struct plat_sci_port scif7_platform_data = { 172static struct plat_sci_port scif7_platform_data = {
138 .mapbase = 0xff92a000,
139 .flags = UPF_BOOT_AUTOCONF, 173 .flags = UPF_BOOT_AUTOCONF,
140 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 174 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
141 .scbrr_algo_id = SCBRR_ALGO_2, 175 .scbrr_algo_id = SCBRR_ALGO_2,
142 .type = PORT_SCIF, 176 .type = PORT_SCIF,
143 .irqs = SCIx_IRQ_MUXED(evt2irq(0xa80)), 177};
178
179static struct resource scif7_resources[] = {
180 DEFINE_RES_MEM(0xff92a000, 0x100),
181 DEFINE_RES_IRQ(evt2irq(0xa80)),
144}; 182};
145 183
146static struct platform_device scif7_device = { 184static struct platform_device scif7_device = {
147 .name = "sh-sci", 185 .name = "sh-sci",
148 .id = 7, 186 .id = 7,
187 .resource = scif7_resources,
188 .num_resources = ARRAY_SIZE(scif7_resources),
149 .dev = { 189 .dev = {
150 .platform_data = &scif7_platform_data, 190 .platform_data = &scif7_platform_data,
151 }, 191 },
152}; 192};
153 193
154static struct plat_sci_port scif8_platform_data = { 194static struct plat_sci_port scif8_platform_data = {
155 .mapbase = 0xff92b000,
156 .flags = UPF_BOOT_AUTOCONF, 195 .flags = UPF_BOOT_AUTOCONF,
157 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 196 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
158 .scbrr_algo_id = SCBRR_ALGO_2, 197 .scbrr_algo_id = SCBRR_ALGO_2,
159 .type = PORT_SCIF, 198 .type = PORT_SCIF,
160 .irqs = SCIx_IRQ_MUXED(evt2irq(0xaa0)), 199};
200
201static struct resource scif8_resources[] = {
202 DEFINE_RES_MEM(0xff92b000, 0x100),
203 DEFINE_RES_IRQ(evt2irq(0xaa0)),
161}; 204};
162 205
163static struct platform_device scif8_device = { 206static struct platform_device scif8_device = {
164 .name = "sh-sci", 207 .name = "sh-sci",
165 .id = 8, 208 .id = 8,
209 .resource = scif8_resources,
210 .num_resources = ARRAY_SIZE(scif8_resources),
166 .dev = { 211 .dev = {
167 .platform_data = &scif8_platform_data, 212 .platform_data = &scif8_platform_data,
168 }, 213 },
169}; 214};
170 215
171static struct plat_sci_port scif9_platform_data = { 216static struct plat_sci_port scif9_platform_data = {
172 .mapbase = 0xff92c000,
173 .flags = UPF_BOOT_AUTOCONF, 217 .flags = UPF_BOOT_AUTOCONF,
174 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, 218 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
175 .scbrr_algo_id = SCBRR_ALGO_2, 219 .scbrr_algo_id = SCBRR_ALGO_2,
176 .type = PORT_SCIF, 220 .type = PORT_SCIF,
177 .irqs = SCIx_IRQ_MUXED(evt2irq(0xac0)), 221};
222
223static struct resource scif9_resources[] = {
224 DEFINE_RES_MEM(0xff92c000, 0x100),
225 DEFINE_RES_IRQ(evt2irq(0xac0)),
178}; 226};
179 227
180static struct platform_device scif9_device = { 228static struct platform_device scif9_device = {
181 .name = "sh-sci", 229 .name = "sh-sci",
182 .id = 9, 230 .id = 9,
231 .resource = scif9_resources,
232 .num_resources = ARRAY_SIZE(scif9_resources),
183 .dev = { 233 .dev = {
184 .platform_data = &scif9_platform_data, 234 .platform_data = &scif9_platform_data,
185 }, 235 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index de45b704687a..227f8f4080fa 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -18,36 +18,46 @@
18#include <cpu/dma-register.h> 18#include <cpu/dma-register.h>
19 19
20static struct plat_sci_port scif0_platform_data = { 20static struct plat_sci_port scif0_platform_data = {
21 .mapbase = 0xffe00000,
22 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
24 .scbrr_algo_id = SCBRR_ALGO_1, 23 .scbrr_algo_id = SCBRR_ALGO_1,
25 .type = PORT_SCIF, 24 .type = PORT_SCIF,
26 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
27 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 25 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
28}; 26};
29 27
28static struct resource scif0_resources[] = {
29 DEFINE_RES_MEM(0xffe00000, 0x100),
30 DEFINE_RES_IRQ(evt2irq(0x700)),
31};
32
30static struct platform_device scif0_device = { 33static struct platform_device scif0_device = {
31 .name = "sh-sci", 34 .name = "sh-sci",
32 .id = 0, 35 .id = 0,
36 .resource = scif0_resources,
37 .num_resources = ARRAY_SIZE(scif0_resources),
33 .dev = { 38 .dev = {
34 .platform_data = &scif0_platform_data, 39 .platform_data = &scif0_platform_data,
35 }, 40 },
36}; 41};
37 42
38static struct plat_sci_port scif1_platform_data = { 43static struct plat_sci_port scif1_platform_data = {
39 .mapbase = 0xffe10000,
40 .flags = UPF_BOOT_AUTOCONF, 44 .flags = UPF_BOOT_AUTOCONF,
41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 45 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
42 .scbrr_algo_id = SCBRR_ALGO_1, 46 .scbrr_algo_id = SCBRR_ALGO_1,
43 .type = PORT_SCIF, 47 .type = PORT_SCIF,
44 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)),
45 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 48 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
46}; 49};
47 50
51static struct resource scif1_resources[] = {
52 DEFINE_RES_MEM(0xffe10000, 0x100),
53 DEFINE_RES_IRQ(evt2irq(0xb80)),
54};
55
48static struct platform_device scif1_device = { 56static struct platform_device scif1_device = {
49 .name = "sh-sci", 57 .name = "sh-sci",
50 .id = 1, 58 .id = 1,
59 .resource = scif1_resources,
60 .num_resources = ARRAY_SIZE(scif1_resources),
51 .dev = { 61 .dev = {
52 .platform_data = &scif1_platform_data, 62 .platform_data = &scif1_platform_data,
53 }, 63 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 0968ecb962e6..b9f64c1ee895 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -20,108 +20,138 @@
20#include <cpu/dma-register.h> 20#include <cpu/dma-register.h>
21 21
22static struct plat_sci_port scif0_platform_data = { 22static struct plat_sci_port scif0_platform_data = {
23 .mapbase = 0xffea0000,
24 .flags = UPF_BOOT_AUTOCONF, 23 .flags = UPF_BOOT_AUTOCONF,
25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
26 .scbrr_algo_id = SCBRR_ALGO_1, 25 .scbrr_algo_id = SCBRR_ALGO_1,
27 .type = PORT_SCIF, 26 .type = PORT_SCIF,
28 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
29 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 27 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
30}; 28};
31 29
30static struct resource scif0_resources[] = {
31 DEFINE_RES_MEM(0xffea0000, 0x100),
32 DEFINE_RES_IRQ(evt2irq(0x700)),
33};
34
32static struct platform_device scif0_device = { 35static struct platform_device scif0_device = {
33 .name = "sh-sci", 36 .name = "sh-sci",
34 .id = 0, 37 .id = 0,
38 .resource = scif0_resources,
39 .num_resources = ARRAY_SIZE(scif0_resources),
35 .dev = { 40 .dev = {
36 .platform_data = &scif0_platform_data, 41 .platform_data = &scif0_platform_data,
37 }, 42 },
38}; 43};
39 44
40static struct plat_sci_port scif1_platform_data = { 45static struct plat_sci_port scif1_platform_data = {
41 .mapbase = 0xffeb0000,
42 .flags = UPF_BOOT_AUTOCONF, 46 .flags = UPF_BOOT_AUTOCONF,
43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 47 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
44 .scbrr_algo_id = SCBRR_ALGO_1, 48 .scbrr_algo_id = SCBRR_ALGO_1,
45 .type = PORT_SCIF, 49 .type = PORT_SCIF,
46 .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)),
47 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 50 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
48}; 51};
49 52
53static struct resource scif1_resources[] = {
54 DEFINE_RES_MEM(0xffeb0000, 0x100),
55 DEFINE_RES_IRQ(evt2irq(0x780)),
56};
57
50static struct platform_device scif1_device = { 58static struct platform_device scif1_device = {
51 .name = "sh-sci", 59 .name = "sh-sci",
52 .id = 1, 60 .id = 1,
61 .resource = scif1_resources,
62 .num_resources = ARRAY_SIZE(scif1_resources),
53 .dev = { 63 .dev = {
54 .platform_data = &scif1_platform_data, 64 .platform_data = &scif1_platform_data,
55 }, 65 },
56}; 66};
57 67
58static struct plat_sci_port scif2_platform_data = { 68static struct plat_sci_port scif2_platform_data = {
59 .mapbase = 0xffec0000,
60 .flags = UPF_BOOT_AUTOCONF, 69 .flags = UPF_BOOT_AUTOCONF,
61 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 70 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
62 .scbrr_algo_id = SCBRR_ALGO_1, 71 .scbrr_algo_id = SCBRR_ALGO_1,
63 .type = PORT_SCIF, 72 .type = PORT_SCIF,
64 .irqs = SCIx_IRQ_MUXED(evt2irq(0x980)),
65 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 73 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
66}; 74};
67 75
76static struct resource scif2_resources[] = {
77 DEFINE_RES_MEM(0xffec0000, 0x100),
78 DEFINE_RES_IRQ(evt2irq(0x980)),
79};
80
68static struct platform_device scif2_device = { 81static struct platform_device scif2_device = {
69 .name = "sh-sci", 82 .name = "sh-sci",
70 .id = 2, 83 .id = 2,
84 .resource = scif2_resources,
85 .num_resources = ARRAY_SIZE(scif2_resources),
71 .dev = { 86 .dev = {
72 .platform_data = &scif2_platform_data, 87 .platform_data = &scif2_platform_data,
73 }, 88 },
74}; 89};
75 90
76static struct plat_sci_port scif3_platform_data = { 91static struct plat_sci_port scif3_platform_data = {
77 .mapbase = 0xffed0000,
78 .flags = UPF_BOOT_AUTOCONF, 92 .flags = UPF_BOOT_AUTOCONF,
79 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 93 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
80 .scbrr_algo_id = SCBRR_ALGO_1, 94 .scbrr_algo_id = SCBRR_ALGO_1,
81 .type = PORT_SCIF, 95 .type = PORT_SCIF,
82 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)),
83 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 96 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
84}; 97};
85 98
99static struct resource scif3_resources[] = {
100 DEFINE_RES_MEM(0xffed0000, 0x100),
101 DEFINE_RES_IRQ(evt2irq(0x9a0)),
102};
103
86static struct platform_device scif3_device = { 104static struct platform_device scif3_device = {
87 .name = "sh-sci", 105 .name = "sh-sci",
88 .id = 3, 106 .id = 3,
107 .resource = scif3_resources,
108 .num_resources = ARRAY_SIZE(scif3_resources),
89 .dev = { 109 .dev = {
90 .platform_data = &scif3_platform_data, 110 .platform_data = &scif3_platform_data,
91 }, 111 },
92}; 112};
93 113
94static struct plat_sci_port scif4_platform_data = { 114static struct plat_sci_port scif4_platform_data = {
95 .mapbase = 0xffee0000,
96 .flags = UPF_BOOT_AUTOCONF, 115 .flags = UPF_BOOT_AUTOCONF,
97 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 116 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
98 .scbrr_algo_id = SCBRR_ALGO_1, 117 .scbrr_algo_id = SCBRR_ALGO_1,
99 .type = PORT_SCIF, 118 .type = PORT_SCIF,
100 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)),
101 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 119 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
102}; 120};
103 121
122static struct resource scif4_resources[] = {
123 DEFINE_RES_MEM(0xffee0000, 0x100),
124 DEFINE_RES_IRQ(evt2irq(0x9c0)),
125};
126
104static struct platform_device scif4_device = { 127static struct platform_device scif4_device = {
105 .name = "sh-sci", 128 .name = "sh-sci",
106 .id = 4, 129 .id = 4,
130 .resource = scif4_resources,
131 .num_resources = ARRAY_SIZE(scif4_resources),
107 .dev = { 132 .dev = {
108 .platform_data = &scif4_platform_data, 133 .platform_data = &scif4_platform_data,
109 }, 134 },
110}; 135};
111 136
112static struct plat_sci_port scif5_platform_data = { 137static struct plat_sci_port scif5_platform_data = {
113 .mapbase = 0xffef0000,
114 .flags = UPF_BOOT_AUTOCONF, 138 .flags = UPF_BOOT_AUTOCONF,
115 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
116 .scbrr_algo_id = SCBRR_ALGO_1, 140 .scbrr_algo_id = SCBRR_ALGO_1,
117 .type = PORT_SCIF, 141 .type = PORT_SCIF,
118 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)),
119 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 142 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
120}; 143};
121 144
145static struct resource scif5_resources[] = {
146 DEFINE_RES_MEM(0xffef0000, 0x100),
147 DEFINE_RES_IRQ(evt2irq(0x9e0)),
148};
149
122static struct platform_device scif5_device = { 150static struct platform_device scif5_device = {
123 .name = "sh-sci", 151 .name = "sh-sci",
124 .id = 5, 152 .id = 5,
153 .resource = scif5_resources,
154 .num_resources = ARRAY_SIZE(scif5_resources),
125 .dev = { 155 .dev = {
126 .platform_data = &scif5_platform_data, 156 .platform_data = &scif5_platform_data,
127 }, 157 },
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index ab52d4d4484d..92b95ceabd6e 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -28,21 +28,26 @@
28#include <asm/mmzone.h> 28#include <asm/mmzone.h>
29 29
30static struct plat_sci_port scif0_platform_data = { 30static struct plat_sci_port scif0_platform_data = {
31 .mapbase = 0xffea0000,
32 .flags = UPF_BOOT_AUTOCONF, 31 .flags = UPF_BOOT_AUTOCONF,
33 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
34 .scbrr_algo_id = SCBRR_ALGO_1, 33 .scbrr_algo_id = SCBRR_ALGO_1,
35 .type = PORT_SCIF, 34 .type = PORT_SCIF,
36 .irqs = { evt2irq(0x700),
37 evt2irq(0x720),
38 evt2irq(0x760),
39 evt2irq(0x740) },
40 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 35 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
41}; 36};
42 37
38static struct resource scif0_resources[] = {
39 DEFINE_RES_MEM(0xffea0000, 0x100),
40 DEFINE_RES_IRQ(evt2irq(0x700)),
41 DEFINE_RES_IRQ(evt2irq(0x720)),
42 DEFINE_RES_IRQ(evt2irq(0x760)),
43 DEFINE_RES_IRQ(evt2irq(0x740)),
44};
45
43static struct platform_device scif0_device = { 46static struct platform_device scif0_device = {
44 .name = "sh-sci", 47 .name = "sh-sci",
45 .id = 0, 48 .id = 0,
49 .resource = scif0_resources,
50 .num_resources = ARRAY_SIZE(scif0_resources),
46 .dev = { 51 .dev = {
47 .platform_data = &scif0_platform_data, 52 .platform_data = &scif0_platform_data,
48 }, 53 },
@@ -52,90 +57,124 @@ static struct platform_device scif0_device = {
52 * The rest of these all have multiplexed IRQs 57 * The rest of these all have multiplexed IRQs
53 */ 58 */
54static struct plat_sci_port scif1_platform_data = { 59static struct plat_sci_port scif1_platform_data = {
55 .mapbase = 0xffeb0000,
56 .flags = UPF_BOOT_AUTOCONF, 60 .flags = UPF_BOOT_AUTOCONF,
57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 61 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
58 .scbrr_algo_id = SCBRR_ALGO_1, 62 .scbrr_algo_id = SCBRR_ALGO_1,
59 .type = PORT_SCIF, 63 .type = PORT_SCIF,
60 .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)),
61 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 64 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
62}; 65};
63 66
67static struct resource scif1_resources[] = {
68 DEFINE_RES_MEM(0xffeb0000, 0x100),
69 DEFINE_RES_IRQ(evt2irq(0x780)),
70};
71
72static struct resource scif1_demux_resources[] = {
73 DEFINE_RES_MEM(0xffeb0000, 0x100),
74 /* Placeholders, see sh7786_devices_setup() */
75 DEFINE_RES_IRQ(0),
76 DEFINE_RES_IRQ(0),
77 DEFINE_RES_IRQ(0),
78 DEFINE_RES_IRQ(0),
79};
80
64static struct platform_device scif1_device = { 81static struct platform_device scif1_device = {
65 .name = "sh-sci", 82 .name = "sh-sci",
66 .id = 1, 83 .id = 1,
84 .resource = scif1_resources,
85 .num_resources = ARRAY_SIZE(scif1_resources),
67 .dev = { 86 .dev = {
68 .platform_data = &scif1_platform_data, 87 .platform_data = &scif1_platform_data,
69 }, 88 },
70}; 89};
71 90
72static struct plat_sci_port scif2_platform_data = { 91static struct plat_sci_port scif2_platform_data = {
73 .mapbase = 0xffec0000,
74 .flags = UPF_BOOT_AUTOCONF, 92 .flags = UPF_BOOT_AUTOCONF,
75 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 93 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
76 .scbrr_algo_id = SCBRR_ALGO_1, 94 .scbrr_algo_id = SCBRR_ALGO_1,
77 .type = PORT_SCIF, 95 .type = PORT_SCIF,
78 .irqs = SCIx_IRQ_MUXED(evt2irq(0x840)),
79 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 96 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
80}; 97};
81 98
99static struct resource scif2_resources[] = {
100 DEFINE_RES_MEM(0xffec0000, 0x100),
101 DEFINE_RES_IRQ(evt2irq(0x840)),
102};
103
82static struct platform_device scif2_device = { 104static struct platform_device scif2_device = {
83 .name = "sh-sci", 105 .name = "sh-sci",
84 .id = 2, 106 .id = 2,
107 .resource = scif2_resources,
108 .num_resources = ARRAY_SIZE(scif2_resources),
85 .dev = { 109 .dev = {
86 .platform_data = &scif2_platform_data, 110 .platform_data = &scif2_platform_data,
87 }, 111 },
88}; 112};
89 113
90static struct plat_sci_port scif3_platform_data = { 114static struct plat_sci_port scif3_platform_data = {
91 .mapbase = 0xffed0000,
92 .flags = UPF_BOOT_AUTOCONF, 115 .flags = UPF_BOOT_AUTOCONF,
93 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 116 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
94 .scbrr_algo_id = SCBRR_ALGO_1, 117 .scbrr_algo_id = SCBRR_ALGO_1,
95 .type = PORT_SCIF, 118 .type = PORT_SCIF,
96 .irqs = SCIx_IRQ_MUXED(evt2irq(0x860)),
97 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 119 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
98}; 120};
99 121
122static struct resource scif3_resources[] = {
123 DEFINE_RES_MEM(0xffed0000, 0x100),
124 DEFINE_RES_IRQ(evt2irq(0x860)),
125};
126
100static struct platform_device scif3_device = { 127static struct platform_device scif3_device = {
101 .name = "sh-sci", 128 .name = "sh-sci",
102 .id = 3, 129 .id = 3,
130 .resource = scif3_resources,
131 .num_resources = ARRAY_SIZE(scif3_resources),
103 .dev = { 132 .dev = {
104 .platform_data = &scif3_platform_data, 133 .platform_data = &scif3_platform_data,
105 }, 134 },
106}; 135};
107 136
108static struct plat_sci_port scif4_platform_data = { 137static struct plat_sci_port scif4_platform_data = {
109 .mapbase = 0xffee0000,
110 .flags = UPF_BOOT_AUTOCONF, 138 .flags = UPF_BOOT_AUTOCONF,
111 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
112 .scbrr_algo_id = SCBRR_ALGO_1, 140 .scbrr_algo_id = SCBRR_ALGO_1,
113 .type = PORT_SCIF, 141 .type = PORT_SCIF,
114 .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)),
115 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 142 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
116}; 143};
117 144
145static struct resource scif4_resources[] = {
146 DEFINE_RES_MEM(0xffee0000, 0x100),
147 DEFINE_RES_IRQ(evt2irq(0x880)),
148};
149
118static struct platform_device scif4_device = { 150static struct platform_device scif4_device = {
119 .name = "sh-sci", 151 .name = "sh-sci",
120 .id = 4, 152 .id = 4,
153 .resource = scif4_resources,
154 .num_resources = ARRAY_SIZE(scif4_resources),
121 .dev = { 155 .dev = {
122 .platform_data = &scif4_platform_data, 156 .platform_data = &scif4_platform_data,
123 }, 157 },
124}; 158};
125 159
126static struct plat_sci_port scif5_platform_data = { 160static struct plat_sci_port scif5_platform_data = {
127 .mapbase = 0xffef0000,
128 .flags = UPF_BOOT_AUTOCONF, 161 .flags = UPF_BOOT_AUTOCONF,
129 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, 162 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
130 .scbrr_algo_id = SCBRR_ALGO_1, 163 .scbrr_algo_id = SCBRR_ALGO_1,
131 .type = PORT_SCIF, 164 .type = PORT_SCIF,
132 .irqs = SCIx_IRQ_MUXED(evt2irq(0x8a0)),
133 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, 165 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
134}; 166};
135 167
168static struct resource scif5_resources[] = {
169 DEFINE_RES_MEM(0xffef0000, 0x100),
170 DEFINE_RES_IRQ(evt2irq(0x8a0)),
171};
172
136static struct platform_device scif5_device = { 173static struct platform_device scif5_device = {
137 .name = "sh-sci", 174 .name = "sh-sci",
138 .id = 5, 175 .id = 5,
176 .resource = scif5_resources,
177 .num_resources = ARRAY_SIZE(scif5_resources),
139 .dev = { 178 .dev = {
140 .platform_data = &scif5_platform_data, 179 .platform_data = &scif5_platform_data,
141 }, 180 },
@@ -1037,13 +1076,16 @@ static int __init sh7786_devices_setup(void)
1037 */ 1076 */
1038 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1); 1077 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
1039 if (irq > 0) { 1078 if (irq > 0) {
1040 scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq; 1079 scif1_demux_resources[1].start =
1041 scif1_platform_data.irqs[SCIx_ERI_IRQ] =
1042 intc_irq_lookup(sh7786_intc_desc.name, ERI1); 1080 intc_irq_lookup(sh7786_intc_desc.name, ERI1);
1043 scif1_platform_data.irqs[SCIx_BRI_IRQ] = 1081 scif1_demux_resources[2].start =
1044 intc_irq_lookup(sh7786_intc_desc.name, BRI1);
1045 scif1_platform_data.irqs[SCIx_RXI_IRQ] =
1046 intc_irq_lookup(sh7786_intc_desc.name, RXI1); 1082 intc_irq_lookup(sh7786_intc_desc.name, RXI1);
1083 scif1_demux_resources[3].start = irq;
1084 scif1_demux_resources[4].start =
1085 intc_irq_lookup(sh7786_intc_desc.name, BRI1);
1086
1087 scif1_device.resource = scif1_demux_resources;
1088 scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources);
1047 } 1089 }
1048 1090
1049 ret = platform_add_devices(sh7786_early_devices, 1091 ret = platform_add_devices(sh7786_early_devices,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 688f7ed1bab1..4d65be9be001 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -28,60 +28,75 @@
28 * all rather than adding infrastructure to hack around it. 28 * all rather than adding infrastructure to hack around it.
29 */ 29 */
30static struct plat_sci_port scif0_platform_data = { 30static struct plat_sci_port scif0_platform_data = {
31 .mapbase = 0xffc30000,
32 .flags = UPF_BOOT_AUTOCONF, 31 .flags = UPF_BOOT_AUTOCONF,
33 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
34 .scbrr_algo_id = SCBRR_ALGO_2, 33 .scbrr_algo_id = SCBRR_ALGO_2,
35 .type = PORT_SCIF, 34 .type = PORT_SCIF,
36 .irqs = { evt2irq(0x700), 35};
37 evt2irq(0x720), 36
38 evt2irq(0x760), 37static struct resource scif0_resources[] = {
39 evt2irq(0x740) }, 38 DEFINE_RES_MEM(0xffc30000, 0x100),
39 DEFINE_RES_IRQ(evt2irq(0x700)),
40 DEFINE_RES_IRQ(evt2irq(0x720)),
41 DEFINE_RES_IRQ(evt2irq(0x760)),
42 DEFINE_RES_IRQ(evt2irq(0x740)),
40}; 43};
41 44
42static struct platform_device scif0_device = { 45static struct platform_device scif0_device = {
43 .name = "sh-sci", 46 .name = "sh-sci",
44 .id = 0, 47 .id = 0,
48 .resource = scif0_resources,
49 .num_resources = ARRAY_SIZE(scif0_resources),
45 .dev = { 50 .dev = {
46 .platform_data = &scif0_platform_data, 51 .platform_data = &scif0_platform_data,
47 }, 52 },
48}; 53};
49 54
50static struct plat_sci_port scif1_platform_data = { 55static struct plat_sci_port scif1_platform_data = {
51 .mapbase = 0xffc40000,
52 .flags = UPF_BOOT_AUTOCONF, 56 .flags = UPF_BOOT_AUTOCONF,
53 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
54 .scbrr_algo_id = SCBRR_ALGO_2, 58 .scbrr_algo_id = SCBRR_ALGO_2,
55 .type = PORT_SCIF, 59 .type = PORT_SCIF,
56 .irqs = { evt2irq(0x780), 60};
57 evt2irq(0x7a0), 61
58 evt2irq(0x7e0), 62static struct resource scif1_resources[] = {
59 evt2irq(0x7c0) }, 63 DEFINE_RES_MEM(0xffc40000, 0x100),
64 DEFINE_RES_IRQ(evt2irq(0x780)),
65 DEFINE_RES_IRQ(evt2irq(0x7a0)),
66 DEFINE_RES_IRQ(evt2irq(0x7e0)),
67 DEFINE_RES_IRQ(evt2irq(0x7c0)),
60}; 68};
61 69
62static struct platform_device scif1_device = { 70static struct platform_device scif1_device = {
63 .name = "sh-sci", 71 .name = "sh-sci",
64 .id = 1, 72 .id = 1,
73 .resource = scif1_resources,
74 .num_resources = ARRAY_SIZE(scif1_resources),
65 .dev = { 75 .dev = {
66 .platform_data = &scif1_platform_data, 76 .platform_data = &scif1_platform_data,
67 }, 77 },
68}; 78};
69 79
70static struct plat_sci_port scif2_platform_data = { 80static struct plat_sci_port scif2_platform_data = {
71 .mapbase = 0xffc60000,
72 .flags = UPF_BOOT_AUTOCONF, 81 .flags = UPF_BOOT_AUTOCONF,
73 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 82 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
74 .scbrr_algo_id = SCBRR_ALGO_2, 83 .scbrr_algo_id = SCBRR_ALGO_2,
75 .type = PORT_SCIF, 84 .type = PORT_SCIF,
76 .irqs = { evt2irq(0x880), 85};
77 evt2irq(0x8a0), 86
78 evt2irq(0x8e0), 87static struct resource scif2_resources[] = {
79 evt2irq(0x8c0) }, 88 DEFINE_RES_MEM(0xffc60000, 0x100),
89 DEFINE_RES_IRQ(evt2irq(0x880)),
90 DEFINE_RES_IRQ(evt2irq(0x8a0)),
91 DEFINE_RES_IRQ(evt2irq(0x8e0)),
92 DEFINE_RES_IRQ(evt2irq(0x8c0)),
80}; 93};
81 94
82static struct platform_device scif2_device = { 95static struct platform_device scif2_device = {
83 .name = "sh-sci", 96 .name = "sh-sci",
84 .id = 2, 97 .id = 2,
98 .resource = scif2_resources,
99 .num_resources = ARRAY_SIZE(scif2_resources),
85 .dev = { 100 .dev = {
86 .platform_data = &scif2_platform_data, 101 .platform_data = &scif2_platform_data,
87 }, 102 },
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index 18419f1de963..64b098162c98 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -17,17 +17,24 @@
17#include <asm/addrspace.h> 17#include <asm/addrspace.h>
18 18
19static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
20 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000,
21 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 20 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
23 .scbrr_algo_id = SCBRR_ALGO_2, 22 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 23 .type = PORT_SCIF,
25 .irqs = { 39, 40, 42, 0 }, 24};
25
26static struct resource scif0_resources[] = {
27 DEFINE_RES_MEM(PHYS_PERIPHERAL_BLOCK + 0x01030000, 0x100),
28 DEFINE_RES_IRQ(39),
29 DEFINE_RES_IRQ(40),
30 DEFINE_RES_IRQ(42),
26}; 31};
27 32
28static struct platform_device scif0_device = { 33static struct platform_device scif0_device = {
29 .name = "sh-sci", 34 .name = "sh-sci",
30 .id = 0, 35 .id = 0,
36 .resource = scif0_resources,
37 .num_resources = ARRAY_SIZE(scif0_resources),
31 .dev = { 38 .dev = {
32 .platform_data = &scif0_platform_data, 39 .platform_data = &scif0_platform_data,
33 }, 40 },
generated by cgit v1.2.2 (git 2.25.0) at 2026-02-28 03:44:47 -0500